Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes a substrate, a gate structure, a first interlayer dielectric layer, a source structure, a drain structure, a dielectric pattern, a first field plate, and a second field plate. The gate structure is disposed on the substrate. The first interlayer dielectric layer is disposed on the substrate and partially covers the gate structure. The source electrode structure and the drain electrode structure are arranged on the substrate and located on the two sides of the gate electrode structure. The dielectric pattern is disposed on the first interlayer dielectric layer between the gate structure and the drain structure. The first field plate is arranged on the substrate and covers the first interlayer dielectric layer between the gate structure and the dielectric pattern and the dielectric pattern. The second field plate is disposed over the first field plate and the dielectric pattern and extends toward the drain structure.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to high electron mobility transistor devices. Background Technology

[0002] High electron mobility transistors (HEMTs), also known as heterostructure field-effect transistors (HFETs) or modulation-doped field-effect transistors (MODFETs), are a type of field-effect transistor composed of semiconductor materials with different energy gaps. A two-dimensional electron gas layer is generated at the interface between adjacent different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, HEMT devices can possess advantages such as high breakdown voltage, high electron mobility, low on-resistance, and low input capacitance, making them suitable for high-power devices.

[0003] However, while these high electron mobility transistor devices generally meet the requirements, they are not satisfactory in every aspect. Therefore, further improvements to high electron mobility transistor devices and their manufacturing methods are needed to enhance performance and reliability. Summary of the Invention

[0004] Some embodiments of the present invention provide a semiconductor device. The semiconductor device includes a substrate, a gate structure, a first interlayer dielectric layer, a source structure, a drain structure, a dielectric pattern, a first field plate, and a second field plate. The gate structure is disposed on the substrate. The first interlayer dielectric layer is disposed on the substrate and partially covers the gate structure. The source structure and the drain structure are disposed on the substrate and located on opposite sides of the gate structure. The dielectric pattern is disposed on the first interlayer dielectric layer between the gate structure and the drain structure. The first field plate is disposed on the substrate and covers the first interlayer dielectric layer between the gate structure and the dielectric pattern, as well as the dielectric pattern. The second field plate is disposed above the first field plate and the dielectric pattern and extends toward the drain structure.

[0005] In some embodiments, the first and second field plates of the semiconductor device extend toward the drain structure and are electrically connected to the source structure. Therefore, the first and second field plates can also serve as source field plates, effectively reducing the surface electric field. Furthermore, the first field plate is a stepped source field plate compliantly formed on the interlayer dielectric layer and dielectric pattern, and the second field plate is a stepped source field plate compliantly formed on the interlayer dielectric layer, dielectric pattern, and the first field plate. Therefore, a multi-layer (e.g., double-layer) field plate structure can be fabricated using a single-layer field plate process. The first and second field plates of this embodiment can achieve the electric field dispersion effect of a multi-layer field plate structure while saving the process cost of one layer of field plate structure (e.g., photomask cost), thereby reducing the number of field plates and lowering the capacitance generated between the gate electrode and the drain region. The first and second field plates can also avoid large electric field peaks at the field plate edges, thereby reducing the source-to-drain on-resistance (Rd). DS-ON Furthermore, it increases the breakdown voltage of high electron mobility transistors. In addition, since the first and second field plates are disposed on different interlayer dielectric layers, the distance between each field plate and the barrier layer can be adjusted to further increase the breakdown voltage. Attached Figure Description

[0006] The viewpoints of embodiments of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly demonstrate the features of embodiments of the invention.

[0007] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0008] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to some embodiments of the present invention.

[0009] Symbol Explanation

[0010] 100, 110: Direction

[0011] 200:Substrate

[0012] 200T, 208T, 210T, 212T: Top surface

[0013] 202: Buffer layer

[0014] 204: Channel Layer

[0015] 206: Barrier Layer

[0016] 208: Gate layer

[0017] 208E: Edge

[0018] 210, 216, 226, 310: Interlayer dielectric layers

[0019] 212: Dielectric pattern

[0020] 212S1, 212S2, 214S1, 214S2, 218S1, 218S2, 230S-S: Side view

[0021] 212T1: Part 1

[0022] 212T2: Part Two

[0023] 214: First game board

[0024] 214-1T, 214-2T, 218-1T, 218-2T: Upper surface

[0025] 218: Second game board

[0026] 218G: Gate electrode layer

[0027] 220: Gate structure

[0028] 230S: Source structure

[0029] 230D: Drain structure

[0030] 310-1, 310-2: Mesonosphere

[0031] 500A, 500B: Semiconductor devices

[0032] D1: First Distance

[0033] D2: Second distance Detailed Implementation

[0034] The present disclosure is described more fully below with reference to the accompanying drawings of embodiments of the invention. However, the present disclosure may be implemented in various different ways and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be enlarged for clarity, and the same or similar reference numerals in the drawings denote the same or similar elements. It is understood that additional steps may be provided before, during, and after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0035] Various embodiments or examples are provided below for implementing different elements of the provided semiconductor structure. When the description refers to a first component being formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components, so that the first and second components are not in direct contact. Furthermore, the embodiments of the invention may use repeated component symbols in many examples. These repetitions are for simplification and clarity only and do not represent a specific relationship between the various embodiments and / or configurations discussed.

[0036] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the direction depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0037] Figure 1 This is a schematic cross-sectional view of a semiconductor device 500A according to some embodiments of the present invention. In some embodiments, the semiconductor device 500A includes a high electron mobility transistor (HEMT), such as an enhancement-mode high electron mobility transistor (E-mode GaN HEMT) based on gallium nitride (GaN). Figure 1 As shown, the semiconductor device 500A includes a substrate 200, a gate structure 220, an interlayer dielectric layer 210, a dielectric pattern 212, a first field plate 214, and a second field plate 218.

[0038] In some embodiments, the substrate 200 may include: elemental semiconductors, including silicon or germanium; compound semiconductors, including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb); alloy semiconductors, including silicon-germanium alloy, gallium arsenide-gallium phosphide alloy, aluminum arsenide-indium phosphide alloy, aluminum arsenide-gallium phosphide alloy, indium arsenide-gallium phosphide alloy and / or indium arsenide-indium phosphide alloy, or combinations of the above materials.

[0039] In some embodiments, substrate 200 may be a semiconductor-on-insulator (SOI) substrate, such as silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI). In other embodiments, substrate 200 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an alumina (Al2O3) substrate (or sapphire substrate), a glass substrate, or other similar substrates. In some embodiments, substrate 200 may include a ceramic substrate and a pair of barrier layers respectively disposed on the upper and lower surfaces of the ceramic substrate, wherein the ceramic substrate may include ceramic materials, and the ceramic materials include metallic inorganic materials. For example, the ceramic substrate may include silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The sapphire substrate may be alumina. In some embodiments, the barrier layers located on the upper and lower surfaces of the ceramic substrate may include a single or multiple layers of insulating material and / or other suitable material layers, such as semiconductor layers. The insulating material layer can be an oxide, nitride, oxynitride, or other suitable insulating material. The semiconductor layer can be polycrystalline silicon. The barrier layer prevents diffusion into the ceramic substrate and also prevents the ceramic substrate from interacting with other film layers or process equipment. In some embodiments, the barrier layer can also encapsulate the ceramic substrate. In this case, the barrier layer covers not only the top and bottom surfaces of the ceramic substrate but also both sides of the ceramic substrate.

[0040] In some embodiments, the semiconductor device 500A further includes a buffer layer 202. For example... Figure 1 As shown, a buffer layer 202 is located on the top surface 200T of the substrate 200. Since the lattice or thermal expansion coefficient of the substrate 200 may differ from that of the upper component (e.g., channel layer 204), strain may occur at or near the interface between the substrate 200 and the upper component, easily leading to defects such as cracks or warping. Therefore, the buffer layer 202 located on the substrate 200 can alleviate the strain of the component (e.g., channel layer 204) formed above the buffer layer 202, preventing defects from forming in the upper component. In some embodiments, the material of the buffer layer 202 may include a III-V compound semiconductor material, such as a III-V nitride. For example, the material of the buffer layer 202 may include: aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (Al2N), etc. x Ga 1-xN, where 0 < x < 1), aluminum indium nitride (AlInN), the above combinations, or other similar materials. In some embodiments, the buffer layer 202 can be formed by an epitaxial growth process, such as: metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or the above combinations. In some embodiments, the buffer layer 202 can be a multi-layer structure (not shown in the figure). For example, the buffer layer 202 can include a superlattice buffer layer and / or a graded buffer layer. The superlattice buffer layer is disposed on the substrate 200, and the graded buffer layer is disposed on the superlattice buffer layer, which can effectively prevent dislocations in the substrate 200 from entering the upper components and further improve the crystal quality of other films and / or layers above.

[0041] In some embodiments, the semiconductor device 500A can optionally include a seed layer (not shown in the figure) located between the substrate 200 and the buffer layer 202. The seed layer can relieve the lattice difference between the substrate 200 and the films and / or layers grown above to improve the crystal quality. In some embodiments, the material of the seed layer can include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or the above combinations. In some embodiments, a seed layer having a single-layer or multi-layer structure can be formed by, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable processes, or the above combinations.

[0042] In some embodiments, the semiconductor device 500A further includes a channel layer 204. As Figure 1 shown, the channel layer 204 is located on the buffer layer 202. In some embodiments, the material of the channel layer 204 includes a binary III-V compound semiconductor material, such as a group III nitride. For example, the material of the channel layer 204 can include gallium nitride (GaN). In some embodiments, the channel layer 204 can be doped with an n-type dopant or a p-type dopant. In some embodiments, the channel layer 204 can be formed by an epitaxial growth process, such as: metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable processes, or the above combinations.

[0043] In some embodiments, the semiconductor device 500A further includes a blocking layer 206. As Figure 1 shown, the blocking layer 206 is located on the channel layer 204. The material of the blocking layer 206 can include a ternary III-V compound semiconductor, such as a group III nitride. For example, the material of the blocking layer 206 can include aluminum gallium nitride (Al y Ga 1-yN, where 0 < y < 1), aluminum indium nitride (AlInN), or a combination of the above. In some other embodiments, the barrier layer 206 may also include: gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable group III-V materials, or a combination of the above. In some embodiments, the barrier layer 206 can be doped with an n-type dopant or a p-type dopant. In some embodiments, the barrier layer 206 can be formed by an epitaxial growth process, such as: metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), other suitable processes, or a combination of the above.

[0044] According to some embodiments of the present invention, the channel layer 204 and the barrier layer 206 include different materials, and the interface between the two is a heterojunction structure. Due to the lattice mismatch between the channel layer 204 and the barrier layer 206, stress may be generated, resulting in a piezoelectric polarization effect. Moreover, the ionic nature of the bonding between group III metals (such as aluminum (Al), gallium (Ga), or indium (In)) and nitrogen is relatively strong, leading to spontaneous polarization. By virtue of the energy gap between the heteromaterials of the channel layer 204 and the barrier layer 206 and the aforementioned piezoelectric polarization and spontaneous polarization effects, a two-dimensional electron gas (2DEG) (not shown in the figure) is formed on the heterojunction interface between the channel layer 204 and the barrier layer 206. In some embodiments, the two-dimensional electron gas is used as the conductive carriers of the semiconductor device 500A.

[0045] The gate structure 220 is disposed on the barrier layer 206 and covers a part of the barrier layer 206. In some embodiments, the gate structure 220 includes a gate layer 208 and a gate electrode layer 218G.

[0046] The gate layer 208 is located on a part of the barrier layer 206 and is in contact with the barrier layer 206. As Figure 1 shown, the gate layer 208 can have as Figure 1The rectangular cross-section shown is not provided. Alternatively, the cross-section of the gate layer 208 may also be of other shapes, such as a trapezoidal cross-section. In some embodiments, the material of the gate layer 208 may include n-type or p-type doped III-V semiconductors, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), or other III-V semiconductors. In other embodiments, the gate layer 208 comprises p-type doped II-VI semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), zinc sulfide (ZnS), or other II-VI semiconductors. In some embodiments, the gate layer 208 may be formed by metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), combinations thereof, or other suitable methods and subsequent patterning processes. In this embodiment, the gate layer 208 may be doped. For example, the dopants include magnesium (Mg), zinc (Zn), calcium (Ca), beryllium (Be), strontium (Sr), barium (Ba), radium (Ra), carbon (C), silver (Ag), gold (Au), lithium (Li), or sodium (Na), so that the gate layer 208 has a p-type conductivity.

[0047] A gate electrode layer 218G is located on the gate layer 208. The gate electrode layer 218G contacts and partially covers the top surface 208T of the gate layer 208. In some embodiments, the material of the gate electrode layer 218G may include a metal, a metal nitride, a metal oxide, a metal alloy, other suitable conductive materials, or a single-layer or multi-layer structure formed by a combination of the above. For example, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, alloys of the above, or combinations thereof. Metal alloys may include titanium tungstenide (TiW). Metal nitrides may include molybdenum nitride (MoN), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), silicon tantalum nitride (TaSiN), tantalum carbide (TaCN), titanium aluminum nitride (TiAlN), or other similar materials. In other embodiments, the conductive material of the gate electrode layer 218G may include nickel silicide (NiSi), cobalt silicide (CoSi), tantalum carbide (TaC), titanium aluminide (TiAl), or other similar materials. In this embodiment, the gate electrode layer 218G is titanium nitride (TiN).

[0048] In some embodiments, the gate electrode layer 218G may be formed by a deposition process and a subsequent patterning process. For example, the deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) (e.g., sputtering or evaporation).

[0049] like Figure 1 As shown, the semiconductor device 500A also includes an interlayer dielectric layer 210 disposed on the barrier layer 206. Furthermore, the interlayer dielectric layer 210 partially covers the gate structure 220. As... Figure 1 As shown, the interlayer dielectric layer 210 contacts the opposite side (not shown) of the gate layer 208 and part of the top surface 208T, part of the side gate electrode layer 218G of the gate electrode layer 218G, and the barrier layer 206 not covered by the gate structure 220.

[0050] In some embodiments, the interlayer dielectric layer 210 may be a single-layer structure or a multilayer structure. In this embodiment, the interlayer dielectric layer 210 may be a single-layer structure or a multilayer structure formed of the same material.

[0051] In some embodiments, the interlayer dielectric layer 210 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), low dielectric constant dielectric material, and / or other suitable dielectric materials, or combinations thereof. The aforementioned low dielectric constant dielectric material may include (but is not limited to): fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polyimide, or other suitable dielectric materials. In some embodiments, the interlayer dielectric layer 210 may be formed by a deposition process. For example, the deposition process may include: spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDPCVD), other suitable processes, or combinations thereof.

[0052] like Figure 1 As shown, source structure 230S and drain structure 230D are disposed on substrate 200 and are located on both sides of gate structure 220 and interlayer dielectric layer 210 along direction 100 (which can also be considered a lateral direction) substantially parallel to the top surface 200T of substrate 200. Furthermore, source structure 230S and drain structure 230D located on both sides of gate layer 208 are separated from gate layer 208 by interlayer dielectric layer 210 along direction 100. In addition, interlayer dielectric layer 210 extends along direction 100 between source structure 230S and drain structure 230D. Source structure 230S and drain structure 230D extend from above interlayer dielectric layer 210 along direction 110 (which can also be considered a vertical direction) substantially perpendicular to the top surface 200T of substrate 200 and enter a portion of channel layer 204 and contact channel layer 204.

[0053] In some embodiments, the source structure 230S may be a composite structure (multilayer structure), which, from bottom to top, may sequentially include a source electrode layer (not shown) disposed on the barrier layer 206 and extending along direction 100 to cover the top surface 210T of the interlayer dielectric layer 210, a source contact member (not shown) located on the source electrode layer and extending along direction 110, and a source metal layer (not shown) located on the source contact member and extending along direction 100 toward the drain structure 230D. In some embodiments, the source metal layer completely covers the source electrode layer.

[0054] In some embodiments, the source electrode layer conforms to the interlayer dielectric layer 210 and the barrier layer 206. Figure 1 In the cross-sectional view shown, the source electrode layer is stepped. In this embodiment, the stepped source electrode layer has two steps and may have two upper surfaces.

[0055] Similar to the source structure 230S, the drain structure 230D can be a composite structure (multilayer structure), which, from bottom to top, may sequentially include a drain electrode layer (not shown) disposed on the barrier layer 206 and extending along direction 100 to cover a portion of the top surface 210T of the interlayer dielectric layer 210, a drain contact member (not shown) located on the drain electrode layer and extending along direction 110, and a drain metal layer (not shown) located on the drain contact member and extending along direction 100. In some embodiments, the source electrode layer and the drain electrode layer are formed simultaneously, the source contact member and the drain contact member are formed simultaneously, and the source metal layer and the drain metal layer are formed simultaneously.

[0056] Similar to the source electrode layer, the drain electrode layer is compliantly formed on the interlayer dielectric layer 210 and the barrier layer 206. Figure 1 In the cross-sectional view shown, the drain electrode layer is stepped. In this embodiment, the stepped drain electrode layer has two steps and may have two upper surfaces.

[0057] A dielectric pattern 212 is disposed on a portion of the interlayer dielectric layer 210 between the gate structure 220 and the drain structure 230D. The dielectric pattern 212 also covers a portion of the top surface 210T of the interlayer dielectric layer 210. The dielectric pattern 212 has a top surface 212T and side surfaces 212S1 and 212S2 connected to and opposite to the top surface 212T. The side surfaces 212S1 and 212S2 of the dielectric pattern 212 are both located on the top surface 210T of the interlayer dielectric layer 210. In a direction 110 (which can also be considered a vertical direction) substantially perpendicular to the top surface 200T of the substrate 200, the dielectric pattern 212 partially overlaps with the interlayer dielectric layer 210. Figure 1As shown, in the direction 100 (which can also be considered as the lateral direction) substantially parallel to the top surface 200T of the substrate 200, the side surface 212S1 of the dielectric pattern 212 is separated from the gate layer 208 of the gate structure 220 by a first distance D1. Furthermore, the side surface 212S2 of the dielectric pattern 212 is separated from the drain structure 230D (e.g., the drain electrode layer of the drain structure 230D) by a second distance D2. In some embodiments, the first distance D1 is smaller than the second distance D2. In other words, in the direction 100, the gate structure 220 is closer to the dielectric pattern 212 than the drain structure 230D.

[0058] In some embodiments, the dielectric pattern 212 may include a dielectric material, such as silicon oxide (SiO2) or silicon nitride (SiN). X The dielectric material may include silicon oxynitride (SiON), tetraethoxysilane (TEOS) oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), and / or other suitable dielectric materials, or combinations thereof. In some embodiments, the dielectric pattern 212 may include a low dielectric constant dielectric material, a high dielectric constant dielectric material (a dielectric constant (k) higher than that of silicon oxide (SiO2) (k = 3.9), and / or other suitable dielectric materials, or combinations thereof. The aforementioned low-dielectric-constant dielectric materials may include (but are not limited to): fluorinated silica glass (FSG), hydrogen silsesquioxane (HSQ), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), polyimide, or combinations thereof. The aforementioned high-dielectric-constant dielectric materials may include (but are not limited to): silicon nitride, hafnium oxide, hafnium silicon oxide, hafnium oxysilicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium oxide-aluminum oxide alloy, and / or combinations thereof or similar materials. In some embodiments, the dielectric pattern 212 may be a single-layer structure or a multilayer structure formed from the aforementioned dielectric materials.

[0059] In some embodiments, the dielectric constant of the interlayer dielectric layer 210 is the same as that of the dielectric pattern 212. For example, both the interlayer dielectric layer 210 and the dielectric pattern 212 are silicon dioxide and have the same dielectric constant (k = 3.9). In some embodiments, the dielectric constant of the interlayer dielectric layer 210 is different from that of the dielectric pattern 212. The dielectric constant of the interlayer dielectric layer 210 may be less than that of the dielectric pattern 212. For example, the interlayer dielectric layer 210 is silicon dioxide (k = 3.9), and the dielectric pattern 212 is silicon nitride (k = 7.5).

[0060] In some embodiments, the dielectric pattern 212 may be formed by a deposition process and a subsequent patterning process. For example, the deposition process may include: spin-on coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDPCVD), other suitable processes, or combinations thereof.

[0061] In some embodiments, when the dielectric pattern 212 is formed of a high-dielectric-constant dielectric material such as silicon nitride, and the interlayer dielectric layer 210 is formed of silicon dioxide, the dielectric pattern 212 can withstand a high electric field, thereby making the surface electric field distribution of the semiconductor device 500A more uniform. For example, it can reduce the electric field peak at the edge of the subsequently formed field plate (e.g., the side 214S2 of the first field plate 214 near the drain structure 230D). Furthermore, since the interlayer dielectric layer 210 and the dielectric pattern 212 are formed of different dielectric materials, the interlayer dielectric layer 210 can serve as an etch stop layer for the dielectric pattern 212 during the patterning process (including photolithography and etching processes) to form the dielectric pattern 212, and the thickness of the interlayer dielectric layer 310 is not affected by the etching process, thereby further improving the figure of merit (FOM) of the semiconductor device 500A (e.g., the pinch-off voltage of the semiconductor device 500A).

[0062] A first field plate 214 is disposed on the substrate 200. Furthermore, the first field plate 214 covers the interlayer dielectric layer 210 and the dielectric pattern 212 between the gate structure 220 and the dielectric pattern 212. For example... Figure 1As shown, the first field plate 214 extends from the top surface 210T of the interlayer dielectric layer 210 along direction 100, covering and contacting all sides 212S1 of the dielectric pattern 212 and the first portion 212T1 of the top surface 212T, while exposing the second portion 212T2 of the top surface 212T from the first field plate 214. In other words, the first field plate 214 does not extend to cover the side surface 212S2 of the dielectric pattern 212 near the drain structure 230D, which reduces the risk of a short circuit between the first field plate 214 and the drain structure 230D. Furthermore, the first portion 212T1 and the second portion 212T2 of the top surface 212T of the dielectric pattern 212 are adjacent to each other and are different portions of the top surface 212T of the dielectric pattern 212. For example, the first portion 212T1 of the top surface 212T of the dielectric pattern 212 is closer to the gate structure 220, while the second portion 212T2 is closer to the drain structure 230D.

[0063] In some embodiments, a first field plate 214 is compliantly formed on the interlayer dielectric layer 210 and the dielectric pattern 212. Therefore, the first field plate 214 is as follows: Figure 1 The cross-sectional view shown is stepped. In this embodiment, the stepped first field plate 214 has a step number of 2. Therefore, the first field plate 214 has two upper surfaces 214-1T and 214-2T in direction 110, and side surfaces 214S1 and 214S2 respectively connected to and opposite to the upper surfaces 214-1T and 214-2T. The upper surface 214-1T of the first field plate 214 is located directly above a portion of the interlayer dielectric layer 210 between the gate structure 220 and the dielectric pattern 212. The upper surface 214-2T of the first field plate 214 is located directly above the first portion 212T1 of the top surface 212T of the dielectric pattern 212. In some embodiments, the upper surfaces 214-1T and 214-2T are not coplanar. For example, in direction 110. The upper surface 214-1T is below the upper surface 214-2T (meaning that the upper surface 214-1T is closer to the top surface 200T of the substrate 200 than the upper surface 214-2T).

[0064] like Figure 1 As shown, the side 214S1 of the first field plate 214 near the gate structure 220 is located directly above the portion of the interlayer dielectric layer 210 between the gate structure 220 and the dielectric pattern 212, and the side 214S2 of the first field plate 214 near the drain structure 230D is located directly above the dielectric pattern 212. In some embodiments, the side 214S2 of the first field plate 214 and the side 212S2 of the dielectric pattern 212 near the drain structure 230D are not aligned with each other.

[0065] In some embodiments, the first field plate 214 may include polysilicon, metals (e.g., tungsten, titanium, aluminum, copper, iron, molybdenum, nickel, platinum, similar materials, or combinations thereof), metal alloys (e.g., nickel-iron alloy (NiFe), beryllium-copper alloy (BeCu)), metal nitrides (e.g., tungsten nitride, molybdenum nitride, titanium nitride, tantalum nitride, similar materials, or combinations thereof), metal silicides (e.g., tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, similar materials, or combinations thereof), metal oxides (ruthenium oxide, indium tin oxide, similar materials, or combinations thereof), other suitable conductive materials, or combinations thereof. In some embodiments, the first field plate 214 may be formed by a deposition process and a subsequent patterning process. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam deposition, plasma-enhanced chemical vapor deposition, other suitable processes, or combinations thereof. In some embodiments, the first field plate 214 may be formed simultaneously with the source electrode layer of the source structure 230S and the drain electrode layer of the drain structure 230D.

[0066] like Figure 1 As shown, the semiconductor device 500A also includes an interlayer dielectric layer 216. The interlayer dielectric layer 216 is disposed on the interlayer dielectric layer 210, extending from the source structure 230S to the drain structure 230D, and completely covers the dielectric pattern 212 and the first field plate 214, such that the dielectric pattern 212 and the first field plate 214 are sandwiched between the interlayer dielectric layers 210 and 216 along direction 110. Specifically, the interlayer dielectric layer 216 covers and contacts the interlayer dielectric layer 210 exposed from the dielectric pattern 212 and the first field plate 214. The interlayer dielectric layer 216 covers and contacts the upper surfaces 214-1T, 214-2T and the side surfaces 214S1, 214S2 of the first field plate 214. Furthermore, the interlayer dielectric layer 216 covers and contacts the second portion 212T2 of the top surface 212T of the dielectric pattern 212 and the side surface 212S2. Figure 1 As shown, the first field plate 214 and the interlayer dielectric layer 216 respectively contact the opposite sides 212S1 and 212S2 of the dielectric pattern 212. Figure 1 As shown, the source structure 230S and the drain structure 230D penetrate the interlayer dielectric layers 210 and 216 and the barrier layer 206, respectively, and contact the channel layer 204. Furthermore, the drain structure 230D and the gate electrode layer 218G located on both sides of the first field plate 214 are separated from the first field plate 214 by the interlayer dielectric layer 216 along the direction 100.

[0067] In some embodiments, interlayer dielectric layers 210 and 216 may comprise the same or similar materials and processes. Therefore, in some embodiments, the dielectric constant of interlayer dielectric layer 216 is the same as the dielectric constant of dielectric pattern 212. For example, both interlayer dielectric layer 216 and dielectric pattern 212 are silicon dioxide and have the same dielectric constant (k = 3.9). In some embodiments, the dielectric constant of interlayer dielectric layer 216 is different from the dielectric constant of dielectric pattern 212. The dielectric constant of interlayer dielectric layer 216 may be less than the dielectric constant of dielectric pattern 212. For example, interlayer dielectric layer 216 is silicon dioxide (k = 3.9), and dielectric pattern 212 is silicon nitride (k = 7.5).

[0068] The second field plate 218 is disposed above the first field plate 214 and the dielectric pattern 212, and extends toward the drain structure 230D. The second field plate 218 covers a portion of the interlayer dielectric layer 216 directly above the top surface 212T of the dielectric pattern 212, and is separated from the first field plate 214 by the interlayer dielectric layer 216. In some embodiments, the first field plate 214 and the second field plate 218 partially overlap. Specifically, in direction 110, the second field plate 218 overlaps with a portion of the first field plate 214 on the first portion 212T1 of the top surface 212T of the dielectric pattern 212. Furthermore, the second field plate 218 does not overlap with a portion of the first field plate 214 on the interlayer dielectric layer 210 between the gate structure 220 and the dielectric pattern 212. Therefore, the second field plate 218 is closer to the drain structure 230D than the first field plate 214. Furthermore, in direction 110, the first field plate 214 and the second field plate 218 overlap with the source metal layer (not shown in the figure) of the source structure 230S.

[0069] In some embodiments, a second field plate 218 is compliantly formed on the interlayer dielectric layer 210, the dielectric pattern 212, and the first field plate 214. Therefore, the second field plate 218 is as follows: Figure 1The cross-sectional view shown is stepped. In this embodiment, the stepped second field plate 218 has a step number of 2. Therefore, the second field plate 218 has two upper surfaces 218-1T and 218-2T in direction 110, and side surfaces 218S1 and 218S2 connected to and opposite to the upper surfaces 218-1T and 218-2T, respectively. The upper surface 218-1T of the second field plate 218 is located directly above the first portion 212T1 of the top surface 212T of the dielectric pattern 212 (or the upper surface 214-2T of the first field plate 214), and the upper surface 218-2T of the second field plate 218 is located directly above the second portion 212T2 of the top surface 212T of the dielectric pattern 212. In some embodiments, the upper surfaces 218-1T and 218-2T are not coplanar. For example, in direction 110, the upper surface 218-1T is above the upper surface 218-2T (meaning that the upper surface 218-2T is closer to the top surface 200T of the substrate 200 than the upper surface 218-1T).

[0070] like Figure 1 As shown, the side 218S1 of the second field plate 218 near the gate structure 220 is located directly above the first portion 212T1 of the top surface 212T of the dielectric pattern 212 (or the upper surface 214-2T of the first field plate 214), and the side 218S2 of the second field plate 218 near the drain structure 230D is located directly above the second portion 212T2 of the top surface 212T of the dielectric pattern 212. In some embodiments, the second field plate 218 is located directly above the dielectric pattern 212 and covers a portion of the dielectric pattern 212. Therefore, the opposite sides 218S1 and 218S2 of the second field plate 218 may not be aligned with the corresponding sides 212S1 and 212S2 of the dielectric pattern 212. Furthermore, in direction 100, the side 218S2 of the second field plate 218 near the drain structure 230D is closer to the drain structure 230D than the side 214S2 of the first field plate 214 near the drain structure 230D, and the source metal layer (not shown in the figure) of the source structure 230S near the drain structure 230D is closer to the drain structure 230D than the side 218S2 of the second field plate 218.

[0071] In some embodiments, the first field plate 214 and the second field plate 218 may include the same or similar materials and processes. In some embodiments, the second field plate 218 may be formed simultaneously with the gate electrode layer 218G.

[0072] like Figure 1As shown, the semiconductor device 500A further includes an interlayer dielectric layer 226. The interlayer dielectric layer 226 is disposed on the interlayer dielectric layer 216 and completely covers the source structure 230S, the drain structure 230D, and the source structure 230S extending to the drain structure 230D. Furthermore, the drain structure 230D and the second field plate 218 are separated from each other along direction 100 by the interlayer dielectric layer 226. In some embodiments, the interlayer dielectric layers 210, 216, and 226 may include the same or similar materials and processes. Therefore, in some embodiments, the dielectric constant of the interlayer dielectric layer 226 is the same as the dielectric constant of the dielectric pattern 212. For example, both the interlayer dielectric layer 226 and the dielectric pattern 212 are silicon dioxide and have the same dielectric constant (k = 3.9). In some embodiments, the dielectric constant of the interlayer dielectric layer 226 is different from the dielectric constant of the dielectric pattern 212. The dielectric constant of the interlayer dielectric layer 226 may be less than that of the dielectric pattern 212. For example, the interlayer dielectric layer 226 may be silicon dioxide (k = 3.9), and the dielectric pattern 212 may be silicon nitride (k = 7.5). In some embodiments, the interlayer dielectric layer 226 may be a single-layer structure or a multi-layer structure.

[0073] In some embodiments, the first field plate 214 and the second field plate 218 of the semiconductor device 500A extend along direction 100 toward the drain structure 230D and are electrically connected to the source structure 230S. Therefore, the first field plate 214 and the second field plate 218 can also serve as source field plates 214 and 218, which can effectively reduce the surface field (RESURF). Furthermore, the first field plate 214 is a stepped source field plate compliantly formed on the interlayer dielectric layer 210 and the dielectric pattern 212, and the second field plate 218 is a stepped source field plate compliantly formed on the interlayer dielectric layer 210, the dielectric pattern 212, and the first field plate 214. Therefore, a multilayer (e.g., double-layer) field plate structure can be fabricated using a single-layer field plate process. The first field plate 214 and the second field plate 218 of this embodiment of the invention can achieve the electric field dispersion effect of a multi-layer field plate structure while saving the process cost of one layer of field plate structure (e.g., photomask cost). This reduces the number of field plates and lowers the capacitance generated between the gate electrode and the drain region. The first field plate 214 and the second field plate 218 can also avoid large electric field peaks at the edges of the field plates (e.g., the side 214S2 of the first field plate 214 near the drain structure 230D or the side 218S2 of the second field plate 218 near the drain structure 230D), thereby reducing the source-to-drain on-resistance (Rdrain). DS-ONFurthermore, the breakdown voltage of the high electron mobility transistor is increased. In addition, the first field plate 214 and the second field plate 218 are respectively disposed on different interlayer dielectric layers 210 and 216, so the distance between each field plate and the barrier layer 206 can be adjusted to further increase the breakdown voltage.

[0074] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device 500B according to some embodiments of the present invention. Figure 1 The same or similar component symbols represent the same or similar components. For example... Figure 2 As shown, the difference between semiconductor device 500B and semiconductor device 500A is that semiconductor device 500B includes an interlayer dielectric layer 310 disposed on the barrier layer 206 and partially covering the gate structure 220. The difference between the interlayer dielectric layer 310 of semiconductor device 500B and the interlayer dielectric layer 210 of semiconductor device 500A is that the interlayer dielectric layer 310 is a multilayer structure formed of dielectric materials with different dielectric constants.

[0075] In some embodiments, the interlayer dielectric layer 310 includes multiple dielectric layers. For example, the interlayer dielectric layer 310 includes two dielectric layers 310-1 and 310-2, but the embodiments disclosed herein are not limited thereto. Figure 2 As shown, dielectric layer 310-1 is disposed on gate layer 208 of gate structure 220, and dielectric layer 310-2 is disposed on dielectric layer 310-1. Furthermore, dielectric layers 310-1 and 310-2 are adjacent to different portions of the sidewalls of gate electrode layer 218G. Dielectric pattern 212, first field plate 214, and interlayer dielectric layer 216 contact dielectric layer 310-2 and are separated from dielectric layer 310-1 by dielectric layer 310-2.

[0076] Dielectron layer 310-1 has a first dielectric constant, and dielectron layer 310-2 has a second dielectric constant. In some embodiments, the second dielectric constant is different from the first dielectric constant. The second dielectric constant of dielectron layer 310-2 contacting dielectric pattern 212 may be greater than the first dielectric constant of dielectron layer 310-1, and higher than the dielectric constant of silicon dioxide (k = 3.9). In other words, dielectron layer 310-2 may be formed of a high dielectric constant dielectric material. For example, dielectron layer 310-1 may be silicon dioxide (k = 3.9), and dielectron layer 310-2 may be silicon nitride (k = 7.5).

[0077] In some embodiments, the second dielectric constant of the dielectric layer 310-2 is different from the dielectric constant of the dielectric pattern 212. The second dielectric constant of the dielectric layer 310-2 may be greater than the dielectric constant of the dielectric pattern 212. For example, the dielectric pattern 212 may be silicon dioxide (k = 3.9), and the dielectric layer 310-2 may be silicon nitride (k = 7.5).

[0078] In some embodiments, the semiconductor device 500B not only possesses the advantages of the semiconductor device 500A, but also, since the interlayer dielectric layer 310 of the semiconductor device 500B includes a dielectric electron layer 310-2 with a high dielectric constant, it can withstand a high electric field, resulting in a more uniform surface electric field distribution in the semiconductor device 500B. For example, it can reduce the electric field peak at the edge 208E of the gate layer 208 near the drain structure 230D. Furthermore, the dielectric pattern 212 in contact with each other and the dielectric electron layer 310-2 beneath it can be formed from different dielectric materials. Therefore, during the patterning process (including photolithography and etching processes) for forming the dielectric pattern 212, the dielectric electron layer 310-2 can serve as an etch stop layer for the dielectric pattern 212, allowing for precise control of the thickness of the interlayer dielectric layer 310, thereby further improving the figure of merit (FOM) of the semiconductor device 500B (e.g., the pinch-off voltage of the semiconductor device 500B).

[0079] This invention provides a semiconductor device, such as a high electron mobility transistor (HEMT) device. In some embodiments, the semiconductor device includes a dielectric pattern disposed on a portion of a first interlayer dielectric layer (e.g., interlayer dielectric layer 210) between a gate structure and a drain structure, such that the first field plate and the second field plate above it of the semiconductor device are stepped source field plates. Therefore, a multi-layer (e.g., double-layer) field plate structure can be fabricated using a single-layer field plate process, achieving the electric field dispersion effect of a multi-layer field plate structure while saving the process cost of a single field plate structure (e.g., photomask cost), and avoiding large surface electric field peaks. By setting the stepped source field plate, the number of field plates can be reduced, and the capacitance generated between the gate electrode and the drain region can be reduced. Furthermore, the distance between each field plate and the barrier layer can be adjusted to reduce the on-resistance (R) from the source to the drain. DS-ONFurthermore, this improves the breakdown voltage of high electron mobility transistors. In some embodiments, the dielectric pattern of the semiconductor device and the underlying first interlayer dielectric layer are formed of dielectric materials with different dielectric constants. For example, the first interlayer dielectric layer may be formed of silicon dioxide, and the dielectric pattern may be formed of a high-dielectric-constant dielectric material, such as silicon oxide. Alternatively, the first interlayer dielectric layer of the semiconductor device includes multiple dielectric layers, with the dielectric pattern and the underlying dielectric layers in contact with each other formed of dielectric materials with different dielectric constants. For example, the dielectric pattern may be formed of silicon dioxide, and the dielectric layers may be formed of a high-dielectric-constant dielectric material, such as silicon oxide. The aforementioned dielectric pattern or dielectric layer with a high dielectric constant can make the surface electric field distribution of the semiconductor device more uniform. Moreover, during the etching process of forming the dielectric pattern, the aforementioned first interlayer dielectric layer or dielectric layer with a high dielectric constant can serve as an etch stop layer for the etching process, so that the thickness of the first interlayer dielectric layer does not change due to the etching process, thereby further improving the performance of the semiconductor device.

[0080] While the present invention has been disclosed above with reference to the foregoing embodiments, it is not intended to limit the invention. Those skilled in the art will be able to make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor device, characterized in that, include: One substrate; A gate structure is disposed on the substrate; A first interlayer dielectric layer is disposed on the substrate and partially covers the gate structure; A source structure and a drain structure are disposed on the substrate and located on both sides of the gate structure; A dielectric pattern is disposed on the first interlayer dielectric layer between the gate structure and the drain structure; A first field plate is disposed on the substrate and covers the first interlayer dielectric layer and the dielectric pattern between the gate structure and the dielectric pattern; as well as A second field plate is disposed above the first field plate and the dielectric pattern, and extends toward the drain structure.

2. The semiconductor device as claimed in claim 1, characterized in that, In a first direction, the dielectric pattern is separated from the gate structure by a first distance, and the dielectric pattern is separated from the drain structure by a second distance, wherein the first distance is less than the second distance.

3. The semiconductor device as claimed in claim 1, characterized in that, The first board includes: A first upper surface, located directly above the first interlayer dielectric layer between the gate structure and the dielectric pattern; and A second upper surface is located directly above a first portion of a top surface of the dielectric pattern, wherein the first upper surface and the second upper surface are not coplanar.

4. The semiconductor device as claimed in claim 3, characterized in that, The first upper surface is below the second upper surface.

5. The semiconductor device as claimed in claim 3, characterized in that, The first field plate contacts the first portion of the top surface of the dielectric pattern.

6. The semiconductor device as claimed in claim 3, characterized in that, The first field plate is located on a first side of the drain structure directly above the dielectric pattern.

7. The semiconductor device as claimed in claim 3, characterized in that, The second field plate is located on a second side of the drain structure directly above a second portion of the top surface of the dielectric pattern, wherein the first portion and the second portion are adjacent to each other and are different portions of the top surface of the dielectric pattern.

8. The semiconductor device as claimed in claim 7, characterized in that, The second board includes: A third upper surface, located directly above the first portion of the top surface of the dielectric pattern; and A fourth upper surface is located directly above the second portion of the top surface of the dielectric pattern, wherein the third upper surface is above the fourth upper surface.

9. The semiconductor device as claimed in claim 1, characterized in that, The first interlayer dielectric layer and the dielectric pattern comprise different materials.

10. The semiconductor device as claimed in claim 1, characterized in that, The first interlayer dielectric layer includes: A first dielectric layer is disposed on a gate layer of the gate structure, wherein the first dielectric layer has a first dielectric constant; and A second dielectric layer is disposed on the first dielectric layer, wherein the second dielectric layer has a second dielectric constant that is different from the first dielectric constant.

11. The semiconductor device as claimed in claim 10, characterized in that, The second dielectric constant is greater than the first dielectric constant.

12. The semiconductor device as claimed in claim 10, characterized in that, The dielectric pattern has a third dielectric constant, and the second dielectric constant is different from the third dielectric constant.

13. The semiconductor device as claimed in claim 12, characterized in that, The second dielectric constant is greater than the third dielectric constant.

14. The semiconductor device as claimed in claim 12, characterized in that, The third dielectric constant is equal to the first dielectric constant.

15. The semiconductor device as claimed in claim 1, characterized in that, The first plate partially overlaps with the second plate.

16. The semiconductor device as claimed in claim 1, characterized in that, The first field plate and the second field plate are electrically connected to the source structure.

17. The semiconductor device as claimed in claim 1, characterized in that, In a cross-sectional view, the first field plate is stepped.

18. The semiconductor device as claimed in claim 1, characterized in that, Including: A second interlayer dielectric layer is disposed on the first interlayer dielectric layer and covers the dielectric pattern and the first field plate.

19. The semiconductor device as claimed in claim 18, characterized in that, The first field plate and the second interlayer dielectric layer respectively contact the opposite sides of the dielectric pattern.

20. The semiconductor device as claimed in claim 18, characterized in that, Including: A buffer layer is located on the substrate; A channel layer, located on the buffer layer; and A barrier layer is located on the channel layer, wherein the gate structure is disposed on the barrier layer, and the source structure and the drain structure respectively penetrate the second interlayer dielectric layer, the first interlayer dielectric layer and the barrier layer and contact the channel layer.

Images