MOSFET device and preparation method thereof

Abstract

The invention discloses a metal-oxide-semiconductor field effect transistor (MOSFET) device and a preparation method thereof. The MOSFET device comprises a substrate which comprises a substrate and an epitaxial layer which are stacked; the doped region is located in the epitaxial layer, the doped region comprises a first doped region and a second doped region which are spaced in the direction parallel to the surface of the substrate, and the first doped region and the second doped region are regions formed by performing ion implantation on one side surface of a part of the epitaxial layer; the semi-insulating region is located in the epitaxial layer, and the two sides of the semi-insulating region are in contact with the first doped region and the second doped region respectively; the transparent insulating layer is located on the surface of the substrate, and the transparent insulating layer is in contact with the semi-insulating region; the light-emitting layer is located over the transparent insulating layer, and the light-emitting layer makes contact with the transparent insulating layer. According to the technical scheme, the problems that in the prior art, the switching speed of a traditional MOSFET device is limited, reliability is low, and the device is prone to failure due to an electric field can be effectively solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a MOSFET device and a method for fabricating the same. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, is suitable for manufacturing high-voltage, high-power semiconductor devices due to its wide bandgap, high saturation drift velocity, and high thermal conductivity. In existing technologies, regardless of the optimization of the drive circuit, the switching speed is ultimately limited by the physical property of gate capacitance and its parasitic parameters, resulting in increasingly limited room for improvement. Furthermore, faster dv / dt and di / dt mean more stringent gate oxide stress, exacerbating the risk to gate oxide reliability while increasing speed, creating a performance-reliability contradiction. Rapidly changing voltage and current generate severe electromagnetic interference, complicating drive circuit design and increasing cost and design difficulty.

[0003] Traditional SiC MOSFETs control channel conduction via electrical gate voltage. However, their switching speed is limited by gate capacitance charging and discharging and parasitic parameters, and the high gate oxide interface state density leads to low channel mobility, while also presenting gate oxide reliability issues.

[0004] In summary, existing SiC MOSFETs have significant shortcomings in improving switching speed while ensuring long-term device reliability and stability, particularly in preventing stress damage at the gate oxide interface and effectively managing electromagnetic interference generated during high-frequency operation. Therefore, a MOSFET device that can overcome these problems is urgently needed. Summary of the Invention

[0005] This application provides a MOSFET device and its fabrication method to solve the problems of limited switching speed, low reliability, and easy failure of traditional MOSFET devices caused by electric fields in the prior art.

[0006] According to one aspect of this application, a MOSFET device is provided, comprising:

[0007] The substrate includes a stacked substrate and an epitaxial layer;

[0008] The doped region is located in the epitaxial layer. The doped region is a region formed by ion implantation on one side surface of a portion of the epitaxial layer, and the doped region includes a first doped region and a second doped region spaced apart along a direction parallel to the surface of the substrate.

[0009] A semi-insulating region is located in the epitaxial layer. The semi-insulating region is a region formed by ion implantation on one side surface of the epitaxial layer, and the two sides of the semi-insulating region are in contact with the first doped region and the second doped region, respectively.

[0010] A transparent insulating layer is located on the surface of the substrate, and the transparent insulating layer is in contact with the semi-insulating region;

[0011] A light-emitting layer is located directly above the transparent insulating layer, and the light-emitting layer and the transparent insulating layer are in contact.

[0012] Optionally, the doping ions in the semi-insulating region include one of the elements selected from vanadium, chromium, iron, and titanium.

[0013] Optionally, the material of the light-emitting layer includes gallium nitride or indium phosphide, and the material of the transparent insulating layer includes one or more combinations of silicon dioxide, aluminum oxide, and magnesium fluoride.

[0014] Optionally, both the first doped region and the second doped region include a first implantation region and a second implantation region. The first implantation region is a region formed by ion implantation on one side surface of a portion of the epitaxial layer, and the second implantation region is a region formed by ion implantation on one side surface of a portion of the first implantation region. The MOSFET device further includes a third implantation region, which is a region formed by ion implantation on the other side surface of a portion of the first implantation region. The surfaces of the third implantation region and the second implantation region are in contact.

[0015] Optionally, the two sides of the semi-insulating region are in contact with the third implantation region in the first doped region and the third implantation region in the second doped region, respectively, and the bottom of a portion of the semi-insulating region is in contact with the first implantation region in the first doped region and the first implantation region in the second doped region, respectively; or one side of the semi-insulating region is in contact with the first implantation region and the third implantation region in the first doped region, and the other side of the semi-insulating region is in contact with the first implantation region and the third implantation region in the second doped region.

[0016] Optionally, the depth of the semi-insulating region is less than or equal to the depth of the first injection region.

[0017] Optionally, in the direction from the first doped region to the second doped region, the transparent insulating layer and the light-emitting layer have the same width, the width of the semi-insulating region is smaller than the width of the transparent insulating layer and the light-emitting layer, and the light-emitting layer is located on the side of the semi-insulating region away from the substrate.

[0018] Optionally, the light-emitting layer is located directly above the transparent insulating layer or on the side of the transparent insulating layer.

[0019] According to one aspect of this application, a method for fabricating a MOSFET device is provided, the method comprising the following steps:

[0020] A substrate is provided, the substrate comprising a stacked substrate and an epitaxial layer;

[0021] Ion implantation is performed on one side surface of a portion of the epitaxial layer to form the doped region, and the doped region includes a first doped region and a second doped region spaced apart along a direction parallel to the substrate surface;

[0022] A semi-insulating region and a transparent insulating layer are formed. Ion implantation is performed on a portion of the epitaxial layer surface away from the substrate to form a semi-insulating region. The semi-insulating region is located between the first doped region and the second doped region. A transparent insulating layer is deposited on top of the semi-insulating region, and the transparent insulating layer is in contact with the semi-insulating region.

[0023] A light-emitting layer is deposited on top of the transparent insulating layer, and the light-emitting layer is in contact with the transparent insulating layer.

[0024] Optionally, the steps for forming the doped region and the semi-insulating region include:

[0025] Ion implantation is performed on one side surface of a portion of the epitaxial layer to form a first implantation region, ion implantation is performed on one side surface of a portion of the first implantation region to form a second implantation region, and ion implantation is performed on the other side of a portion of the first implantation region to form a third implantation region, wherein the third implantation region is in contact with the surface of the second implantation region;

[0026] Ion implantation and annealing are performed on one side of the epitaxial layer to form a semi-insulating region. The two sides of the semi-insulating region are in contact with the third implantation region in the first doped region and the third implantation region in the second doped region, respectively. The bottom of part of the semi-insulating region is in contact with the first implantation region in the first doped region and the first implantation region in the second doped region, respectively.

[0027] According to this application, in a semiconductor device, a doped region is located in an epitaxial layer. The doped region is a region formed by ion implantation on one side surface of a portion of the epitaxial layer, and the doped region includes a first doped region and a second doped region spaced apart along a direction parallel to the substrate surface. A semi-insulating region is located in the epitaxial layer, with the first doped region and the second doped region respectively on both sides of the semi-insulating region. A transparent insulating layer is located on the substrate surface, and the transparent insulating layer is in contact with the semi-insulating region. A light-emitting layer is located directly above the transparent insulating layer, and the light-emitting layer is in contact with the transparent insulating layer. In traditional MOSFETs, channel conduction is typically controlled by electrical gate voltage. However, their switching speed is limited by gate capacitance charging and discharging and parasitic parameters, and the high gate oxide interface state density leads to low channel mobility and gate oxide reliability issues. The MOSFET device of this application uses a semi-insulating region instead of the traditional channel, avoiding the interface problems present in the channel region. In the off state, the semi-insulating region protects the corner of the PN junction formed by the P-type base region and the drift region, avoiding electric field concentration and reducing the risk of device failure. When the gate is excited, the resistance of the semi-insulating region drops sharply, turning it into a conducting state. Electrons can flow throughout the entire semi-insulating region, no longer confined to the substrate surface channel, thus avoiding the low channel mobility problem and greatly reducing device failure risk. This invention improves device reliability and extends lifespan by reducing on-resistance. Furthermore, by introducing a light-emitting layer, it achieves channel formation through an internal photogenerated carrier effect, replacing the traditional external gate electric field effect. When the device is turned on, a laser is emitted by energizing the light-emitting layer. The laser passes through a transparent insulating layer and irradiates the semi-insulated region of the channel. When the laser excitation energy exceeds the bandgap, electrons are directly excited from the valence band to the conduction band, instantly generating a large number of photogenerated carriers—the photoconductive effect. This instantaneous change in channel conductivity by photogenerated carriers bypasses the speed limitation of gate capacitance charging and discharging in a physical principle. Simultaneously, this invention eliminates the need for electrically controlled channel formation. By replacing the thin gate oxide layer with a transparent insulating layer, the gate oxide layer does not need to bear a large voltage, avoiding the gate oxide interface stress problem. Therefore, the MOSFET device of this application primarily solves the problems of limited switching speed, low reliability, and easy failure of traditional MOSFET devices due to electric fields. By employing the photoconductive effect as the dominant turn-on mechanism, it achieves ultra-high-speed switching characteristics and enhances the long-term reliability of the device. Attached Figure Description

[0028] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0029] Figure 1 A cross-sectional structural schematic diagram of a MOSFET device according to an embodiment of this application is shown;

[0030] Figure 2A cross-sectional structural schematic diagram of another MOSFET device according to an embodiment of this application is shown;

[0031] Figure 3 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0032] Figure 4 A schematic cross-sectional view of a substrate is shown in a method for fabricating a semiconductor device according to an embodiment of this application.

[0033] Figure 5 It shows in Figure 4 A schematic diagram of the cross-sectional structure of the matrix after the second injection region is formed on the epitaxial layer;

[0034] Figure 6 It shows in Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the first injection region is formed on the epitaxial layer;

[0035] Figure 7 It shows that Figure 6 A schematic diagram of the cross-sectional structure of the matrix after the formation of the third injection region in the first injection region;

[0036] Figure 8 It shows the Figure 7 A schematic diagram of the cross-sectional structure of the substrate after a semi-insulating region is formed in the substrate and a transparent insulating layer is formed on the substrate surface;

[0037] Figure 9 It shows that Figure 8 A schematic diagram of the cross-sectional structure of the substrate after the light-emitting layer is formed on the substrate;

[0038] Figure 10 It shows that Figure 9 A schematic diagram of the cross-sectional structure of the substrate after forming ohmic contacts and gate electrodes on the doped region;

[0039] Figure 11 It shows in Figure 10 A schematic diagram of the cross-sectional structure of the substrate after the interlayer dielectric layer, source electrode, and drain electrode are formed on the substrate.

[0040] The above figures include the following reference numerals:

[0041] 10. Substrate; 20. Epitaxial layer; 30. Doped region; 301. First doped region; 302. Second doped region; 310. First implantation region; 320. Second implantation region; 330. Third implantation region; 40. Semi-insulating region; 50. Transparent insulating layer; 60. Light-emitting layer; 70. Interlayer dielectric layer; 80. Gate electrode; 90. Source electrode; 100. Drain electrode; 110. Ohmic contact. Detailed Implementation

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] As described in the background section, existing SiC MOSFETs have significant shortcomings in improving switching speed while ensuring long-term device reliability and stability, particularly in avoiding stress damage at the gate oxide interface and effectively managing electromagnetic interference generated during high-frequency operation. To address these issues, this application provides a MOSFET device and its fabrication method.

[0046] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0047] According to embodiments of this application, a MOSFET device is provided, such as... Figure 1 and Figure 2 As shown, it includes:

[0048] The substrate includes a stacked substrate 10 and an epitaxial layer 20;

[0049] The doped region 30 is located in the epitaxial layer 20. The doped region 30 is a region formed by ion implantation on one side surface of a portion of the epitaxial layer 20. The doped region 30 includes a first doped region 301 and a second doped region 302 spaced apart along a direction parallel to the substrate surface.

[0050] The semi-insulating region 40 is located in the epitaxial layer 20. The semi-insulating region 40 is a region formed by ion implantation on one side of the surface of the epitaxial layer 20. The two sides of the semi-insulating region 40 are in contact with the first doped region 301 and the second doped region 302, respectively.

[0051] A transparent insulating layer 50 is located on the surface of the substrate, and the transparent insulating layer 50 is in contact with the semi-insulating region 40;

[0052] The light-emitting layer 60 is located directly above the transparent insulating layer 50, and the light-emitting layer 60 and the transparent insulating layer 50 are in contact.

[0053] In the semiconductor device provided in the above embodiments, the doped regions are located in the epitaxial layer 20, the doped region 30 is a region formed by ion implantation on one side surface of a portion of the epitaxial layer 20, the semi-insulating region 40 is located in the epitaxial layer 20, and the two sides of the semi-insulating region 40 are in contact with the first doped region 301 and the second doped region 302, respectively. The transparent insulating layer 50 is located on the substrate surface and is in contact with the semi-insulating region 40. The light-emitting layer 60 is located above the transparent insulating layer 50 and is in contact with the transparent insulating layer 50. In traditional MOSFETs, channel conduction is typically controlled by electrical gate voltage. However, their switching speed is limited by gate capacitance charging and discharging and parasitic parameters, and the high gate oxide interface state density leads to low channel mobility and gate oxide reliability issues. The MOSFET device of this application uses a semi-insulating region instead of the traditional channel, avoiding the interface problems present in the channel region. In the off state, the semi-insulating region protects the corner of the PN junction formed by the P-type base region and the drift region, avoiding electric field concentration and reducing the risk of device failure. When the gate is excited, the resistance of the semi-insulating region drops sharply, turning it into a conducting state. Electrons can flow throughout the entire semi-insulating region, no longer confined to the substrate surface channel, thus avoiding the low channel mobility problem and greatly reducing device failure risk. The device's on-resistance is reduced, improving reliability and extending lifespan. Furthermore, this application introduces a light-emitting layer to achieve an internal photogenerated carrier effect, replacing the traditional external gate electric field effect to induce channel formation. When the device is turned on, a laser is emitted by energizing the light-emitting layer. The laser passes through a transparent insulating layer and irradiates the semi-insulating region of the channel. When the laser excitation energy is greater than the bandgap, electrons are directly excited from the valence band to the conduction band, instantly generating a large number of photogenerated carriers, i.e., the photoconductive effect. The instantaneous change in channel conductivity by photogenerated carriers bypasses the speed limitation of gate capacitance charging and discharging in physical principle. At the same time, this application does not require electrical control of channel formation. By using a transparent insulating layer instead of a thin gate oxide layer, the gate oxide layer does not need to bear a large voltage, avoiding the problem of gate oxide interface stress.

[0054] Therefore, the MOSFET device of this application mainly solves the problems of limited switching speed, low reliability and easy failure of the device by electric field in the traditional MOSFET device in the prior art. By adopting the photoconductive effect as the dominant switching mechanism, ultra-high speed switching characteristics are achieved and the long-term reliability of the device is enhanced.

[0055] In the embodiments of this application, the substrate material can be silicon carbide, which can enable the device to have a wide bandgap, high saturation drift velocity, high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance semiconductor devices that can operate in high temperature, high pressure and high power environments.

[0056] In this embodiment of the application, the doped ions of the semi-insulating region 40 may include one of the elements selected from vanadium, chromium, iron and titanium.

[0057] For example, in the semi-insulating region 40, the doped ion is V, and the doping concentration can be 1E+19±50%cm³. -3 Vanadium, with a doping depth of 0.5–0.6 μm, possesses unique amphoteric properties that allow it to effectively compensate in both the N-type and P-type regions, achieving a semi-insulating effect in the silicon carbide channel region. By precisely controlling the doping dosage and depth of vanadium, a balance can be created within the silicon carbide material, where donor and acceptor impurities are almost completely compensated, resulting in a significant increase in resistivity, approaching that of an insulator. However, when light irradiates this semi-insulating region, photogenerated electron-hole pairs effectively reduce resistivity, rapidly opening conductive channels and thus realizing a light-controlled switching mechanism. Amphoteric doping not only optimizes the photoelectric properties of the material but also provides additional flexibility for device design, allowing for high impedance in the off state to suppress leakage current, while rapidly switching to a low impedance state during laser triggering to promote current flow. This enables light-controlled silicon carbide MOSFETs to achieve an ideal balance between high-speed switching and low power consumption.

[0058] In this embodiment, the material of the light-emitting layer 60 may include gallium nitride or indium phosphide. The material of the transparent insulating layer 50 may include one or more combinations of silicon dioxide, aluminum oxide, and magnesium fluoride.

[0059] Specifically, the material of the light-emitting layer 60 can be a multilayer gallium nitride or indium phosphide structure. Taking gallium nitride as an example, the material of the gallium nitride light-emitting layer includes one or more combinations of p-GaN, AlGaN, i-GaN, AlGaN, and n-GaN. The transparent insulating layer 50 adopts one or more combinations of silicon dioxide, aluminum oxide, and magnesium fluoride to ensure efficient transmission of optical signals and stability of the device structure.

[0060] In some alternative implementations, such as Figure 1As shown, the doped region 30 includes a first implantation region 310, a second implantation region 320, and a third implantation region 330. The first implantation region 310 is a region formed by ion implantation on one side of a portion of the epitaxial layer 20. The second implantation region 320 is a region formed by ion implantation on one side of a portion of the first implantation region 310. The third implantation region 330 implants ions on the other side of a portion of the first implantation region 310. The third implantation region 330 is in contact with the surface of the second implantation region 320.

[0061] Specifically, the second implantation region 320 is p-type doped with Al ions, and the doping concentration can be 1E+19±50%cm³. -3 The doping depth can be 0.2~0.3μm; the first implantation region 310 is p-type doped with Al ions, and the doping concentration can be 1E+17±50%cm³. -3 The doping depth can be 0.7~0.8μm; the doping type of the third implantation region 330 is N-type, the dopant ion is nitrogen element, and the doping concentration can be (1E+19)~(1E+20) cm⁻¹. -3 The doping depth can be 0.2~0.3μm.

[0062] In the above embodiments, the N-type dopant can be any one of the pentavalent elements, including nitrogen (N), phosphorus (P), arsenic (As) and antimony (Sb), and the P-type dopant can be any one of the trivalent elements, including boron (B), aluminum (Al) and gallium (Ga). The embodiments of this application do not make specific limitations.

[0063] In some alternative implementations, such as Figure 1 As shown, the two sides of the semi-insulating region 40 are in contact with the third implantation region in the first doped region 301 and the third implantation region in the second doped region 302, respectively, and the bottom of part of the semi-insulating region 40 is in contact with the first implantation region in the first doped region 301 and the first implantation region in the second doped region 302, respectively; as Figure 2 As shown, the two sides of the semi-insulating region 40 are in contact with the first implantation region and the third implantation region in the first doped region 301 and the first implantation region and the third implantation region in the second doped region 302, respectively.

[0064] In this embodiment, when the laser irradiates the semi-insulating region 40 through the transparent insulating layer 50, the photon energy is greater than the band gap of SiC, which rapidly excites electrons to jump from the valence band to the conduction band, forming a conductive channel and realizing the rapid conduction of the device.

[0065] In some alternative implementations, such as Figure 1 and Figure 2 As shown, the depth of the semi-insulating region 40 is less than or equal to the depth of the first injection region 310.

[0066] Specifically, when the depth of the semi-insulating region is equal to the depth of the first injection region, the channel region resembles a trench gate structure when the device is off. Since the entire gate is still on the silicon carbide surface, the problem of a large gate oxide electric field (where the gate oxide layer is inside the silicon carbide, and the electric field concentration effect is obvious at the corner) is avoided. When the device is on, the entire semi-insulating region 40 is larger and allows electrons to flow, similar to a trench gate, eliminating the JFET region and reducing resistance, allowing the device to withstand a larger current in the on state. By adjusting the depth of the semi-insulating region 40, not only is the turn-off speed of the device optimized, but the PN junction corner formed by the P-type base region and the N-drift region is also protected from the effects of electric field concentration, enhancing the long-term stability and reliability of the device.

[0067] In the above embodiments, such as Figure 1 As shown, the MOSFET device in this embodiment further includes a transparent insulating layer 50 and a light-emitting layer 60. In the direction from the first doped region 301 to the second doped region 302, the transparent insulating layer 50 and the light-emitting layer 60 may have the same width. The width of the semi-insulating region 40 is smaller than the width of the transparent insulating layer 50 and the light-emitting layer 60. The light-emitting layer 60 is located on the side of the semi-insulating region 40 away from the substrate 10.

[0068] In this embodiment, by setting the light-emitting layer 60, the widths of the semi-insulating region 40, the transparent insulating layer 50, and the light-emitting layer 60 satisfy the above relationship, which effectively ensures that the laser beam can accurately and uniformly irradiate the entire semi-insulating region 40, and maximizes the use of the photogenerated carrier effect to achieve rapid conduction in the channel region.

[0069] In some alternative implementations, such as Figure 1 and Figure 2 As shown, the light-emitting layer 60 is located directly above the transparent insulating layer 50. It should be noted that the positional relationship between the light-emitting layer 60 and the transparent insulating layer 50 is not limited to the above-described positional relationship. For example, the light-emitting layer 60 can also be located on the side of the transparent insulating layer 50. This embodiment of the application does not make specific limitations.

[0070] Specifically, when the emitting layer is placed directly above, the generated light beam directly illuminates the semi-insulating region 40, maximizing the excitation of photogenerated carriers and achieving efficient conduction switching in the channel region. This layout simplifies the optical path design and enhances the interaction between light and matter. Photon energy can be rapidly and concentratedly absorbed by the semi-insulating silicon carbide, thereby promoting electron transitions from the valence band to the conduction band, forming a conductive channel. When the emitting layer is placed to the side of the transparent insulating layer, the light signal is directed to a specific photogenerated carrier generation region, such as the channel position of the device. Although the optical path is more complex, it effectively avoids obstruction on the front side of the device, making high-density integration possible.

[0071] According to embodiments of this application, a method for fabricating a MOSFET device is also provided, for fabricating the MOSFET device described in the above embodiments, such as... Figure 3 As shown, the preparation method includes:

[0072] Step S1, providing a substrate, the substrate comprising a stacked substrate and an epitaxial layer;

[0073] Step S2: A doped region is formed in the epitaxial layer. The doped region is a region formed by ion implantation on one side surface of a portion of the epitaxial layer. The doped region includes a first doped region and a second doped region spaced apart along a direction parallel to the substrate surface. The semi-insulating region is located between the first doped region and the second doped region.

[0074] Step S3: Ion implantation is performed on one side surface of a portion of the epitaxial layer to form a semi-insulating region. The semi-insulating region is located between the first doped region and the second doped region. A transparent insulating layer is deposited on top of the semi-insulating region, and the transparent insulating layer is in contact with the semi-insulating region.

[0075] Step S4: A light-emitting layer is deposited on top of the transparent insulating layer, and the light-emitting layer and the transparent insulating layer are in contact.

[0076] In the preparation method provided in the above embodiments, ion implantation is performed on one side surface of a portion of the epitaxial layer to form a first implantation region, ion implantation is performed on one side surface of a portion of the first implantation region to form a second implantation region, and ion implantation is performed on the other side of a portion of the first implantation region to form a third implantation region, with the third implantation region in contact with the surface of the second implantation region; ion implantation is performed on a portion of the epitaxial layer to form a semi-insulating region, with both sides of the semi-insulating region in contact with the third implantation region in the first doped region and the third implantation region in the second doped region, respectively; the bottom of the semi-insulating region is in contact with the first implantation region in the first doped region and the first implantation region in the second doped region, respectively; and after ion implantation, the implanted impurities are activated by annealing. In traditional MOSFETs, channel conduction is typically controlled by electrical gate voltage. However, their switching speed is limited by gate capacitance charging and discharging and parasitic parameters, and the high gate oxide interface state density leads to low channel mobility and gate oxide reliability issues. The MOSFET device of this application uses a semi-insulating region instead of the traditional channel, avoiding the interface problems present in the channel region. In the off state, the semi-insulating region protects the corner of the PN junction formed by the P-type base region and the drift region, avoiding electric field concentration and reducing the risk of device failure. When the gate is excited, the resistance of the semi-insulating region drops sharply, turning it into a conducting state. Electrons can flow throughout the entire semi-insulating region, no longer confined to the substrate surface channel, thus avoiding the low channel mobility problem and greatly reducing device failure risk. This invention improves device reliability and extends lifespan by reducing on-resistance. Furthermore, by introducing a light-emitting layer, it achieves channel formation through an internal photogenerated carrier effect, replacing the traditional external gate electric field effect. When the device is turned on, a laser is emitted by energizing the light-emitting layer. The laser passes through a transparent insulating layer and irradiates the semi-insulated region of the channel. When the laser excitation energy exceeds the bandgap, electrons are directly excited from the valence band to the conduction band, instantly generating a large number of photogenerated carriers—the photoconductive effect. This instantaneous change in channel conductivity by photogenerated carriers bypasses the speed limitation of gate capacitance charging and discharging in a physical principle. Simultaneously, this invention eliminates the need for electrically controlled channel formation. By replacing the thin gate oxide layer with a transparent insulating layer, the gate oxide layer does not need to bear a large voltage, avoiding the gate oxide interface stress problem. Therefore, the MOSFET device of this application primarily solves the problems of limited switching speed, low reliability, and easy failure of traditional MOSFET devices due to electric fields. By employing the photoconductive effect as the dominant turn-on mechanism, it achieves ultra-high-speed switching characteristics and enhances the long-term reliability of the device.

[0077] Exemplary embodiments of the method for fabricating a MOSFET device according to embodiments of this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0078] First, proceed to step S1: as follows Figure 4 As shown, a substrate is provided, which includes a stacked substrate 10 and an epitaxial layer 20.

[0079] In some optional embodiments, this application further includes the step of forming the above-described substrate: providing a substrate 10 made of silicon carbide; and forming an epitaxial layer 20 on the substrate 10 using an epitaxial process. Specifically, the material of the epitaxial layer 20 may include silicon carbide.

[0080] In the above optional embodiments, the substrate 10 and the epitaxial layer 20 in the MOSFET device may have the same doping type. For example, the substrate 10 is a heavily doped N+ type silicon carbide material, the epitaxial layer 20 is a lightly doped N- type silicon carbide material, and the epitaxial layer 20 includes a drift region in which a doped region 30 is formed.

[0081] After providing a substrate including substrate 10 and epitaxial layer 20, step S2 is performed: as follows Figure 5 , Figure 6 and Figure 7 As shown, ion implantation is performed on both sides of a portion of the epitaxial layer 20 to form doped regions 30. The doped regions 30 include a first doped region 301 and a second doped region 302 spaced apart along a direction parallel to the substrate surface.

[0082] In some alternative embodiments, the step of forming the doped region 30 includes: as follows Figures 5 to 7 As shown, a second implantation region 320 is formed by ion implantation on one side of a portion of the epitaxial layer 20, a first implantation region 310 is formed by ion implantation on one side of a portion of the epitaxial layer 20, and a third implantation region 330 is formed by ion implantation on one side of a portion of the first implantation region 310. The third implantation region 330 is in contact with the surface of the second implantation region 320.

[0083] Specifically, the doping type of the first implantation region can be P-type doping, and the doping type of the second implantation region can be N-type doping. The N-type doping element can be any one of the pentavalent elements, including nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of the trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). The embodiments of this application do not impose specific limitations.

[0084] After forming the doped region 30 as described above, step S3 is performed: as follows Figure 8 As shown, ion implantation is performed on one side of the epitaxial layer 20 to form a semi-insulating region 40. The semi-insulating region 40 is in contact with the first doped region 301 and the second doped region 302, respectively. A transparent insulating layer 50 is deposited on the semi-insulating region 40, and the transparent insulating layer 50 is in contact with the semi-insulating region 40.

[0085] Specifically, the implanted element in the semi-insulating region can be one of vanadium, chromium, iron, and titanium. Vanadium, chromium, iron, and titanium can compensate for the N-type and P-type regions, achieving semi-insulation in the channel region. After ion implantation, thermal annealing is required to complete the activation of the implanted layer and the formation and etching of the active region layer. The transparent insulating layer is grown on top of the semi-insulating region by methods such as atomic layer deposition or chemical vapor deposition. Its material includes one or more combinations of silicon dioxide, aluminum oxide, and magnesium fluoride.

[0086] The above fabrication method forms a semi-insulating region 40 and a transparent insulating layer 50. The side of the semi-insulating region 40 facing away from the substrate is in contact with the transparent insulating layer 50. When a laser beam passes through the transparent insulating layer 50 and irradiates the semi-insulating region 40, the photon energy is greater than the bandgap of SiC, rapidly exciting electrons to transition from the valence band to the conduction band, forming a conductive channel and enabling rapid device conduction. Due to the special design of the semi-insulating region 40, not only is the turn-off speed of the device optimized, but the PN junction corner formed by the P-type base region and the N-drift region is also protected from the effects of electric field concentration, enhancing the long-term stability and reliability of the device. Replacing the gate oxide layer with the transparent insulating layer 50 increases the thickness of the transparent insulating layer, thereby reducing the electric field strength and avoiding the problem of traditional thin gate oxide layers being prone to breakdown due to high electric field strength.

[0087] After forming the semi-insulating region 40 and the transparent insulating layer 50 as described above, step S4 is performed: as follows Figure 9 As shown, a light-emitting layer 60 is formed on the transparent insulating layer 50.

[0088] For example, a high-quality, high-efficiency light-emitting layer 60 is generated by using metal-organic chemical vapor deposition or atomic layer deposition processes. The material of the light-emitting layer can be composed of multiple layers of gallium nitride or indium phosphide. Taking gallium nitride as an example, the material of the gallium nitride light-emitting layer is at least one or more combinations of p-GaN, AlGaN, i-GaN, AlGaN, and n-GaN.

[0089] Specifically, taking gallium nitride (GaN) as an example, by energizing the GaN emissive layer, it emits a 355nm wavelength laser. This laser light passes through a transparent insulating layer and irradiates the semi-insulating silicon carbide in the channel region. According to Planck's relation, this laser can excite the band gap to reach 3.5eV, which is greater than the 3.2eV band gap of silicon carbide. This directly excites electrons from the valence band to the conduction band, instantly generating a large number of photogenerated carriers. The response speed reaches the nanosecond (ns) or even picosecond (ps) level, which is the photoconductive mechanism. The resistivity of this region decreases sharply, thereby achieving an electrical connection between the N+ region and the drift layer, i.e., the device enters the conduction state.

[0090] In some alternative embodiments, after the step of forming the light-emitting layer 60 described above, such as Figure 10 and Figure 11 As shown, a metal material is deposited above the doped region 30, and the portion where the metal material contacts the doped region forms a front ohmic contact 110. A gate electrode 80 is formed above the light-emitting layer 60. Then, an interlayer dielectric layer 70 is formed above the gate electrode 80 and the partially doped region 30 to ensure electrical isolation. Next, a source electrode 90 is fabricated above the interlayer dielectric layer 70 and the ohmic contact. Through metal deposition and patterning processes, the source electrode and the N+ region are electrically connected, thus making the current path inside the device clearer and more efficient. Finally, a drain electrode 100 is deposited under the substrate.

[0091] For example, the metal material forming the ohmic contact 110 and the source electrode 90 is selected from one or more of nickel (Ni), titanium (Ti), platinum (Pt), gold (Au), and tungsten (Wu), but is not limited to the above types, and this application does not make specific limitations; the interlayer dielectric layer 70 is used to isolate the gate and the subsequent metal layer, and the material can be selected from silicon oxide film (SiOF), tetraethoxysilane (TEOS), mesoporous silica-based quartz (MSQ), boron phosphosilicate glass (BPSG), or a combination thereof.

[0092] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0093] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A MOSFET device, characterized in that, include: The substrate includes a stacked substrate and an epitaxial layer; The doped region is located in the epitaxial layer. The doped region is a region formed by ion implantation on one side surface of a portion of the epitaxial layer, and the doped region includes a first doped region and a second doped region spaced apart along a direction parallel to the surface of the substrate. A semi-insulating region is located in the epitaxial layer. The semi-insulating region is a region formed by ion implantation on one side surface of the epitaxial layer, and the two sides of the semi-insulating region are in contact with the first doped region and the second doped region, respectively. A transparent insulating layer is located on the surface of the substrate, and the transparent insulating layer is in contact with the semi-insulating region; A light-emitting layer is located directly above the transparent insulating layer, and the light-emitting layer and the transparent insulating layer are in contact.

2. The MOSFET device according to claim 1, characterized in that, The doped ions in the semi-insulating region include one of the elements vanadium, chromium, iron, and titanium.

3. The MOSFET device according to claim 1, characterized in that, The material of the light-emitting layer includes gallium nitride or indium phosphide, and the material of the transparent insulating layer includes one or more combinations of silicon dioxide, aluminum oxide, and magnesium fluoride.

4. The MOSFET device according to claim 1, characterized in that, Both the first doped region and the second doped region include a first implantation region and a second implantation region. The first implantation region is a region formed by ion implantation on one side surface of a portion of the epitaxial layer, and the second implantation region is a region formed by ion implantation on one side surface of a portion of the first implantation region. The MOSFET device also includes a third implantation region, which is a region formed by ion implantation on the other side surface of a portion of the first implantation region. The surfaces of the third implantation region and the second implantation region are in contact.

5. The MOSFET device according to claim 4, characterized in that: The two sides of the semi-insulating region are respectively in contact with the third implantation region in the first doped region and the third implantation region in the second doped region, and the bottom of part of the semi-insulating region is respectively in contact with the first implantation region in the first doped region and the first implantation region in the second doped region; Alternatively, one side of the semi-insulating region may be in contact with the first implantation region and the third implantation region in the first doped region, and the other side of the semi-insulating region may be in contact with the first implantation region and the third implantation region in the second doped region.

6. The MOSFET device according to claim 5, characterized in that: The depth of the semi-insulating region is less than or equal to the depth of the first injection region.

7. The MOSFET device according to any one of claims 1 to 6, characterized in that, In the direction from the first doped region to the second doped region, the transparent insulating layer and the light-emitting layer have the same width, the width of the semi-insulating region is smaller than the width of the transparent insulating layer and the light-emitting layer, and the light-emitting layer is located on the side of the semi-insulating region away from the substrate.

8. The MOSFET device according to any one of claims 1 to 6, characterized in that, The light-emitting layer is located directly above the transparent insulating layer or on the side of the transparent insulating layer.

9. A method for fabricating a MOSFET device, characterized in that, The method for fabricating the MOSFET device according to any one of claims 1 to 8 comprises the following steps: A substrate is provided, the substrate comprising a stacked substrate and an epitaxial layer; Ion implantation is performed on one side surface of a portion of the epitaxial layer to form the doped region, and the doped region includes a first doped region and a second doped region spaced apart along a direction parallel to the substrate surface; A semi-insulating region and a transparent insulating layer are formed. Ion implantation is performed on one side surface of the epitaxial layer to form a semi-insulating region. The semi-insulating region is located between the first doped region and the second doped region. A transparent insulating layer is deposited on top of the semi-insulating region, and the transparent insulating layer is in contact with the semi-insulating region. A light-emitting layer is deposited on top of the transparent insulating layer, and the light-emitting layer is in contact with the transparent insulating layer.

10. The preparation method according to claim 9, characterized in that, The steps for forming the doped and semi-insulating regions include: Ion implantation is performed on one side surface of a portion of the epitaxial layer to form a first implantation region, ion implantation is performed on one side surface of a portion of the first implantation region to form a second implantation region, and ion implantation is performed on the other side of a portion of the first implantation region to form a third implantation region, wherein the third implantation region is in contact with the surface of the second implantation region; Ion implantation and annealing are performed on one side of the epitaxial layer to form a semi-insulating region. The two sides of the semi-insulating region are in contact with the third implantation region in the first doped region and the third implantation region in the second doped region, respectively. The bottom of part of the semi-insulating region is in contact with the first implantation region in the first doped region and the first implantation region in the second doped region, respectively.

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