Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a base which comprises a substrate and an epitaxial layer, and the epitaxial layer is provided with a groove extending to the interior along a first surface; the gate structure part is located in the groove; the two source region structures are located in the epitaxial layer at intervals and located on the two sides of the gate structure in the first direction, each source region structure comprises a first doped region and a second doped region, the first doped region and the second doped region are regions formed by ion implantation on the surface of the epitaxial layer, the second doped region is located in the first doped region, and the first doped region is located in the epitaxial layer; the second doped region comprises a first part and a second part, the second part is located on the side, away from the substrate, of the first part, the first part and the second part make contact with the gate structure on the same side in the first direction, and in the first direction, the width of the first part is smaller than that of the second part; the problem of poor performance of a semiconductor device in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] In the field of silicon carbide (SiC)-based MOSFET technology, the traditional planar or trench structure has a small current path, which limits the lateral current diffusion capability, resulting in high on-resistance and unsatisfactory heat dissipation. Especially under high-frequency and high-voltage operating conditions, this design defect exacerbates the JFET effect, causing additional energy loss and potentially reducing the device's UIS capability, thus affecting its application in fields such as new energy vehicles and photovoltaic inverters.

[0003] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] The main objective of this application is to provide a semiconductor device and its fabrication method to solve the problem of poor performance of semiconductor devices in the prior art.

[0005] To achieve the above objectives, according to one aspect of this application, a semiconductor device is provided, comprising: a substrate including a base and an epitaxial layer, the epitaxial layer having a groove extending into the interior along a first surface, the first surface being a surface of the epitaxial layer facing away from the base; a gate structure, a portion of the gate structure being located in the groove; two source region structures, spaced apart in the epitaxial layer and located on opposite sides of the gate structure in a first direction, each source region structure including a first doped region and a second doped region, the first doped region and the second doped region being regions formed by ion implantation on the surface of the epitaxial layer, the second doped region being located in the first doped region, the second doped region including a first portion and a second portion, the second portion being located on the side of the first portion facing away from the base, the first portion and the second portion being in contact with the gate structure on the same side in the first direction, the width of the first portion being smaller than the width of the second portion in the first direction, the first doped region and the second doped region having different doping types, the first direction being perpendicular to the thickness direction of the semiconductor device; a source electrode located on the side of the gate structure and the source region structures facing away from the base; and a drain electrode located on the side of the base facing away from the epitaxial layer.

[0006] Optionally, the second part includes a first sub-doped region and a second sub-doped region, and the first part is a third sub-doped region, wherein the second sub-doped region is located on the side of the first sub-doped region away from the substrate, and the doping concentration of the third sub-doped region is greater than the doping concentration of the second sub-doped region, and the doping concentration of the second sub-doped region is greater than the doping concentration of the first sub-doped region.

[0007] Optionally, the semiconductor device further includes an insulating layer that covers a portion of the third sub-doped region in the gate structure and the epitaxial layer, wherein the projections of the second sub-doped region and the first sub-doped region on the surface of the substrate lie within the projection of the insulating layer on the surface of the substrate.

[0008] Optionally, the sum of the depths of the first sub-doped region and the second sub-doped region is greater than twice the depth of the third sub-doped region.

[0009] Optionally, the semiconductor device further includes an ohmic contact metal located on both sides of the insulating layer in a first direction and between the source region structure and the source electrode, the ohmic contact metal being in contact with the third sub-doped region.

[0010] Optionally, the gate structure includes a gate oxide layer, a polysilicon gate, and a gate electrode, wherein the gate oxide layer and the polysilicon gate are located in the groove, the gate oxide layer covers the sidewalls and bottom of the polysilicon gate, and the gate electrode is located on the side of the polysilicon gate opposite to the gate oxide layer.

[0011] According to another aspect of this application, a method for fabricating a semiconductor device is provided. The method includes: providing a substrate, the substrate including a substrate and an epitaxial layer, the epitaxial layer having a groove extending inward along a first surface, the first surface being a surface of the epitaxial layer facing away from the substrate; forming two spaced source region structures in the epitaxial layer, the source region structures including a first doped region and a second doped region, the first doped region and the second doped region being regions formed by ion implantation on the surface of the epitaxial layer, the second doped region being located within the first doped region, the second doped region including a first portion and a second portion, the second portion being located on the side of the first portion facing away from the substrate, the width of the first portion being smaller than the width of the second portion in a first direction, the first doped region and the second doped region having different doping types, the first direction being perpendicular to the thickness direction of the semiconductor device; forming a partial gate structure in the groove, the source region structures located on both sides of the gate structure in the first direction, the first portion and the second portion being in contact with the gate structure on the same side in the first direction; forming a source electrode on the side of the gate structure and the source region structures facing away from the substrate; and forming a drain electrode on the side of the substrate facing away from the epitaxial layer.

[0012] Optionally, the step of forming a source region structure in the epitaxial layer includes: performing ion implantation in the epitaxial layer to form a first doped region; performing ion implantation in a portion of the first doped region to form a first sub-doped region; performing ion implantation in a portion of the first sub-doped region to form a second sub-doped region; performing ion implantation in a portion of the second sub-doped region and a portion of the first doped region to form a third sub-doped region; and the remaining first sub-doped region, the remaining second sub-doped region, and the third sub-doped region constitute the second doped region.

[0013] Optionally, the step of forming the gate structure includes: etching the groove in the epitaxial layer, the groove being located between the two source regions; depositing a gate oxide material in the groove to form the gate oxide layer at the bottom and sidewalls of the groove; depositing a polysilicon material on the gate oxide layer to fill the groove and form the polysilicon gate; and depositing a gate electrode material on the polysilicon gate to form a gate electrode.

[0014] Optionally, the step of forming the source electrode includes: depositing a material of an insulating layer on the outer periphery of the gate structure to form an insulating layer covering the gate structure and a portion of the second doped region; depositing a material of an ohmic contact metal on the insulating layer and the epitaxial layer, and removing the material of the ohmic contact metal located on the insulating layer to form the ohmic contact metal located on the epitaxial layer; and depositing a material of the source electrode on the insulating layer and the ohmic contact metal to form the source electrode.

[0015] Using the technical solution of this application, a semiconductor device includes a substrate, an epitaxial layer, a gate structure, a source region structure, a source electrode, and a drain electrode. The second doped region in the source region structure is divided into a first part and a second part. The width of the second part is set to be greater than the width of the first part. This increases the contact area between the second doped region (composed of the first and second parts) and the first doped region, effectively increasing the contact area of ​​the channel generated at the first doped region corresponding to the gate oxide layer in the gate structure. This widens the current path when the semiconductor device is turned on. By lengthening the lateral dimension of the first part, the "entry point" for current to flow from the second part through the channel to the epitaxial layer is wider. This effectively increases the side area in contact with the channel without significantly increasing the lateral dimension of the cell (i.e., without reducing chip density). This increases the total channel width per unit cell area, thereby helping to reduce the specific on-resistance. Furthermore, the increased total channel width allows for a more uniform current distribution when the device is turned on, improving device reliability and performance, thus solving the problem of poor semiconductor device performance. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic cross-sectional view of a semiconductor device according to an embodiment of this application is shown;

[0018] Figure 2 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0019] Figure 3 It indicates Figure 2 In the preparation method, a schematic diagram of the cross-sectional structure of the substrate after the substrate is provided;

[0020] Figure 4 It indicates that in Figure 3 A schematic diagram of the cross-sectional structure of the substrate after the formation of the first doped region in the structure;

[0021] Figure 5 It indicates that in Figure 4 A schematic diagram of the cross-sectional structure of the substrate after the formation of the second doped region in the structure;

[0022] Figure 6 It indicates that in Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the groove is formed in the structure;

[0023] Figure 7 It indicates that in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after the gate oxide layer and polysilicon gate are formed in the groove;

[0024] Figure 8 It indicates that in Figure 7 A schematic diagram of the cross-sectional structure of the substrate after the gate electrode and insulating layer are formed in the structure.

[0025] The above figures include the following reference numerals:

[0026] 10. Substrate; 11. Substrate; 12. Epitaxial layer; 20. Gate structure; 21. Gate oxide layer; 22. Polysilicon gate; 23. Gate electrode; 30. Source region structure; 31. First doped region; 32. Second doped region; 321. First sub-doped region; 322. Second sub-doped region; 323. Third sub-doped region; 40. Source electrode; 50. Drain electrode; 60. Insulating layer; 70. Ohmic contact metal. Detailed Implementation

[0027] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0028] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0031] As described in the background section, in conventional planar or trench structures in the prior art, the current path is small, which limits the lateral diffusion capability of the current, resulting in high on-resistance and unsatisfactory heat dissipation. Especially under high-frequency and high-voltage operating conditions, this design defect exacerbates the JFET effect, causing additional energy loss. To address the problem of poor performance of semiconductor devices in the prior art, embodiments of this application provide a semiconductor device and its fabrication method.

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0033] One embodiment of this application provides a semiconductor device, such as... Figure 1As shown, it includes: a substrate 10, comprising a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 having a groove extending along a first surface into the interior, the first surface being the side surface of the epitaxial layer 12 facing away from the substrate 11; a gate structure 20, a portion of the gate structure 20 being located in the groove; and two source regions 30, spaced apart in the epitaxial layer 12 and located on opposite sides of the gate structure 20 in a first direction X, the source regions 30 including a first doped region 31 and a second doped region 32, the first doped region 31 and the second doped region 32 being regions formed by ion implantation on the surface of the epitaxial layer 12, the second doped region 32 being located on the first doped region 11. In the first doped region 31, the second doped region 32 includes a first part and a second part. The second part is located on the side of the first part away from the substrate 11. The first part and the second part are in contact with the gate structure 20 on the same side in the first direction X. In the first direction X, the width of the first part is smaller than the width of the second part. The doping types of the first doped region 31 and the second doped region 32 are different. The first direction X is perpendicular to the thickness direction of the semiconductor device. The source electrode 40 is located on the side of the gate structure 20 and the source region structure 30 away from the substrate 10. The drain electrode 50 is located on the side of the substrate 11 away from the epitaxial layer 12.

[0034] By dividing the second doped region in the source region structure of a semiconductor device into a first part and a second part, with the width of the second part being greater than that of the first part, the contact area between the second doped region (composed of the first and second parts) and the first doped region is increased. This is equivalent to increasing the contact area of ​​the channel generated at the first doped region corresponding to the gate oxide layer in the gate structure, thus widening the current path when the device is turned on. By lengthening the lateral dimension of the first part, the "entry point" for current to flow from the second part through the channel to the epitaxial layer is wider. This effectively increases the side area in contact with the channel without significantly increasing the lateral dimension of the semiconductor device (i.e., without reducing chip density). This increases the total channel width per unit semiconductor device, thereby helping to reduce the specific on-resistance. Furthermore, the increased total channel width also allows for a more uniform current distribution when the device is turned on, improving device reliability and thus enhancing device performance, thereby solving the problem of poor semiconductor device performance.

[0035] In the above embodiments, the substrate can be a silicon carbide substrate with a resistivity of 0.02 ± 20% Ωcm, and the epitaxial layer, as the drift region, serves as the structural layer responsible for the main breakdown, with a doping concentration of 1E15~1E16 cm⁻¹. -3 The thickness can be adjusted according to product requirements. For example, the thickness of the epitaxial layer of a 1200V MOS can be 9~11μm, and the thickness of the epitaxial layer of a 650V MOS can be 5~7μm.

[0036] In the above embodiments, the implanted element in the first doped region can be Al, and its doping concentration can be 1E17±50%cm⁻¹.-3 The thickness is 0.7~0.9μm. The first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping. For example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element can be any one of pentavalent elements including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements including boron (B), aluminum (Al), and gallium (Ga). This application does not make specific limitations.

[0037] In the above embodiments, the source electrode can be made of any one or more of titanium, copper, and nickel, and is used to provide the source signal required for device operation. The source electrode can also be made of any one or more of titanium, copper, and nickel, and the drain electrode is used to collect the current flowing from the substrate to the drain region, forming a drain current path.

[0038] In some alternative implementations, such as Figure 1 As shown, the second part includes a first sub-doped region 321 and a second sub-doped region 322, and the first part is a third sub-doped region 323. The second sub-doped region 322 is located on the side of the first sub-doped region 321 facing away from the substrate 11. The doping concentration of the third sub-doped region 323 is greater than that of the second sub-doped region 322, and the doping concentration of the second sub-doped region 322 is greater than that of the first sub-doped region 321. The higher doping concentration of the third sub-doped region 323 allows for better contact with the source electrode, reducing resistance. The lower doping concentrations of the first and second sub-doped regions 321, especially the first sub-doped region 321, make it easier to completely deplete under the same electric field. This avoids the drastic resistance changes caused by the sudden depletion of highly doped regions in traditional structures, resulting in smoother current transport. Especially in high-voltage applications, this effectively reduces saturation on-resistance. A first sub-doped region 321 with a low doping concentration is set below the third sub-doped region 323. This avoids the risk that the third sub-doped region 323 may be depleted prematurely under a high electric field, cutting off the current path and causing a nonlinear increase in resistance.

[0039] When avalanche breakdown occurs in a device, the electron-hole pairs generated by impact ionization need to be effectively managed. In this application, the three sublayers in the second doped region are distributed in a "T-shape." This structure allows for a better distribution of the depletion region formed by the first doped region and the drift region (epitaxy layer), and the low-doped first sub-doped region helps avalanche breakdown occur more uniformly within the device (drift region), rather than concentrating in vulnerable areas such as the gate oxide interface. Bulk avalanche is more uniform and has a weaker thermal concentration effect than surface avalanche, allowing the device to withstand higher energy and enhancing its bulk avalanche resistance. Furthermore, the current path is extended and optimized due to the "T-shaped" structure of the second doped region, preventing excessive heat concentration in a small area during avalanche and reducing the risk of localized hotspots.

[0040] In the above optional embodiments, the doping concentration of the third sub-doped region can be 1E20cm⁻¹. -3 With a doping concentration of ±20% and a depth of 0.1~0.2μm, the lateral expansion width compared to the first and second sub-doped regions is also 0.1~0.2μm. This high doping concentration ensures a low-resistance connection with the metal source. The "T-shaped" structure increases the lateral length and contact area, significantly increasing the perimeter of the channel and providing a wider "entry point" for current. Increasing the lateral length also increases the effective channel width (Weff): in semiconductor devices, the total channel width determines the channel resistance, which in turn affects the on-resistance. The "T-shaped" structure also effectively increases the depth of the source region vertically. By lengthening the lateral dimension of the third sub-doped region, the side area in contact with the channel can be effectively increased without significantly increasing the lateral dimension of the cell (i.e., without reducing device density). This can be understood as a wider "entry point" for current to flow from the second doped region through the channel to the drift region. This directly leads to an increase in the total channel width per unit device cell area, thus helping to reduce the specific on-resistance. The doping concentration of the second sub-doped region can be 1E18~3E18 cm⁻¹ -3 The depth can be 0.15~0.3μm. The second sub-doped region and the first doped region together form a conductive channel on the gate oxide sidewall, which is the main path for current vertical flow. Serving as a transition between the highly doped third sub-doped region and the lightly doped first sub-doped region, it can optimize current spread and reduce contact resistance. The doping concentration of the first sub-doped region can be 3E17~6E17 cm⁻¹. -3The depth of the second doped region can be 0.25~0.4μm. Low doping makes this region easier to deplete, which helps improve the electric field inside the cell and enhances the breakdown voltage potential. The second doped region increases the contact area between the source region and the channel, reduces the JFET effect, and lowers the on-resistance by 15%~20%. At the same time, it significantly improves the UIS (non-clamped inductive switch) capability (UIS capability is a measure of the device's ability to absorb energy during avalanche breakdown, i.e., avalanche resistance). Simply extending the third sub-doped region laterally can suppress parasitic transistor conduction (the structure composed of the second doped region, the first doped region, and the epitaxial layer) without increasing the source region structure area, reducing the device's UIS capability and affecting device reliability.

[0041] In some alternative implementations, such as Figure 1 As shown, the semiconductor device also includes an insulating layer 60, which covers a portion of the third sub-doped region 323 in the gate structure 20 and the epitaxial layer 12. The projections of the second sub-doped region 322 and the first sub-doped region 321 onto the surface of the substrate 11 lie within the projection of the insulating layer 60 onto the surface of the substrate 11. The insulating layer 60 isolates the gate structure 20 from the subsequently formed source electrode 40, preventing electrical short circuits. Using this layer also effectively controls the parasitic capacitance of the device, playing a crucial role in improving the switching speed and reducing switching losses. Typically, SiO2 or other dielectric materials, such as silicon nitride (Si3N4), can be used. These materials possess good dielectric constants and thermal stability, enabling them to withstand the high-temperature environment of SiC device operation while providing the necessary electrical insulation properties. Their thickness can range from 600 to 1000 nm. The relative positional relationship between the insulating layer 60, the second sub-doped region 322, and the first sub-doped region 321 ensures that the lateral expansion of the third sub-doped region 323 is large enough, so that the contact area between the second doped region 32 and the channel is large enough, without increasing the source region size.

[0042] In some alternative implementations, the sum of the depths of the first and second sub-doped regions is greater than twice the depth of the third sub-doped region. By ensuring that the depths of the first and second sub-doped regions significantly exceed the depth of the third sub-doped region, the vertical path length of the contact between the source region and the channel can be increased. This means that when the device is in the on-state, the vertical current conduction path is longer and more continuous, which is beneficial for uniform current distribution, avoids the generation of local hot spots, and improves the long-term stability and reliability of the device. The depth of the first sub-doped region can be 0.25~0.4μm, the depth of the second sub-doped region can be 0.15~0.3μm, and the depth of the third sub-doped region can be 0.1~0.2μm.

[0043] In some alternative implementations, such as Figure 1As shown, the semiconductor device also includes an ohmic contact metal 70, which is located on both sides of the insulating layer 60 in the first direction X, and between the source region structure 30 and the source electrode 40. The ohmic contact metal 70 is in contact with the third sub-doped region 323. The direct contact between the ohmic contact metal 70 and the third sub-doped region 323 can significantly reduce the contact resistance between the source and the third sub-doped region 323. This is because the selection and design of the ohmic contact metal 70, combined with the highly doped third sub-doped region 323, can form a low-impedance ohmic contact, thereby making the current transmission from the source region to the source electrode smoother and reducing the on-resistance of the entire device.

[0044] In some alternative implementations, such as Figure 1 As shown, the gate structure 20 includes a gate oxide layer 21, a polysilicon gate 22, and a gate electrode 23. The gate oxide layer 21 and the polysilicon gate 22 are located in a recess. The gate oxide layer 21 covers the sidewalls and bottom of the polysilicon gate 22, and the gate electrode 23 is located on the side of the polysilicon gate 22 facing away from the gate oxide layer 21. The gate oxide layer 21, located between the polysilicon gate 22 and the recess interface of the epitaxial layer 12, can provide electrical isolation and can be made of silicon dioxide. The gate electrode 23, located on the side of the polysilicon gate 22 facing away from the gate oxide layer 21, can be made of a metal material such as aluminum, copper, molybdenum, or gold. The function of the gate electrode 23 is to receive external drive signals, thereby controlling the voltage of the polysilicon gate 22 and determining whether the channel is open or closed.

[0045] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. For example... Figure 2 As shown, the method includes the following steps:

[0046] Step S1, as follows Figure 3 As shown, a substrate 10 is provided, the substrate 10 including a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 having a groove extending into the interior along a first surface, the first surface being the side surface of the epitaxial layer 12 facing away from the substrate 11.

[0047] Specifically, the substrate can be a silicon carbide substrate with a resistivity of 0.02 ± 20% Ωcm, and the epitaxial layer, as the drift region, serves as the structural layer responsible for the main breakdown, with a doping concentration of 1E15~1E16cm. -3 The thickness can be adjusted according to product requirements. For example, the thickness of the epitaxial layer of a 1200V MOS can be 9~11μm, and the thickness of the epitaxial layer of a 650V MOS can be 5~7μm.

[0048] Step S2, as follows Figure 4 and Figure 5As shown, two spaced source region structures 30 are formed in the epitaxial layer 12. The source region structure 30 includes a first doped region 31 and a second doped region 32. The first doped region 31 and the second doped region 32 are regions formed by ion implantation on the surface of the epitaxial layer 12. The second doped region 32 is located in the first doped region 31. The second doped region 32 includes a first part and a second part. The second part is located on the side of the first part away from the substrate 11. In the first direction, the width of the first part is smaller than the width of the second part. The doping types of the first doped region 31 and the second doped region 32 are different. The first direction is perpendicular to the thickness direction of the semiconductor device.

[0049] Specifically, the implanted element in the first doped region can be Al, and its doping concentration can be 1E17±50%cm³. -3 The thickness is 0.7~0.9μm; the second part includes a first sub-doped region 321 and a second sub-doped region 322, and the first part is a third sub-doped region 323. The doping concentration of the third sub-doped region can be 1E20cm. -3 ±20%, with a depth of 0.1~0.2μm, and a lateral expansion width of 0.1~0.2μm compared to the first and second sub-doped regions; the doping concentration of the second sub-doped region can be 1E18~3E18cm. -3 The depth can be 0.15~0.3μm; the doping concentration of the first sub-doped region can be 3E17~6E17cm. -3 The depth can be 0.25~0.4μm.

[0050] Step S3, as follows Figures 6 to 8 As shown, a partial gate structure 20 is formed in the groove, and the source region structure 30 is located on both sides of the gate structure 20 in the first direction X. The first part and the second part are in contact with the gate structure 20 on the same side in the first direction X.

[0051] Specifically, the gate structure 20 includes a gate oxide layer 21, a polysilicon gate 22, and a gate electrode 23. The gate oxide layer 21 can be made of silicon dioxide, and the gate electrode 23 can be made of aluminum, copper, molybdenum, etc.

[0052] Step S4, as follows Figure 1 As shown, a source electrode 40 is formed on the side of the gate structure 20 and the source region structure 30 that is away from the substrate 10.

[0053] Step S5, as follows Figure 1 As shown, a drain electrode 50 is formed on the side of the substrate 11 opposite to the epitaxial layer 12;

[0054] Specifically, the source electrode can be made of any one or more of titanium, copper, and nickel, and is used to provide the source signal required for device operation. The drain electrode can also be made of any one or more of titanium, copper, and nickel, and is used to collect the current flowing from the substrate to the drain region, forming a drain current path.

[0055] The semiconductor device prepared by the above-described fabrication method in this embodiment has a second doped region in its source region structure divided into a first part and a second part. The width of the second part is set to be greater than the width of the first part. This increases the contact area between the second doped region (composed of the first and second parts) and the first doped region, which is equivalent to increasing the contact area of ​​the channel generated at the first doped region corresponding to the gate oxide layer in the gate structure. This widens the current path of the device cell when it is turned on. By lengthening the lateral dimension of the first part, the "entry point" for current to flow from the second part through the channel to the epitaxial layer is wider. This effectively increases the side area in contact with the channel without significantly increasing the lateral dimension of the cell (i.e., without reducing the chip density). This increases the total channel width per unit cell area, thereby helping to reduce the specific on-resistance. Furthermore, the increased total channel width also makes the current distribution more uniform when the device is turned on, improving the reliability of the device and thus improving its performance. This solves the problem of poor performance of semiconductor devices.

[0056] In the specific implementation process, step S2 above forms the source region structure in the epitaxial layer, which can be achieved through the following steps:

[0057] like Figure 4 As shown, ion implantation is performed in the epitaxial layer 12 to form the first doped region 31; as Figure 5 As shown, ion implantation is performed in a portion of the first doped region 31 to form a first sub-doped region 321, ion implantation is performed in a portion of the first sub-doped region 321 to form a second sub-doped region 322, ion implantation is performed in a portion of the second sub-doped region 322 and a portion of the first doped region 31 to form a third sub-doped region 323, and the remaining first sub-doped region 321, the remaining second sub-doped region 322 and the third sub-doped region 323 constitute the second doped region 32.

[0058] The third sub-doped region formed in the above steps can have a lateral expansion width of 0.1~0.2μm compared to the first and second sub-doped regions. The high doping concentration ensures a low-resistance connection with the metal source. The "T-shaped" structure increases the lateral length and lateral contact area, significantly increasing the contact perimeter with the channel and providing a wider "entry point" for current. Increasing the lateral length also increases the effective channel width (Weff): in semiconductor devices, the total channel width determines the channel resistance, which in turn affects the on-resistance. The "T-shaped" structure is also equivalent to increasing the depth of the source region vertically. By lengthening the lateral dimension of the third sub-doped region, the side area in contact with the channel can be effectively increased without significantly increasing the lateral dimension of the cell (i.e., without reducing device density). This can be understood as a wider "entry point" for current to flow from the second doped region through the channel to the drift region. This directly leads to an increase in the total channel width per unit device cell area, thereby helping to reduce the specific on-resistance. The second sub-doped region, together with the first doped region, forms a conductive channel on the gate oxide sidewall, which is the main path for vertical current flow. As a transition between the highly doped third sub-doped region and the lightly doped first sub-doped region, it optimizes current spread and reduces contact resistance. The low doping of the first sub-doped region makes it easier to deplete, which helps improve the electric field inside the cell and enhances its breakdown voltage potential. The second doped region increases the contact area between the source region and the channel, reduces the JFET effect, lowers the on-resistance by 15%~20%, and significantly improves the UIS capability (UIS (non-clamped inductive switch) capability, which measures the device's ability to absorb energy during avalanche breakdown, i.e., avalanche resistance). Simply extending the third sub-doped region laterally can suppress parasitic transistor conduction (the structure composed of the second doped region, the first doped region, and the epitaxial layer) without increasing the source region structure area, reducing the device's UIS capability and affecting device reliability. The relevant parameters of the above structure are described in step S2 above and will not be repeated.

[0059] The step S3 of this application, which forms the gate structure, can be achieved through the following steps:

[0060] like Figure 6 As shown, a groove is etched in the epitaxial layer 12, and the groove is located between the two source region structures 30; the groove depth can be 1~2μm, and the groove depth-to-width ratio can be 1:1~5:1.

[0061] like Figure 7As shown, a gate oxide layer 21 is deposited in the groove to form a gate oxide layer 21 at the bottom and sidewalls of the groove; a polysilicon material is deposited on the gate oxide layer 21 to fill the groove and form a polysilicon gate 22; the thickness of the gate oxide layer 21 can be 300~800 Å, and the material can be silicon dioxide; the lateral width of the polysilicon gate 22 can be 0.2-1 μm.

[0062] like Figure 8 As shown, material for the gate electrode 23 is deposited on the polysilicon gate 22 to form the gate electrode 23. An insulating material is then deposited to form an insulating layer 60 covering the gate structure 20, so that the gate structure 20 is not connected to the subsequently formed source electrode 40. Figure 1 As shown, after the insulating layer 60 is formed, an ohmic contact metal 70 is formed on the source region structure 30, a gate electrode 23 is formed on the ohmic contact metal 70, and a drain electrode 50 is formed on the back side of the substrate 11, thus completing the fabrication of the semiconductor device.

[0063] like Figure 1 and Figure 8 As shown, the step of forming the source electrode 40 in step S4 above includes:

[0064] Material for an insulating layer 60 is deposited around the gate structure 20, forming an insulating layer 60 covering the gate structure 20 and part of the second doped region 32. The insulating layer 60 isolates the gate structure 20 from the subsequently formed source electrode 40, preventing electrical short circuits. Using this layer also effectively controls the parasitic capacitance of the device, playing a crucial role in improving the device's switching speed and reducing switching losses. Typically, SiO2 or other dielectric materials, such as silicon nitride (Si3N4), can be used, with a thickness of 600~1000 nm.

[0065] Material of ohmic contact metal 70 is deposited on insulating layer 60 and epitaxial layer 12, and material of ohmic contact metal 70 on insulating layer 60 is removed to form ohmic contact metal 70 on epitaxial layer 12; the material of ohmic contact metal 70 can be nickel, titanium or nickel-titanium alloy, which can form ohmic contact with source region structure 30, thereby reducing on-resistance.

[0066] Material for the source electrode 40 is deposited on the insulating layer 60 and the ohmic contact metal 70 to form the source electrode 40. The material of the source electrode 40 can be any one or more of titanium, copper, and nickel. The source electrode 40 is used to provide the source signal required for device operation. Material for the drain electrode 50 can also be deposited on the back side of the substrate 11 to form the drain electrode 50.

[0067] The above deposition process can employ physical vapor deposition, chemical vapor deposition, and atomic layer deposition processes, and this application does not impose any specific limitations.

[0068] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate comprising a substrate and an epitaxial layer, the epitaxial layer having a recess extending to an interior along a first surface, the first surface being a side surface of the epitaxial layer facing away from the substrate; a gate structure, part of the gate structure being located in the recess; two source region structures, spaced apart and located in the epitaxial layer and on two sides of the gate structure in a first direction, the source region structures comprising a first doped region and a second doped region, the first doped region and the second doped region being regions formed by ion implantation on a surface of the epitaxial layer, the second doped region being located in the first doped region, the second doped region comprising a first part and a second part, the second part being located on a side of the first part facing away from the substrate, the first part and the second part being in contact with the gate structure on a same side of the first part and the second part in the first direction, the first part having a width smaller than a width of the second part in the first direction, the first doped region and the second doped region being of different doping types, the first direction being perpendicular to a thickness direction of the semiconductor device; a source electrode located on a side of the gate structure and the source region structures facing away from the substrate; a drain electrode located on a side of the substrate facing away from the epitaxial layer.

2. The semiconductor device according to claim 1, wherein The second part comprises a first sub-doped region and a second sub-doped region, and the first part is a third sub-doped region, wherein the second sub-doped region is located on a side of the first sub-doped region facing away from the substrate, the third sub-doped region has a doping concentration greater than a doping concentration of the second sub-doped region, and the second sub-doped region has a doping concentration greater than a doping concentration of the first sub-doped region.

3. The semiconductor device of claim 2, wherein, The semiconductor device further comprises an insulating layer covering the gate structure and part of the third sub-doped region in the epitaxial layer, and projections of the second sub-doped region and the first sub-doped region on a surface of the substrate are located in a projection of the insulating layer on the surface of the substrate.

4. The semiconductor device of claim 2, wherein A sum of depths of the first sub-doped region and the second sub-doped region is greater than twice a depth of the third sub-doped region.

5. The semiconductor device of claim 3, wherein The semiconductor device further comprises an ohmic contact metal located on two sides of the insulating layer in the first direction and between the source region structures and the source electrode, the ohmic contact metal being in contact with the third sub-doped region.

6. The semiconductor device of claim 1, wherein The gate structure comprises a gate oxide layer, a polysilicon gate, and a gate electrode, wherein the gate oxide layer and the polysilicon gate are located in the recess, the gate oxide layer wrapping a side wall and a bottom of the polysilicon gate, and the gate electrode is located on a side of the polysilicon gate facing away from the gate oxide layer.

7. A method of manufacturing a semiconductor device, characterized by A method for manufacturing the semiconductor device of any one of claims 1 to 6, the method comprising: providing a substrate comprising a substrate and an epitaxial layer, the epitaxial layer having a recess extending to an interior along a first surface, the first surface being a side surface of the epitaxial layer facing away from the substrate; forming two spaced source region structures in the epitaxial layer, the source region structures comprising a first doped region and a second doped region, the first doped region and the second doped region being regions formed by ion implantation on the surface of the epitaxial layer, the second doped region being located in the first doped region, the second doped region comprising a first part and a second part, the second part being located on the side of the first part away from the substrate, in a first direction, the width of the first part being less than the width of the second part, the first doped region and the second doped region being of different doping types, the first direction being perpendicular to the thickness direction of the semiconductor device; forming a partial gate structure in the recess, the source region structures being located on both sides of the gate structure in the first direction, the first part and the second part being in contact with the gate structure on the same side in the first direction; forming a source electrode on the side of the gate structure and the source region structures away from the substrate; forming a drain electrode on the side of the substrate away from the epitaxial layer.

8. The preparation method according to claim 7, characterized in that, The step of forming the source region structures in the epitaxial layer comprises: forming the first doped region by ion implantation in the epitaxial layer; forming a first sub-doped region by ion implantation in part of the first doped region, forming a second sub-doped region by ion implantation in part of the first sub-doped region, and forming a third sub-doped region by ion implantation in part of the second sub-doped region and part of the first doped region, the remaining first sub-doped region, the remaining second sub-doped region, and the third sub-doped region constituting the second doped region.

9. The production method according to claim 8, characterized by, The step of forming the gate structure comprises: etching the recess in the epitaxial layer, the recess being located between the two source region structures; depositing a material of the gate oxide layer in the recess to form the gate oxide layer at the bottom and the sidewall of the recess; depositing a material of polysilicon on the gate oxide layer to fill the recess and form a polysilicon gate; depositing a material of the gate electrode on the polysilicon gate to form the gate electrode.

10. The method of claim 8, wherein, The step of forming the source electrode comprises: depositing a material of the insulating layer on the periphery of the gate structure to form the insulating layer covering the gate structure and part of the second doped region; depositing a material of the ohmic contact metal on the insulating layer and the epitaxial layer, and removing the material of the ohmic contact metal located on the insulating layer to form the ohmic contact metal located on the epitaxial layer; depositing a material of the source electrode on the insulating layer and the ohmic contact metal to form the source electrode.

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