Semiconductor device and manufacturing method thereof
By setting a dielectric-free isolation region below the gate of the MOSFET, the problem of weakened gate control caused by the short-channel effect is solved, the gate's control over the channel is enhanced, and the process cost is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2026-03-31
AI Technical Summary
The short-channel effect weakens the gate's control over the channel depletion region, affecting MOSFET performance. Existing technologies have increased costs by improving gate structures and materials.
A dielectric-free isolation region is formed in the well region below the gate by forming a groove in the substrate and closing its opening. Then, a shallow trench isolation structure and a well region are formed in the substrate, and finally the gate is formed on the substrate.
This reduces the impact of the depletion region on the channel, enhances the gate's control over the device, weakens the short-channel effect, and reduces process costs.
Smart Images
Figure CN121772298A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] As the channel length of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) continues to shorten, a series of effects that were negligible in the long-channel model of MOSFETs have become increasingly significant, even becoming the dominant factors affecting performance. This phenomenon is collectively known as the short-channel effect. The short-channel effect leads to a gradual weakening of the gate's control over the channel depletion region, thereby reducing the control over the source and drain regions. This results in a decrease in threshold voltage, a decrease in subthreshold slope, an increase in leakage current, and the emergence of hot carrier effects. These effects work together to weaken the gate's control capability.
[0003] Existing technologies improve the short-channel effect by employing more advanced gate structures and materials. For example, using gate dielectric layer materials with higher dielectric constants can enhance gate control. However, such improvement methods increase costs. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method, which enhances gate control capability by setting a dielectric-free isolation region in the well region below the gate to reduce the influence of the depletion region on the gate control channel, thereby reducing the short-channel effect.
[0005] To address the aforementioned technical problems, according to a first aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising the following steps:
[0006] A substrate is provided, a groove is formed in the substrate, and the opening of the groove is closed to form a dielectric-free isolation region;
[0007] A shallow trench isolation structure is formed within the substrate, and the dielectric-free isolation region is located between adjacent shallow trench isolation structures;
[0008] The substrate is subjected to trap ion implantation to form a trap region between adjacent shallow trench isolation structures, wherein the dielectric-free isolation region is located within the trap region; and
[0009] A gate is formed on the substrate, and the dielectric-free isolation region is located below the gate.
[0010] Optionally, the cross-section of the groove is narrower at the top and wider at the bottom.
[0011] Optionally, the method of closing the opening of the groove to form a medium-free isolation zone includes:
[0012] An epitaxial layer is formed on the substrate using an epitaxial process, the epitaxial layer covering the substrate and closing the opening of the groove; and
[0013] The epitaxial layer is planarized.
[0014] Optionally, the material of the epitaxial layer is the same as the material of the substrate.
[0015] Optionally, the method for forming the shallow trench isolation structure includes:
[0016] An oxide layer, a nitride layer, and a first patterned photoresist layer are sequentially formed on the substrate;
[0017] Using the first patterned photoresist layer as a mask, shallow trenches are formed by sequentially etching the nitride layer, the oxide layer, and a portion of the substrate thickness.
[0018] The shallow trench is filled with insulating material; and
[0019] Remove the nitrided layer.
[0020] Optionally, trap ion implantation can be performed on the substrate using the oxide layer as a mask.
[0021] Optionally, after trap ion implantation and before forming the gate, the fabrication method further includes removing the oxide layer.
[0022] Optionally, after trap ion implantation and before forming the gate, the fabrication method further includes forming a gate oxide layer on the substrate.
[0023] Optionally, after forming the gate, the fabrication method further includes:
[0024] A first sidewall is formed on the sidewall of the gate;
[0025] Lightly doped ions are implanted using the gate and the first sidewall as a mask to form a lightly doped region in the well region.
[0026] A second sidewall is formed on the sidewall of the gate; and
[0027] Source / drain ion implantation is performed using the gate, the first sidewall, and the second sidewall as masks to form a source / drain region within the trap region.
[0028] Optionally, the distance from the upper interface of the dielectric-free isolation region to the lower surface of the gate or the lower surface of the gate oxide layer is less than half the depth of the source / drain region, or the distance from the upper interface of the dielectric-free isolation region to the lower surface of the gate or the lower surface of the gate oxide layer is less than 6-30 nm.
[0029] To address the aforementioned technical problems, according to a second aspect of the present invention, a semiconductor device is also provided, manufactured using the semiconductor device fabrication method described above, the semiconductor device comprising:
[0030] Substrate;
[0031] The gate is located on the substrate;
[0032] A shallow trench isolation structure is located within the substrate;
[0033] The trap region is located between adjacent shallow trench isolation structures; and
[0034] A dielectric-free isolation region is located within the well region below the gate and is spaced apart from the upper surface of the substrate.
[0035] In summary, the semiconductor device and its fabrication method provided by this invention first provide a substrate, form a trench within the substrate, and close the opening of the trench to form a dielectric-free isolation region. Then, a shallow trench isolation structure is formed within the substrate, with the dielectric-free isolation region located between adjacent shallow trench isolation structures. Next, trap ion implantation is performed on the substrate to form a trap region between adjacent shallow trench isolation structures, with the cavity gap located within the trap region. Finally, a gate is formed on the substrate, with the dielectric-free isolation region located below the gate. This invention reduces the impact of the depletion region on the channel by forming a dielectric-free isolation region within the trap region below the gate, thereby increasing the gate's control over the device and weakening the short-channel effect.
[0036] In addition, since only a dielectric-free isolation region needs to be formed in the substrate before forming the shallow trench isolation structure, and no changes are required to the remaining process steps and device structure, the process cost is reduced compared to the improvement methods using more advanced gate structures and materials in the prior art. Attached Figure Description
[0037] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0038] Figures 2 to 13 This is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0039] Explanation of reference numerals in the attached figures:
[0040] 10-Substrate; 11-Second patterned photoresist layer; 12-Groove; 13-Dielectric-free isolation region; 14-Oxide layer; 15-Nitride layer; 16-First patterned photoresist layer; 17-Shallow trench; 18-Shallow trench isolation structure; 19-Trap region; 20-Gate oxide layer; 21-Gate; 22-First sidewall; 23-Lightly doped region; 24-Second sidewall; 25-Source / drain region. Detailed Implementation
[0041] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0042] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0043] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for fabricating a semiconductor device includes the following steps:
[0044] S1: Provide a substrate, form a groove in the substrate, and close the opening of the groove to form a dielectric-free isolation region;
[0045] S2: A shallow trench isolation structure is formed in the substrate, wherein the dielectric-free isolation region is located between adjacent shallow trench isolation structures;
[0046] S3: Perform trap ion implantation on the substrate to form a trap region between adjacent shallow trench isolation structures, wherein the dielectric-free isolation region is located within the trap region; and
[0047] S4: A gate is formed on the substrate, and the dielectric-free isolation region is located below the gate.
[0048] Figures 2 to 13 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of the present invention. Next, it will be discussed in conjunction with... Figure 1 and Figures 2 to 13 A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.
[0049] In step S1, please refer to Figures 2 to 6 As shown, a substrate 10 is provided, a groove 12 is formed in the substrate 10, and the opening of the groove 12 is closed to form a dielectric-free isolation region 13.
[0050] In this embodiment, the substrate 10 can be made of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is a silicon substrate.
[0051] In one embodiment of the present invention, please refer to Figure 2 As shown, firstly, a photoresist layer is formed on the substrate 10, and the photoresist layer is exposed and developed to form a second patterned photoresist layer 11. The second patterned photoresist layer 11 covers the substrate 10 and exposes the area where a groove is to be formed.
[0052] Next, please refer to Figure 3 As shown, using the second patterned photoresist layer 11 as a mask, a portion of the thickness of the substrate 10 is etched to form a groove 12 within the substrate 10. In one embodiment of the present invention, the cross-section of the groove 12 is narrower at the top and wider at the bottom to facilitate subsequent sealing of the groove 12, thereby forming a dielectric-free isolation region within the substrate 10. In one embodiment, the cross-sectional width of the groove 12 increases sequentially from top to bottom; for example, the cross-section of the groove 12 is trapezoidal. In another embodiment, the cross-sectional width of the groove 12 can increase at intervals from top to bottom; for example, the groove 12 can be divided into two parts, with the upper part having a uniform cross-sectional width and the lower part having a uniform cross-sectional width, but the cross-sectional width of the upper part being smaller than that of the lower part. In another embodiment of the present invention, the cross-sectional width of the groove 12 can also be equal; for example, the cross-section of the groove 12 can be rectangular, as long as it is possible to seal the groove 12. Of course, the cross-section of the groove 12 can also be other shapes known to those skilled in the art.
[0053] Then, please refer to Figure 3 and Figure 4As shown, the second patterned photoresist layer 11 is removed. For example, an ashing process or a wet etching process can be used to remove the second patterned photoresist layer 11.
[0054] After forming the groove 12, the opening of the groove 12 is closed to form a medium-free isolation area 13. First, please refer to... Figure 5 As shown, an epitaxial layer (not labeled) is formed on the substrate 10 using an epitaxial process. This epitaxial layer covers the substrate 10 and seals the opening of the groove 12. Because the opening of the groove 12 is relatively small, the formed epitaxial layer blocks the opening, preventing subsequent epitaxial growth from filling the groove 12, thus forming the dielectric-free isolation region 13. The material of the epitaxial layer can be the same as the material of the substrate 10, for example, both being single-crystal silicon. Alternatively, the material of the epitaxial layer can be different from that of the substrate 10. Since semiconductor devices will be fabricated on this substrate with the dielectric-free isolation region 13, the material of the epitaxial layer can serve as a channel material to meet device requirements; this invention does not limit this. Of course, other methods known to those skilled in the art can also be used to seal the opening of the groove 12, and are not limited to epitaxial processes.
[0055] Then, please refer to Figure 6 As shown, the epitaxial layer is planarized to form a flat surface, for example, by performing chemical mechanical polishing on the epitaxial layer.
[0056] Figure 5 In the subsequent figures, the substrate and the epitaxial layer are not distinguished and are all uniformly identified as 10. The substrate 10 mentioned later includes the substrate provided at the beginning and the epitaxial layer formed on the substrate.
[0057] The shape and position of the dielectric-free isolation region 13 are determined by the shape and position of the groove 12, and the dielectric-free isolation region 13 is in a direction parallel to the substrate 10. Figure 6 The dimension of the horizontal direction shown is determined by the groove 12, while the dielectric-free isolation region 13 is in the direction perpendicular to the substrate 10. Figure 6 The dimension (in the vertical direction shown) is determined by the groove 12 and the dimension of the epitaxial layer filling the groove 12. The shape, size, and specific location of the dielectric-free isolation region 13 can be determined according to actual needs. In one embodiment of the present invention, the upper interface of the dielectric-free isolation region 13 to the upper surface of the substrate 10 ( Figure 6The distance between the upper surface of the substrate 10 (or the subsequently formed lower gate surface or lower gate oxide layer) and the subsequently formed source / drain region depth is less than half of the depth of the source / drain region. Alternatively, the distance between the upper interface of the dielectric-free isolation region 13 and the upper surface of the substrate 10 (or the subsequently formed lower gate surface or lower gate oxide layer) is less than 6 nm to 30 nm. For example, the distance between the upper interface of the dielectric-free isolation region 13 and the lower gate surface or lower gate oxide layer is less than 6 nm, 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm, but it is not limited to these.
[0058] In step S2, please refer to Figure 9 As shown, a shallow trench isolation structure 18 is formed in the substrate 10, and the dielectric-free isolation region 13 is located between adjacent shallow trench isolation structures 18.
[0059] In one embodiment of the present invention, firstly, please refer to... Figure 7 As shown, an oxide layer 14, a nitride layer 15, and a first patterned photoresist layer 16 are sequentially formed on the substrate 10. Exemplarily, the oxide layer 14 is made of silicon oxide, and the nitride layer 15 is made of silicon nitride. The oxide layer 14 and the nitride layer 15 can be formed using any suitable process known to those skilled in the art, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition. A first photoresist layer is formed on the nitride layer 15, and the first photoresist layer is exposed and developed to form the first patterned photoresist layer 16.
[0060] Then, please refer to Figure 8 As shown, using the first patterned photoresist layer 16 as a mask, the nitride layer 15, the oxide layer 14, and a portion of the substrate 10 are sequentially etched to form shallow trenches 17. The dielectric-free isolation region 13 is located between adjacent shallow trenches 17. Then, the first patterned photoresist layer 16 is removed. In this embodiment, the bottom of the shallow trenches 17 is flush with the bottom of the dielectric-free isolation region 13, but this is not a limitation. The bottom of the dielectric-free isolation region 13 may be higher than the bottom of the shallow trenches 17.
[0061] Please refer to Figure 8 and Figure 9 As shown, the shallow trench 17 is filled with an insulating material, which completely fills the trench 17 and covers the nitride layer 15. Then, planarization is performed to expose the nitride layer 15. The insulating material can be silicon oxide. Next, the nitride layer 15 is removed to expose the oxide layer 14, forming a structure as shown. Figure 9 The structure shown.
[0062] In step S3, please refer to Figure 10As shown, trap ion implantation is performed on the substrate 10 to form a trap region 19 between adjacent shallow trench isolation structures 18, and the dielectric-free isolation region 13 is located within the trap region 19.
[0063] The substrate 10 is implanted with trap ions using the oxide layer 14 as a mask. In one embodiment of the present invention, the substrate 10 is a p-type substrate, the trap region 19 is a p-type trap region, and the doping concentration of the trap region 19 is less than the doping concentration of the substrate 10, but it is not limited to this.
[0064] After completing the trap ion implantation to form the trap region 19, the process also includes removing the oxide layer 14. For example, the oxide layer 14 can be removed using a wet etching process.
[0065] In one embodiment of the present invention, the trap ion implantation can be divided into multiple steps of ion implantation. After completing one step of ion implantation with the oxide layer 14 as a mask, the oxide layer 14 can be removed and a new oxide layer can be formed. The next step of ion implantation can be performed with the new oxide layer as a mask. The steps of removing the old oxide layer, forming a new oxide layer and performing trap ion implantation can be repeated until the trap region 19 is formed. Then the last oxide layer formed is removed.
[0066] Next, please continue to refer to... Figure 10 As shown, after removing the oxide layer 14, a gate oxide layer 20 is formed on the substrate 10. In this embodiment, the gate oxide layer 20 is made of silicon oxide and is formed using a thermal oxidation process.
[0067] In step S4, please refer to Figure 11 As shown, a gate 21 is formed on the substrate 10, and the dielectric-free isolation region 13 is located below the gate 21.
[0068] In one embodiment of the present invention, a gate material layer is first formed on the gate oxide layer 20, the gate material layer covering the gate oxide layer 20, and then a third patterned photoresist layer is formed on the gate material layer. Next, the gate material layer is etched to expose the gate oxide layer 20 using the third patterned photoresist layer as a mask, and the remaining gate material layer forms the gate 21. After that, the third patterned photoresist layer is removed.
[0069] The dielectric-free isolation region 13 is located below the gate 21, and its position can be controlled according to the shape of the second patterned photoresist layer 11. The bottom of the dielectric-free isolation region 13 can be flush with the bottom of the well region 19, or it can be higher or lower than the bottom of the well region 19.
[0070] After forming the gate 21, the fabrication method further includes: Please refer to Figure 12 As shown, a first sidewall 22 is formed on the sidewall of the gate 21. The first sidewall 22 can be a single-layer sidewall or a multi-layer sidewall. In one embodiment of the present invention, the first sidewall 22 is a double-layer sidewall. The inner layer sidewall, located in the innermost layer, covers the sidewall and top of the gate 21, and its material can be silicon oxide. The outer layer sidewall, located in the outermost layer, covers the sidewall of the gate 21, specifically the sidewall of the inner layer sidewall, and its material can be silicon nitride.
[0071] For example, firstly, a sidewall material layer, such as an oxide layer and a nitride layer, is deposited on the sidewalls and top of the gate 21 and on the surface of the gate oxide layer 20 using any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. Then, each sidewall material layer is sequentially etched using any suitable sidewall etching process, such as dry etching, to form the first sidewall 22. The remaining oxide layer covers the sidewalls and top of the gate 21, and the remaining nitride layer covers the sidewalls of the gate.
[0072] Please continue to refer to this. Figure 12 As shown, lightly doped ion implantation is performed using the gate 21 and the first sidewall 22 as a mask to form a lightly doped region 23 within the well region 19. In another embodiment of the present invention, after forming the gate 21, lightly doped ion implantation can also be performed directly using the gate 21 as a mask without forming the first sidewall 22. The ions implanted in the lightly doped ion implantation include n-type ions (e.g., P ions, As ions, etc.) or p-type ions (e.g., B ions, Ga ions, etc.). When the substrate 10 is a p-type substrate, the ions implanted in the lightly doped ion implantation are n-type ions.
[0073] Next, please refer to Figure 13 As shown, a second sidewall 24 is formed on the sidewall of the gate 21, and the second sidewall 24 covers the sidewall of the first sidewall 22. The second sidewall 24 can be a single-layer sidewall or a double-layer sidewall. In one embodiment of the present invention, the second sidewall 24 is a double-layer sidewall, with the inner sidewall of the inner layer covering the sidewall of the first sidewall 22, and its material can be silicon oxide, and the outer sidewall of the outer layer covering the sidewall of the inner sidewall, and its material can be silicon nitride.
[0074] Similar to the formation method of the first sidewall 22, firstly, a sidewall material layer, such as an oxide layer and a nitride layer, is deposited on the sidewalls and top of the first sidewall 22 and on the surface of the gate oxide layer 20 using any suitable deposition process, such as atomic layer deposition or chemical vapor deposition. Then, each sidewall material layer is sequentially etched using any suitable sidewall etching process, such as dry etching, to form the second sidewall 24. The remaining oxide layer and the remaining nitride layer cover the sidewalls of the first sidewall 22.
[0075] Then, source / drain ion implantation is performed using the gate 21, the first sidewall 22, and the second sidewall 24 as masks to form a drain region 25 within the well region 19. The ions implanted during source / drain ion implantation include n-type ions (e.g., P ions, As ions, etc.) or p-type ions (e.g., B ions, Ga ions, etc.). When the substrate 10 is a p-type substrate, the ions implanted during source / drain ion implantation are n-type ions.
[0076] After the lightly doped ion implantation described above and / or after the source / drain ion implantation described above, the substrate 10 is subjected to thermal annealing activation treatment to activate the ions in the lightly doped region 23 and the source / drain region 25.
[0077] In one embodiment of the present invention, the distance from the upper interface of the dielectric-free isolation region 13 to the lower surface of the gate 21 or the lower surface of the gate oxide layer 20 is less than half the depth of the source / drain region 25, or the distance from the upper interface of the dielectric-free isolation region 13 to the lower surface of the gate 21 or the lower surface of the gate oxide layer 20 is less than 6 nm to 30 nm, for example, the distance is less than 6 nm, 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, thereby minimizing the impact of the depletion region on the channel and increasing the control of the gate 21 over the device. The cross-sectional dimensions of the dielectric-free isolation region 13 ( Figure 13 The cross-section in the horizontal direction can be larger than the cross-sectional size of the gate 21, or smaller than or equal to the cross-sectional size of the gate 21.
[0078] The dielectric-free isolation region 13 within the well region 19 reduces the impact of the depletion region on the channel, thereby increasing the control of the gate 21 over the device and eliminating the short-channel effect. In one embodiment of the present invention, the cross-section of the dielectric-free isolation region 13 is narrower at the top and wider at the bottom (of course, the cross-section of the dielectric-free isolation region 13 is determined by the cross-section of the groove 12) (for example, the cross-section of the dielectric-free isolation region 13 is trapezoidal). The cross-section of the dielectric-free isolation region 13 is similar to the cross-section of the depletion region (the cross-section of the depletion region is also narrower at the top and wider at the bottom). The presence of the dielectric-free isolation region 13 makes the width of the depletion region narrower (where the depletion region is wide, the dielectric-free isolation region 13 also becomes wider, which is equivalent to occupying the position of the depletion region, making the width of the depletion region narrower), thereby further reducing the impact on the channel and further increasing the control of the gate 21 over the device.
[0079] In addition, since only the dielectric-free isolation region 13 needs to be formed in the substrate 10 before forming the shallow trench isolation structure 18, only two process steps are added: forming the trench 12 and sealing the trench 12. There is no need to change the remaining process steps and device structure. Compared with the improvement methods of using more advanced gate structures and materials in the prior art, the process cost is reduced.
[0080] The method for fabricating a semiconductor device provided in this invention first involves providing a substrate 10, forming a recess 12 within the substrate 10, and sealing the opening of the recess 12 to form a dielectric-free isolation region 13. Then, a shallow trench isolation structure 18 is formed within the substrate 10, with the dielectric-free isolation region 13 located between adjacent shallow trench isolation structures 18. Next, trap ion implantation is performed on the substrate 10 to form a well region 19 between adjacent shallow trench isolation structures 18, with the cavity 13 located within the well region 19. Finally, a gate 21 is formed on the substrate 10, with the dielectric-free isolation region 13 located below the gate 21. By forming the dielectric-free isolation region 13 within the well region 19 below the gate 21, this invention reduces the impact of the depletion region on the channel, thereby increasing the control of the gate 21 over the device and weakening the short-channel effect. In addition, since it is only necessary to form a dielectric-free isolation region 13 in the substrate 10 before forming the shallow trench isolation structure 18, and no changes are required to the remaining process steps and device structure, the process cost is reduced compared to the improvement methods in the prior art that use more advanced gate structures and materials.
[0081] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.
[0082] Please refer to Figure 13As shown, the semiconductor device includes: a substrate 10; a gate 21 located on the substrate 10; a shallow trench isolation structure 18 located within the substrate 10; a well region 19 located between adjacent shallow trench isolation structures 18; and a dielectric-free isolation region 13 located within the well region 19 below the gate 21 and spaced from the upper surface of the substrate 10.
[0083] In one embodiment of the present invention, sidewalls are formed on both sides of the gate 21, and the sidewalls include a first sidewall 22 and a second sidewall 24. The first sidewall 22 and the second sidewall 24 can be single-layer sidewalls or double-layer sidewalls. For example, the first sidewall 22 is a double-layer sidewall, with the inner sidewall covering the sidewall and top of the gate 21, and the outer sidewall covering the sidewall of the inner sidewall. The second sidewall 24 is also a double-layer sidewall, with the inner sidewall covering the sidewall of the first sidewall 22, and the outer sidewall covering the sidewall of the inner sidewall.
[0084] In one embodiment of the present invention, a lightly doped region 23 and a source / drain region 25 are formed in the substrate 10.
[0085] In one embodiment of the present invention, the distance from the dielectric-free isolation region 13 to the upper surface of the substrate 10 is greater than half the depth of the source / drain region 25.
[0086] Due to the presence of the dielectric-free isolation region 13, there is a dielectric-free isolation region in the well region 19 below the gate 21, which can reduce the influence of the depletion region on the channel, thereby increasing the control of the gate 21 over the device and achieving the purpose of weakening the short-channel effect.
[0087] The semiconductor device and its fabrication method provided by this invention first involve providing a substrate, forming a trench within the substrate, and sealing the opening of the trench to form a dielectric-free isolation region. Then, a shallow trench isolation structure is formed within the substrate, with the dielectric-free isolation region located between adjacent shallow trench isolation structures. Next, trap ion implantation is performed on the substrate to form a trap region between adjacent shallow trench isolation structures, with the cavity gap located within the trap region. Finally, a gate is formed on the substrate, with the dielectric-free isolation region located below the gate. This invention reduces the impact of the depletion region on the channel by forming a dielectric-free isolation region within the trap region below the gate, thereby increasing the gate's control over the device and weakening the short-channel effect.
[0088] In addition, since only a dielectric-free isolation region needs to be formed in the substrate before forming the shallow trench isolation structure, and no changes are required to the remaining process steps and device structure, the process cost is reduced compared to the improvement methods using more advanced gate structures and materials in the prior art.
[0089] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, a groove is formed in the substrate, and the opening of the groove is closed to form a dielectric-free isolation region; A shallow trench isolation structure is formed within the substrate, and the dielectric-free isolation region is located between adjacent shallow trench isolation structures; The substrate is subjected to trap ion implantation to form a trap region between adjacent shallow trench isolation structures, and the dielectric-free isolation region is located within the trap region; as well as A gate is formed on the substrate, and the dielectric-free isolation region is located below the gate.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The groove has a cross-section that is narrower at the top and wider at the bottom.
3. The method for fabricating a semiconductor device according to claim 1 or 2, characterized in that, A method for sealing the opening of the groove to form a medium-free isolation zone includes: An epitaxial layer is formed on the substrate using an epitaxial process, the epitaxial layer covering the substrate and closing the opening of the groove; and The epitaxial layer is planarized.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The material of the epitaxial layer is the same as the material of the substrate.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for forming the shallow trench isolation structure includes: An oxide layer, a nitride layer, and a first patterned photoresist layer are sequentially formed on the substrate; Using the first patterned photoresist layer as a mask, shallow trenches are formed by sequentially etching the nitride layer, the oxide layer, and a portion of the substrate thickness. The shallow trench is filled with insulating material; and Remove the nitrided layer.
6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The substrate is implanted with trap ions using the oxide layer as a mask.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, After trap ion implantation and before forming the gate, the fabrication method further includes removing the oxide layer.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After trap ion implantation and before forming the gate, the fabrication method further includes forming a gate oxide layer on the substrate.
9. The method for fabricating a semiconductor device according to claim 1 or 8, characterized in that, After forming the gate, the fabrication method further includes: A first sidewall is formed on the sidewall of the gate; Lightly doped ions are implanted using the gate and the first sidewall as a mask to form a lightly doped region in the well region. A second sidewall is formed on the sidewall of the gate; and Source / drain ion implantation is performed using the gate, the first sidewall, and the second sidewall as masks to form a source / drain region within the trap region.
10. The method for fabricating a semiconductor device according to claim 1 or 8, characterized in that, The distance from the upper interface of the dielectric-free isolation region to the lower surface of the gate or the lower surface of the gate oxide layer is less than half the depth of the source / drain region, or the distance from the upper interface of the dielectric-free isolation region to the lower surface of the gate or the lower surface of the gate oxide layer is less than 6-30 nm.
11. A semiconductor device, characterized in that, The semiconductor device is manufactured using the method described in any one of claims 1 to 10, wherein the semiconductor device comprises: Substrate; The gate is located on the substrate; A shallow trench isolation structure is located within the substrate; The trap region is located between adjacent shallow trench isolation structures; and A dielectric-free isolation region is located within the well region below the gate and is spaced apart from the upper surface of the substrate.