Chip storage and packaging method and packaging structure based on hidden box dam

Abstract

The invention discloses a chip storage and packaging method based on a hidden box dam. The method comprises the following steps: providing a circuit carrier plate; installing a storage bare core on the circuit carrier plate, and electrically connecting the circuit carrier plate with the storage bare core through an electric connecting piece to form a storage chip unit electrically connected with the circuit carrier plate; dam glue dispensing is conducted on the circuit carrier plate around the storage chip unit, the dam glue is cured to form a first dam, and the height of the first dam is larger than or equal to the height of the storage bare chip and larger than the height of the electric connecting piece; filling a packaging adhesive in the first box dam, and curing the filled packaging adhesive to form a first packaging body in which the storage chip unit is packaged; dissolving the first box dam outside the first packaging body by using a dissolving agent and retaining the first packaging body; the computing power chip is installed on the circuit carrier plate, and the circuit carrier plate is electrically connected with the computing power chip. Compared with the prior art, the distance between the computing power chip and the storage bare core can be effectively shortened, and the packaged structure is small in size.

Description

Technical Field

[0001] This invention relates to semiconductor packaging, and more particularly to the packaging of memory computing chips. Background Technology

[0002] Against the backdrop of explosive growth in computing power demand, the "memory wall" problem caused by the separation of storage and computing units in traditional computing architectures is becoming increasingly prominent—data transmission between independently packaged chips faces fundamental bottlenecks such as high latency, limited bandwidth, and high power consumption. To address this challenge, the industry has generally explored in-memory computing technology. Current mainstream in-memory computing solutions often involve first packaging one or more bare memory dies, and then mounting them as independent components onto the system-on-a-chip (SoC) substrate. This secondary packaging structure physically introduces multiple interconnect interfaces—signals must traverse a lengthy path: "bare memory die → packaging substrate → solder balls → PCB substrate → computing chip." This not only significantly increases wire impedance and parasitic capacitance and inductance, leading to limited signal transmission rates, increased latency, and higher power consumption, but also makes signal integrity control at high frequencies extremely complex, severely restricting further breakthroughs in system performance and failing to meet the essential requirements of in-memory computing architectures for high-bandwidth, low-latency interconnects.

[0003] To shorten the interconnection distance between the memory die and the computing chip, the following approach can be adopted: the memory die is directly mounted on the substrate surface in bare die form, and electrical interconnection with the substrate is achieved through wire bonding. To further ensure the mechanical reliability of the bonding wires and control signal interference, adhesive dispensing is required for protection on this structure. However, in practical applications, this dispensing process suffers from the difficulty in precisely controlling the rheological properties of the adhesive, which is prone to uncontrolled diffusion due to adhesive viscosity, dispensing parameters, or environmental fluctuations. To prevent adhesive overflow from contaminating the pads or affecting adjacent components, the layout safety spacing must be increased during the design phase, that is, the distance between the memory die and the computing chip must be increased. This design principle not only increases the physical area occupied by a single chip on the substrate but also makes it difficult to further reduce the overall package size, thus limiting the miniaturization and high-density integration of system-in-package.

[0004] Therefore, there is an urgent need for a storage computing chip packaging method and packaging structure that can solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a chip-based in-memory computing packaging method and packaging structure based on implicit dams, which can effectively shorten the distance between the computing chip and the bare memory chip, and make the packaged structure small in size.

[0006] To achieve the above objectives, the present invention provides a chip-based in-memory computing packaging method based on implicit damming, comprising: Step 1, providing a circuit board; Step 2, mounting a bare memory die on the circuit board and electrically connecting the circuit board and the bare memory die via an electrical connector to form a memory chip unit; Step 3, applying damming adhesive around the memory chip unit on the circuit board and curing the damming adhesive to form a first dam, wherein the height of the first dam is greater than or equal to the height of the bare memory die and greater than the height of the highest point of the electrical connector; Step 4, on the first dam... Step 5: Fill the dam with encapsulating adhesive and cure the encapsulating adhesive to form a first encapsulation body that encapsulates the bare memory chip. The height of the first encapsulation body is greater than or equal to the height of the bare memory chip and greater than the height of the highest point of the electrical connector. The first encapsulation body completely encapsulates the electrical connector and encapsulates the bare memory chip on the circuit board. Step 6: Dissolve the first dam outside the first encapsulation body with a solvent while retaining the first encapsulation body. Step 7: Mount the computing chip on the circuit board and electrically connect the circuit board to the computing chip to form a computing chip unit.

[0007] Preferably, step 6 further includes applying damming adhesive around the computing chip unit on the circuit substrate and curing the damming adhesive to form a second dam with a height reaching a second preset height, the second preset height being greater than or equal to the height of the computing chip unit; filling the second dam with encapsulating adhesive and curing the filled encapsulating adhesive to form a second package containing the computing chip; and using a solvent to dissolve the second dam outside the second package while retaining the second package.

[0008] Preferably, in step 3, after each layer of damming adhesive is applied around the memory chip unit on the circuit substrate, a pre-curing process is performed. This process is repeated multiple times until the height of the damming adhesive reaches a first preset height, forming a pre-cured first dam. The first preset height is greater than or equal to the height of the bare memory chip and is also greater than the height of the highest point of the electrical connector. In step 4, the filling encapsulant and the pre-cured first dam are cured simultaneously to form a fully cured first encapsulation and the first dam.

[0009] Specifically, the pre-curing process is UV pre-curing. In step 4, thermal curing is used to simultaneously cure the filling encapsulant and the pre-cured first dam. The dam encapsulant is an encapsulant that can be cured by both UV and thermal curing, and the encapsulant is an encapsulant that can be cured by thermal curing.

[0010] Preferably, in step 3, after each layer of damming adhesive is applied around the memory chip unit on the circuit board, a complete curing process is performed. This process of applying adhesive and performing complete curing is repeated multiple times until the height of the damming adhesive reaches a first preset height, thereby forming a first cured dam. The first preset height is greater than or equal to the height of the bare memory chip and is also greater than the height of the highest point of the electrical connector.

[0011] Specifically, the damming adhesive is fully cured by heat curing, or it can be fully cured by UV curing.

[0012] Preferably, in step 5, after dissolving the first dam with a solvent, plasma cleaning is also used to remove the residual dam adhesive from the first dam.

[0013] Preferably, in step 6, the computing chip is flip-chip soldered onto the pads of the circuit board, encapsulating adhesive is filled between the bottom of the computing chip and the circuit board, and the encapsulating adhesive is cured to form a protective colloid that wraps the flip-chip pins at the bottom of the computing chip and the pads on the circuit board.

[0014] Preferably, the chip-based in-memory computing packaging method based on implicit dams further includes step 7, attaching a heat dissipation cover surrounding the memory chip unit and the computing chip unit to the circuit substrate.

[0015] Preferably, the main materials of the damming adhesive and the encapsulating adhesive are the same, but the auxiliary materials are different and / or the proportions of the auxiliary materials are different, so that the dissolution rate of the damming adhesive in the solvent is greater than the dissolution rate of the encapsulating adhesive in the solvent.

[0016] Specifically, the main materials of the damming adhesive and the encapsulating adhesive are epoxy resin or polyimide.

[0017] Preferably, in step 5, a solvent is coated or sprayed on the outside of the first dam for a preset time to dissolve the first dam while retaining the first encapsulation, preventing damage to the top of the first encapsulation when removing the first dam.

[0018] Preferably, the memory chip unit includes a plurality of memory dies stacked in a staggered manner on the circuit board, and an arc-shaped bonding wire bonded between the memory dies and the circuit board. Of course, a memory chip unit may also contain only one memory die.

[0019] The present invention also provides a chip-in-memory packaging structure based on implicit dams, which is manufactured by the chip-in-memory packaging method based on implicit dams described above.

[0020] Compared with the prior art, in the memory chip unit of the present invention, the bare die of the memory chip is directly packaged on the circuit board by using a dam and dispensing. The dam can effectively prevent glue from overflowing and contaminating the circuit board during dispensing, so that the volume of the first package can be designed to be smaller. After the first package is formed, the first dam is dissolved to release the space around the memory chip unit, so that the computing chip can be installed closer to the memory chip, further reducing the distance between the memory chip and the computing chip. Attached Figure Description

[0021] Figure 1 This is a flowchart of the first part of the chip-in-memory computing packaging method based on implicit dams in Embodiment 1 of the present invention.

[0022] Figure 2 This is a flowchart of the latter part of the chip-in-memory computing packaging method based on implicit dams in Embodiment 1 of the present invention.

[0023] Figure 3 This is a chip-in-memory computing packaging structure based on implicit dams, which is manufactured by the chip-in-memory computing packaging method based on implicit dams in Embodiment 1 of the present invention.

[0024] Figure 4 This is a partial flowchart of step S6 in the chip-in-memory computing packaging method based on implicit dams in Embodiment 3 of the present invention.

[0025] Figure 5 This is a chip-in-memory computing packaging structure based on implicit dams, which is manufactured by the chip-in-memory computing packaging method based on implicit dams in Embodiment 4 of the present invention.

[0026] Figure label: Circuit board 1, storage packaging unit 10, computing power packaging units 20, 20a, storage bare core 3, arc bonding wire 4, first dam 5, first package 6, computing power chip 7, flip pin 71, protective colloid 8, solder ball 9, second dam 11, second package 12, heat sink 13. Detailed Implementation

[0027] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0028] Example 1: refer to Figure 1 and Figure 2 The present invention discloses a chip-based in-memory computing packaging method based on implicit dams, including steps S1 to S6.

[0029] refer to Figure 1 In section (a), S1, a circuit carrier board 1 is provided. The circuit carrier board 1 can be a common PCB board, which is low in cost and provides stable load-bearing capacity.

[0030] In step S1, the circuit board 1 is cleaned by using argon-oxygen plasma cleaning to remove organic contaminants from the circuit board 1.

[0031] Of course, cleaning of the circuit board 1 is not limited to argon-oxygen plasma cleaning. It can also be done by ultraviolet ozone (UV-Ozone) cleaning, vapor phase cleaning and ultrasonic technology to remove contaminants from the circuit board 1.

[0032] UV-Ozone cleaning: Short-wave ultraviolet light is used to activate oxygen to generate ozone and active oxygen atoms, which decompose organic pollutants on the surface of the carrier plate through strong oxidation, generating volatile products.

[0033] Vapor phase cleaning and ultrasonic technology: First, the organic matter on the surface of the circuit carrier board 1 is dissolved by the vapor condensation of an environmentally friendly solvent. Then, fine particles are removed by high-frequency ultrasonic cavitation. Finally, steam rinsing and drying are performed. This method is highly effective for both organic and inorganic particulate contaminants in complex structures (such as between fine circuit lines). It can be used for batch processing of circuit carrier boards 1 and is suitable for products with extremely high cleanliness requirements.

[0034] refer to Figure 1 In steps (b) and (c), S2, a memory die 3 is mounted on the circuit board 1, and the circuit board 1 is electrically connected to the memory die 3 to form a memory chip unit electrically connected to the circuit board 1. The memory chip unit includes the memory die 3 and an electrical connector that electrically connects the memory die 3 and the circuit board 1 together.

[0035] In this embodiment, in step S2, refer to Figure 1 In (b), storage bare chips 3 are stacked and pasted sequentially on the circuit carrier 1 to form a chip stack structure; see reference. Figure 1 In step (c), an arc-shaped bonding wire 4 is then applied between the electrode pins of the bare memory die 3 and the pads of the circuit carrier 1 to electrically connect the bare memory die 3 and the circuit carrier 1. The electrical connector includes the arc-shaped bonding wire 4. Thus, in this embodiment, the memory chip unit includes a plurality of bare memory dies 3 stacked in a staggered manner on the circuit carrier 1, and an arc-shaped bonding wire 4 bonded between the bare memory die 3 and the circuit carrier 1. The memory chip unit includes the bare memory die 3 and the arc-shaped bonding wire 4.

[0036] Of course, a memory chip unit may also have only one memory die 3. In this case, the memory die 3 can be electrically connected to the circuit board 1 through the arc bonding wire 4, or it can be directly flip-chip soldered onto the circuit board 1. When the memory die 3 is flip-chip soldered onto the circuit board 1, the solder that solders the flip-chip pins of the memory die 3 and the pads of the circuit board 1 together is the electrical connector.

[0037] Specifically, an arc-shaped bonding wire 4 is laid between the electrode pins of each bare memory die 3 and the pads of the electrode carrier 1 to complete the electrical connection between the circuit carrier 1 and the bare memory die 3. Alternatively, arc-shaped bonding wires can be laid between the electrode pins of adjacent bare memory dies 3, and then between the electrode pins of the bottommost bare memory die 3 and the circuit carrier 1 to complete the electrical connection between the circuit carrier 1 and the bare memory die 3.

[0038] The storage die 3 is a die formed after thinning and dicing a wafer. Prior to step S2, the process includes providing the storage die 3: thinning the wafer by grinding (through back-side grinding + wet etching + dry polishing), attaching a black protective film to the back of the thinned wafer (to effectively prevent the wafer from cracking during dicing), dicing the wafer with the protective film to form several diced storage dies 3, and attaching an adhesive film to the back of the storage die 3.

[0039] Of course, the steps for providing the storage die 3 are not limited to the above methods. Another approach is to first cut the front side of the wafer, but only to a depth of 1 / 3 to 1 / 2 of the wafer's effective thickness. Then, a black protective film is applied to the front side of the wafer. Next, the back side of the wafer is thinned (wet etching + dry polishing) until it reaches the previously cut kerf position, allowing the wafer to automatically separate into the storage die 3 during the thinning process. Because the wafer automatically separates into the storage die 3 during the thinning process, the stress on the edges of the ultra-thin chip caused by mechanical sawing is avoided. This is particularly suitable for large-area, ultra-thin chips, significantly improving the mechanical strength of the storage die 3 and the reliability of subsequent stacking. Furthermore, this advanced process simplifies the requirements for the protective film, reducing the requirements for the film's cut resistance and adhesion, and minimizing defects caused by film material issues.

[0040] In step S2, the storage bare die 3 is sequentially and staggeredly pasted onto the circuit carrier board 1 using adhesive film.

[0041] refer to Figure 1 In step (d), S3, damming adhesive is applied around the memory chip cell on the circuit board 1 and the damming adhesive is cured to form a first dam 5. The height of the first dam 5 is greater than or equal to the height of the bare memory chip 3 and is greater than the height of the highest point of the electrical connector (e.g., the arc bonding wire 4).

[0042] The main material of the damming adhesive is epoxy resin or polyimide. The first dam 5 is a ring-shaped component formed after the epoxy adhesive has cured or after the polyimide has cured. Additives are added to the damming adhesive to reduce its fluidity; for example, ABC materials can be added as additives.

[0043] Preferably, in step S3, after each layer of damming adhesive is applied around the memory chip unit on the circuit carrier 1, a pre-curing process is performed. This process of applying adhesive and pre-curing is repeated multiple times until the height of the damming adhesive reaches a first preset height, forming a pre-cured first dam 5. The first preset height is greater than or equal to the height of the bare memory chip 3 and is greater than the height of the highest point of the electrical connector (e.g., the arc bonding wire 4). The pre-curing process is UV pre-curing.

[0044] The thickness of the first cofferdam 5 is 150-300μm.

[0045] refer to Figure 1 In step (e), S4, encapsulating adhesive is filled into the first dam 5, and the filled encapsulating adhesive is cured to form a first encapsulation body 6 encapsulating the bare memory chip 3 within it. The height of the first encapsulation body 6 is greater than or equal to the height of the bare memory chip 3, and is greater than the height of the highest point of the electrical connector (e.g., the arc bonding wire 4). The first encapsulation body 6 completely encapsulates the electrical connector and encapsulates the bare memory chip 3 on the circuit board 1.

[0046] Preferably, in S4, thermosetting is used to simultaneously cure the filling encapsulant and the pre-cured first dam 5, wherein the dam encapsulant is an encapsulant that can be cured by UV and thermosetting, and the encapsulant is a thermosetting encapsulant.

[0047] In this embodiment, a multi-layer dispensing process is first performed on the damming adhesive. After each layer of damming adhesive is dispensed, UV pre-curing is immediately initiated. This "dispensing-UV pre-curing" cycle continues until the damming adhesive layer height reaches a first preset height, forming a pre-cured first dam 5. The first preset height is greater than or equal to the height of the bare storage core 3 and greater than the height of the highest point of the electrical connector (e.g., the arc-shaped bonding wire 4). After the structure of the first dam 5 is formed, encapsulating adhesive is injected. After the encapsulating adhesive is injected, a thermosetting process is simultaneously performed on the composite adhesive structure composed of the pre-cured first dam 5 and the encapsulating adhesive to ensure deep fusion of the two adhesives.

[0048] The main material of the encapsulating adhesive is epoxy resin or polyimide, and the first encapsulant 6 is an epoxy adhesive encapsulant or a polyimide encapsulant. Additives are added to the encapsulating adhesive to increase its fluidity and reduce its viscosity; for example, DEF material can be added as an additive.

[0049] Preferably, the main materials of the damming adhesive and the encapsulating adhesive are the same, which can effectively reduce air bubbles in the encapsulating adhesive when it is filled into the first dam 5, especially at the interface between the encapsulating adhesive and the first dam 5, ensuring that the encapsulating adhesive completely encapsulates the memory chip unit, especially the arc bonding line 4. Of course, the main materials of the damming adhesive and the encapsulating adhesive can also be different.

[0050] refer to Figure 2 In step (f), S5, the first enclosure 5 outside the first encapsulation 6 is dissolved using a solvent while retaining the first encapsulation 6.

[0051] In this embodiment, the excipients for the damming adhesive and the encapsulating adhesive are different, so that the dissolution rate of the damming adhesive in the solvent is greater than that of the encapsulating adhesive in the solvent, and the flowability of the damming adhesive is less than that of the encapsulating adhesive. Of course, the dissolution rates of the damming adhesive and the encapsulating adhesive in the solvent can also be adjusted by other conditions, such as adjusting the proportions of the various components in the damming adhesive and the encapsulating adhesive, or simultaneously adjusting the proportions of the excipients and components of the damming adhesive and the encapsulating adhesive to change their crosslinking density, thereby adjusting the characteristics of the damming adhesive and the encapsulating adhesive, so that the damming adhesive has high solubility and low flowability, and the encapsulating adhesive has low solubility and high flowability.

[0052] The damming adhesive and the encapsulating adhesive are made of the same main materials. A solvent is coated or sprayed onto the outside of the first dam 5 for a preset duration to dissolve the first dam 5 while preserving the first encapsulated body 6, preventing damage to the top of the first encapsulated body 6 when removing the first dam 5. The amount and duration of the solvent coating or spraying ensure that the first dam 5 is completely dissolved while preserving the first encapsulated body 6. The composition of the solvent is determined by the material of the damming adhesive.

[0053] Of course, this is not the only method; other methods can also be used to dissolve and remove the first dam 5. For example, the entire storage encapsulation unit 10 can be immersed in a dissolving solution to remove the first dam 5. In this case, the height difference between the first dam 5 and the first encapsulation body 6 in steps S3 and S4 and the height of the electrical connector (e.g., the arc bonding line 4) is greater than or equal to a preset value to prevent excessive dissolution of the first encapsulation body 6 and exposure of the arc bonding line 4 when the solvent dissolves the first dam 5. This preset value is determined by the difference in the dissolution rates of the first encapsulation body 6 and the first dam 5 in the solvent, as well as the thickness of the first dam 5.

[0054] Wherein, when the damming adhesive is an epoxy resin adhesive, so that the first dam 5 is an epoxy-cured ring-shaped part, the solvent in step S5 is a corresponding organic solvent, such as acetone, ethyl acetate, etc. When the damming adhesive is a polyimide adhesive, so that the first dam 5 is a polyimide-cured ring-shaped part, the solvent in step S5 is dimethylformamide (DMF), N-methylpyrrolidone (NMP), etc.

[0055] Preferably, in step S5, after dissolving the first dam 5 with a solvent, plasma cleaning is also used to remove residual dam adhesive from the first dam 5. For example, argon-oxygen plasma cleaning is used to remove residual dam adhesive from the outside of the first package 6.

[0056] Thus, a storage packaging unit 10 is formed, which consists of the storage die 3, an electrical connector (arc bonding wire 4), and a first package 6.

[0057] refer to Figure 2 In steps (g) and (h), S6, the computing chip 7 is mounted on the circuit carrier board 1, and the circuit carrier board 1 is electrically connected to the computing chip 7 to form a computing chip unit electrically connected to the circuit carrier board 1.

[0058] Step S6 includes S61 to S62.

[0059] refer to Figure 2 In step (g), S61, the computing chip 7 is flip-chip soldered onto the pads of the circuit board 1 to form a computing chip unit. The flip-chip pins 71 at the bottom of the computing chip 7 are soldered to the pads of the circuit board 1 via solder balls 9. This computing chip unit consists of the computing chip 7 (including the flip-chip pins 71 at the bottom of the computing chip 7) and solder balls 9. The solder balls are solder balls. The computing chip 7 is a bare die or a bare die package.

[0060] refer to Figure 2 In step (h), S62, encapsulating adhesive is filled between the bottom of the computing chip 7 and the circuit carrier 1, and the encapsulating adhesive is cured to form a protective colloid 8 that wraps the flip-chip pins 71 on the bottom of the computing chip 7 and the pads on the circuit carrier 1, thereby completing the encapsulation of the computing power encapsulation unit 20. The computing power encapsulation unit 20 consists of the computing chip 7, the protective colloid 8, and the solder balls 9.

[0061] In this embodiment, a storage chip unit and a computing chip unit are formed on the circuit carrier 1. In contrast, multiple storage chip units and a computing chip unit can also be formed on the circuit carrier 1. In this case, the storage chip units are arranged around the computing chip unit, for example, on multiple different sides of the computing chip unit, or even around it.

[0062] The distance between the storage die 3 and the computing chip 7 is 3-4 mm. In this embodiment, the distance between the storage die 3 and the computing chip 7 is about 3.5 mm.

[0063] refer to Figure 3 The present invention discloses a chip-in-memory computing packaging structure based on implicit dams, which is manufactured by the chip-in-memory computing packaging method based on implicit dams of the present invention.

[0064] For the better option, refer to Figure 2In step (i), the chip-based in-memory packaging method based on implicit dams further includes step S7, where a heat dissipation cover 13 surrounding the storage packaging unit 10 and the computing power packaging unit 20 is attached to the circuit carrier board 1. The heat dissipation cover 13 is positioned relative to the spacing between the storage packaging unit 10 and the computing power packaging unit 20.

[0065] Example 2: Unlike Embodiment 1, in step S3 of Embodiment 2, after each layer of damming adhesive is applied around the memory chip unit on the circuit carrier 1, a complete curing process is performed. This process of applying adhesive and performing complete curing is repeated multiple times until the height of the damming adhesive reaches a first preset height, forming a fully cured first dam 5. The first preset height is greater than or equal to the height of the bare memory chip 3 and is greater than the height of the highest point of the electrical connector (e.g., the arc bonding wire 4). The applied damming adhesive is fully cured by thermal curing. In step S4 of Embodiment 2, encapsulating adhesive is filled into the structurally stable first dam 5, and the filled encapsulating adhesive is cured to form a first encapsulation body 6 that encapsulates the bare memory chip 3 and the electrical connector (e.g., the arc bonding wire 4). The height of the first encapsulation body 6 is greater than or equal to the height of the bare memory chip 3 and is greater than the height of the highest point of the electrical connector (e.g., the arc bonding wire 4). The first encapsulation body 6 completely encapsulates the electrical connector and encapsulates the bare memory chip 3 onto the circuit carrier 1. In this process, thermosetting is used to cure the encapsulating adhesive to form the first encapsulation 6.

[0066] In this embodiment, after each layer of damming adhesive is applied, it is not subjected to UV irradiation. Instead, a single layer of damming adhesive undergoes a complete thermosetting process. Through a cyclical operation of "application-single-layer thermosetting," a first dam 5 with extremely stable chemical properties and high physical strength is formed as a robust barrier. After the first dam 5 has completely cured and cooled, the encapsulating adhesive is injected in step S4. Finally, in step S4, only the encapsulating adhesive undergoes final thermosetting, allowing it to complete the cross-linking and curing process independently of the damming adhesive. This approach fundamentally eliminates the risk of mutual diffusion, the formation of blending zones, or adverse reactions at the interface between the encapsulating and damming adhesives, offering the widest process window and the highest reliability. Furthermore, it eliminates the need to excessively consider the chemical compatibility of the two adhesives, allowing for the selection of the optimal adhesive material for both damming and filling functions.

[0067] Preferably, in this embodiment, the main materials of the damming adhesive and the encapsulating adhesive are different. The solvent in step S5 is a solvent for the damming adhesive, not for the encapsulating adhesive. The dissolution rate of the damming adhesive in the solvent is much greater than that of the encapsulating adhesive. It is particularly preferable to select a solvent that easily dissolves the damming adhesive but does not dissolve the encapsulating adhesive. In step S5, the product can be directly immersed in the solvent to dissolve the first dam 5, or the damming adhesive of the first dam 5 can be dissolved using the method described in Example 1.

[0068] Wherein, when the damming adhesive is an epoxy resin adhesive, so that the first dam 5 is an epoxy-cured ring-shaped part, the solvent in step S5 is a corresponding organic solvent, such as acetone, ethyl acetate, etc. When the damming adhesive is a polyimide adhesive, so that the first dam 5 is a polyimide-cured ring-shaped part, the solvent in step S5 is dimethylformamide (DMF), N-methylpyrrolidone (NMP), etc.

[0069] Of course, the main materials of the damming adhesive and the encapsulating adhesive can be the same. In this case, the damming adhesive of the first dam 5 is dissolved in the manner described in Example 1.

[0070] Example 3: Unlike Embodiment 1, in Embodiment 3: step S6 further includes applying damming adhesive around the computing chip unit on the circuit carrier board 1 and curing the damming adhesive to form a second dam 11 with a height reaching a second preset height, the second preset height being greater than or equal to the height of the computing chip unit; filling the second dam 11 with encapsulating adhesive and curing the filled encapsulating adhesive to form a second encapsulation body 12 encapsulating the computing chip; using a solvent to dissolve the second dam 11 outside the second encapsulation body 12 while retaining the second encapsulation body 12.

[0071] Step S6 includes S61 to S65.

[0072] refer to Figure 2 In step (g), S61, the computing chip 7 is flip-chip soldered onto the pads of the circuit board 1 to form a computing chip unit. The flip-chip pins 71 at the bottom of the computing chip 7 are soldered to the pads of the circuit board 1 via solder balls 9. The computing chip unit consists of the computing chip 7 (including the flip-chip pins 71 at the bottom of the computing chip 7) and solder balls 9. The solder balls are solder balls. Of course, the electrical connection method between the computing chip 7 and the circuit board 1 is not limited to flip-chip soldering. The second preset height is greater than or equal to the height of the top surface of the computing chip 7, so that the second package 12 completely encloses the computing chip 7, or encloses the computing chip 7 but only exposes the top surface of the computing chip 7.

[0073] Regardless of the electrical connection method used to connect the computing chip 7 to the circuit board 1, it is necessary to ensure that the height of the second dam 11 and the second package 12 is higher than the electrical connector selected for that electrical connection method.

[0074] refer to Figure 2 (h) or Figure 4 In step (a), S62, encapsulating adhesive is filled between the bottom of the computing chip 7 and the circuit carrier 1, and the encapsulating adhesive is cured to form a protective adhesive 8 that wraps the flip pins 71 at the bottom of the computing chip 7 and the pads on the circuit carrier 1.

[0075] refer to Figure 4 In step (b), S63, damming adhesive is applied to the circuit carrier 1 around the computing chip unit, and the damming adhesive is cured to form a second dam 11 with a height reaching a second preset height. The second preset height is greater than or equal to the height of the computing chip unit.

[0076] Specifically, after each layer of damming adhesive is applied around the computing chip unit on the circuit carrier board 1, a pre-curing process is performed. This process is repeated multiple times until the height of the damming adhesive reaches a second preset height, thus forming a pre-cured second dam 11.

[0077] The main material of the damming adhesive is epoxy resin or polyimide, and the second dam 11 is a ring-shaped body after the epoxy adhesive has cured. Additives are added to the damming adhesive to reduce its fluidity; for example, ABC materials can be added as additives.

[0078] Preferably, in step S63, after each layer of damming adhesive is applied around the computing chip unit on the circuit carrier 1, a pre-curing process is performed. This process is repeated multiple times until the height of the damming adhesive reaches a second preset height, thus forming a pre-cured second dam 11. The pre-curing process is UV pre-curing.

[0079] refer to Figure 4 In step (c), S64, encapsulating adhesive is filled into the second dam 11, and the filled encapsulating adhesive is cured to form a second package 12 that encapsulates the computing chip.

[0080] Preferably, in S64, thermosetting is used to simultaneously cure the encapsulating adhesive filled in the second dam 11 and the pre-cured second dam 11, wherein the dam adhesive is an encapsulating adhesive that can be cured by UV and thermosetting, and the encapsulating adhesive is a thermosetting encapsulating adhesive.

[0081] In this embodiment, the damming adhesive is first applied in multiple layers. After each layer of damming adhesive is applied, UV pre-curing is immediately initiated. This "application-UV pre-curing" cycle continues until the damming adhesive layer height reaches a second preset height, forming a pre-cured second dam 11. After the structure of the second dam 11 is formed, the encapsulating adhesive is injected. After the encapsulating adhesive is injected, a thermosetting process is simultaneously performed on the composite adhesive structure composed of the pre-cured second dam 11 and the encapsulating adhesive to ensure deep fusion of the two adhesives.

[0082] The main material of the damming adhesive is epoxy resin or polyimide, and the second encapsulation body 12 is an epoxy adhesive encapsulation body or a polyimide encapsulation body. Additives (functional fillers) are added to the encapsulation adhesive to increase its fluidity and reduce its viscosity; for example, DEF material can be added as an additive (functional filler).

[0083] Preferably, the main materials of the damming adhesive and the encapsulating adhesive are the same, which can effectively reduce air bubbles in the encapsulating adhesive when it is filled into the second dam 11, especially at the interface between the encapsulating adhesive and the second dam 11, ensuring that the encapsulating adhesive completely encapsulates the computing chip unit. Of course, the main materials of the damming adhesive and the encapsulating adhesive can also be different.

[0084] refer to Figure 4 In step (d), S65, the second enclosure 11 outside the second encapsulation 12 is dissolved using a solvent while retaining the second encapsulation 12.

[0085] In this embodiment, the auxiliary materials (functional fillers) of the damming adhesive and the encapsulating adhesive are different, so that the dissolution rate of the damming adhesive in the solvent is greater than that of the encapsulating adhesive in the solvent, and the flowability of the damming adhesive is less than that of the encapsulating adhesive. Of course, the dissolution rates of the damming adhesive and the encapsulating adhesive in the solvent can also be adjusted by other conditions, such as by adjusting the proportions of various components in the damming adhesive and the encapsulating adhesive, or by simultaneously adjusting the proportions of auxiliary materials and components in the damming adhesive and the encapsulating adhesive to change their crosslinking density, thereby adjusting the characteristics of the damming adhesive and the encapsulating adhesive, so that the damming adhesive has high solubility and low flowability, and the encapsulating adhesive has low solubility and high flowability.

[0086] Specifically, a solvent is coated or sprayed onto the outside of the second cofferdam 11 for a preset duration to dissolve the second cofferdam 11 while retaining the second encapsulation body 12, preventing damage to the top of the second encapsulation body 12 when removing the second cofferdam 11. The amount and duration of the applied or sprayed solvent ensure that the second cofferdam 11 is completely dissolved while retaining the second encapsulation body 12. The composition of the solvent is determined by the material of the cofferdam adhesive.

[0087] Of course, this is not the only method. Other methods can be used to dissolve and remove the second dam 11. For example, the entire computing power packaging unit 20 can be immersed in a dissolving solution to remove the second dam 11. At this time, the height difference between the second dam 11 and the second package 12 in steps S63 and S64 and the height of the highest point of the computing power chip unit is greater than or equal to a preset value, so as to prevent the solvent from dissolving too much of the second package 12 when dissolving the second dam 11.

[0088] Wherein, when the damming adhesive is an epoxy resin adhesive, so that the second dam 11 is a ring-shaped part after epoxy resin curing, the solvent in step S65 is a corresponding organic solvent, such as acetone, ethyl acetate, etc. When the damming adhesive is a polyimide adhesive, so that the second dam 11 is a ring-shaped part after polyimide curing, the solvent in step S65 is dimethylformamide (DMF), N-methylpyrrolidone (NMP), etc.

[0089] Preferably, in step S65, after dissolving the second dam 11 with a solvent, plasma cleaning is also used to remove residual dam adhesive from the second dam 11. For example, argon-oxygen plasma cleaning is used to remove residual dam adhesive from the outside of the second encapsulation 12.

[0090] Thus, a computing power packaging unit 20a is formed, which consists of the computing power chip 7, solder balls 9, and a second package 12.

[0091] refer to Figure 5 The present invention discloses a chip-in-memory computing packaging structure based on implicit dams, which is manufactured by the chip-in-memory computing packaging method based on implicit dams of the present invention.

[0092] Example 4: Unlike Embodiment 3, in step S63 of Embodiment 4, after each layer of damming adhesive is applied around the computing chip unit on the circuit carrier 1, a complete curing process is performed. This process is repeated multiple times until the height of the damming adhesive reaches a second preset height, forming a fully cured second dam 11. The second preset height is greater than or equal to the height of the computing chip unit. The applied damming adhesive is fully cured using thermosetting. In step S64 of Embodiment 4, encapsulating adhesive is filled into the structurally stable second dam 11, and the filled encapsulating adhesive is cured to form a second encapsulation 12 encapsulating the bare computing chip 3. The encapsulating adhesive is cured using thermosetting to form the second encapsulation 12.

[0093] In this embodiment, after each layer of damming adhesive is applied, it is not subjected to UV irradiation. Instead, a single layer of damming adhesive undergoes a complete thermosetting process. Through a cyclical operation of "application-single-layer thermosetting," a second dam 11 with extremely stable chemical properties and high physical strength is formed as a robust barrier. After the second dam 11 is completely cured and cooled, the encapsulating adhesive is injected in step S64. Finally, in step S64, only the encapsulating adhesive undergoes final thermosetting, allowing it to complete the cross-linking and curing process independently of the damming adhesive. This approach fundamentally eliminates the risk of mutual diffusion, the formation of blending zones, or adverse reactions at the interface between the encapsulating and damming adhesives, offering the widest process window and the highest reliability. Furthermore, it eliminates the need to excessively consider the chemical compatibility of the two adhesives, allowing for the selection of the optimal adhesive material for both damming and filling functions.

[0094] Preferably, in this embodiment, the main materials of the damming adhesive and the encapsulating adhesive are different. The solvent in step S65 is a solvent for the damming adhesive, not for the encapsulating adhesive. The dissolution rate of the damming adhesive in the solvent is much greater than that of the encapsulating adhesive. It is particularly preferable to select a solvent that easily dissolves the damming adhesive but does not dissolve the encapsulating adhesive. In step S65, the product can be directly immersed in the solvent to dissolve the second dam 11, or the method of Example 3 can be used to dissolve the second dam 11.

[0095] Of course, the main materials of the damming adhesive and the encapsulating adhesive can be the same. In this case, the damming adhesive of the second dam 11 is dissolved in the manner described in Example 2.

[0096] Compared with the prior art, in the memory chip unit of the present invention, the bare die of the memory chip 3 is directly packaged on the circuit carrier board 1 by using a dam and dispensing. The dam can effectively prevent glue from overflowing and contaminating the circuit carrier board 1 during dispensing, so that the volume of the first package 6 can be designed to be smaller. After the first package 6 is formed, the first dam 5 is dissolved to release the space around the memory chip unit, so that the computing chip 7 can be installed closer to the memory chip 3, further reducing the distance between the memory chip 3 and the computing chip 7.

[0097] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.

Claims

1. A method for chip-in-memory-in- package based on implicit damming, characterized in that: The method comprises the following steps: Step 1, providing a circuit carrier plate; Step 2, mounting a memory die on the circuit carrier plate and electrically connecting the circuit carrier plate and the memory die through an electrical connector to form a memory chip unit; Step 3, damming glue around the memory chip unit on the circuit carrier plate and curing the damming glue to form a first dam, the height of the first dam being greater than or equal to the height of the memory die and greater than the height of the highest point of the electrical connector; Step 4, filling encapsulation glue in the first dam and curing the filled encapsulation glue to form a first encapsulation body, the height of the first encapsulation body being greater than or equal to the height of the memory die and greater than the height of the highest point of the electrical connector, the first encapsulation body fully wrapping the electrical connector and encapsulating the memory die on the circuit carrier plate; Step 5, dissolving the first dam outside the first encapsulation body using a dissolving agent and retaining the first encapsulation body; Step 6, mounting a computing power chip on the circuit carrier plate and electrically connecting the circuit carrier plate and the computing power chip to form a computing power chip unit.

2. The implicit dam-based chip store compute packaging method of claim 1, wherein: Step 6 further comprises damming glue around the computing power chip unit on the circuit carrier plate and curing the damming glue to form a second dam with a height reaching a second preset height, the second preset height being greater than or equal to the height of the computing power chip unit; filling encapsulation glue in the second dam and curing the filled encapsulation glue to form a second encapsulation body encapsulating the computing power chip; dissolving the second dam outside the second encapsulation body using a dissolving agent and retaining the second encapsulation body.

3. The implicit dam-based chip store compute packaging method of claim 1, wherein: In step 3, after completing the damming glue point of each layer around the memory chip unit on the circuit carrier plate, pre-curing treatment is performed, and the point of glue and pre-curing treatment is repeated multiple times until the height of the damming glue reaches a first preset height to form a pre-cured first dam, the first preset height being greater than or equal to the height of the memory die and greater than the height of the highest point of the electrical connector; In step 4, the filled encapsulation glue and the pre-cured first dam are simultaneously cured to form a completely cured first encapsulation body and first dam.

4. The implicit dam-based chiplet-in-package method of claim 3, wherein: The pre-curing treatment is UV pre-curing, in step 4, heat curing is used to simultaneously cure the filled encapsulation glue and the pre-cured first dam, the damming glue is encapsulation glue that can be cured by UV and heat, and the encapsulation glue is encapsulation glue that can be cured by heat.

5. The implicit dam-based chip store compute packaging method of claim 1, wherein: In step 3, after completing the damming glue point of each layer around the memory chip unit on the circuit carrier plate, complete curing treatment is performed, and the point of glue and complete curing treatment is repeated multiple times until the height of the damming glue reaches a first preset height to form a completely cured first dam, the first preset height being greater than or equal to the height of the memory die and greater than the height of the highest point of the electrical connector.

6. The implicit dam-based chiplet compute package method of claim 5, wherein: The point of glued damming glue is completely cured by heat curing.

7. The implicit dam-based chip store compute packaging method of claim 1, wherein: In step 5, after the first dam is dissolved using a dissolving agent, plasma cleaning is further used to remove residual damming glue of the first dam.

8. The implicit dam-based chip store compute packaging method of claim 1, wherein: The main material of the dam glue and the encapsulation glue is the same, and the auxiliary materials are different and / or the proportion of the auxiliary materials is different, so that the dissolving rate of the dam glue in the dissolving agent is greater than the dissolving rate of the encapsulation glue in the dissolving agent.

9. The implicit dam-based chiplet packaging method of claim 8, wherein: The main material of the dam glue and the encapsulation glue is epoxy resin or polyimide.

10. The implicit dam-based chip store compute packaging method of claim 1, wherein: In the step 5, a dissolving agent is coated or sprayed on the outer side of the first dam for a preset time length, so as to dissolve the first dam and reserve the first encapsulation.

11. The implicit dam-based chip store compute packaging method of claim 1, wherein: The memory chip unit comprises a plurality of memory dies stacked in sequence and staggered on the circuit carrier board, and arc-shaped bonding wires bonded between the memory dies and the circuit carrier board.

12. A chip-in-memory computing packaging structure based on implicit dams, characterized in that: The chip-in-memory computing encapsulation method based on the implicit dam is made by any one of claims 1-11. The main material of the dam glue and the encapsulation glue is the same, and the auxiliary materials are different and / or the proportion of the auxiliary materials is different, so that the dissolving rate of the dam glue in the dissolving agent is greater than the dissolving rate of the encapsulation glue in the dissolving agent. The main material of the dam glue and the encapsulation glue is epoxy resin or polyimide. In the step 5, a dissolving agent is coated or sprayed on the outer side of the first dam for a preset time length, so as to dissolve the first dam and reserve the first encapsulation. The memory chip unit comprises a plurality of memory dies stacked in sequence and staggered on the circuit carrier board, and arc-shaped bonding wires bonded between the memory dies and the circuit carrier board. The chip-in-memory computing encapsulation method based on the implicit dam is made by any one of claims 1-11.

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