Semiconductor package and method of manufacturing the same

Abstract

The invention relates to a semiconductor package and a method of manufacturing the same. A semiconductor package includes: a package substrate; a first semiconductor die mounted over the package substrate; a second semiconductor die offset stacked in the first direction over the first semiconductor die; a third semiconductor die offset stacked in a second direction over the second semiconductor die; and a fourth semiconductor die offset from the stack in the second direction over the third semiconductor die. Each of the first to fourth semiconductor dies includes a semiconductor chip and an adhesive layer. The first adhesive layer has a first thickness. Each of the second to fourth adhesive layers has a second thickness. The first thickness is different from the second thickness.

Description

Technical Field

[0001] This disclosure generally relates to packaging, and more specifically, to a semiconductor package and a method of manufacturing the semiconductor package. Background Technology

[0002] Semiconductor packages with multiple offset stacked semiconductor dies have been proposed. Summary of the Invention

[0003] According to embodiments of this disclosure, a semiconductor package may include: a packaging substrate; a first semiconductor die mounted above the packaging substrate; a second semiconductor die offset and stacked above the first semiconductor die in a first direction; a third semiconductor die offset and stacked above the second semiconductor die in a second direction; and a fourth semiconductor die offset and stacked above the third semiconductor die in a second direction. The first direction is opposite to the second direction. The first semiconductor die may include a first semiconductor chip and a first adhesive layer. The second semiconductor die may include a second semiconductor chip and a second adhesive layer. The third semiconductor die may include a third semiconductor chip and a third adhesive layer. The fourth semiconductor die may include a fourth semiconductor chip and a fourth adhesive layer. The first adhesive layer has a first thickness. Each of the second to fourth adhesive layers has a second thickness. The first thickness is thicker than the second thickness.

[0004] According to embodiments of this disclosure, a semiconductor package may include: a package substrate; a first semiconductor chip mounted above the package substrate; a second semiconductor chip offset and stacked above the first semiconductor chip in a first direction; a third semiconductor chip offset and stacked above the second semiconductor chip in a second direction; and a fourth semiconductor chip offset and stacked above the third semiconductor chip in a second direction. The package substrate may include a first side, a second side, and first substrate pads, second substrate pads, third substrate pads, and fourth substrate pads. The first side is opposite to the second side. The first substrate pads and fourth substrate pads are disposed closer to the second side than the first side. The second substrate pads and third substrate pads are disposed closer to the first side than the second side. The first semiconductor chip may include a first chip pad disposed closer to the second side than the first side. The second semiconductor chip may include a second chip pad disposed closer to the first side than the second side. The third semiconductor chip may include a third chip pad disposed closer to the first side than the second side. The fourth semiconductor chip may include a fourth chip pad disposed closer to the second side than the first side.

[0005] According to embodiments of this disclosure, a method for manufacturing a semiconductor package may include the following steps: mounting a first semiconductor die above a package substrate; forming a first connector to electrically connect the first semiconductor die to the package substrate; offsetting and stacking a second semiconductor die above the first semiconductor die in a first direction; offsetting and stacking a third semiconductor die on the second semiconductor die in a second direction; offsetting and stacking a fourth semiconductor die on the third semiconductor die in a second direction; forming a second connector to electrically connect the second semiconductor die to the package substrate; forming a third connector to electrically connect the third semiconductor die to the package substrate; and forming a fourth connector to electrically connect the fourth semiconductor die to the package substrate.

[0006] According to embodiments of this disclosure, a method for manufacturing a semiconductor package may include the following steps: forming a first adhesive film having a first thickness over the back side of a first wafer; forming a second adhesive film having a second thickness over the back side of a second wafer; dicing the first wafer and the first adhesive film to form a first semiconductor die having a first semiconductor chip and a first adhesive layer; dicing the second wafer and the second adhesive film to form a second semiconductor die, a third semiconductor die, and a fourth semiconductor die having a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip, and a second adhesive layer, a third adhesive layer, and a fourth adhesive layer, respectively; mounting the first semiconductor die on a package substrate; and stacking the second semiconductor die, the third semiconductor die, and the fourth semiconductor die over the first semiconductor die. The first adhesive film has a first thickness. The second adhesive film has a second thickness. The first thickness is thicker than the second thickness. Attached Figure Description

[0007] Figure 1A This is a schematic side view of a semiconductor package according to an embodiment of the present disclosure. Figure 1B yes Figure 1A An enlarged view of region "A", and Figure 1C yes Figure 1A A magnified view of region "B".

[0008] Figure 2 This is a schematic side view of a semiconductor package according to an embodiment of the present disclosure.

[0009] Figures 3A to 3F This is a view illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0010] Figures 4A to 4E This is a view illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure. Detailed Implementation

[0011] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Throughout this disclosure, similar reference numerals denote similar parts in the embodiments and various drawings.

[0012] The accompanying drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is formed directly on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate. It will be understood that when an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or there may be intermediate elements or layers. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," or "directly attached to" another element or layer, there are no intermediate elements or layers. For ease of description, spatial relative terms such as "below," "below," "down," "above," "upper," etc., are used herein to describe the relationship of one element or feature to other elements or features as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are intended to also cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as "below" or "under" other elements or features will be oriented "above" other elements or features. Therefore, examples of the term "below" can encompass both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptions used herein are interpreted accordingly. Embodiments of this disclosure relate to a semiconductor die stack structure and a method of manufacturing the semiconductor die stack structure, the semiconductor die stack structure comprising a plurality of semiconductor dies stacked thereon. Embodiments of this disclosure relate to a base-bottom die stack structure and a method of manufacturing the base-bottom die stack structure, in which base dies and bottom dies are joined. Embodiments of this disclosure relate to a method of stacking intermediate dies and top dies above a base-bottom die stack structure. Embodiments of this disclosure relate to a semiconductor stack structure comprising intermediate dies and top dies stacked above a base-bottom die stack structure.

[0013] Throughout this specification, the phrase "closer to the first side of the packaging substrate" can be interpreted as "closer to the first side of the packaging substrate than the second side of the packaging substrate," and the phrase "closer to the second side of the packaging substrate" can be interpreted as "closer to the second side of the packaging substrate than the first side of the packaging substrate."

[0014] Embodiments of this disclosure provide a semiconductor package having a plurality of offset stacked semiconductor dies.

[0015] Embodiments of this disclosure provide a method for manufacturing a semiconductor package having multiple offset stacked semiconductor dies.

[0016] Figure 1A This is a schematic side view of a semiconductor package 1000A according to an embodiment of the present disclosure. Figure 1B yes Figure 1A A magnified view of region "A". Figure 1C yes Figure 1A A magnified view of region "B".

[0017] Reference Figures 1A to 1C The semiconductor package 1000A according to embodiments of the present disclosure may include a semiconductor chip stack 100 mounted on a package substrate 10. The semiconductor package 1000A may also include connectors 113, 123, 133, and 143 electrically connecting the package substrate 10 to the semiconductor chip stack 100. Connectors 113, 123, 133, and 143 may include a first connector 113, a second connector 123, a third connector 133, and a fourth connector 143. Each of the first to fourth connectors 113, 123, 133, and 143 may include a bonding lead. The semiconductor package 1000A may also include a molding member 90 surrounding and covering the semiconductor chip stack 100 and the first to fourth connectors 113, 123, 133, and 143.

[0018] The package substrate 10 may further include substrate pads 11, 12, 13, and 14 and an external connector 19. Substrate pads 11, 12, 13, and 14 may be disposed on the upper surface of the package substrate 10, and the external connector 19 may be disposed on the lower surface of the package substrate 10. Substrate pads 11, 12, 13, and 14 and the external connector 19 may be selectively electrically connected to each other. Substrate pads 11, 12, 13, and 14 may include a first substrate pad 11, a second substrate pad 12, a third substrate pad 13, and a fourth substrate pad 14. The first substrate pad 11 and the fourth substrate pad 14 may be disposed near the second side S2 of the package substrate 10, and the second substrate pad 12 and the third substrate pad 13 may be disposed near the first side S1 of the package substrate 10. The first to fourth substrate pads 11, 12, 13, and 14 may include a metal such as copper. The external connector 19 may include solder balls. The package substrate 10 may include a printed circuit board (PCB). In some embodiments, the packaging substrate 10 may include one of a redistribution layer or a silicon-based interposer.

[0019] The direction from the second side S2 to the first side S1 of the packaging substrate 10 is defined as the first direction D1, and the direction from the first side S1 to the second side S2 of the packaging substrate 10 is defined as the second direction D2. The first direction D1 and the second direction D2 may be opposite to each other. The first side S1 and the second side S2 may be opposite to each other.

[0020] The semiconductor chip stack 100 may include a plurality of stacked semiconductor dies 119, 129, 139, and 149. For example, the semiconductor chip stack 100 may include a first semiconductor die 119, a second semiconductor die 129 stacked on the first semiconductor die 119, a third semiconductor die 139 stacked on the second semiconductor die 129, and a fourth semiconductor die 149 stacked on the third semiconductor die 139. The first semiconductor die 119 may include a first semiconductor chip 110 and a first adhesive layer 115 on the lower surface of the first semiconductor chip 110; the second semiconductor die 129 may include a second semiconductor chip 120 and a second adhesive layer 125 on the lower surface of the second semiconductor chip 120; the third semiconductor die 139 may include a third semiconductor chip 130 and a third adhesive layer 135 on the lower surface of the third semiconductor chip 130; and the fourth semiconductor die 149 may include a fourth semiconductor chip 140 and a fourth adhesive layer 145 on the lower surface of the fourth semiconductor chip 140. The first to fourth semiconductor chips 110, 120, 130, and 140 may be the same memory chip. The first to fourth adhesive layers 115, 125, 135, and 145 may include wafer back laminate (WBL) tapes. In an embodiment, the first to fourth adhesive layers 115, 125, 135, and 145 may include die-attached film (DAF).

[0021] The first semiconductor die 119 can be directly mounted on the packaging substrate 10. The first semiconductor chip 110 can be directly adhered to and stacked on the packaging substrate 10 using a first adhesive layer 115. The horizontal length of the first adhesive layer 115 can be substantially equal to the horizontal length of the first semiconductor chip 110.

[0022] The first semiconductor chip 110 of the first semiconductor die 119 may include a first chip pad 111. The first chip pad 111 may be disposed on the exposed upper surface of the first semiconductor chip 110 near the second side S2 of the package substrate 10. The first chip pad 111 may be electrically connected to the first substrate pad 11 of the package substrate 10 via a first connector 113. The first connector 113 may be disposed near the second side S2 of the package substrate 10.

[0023] The second semiconductor die 129 may be offset and stacked on the first semiconductor die 119 in a first direction D1. The second semiconductor chip 120 may be directly adhered to and stacked on the first semiconductor chip 110 using a second adhesive layer 125. The horizontal length of the second adhesive layer 125 may be substantially equal to the horizontal length of the second semiconductor chip 120. The second semiconductor die 129 may be offset in the first direction D1 to extend beyond the first semiconductor die 119 to approach the first side S1 of the package substrate 10. One side end of the second semiconductor die 129 may protrude laterally from one side end of the first semiconductor die 119 in the first direction D1. A portion of the upper surface of the first semiconductor chip 110 near the second side S2 of the package substrate 10 may be exposed to expose the first chip pad 111 of the first semiconductor chip 110. Another portion of the upper surface of the first semiconductor chip 110 near the first side S1 of the package substrate 10 will not be exposed by the second semiconductor die 129.

[0024] The second semiconductor chip 120 of the second semiconductor die 129 may include a second chip pad 121. The second chip pad 121 may be disposed on the exposed upper surface of the second semiconductor chip 120 near the first side S1 of the package substrate 10. The second chip pad 121 may be electrically connected to the second substrate pad 12 of the package substrate 10 via a second connector 123. The second connector 123 may be disposed near the first side S1 of the package substrate 10.

[0025] The third semiconductor die 139 may be offset and stacked on the second semiconductor die 129 in the second direction D2. The third semiconductor chip 130 may be directly adhered to and stacked on the second semiconductor chip 120 using a third adhesive layer 135. The horizontal length of the third adhesive layer 135 may be substantially equal to the horizontal length of the third semiconductor chip 130. The third semiconductor die 139 may be offset in the second direction D2 to extend beyond the second semiconductor die 129 to approach the second side S2 of the package substrate 10. One side end of the third semiconductor die 139 may protrude laterally from one side end of the second semiconductor die 129 in the second direction D2. A portion of the upper surface of the second semiconductor chip 120 near the first side S1 of the package substrate 10 may be exposed to expose the second chip pad 121 of the second semiconductor chip 120. Another portion of the upper surface of the second semiconductor chip 120 near the second side S2 of the package substrate 10 is not exposed by the third semiconductor die 139. Therefore, by shifting or offsetting the second semiconductor die 129 in the first direction D1, a space Sp1 can be formed between the first semiconductor die 119 and the third semiconductor die 139.

[0026] The third semiconductor chip 130 of the third semiconductor die 139 may include a third chip pad 131. The third chip pad 131 may be disposed on the exposed upper surface of the third semiconductor chip 130 close to the first side S1 of the package substrate 10. The third chip pad 131 may be electrically connected to the third substrate pad 13 of the package substrate 10 via a third connector 133. The third connector 133 may be disposed close to the first side S1 of the package substrate 10.

[0027] A fourth semiconductor die 149 may be offset and stacked on the third semiconductor die 139 in a second direction D2. A fourth semiconductor chip 140 may be directly adhered to and stacked on the third semiconductor chip 130 using a fourth adhesive layer 145. The horizontal length of the fourth adhesive layer 145 may be substantially equal to the horizontal length of the fourth semiconductor chip 140. The fourth semiconductor die 149 may be offset in the second direction D2 to extend beyond the third semiconductor die 139 to approach the second side S2 of the package substrate 10. One side end of the fourth semiconductor die 149 may protrude laterally from the side ends of the first semiconductor die 119 and the third semiconductor die 139 in the second direction D2. A portion of the upper surface of the third semiconductor chip 130 near the first side S1 of the package substrate 10 may be exposed to expose the third chip pad 131 of the third semiconductor chip 130. Another portion of the upper surface of the third semiconductor chip 130 near the second side S2 of the package substrate 10 may not be exposed by the fourth semiconductor die 149.

[0028] The fourth semiconductor chip 140 of the fourth semiconductor die 149 may include a fourth chip pad 141. The fourth chip pad 141 may be disposed on the exposed upper surface of the fourth semiconductor chip 140 close to the second side S2 of the package substrate 10. The fourth chip pad 141 may be electrically connected to the fourth substrate pad 14 of the package substrate 10 via a fourth connector 143. The fourth connector 143 may be disposed close to the second side S2 of the package substrate 10.

[0029] The second semiconductor die 129, the third semiconductor die 139, and the fourth semiconductor die 149 may be offsetly stacked on the first semiconductor die 119 in a three-layer stepped (i.e., cascaded) configuration, which increases sequentially from the first side S1 to the second side S2 of the package substrate 10 in the second direction D2. In an embodiment, the first semiconductor die 119 and the third semiconductor die 139 may be precisely aligned and overlapped perpendicularly to each other.

[0030] As described above, compared to the first side S1 of the packaging substrate 10, the first chip pad 111 of the first semiconductor chip 110, the first connector 113, the fourth chip pad 141 and the fourth connector 143 of the fourth semiconductor chip 140 can be disposed closer to the second side S2 of the packaging substrate 10. Compared to the second side S2 of the packaging substrate 10, the second chip pad 121 of the second semiconductor chip 120, the second connector 123, the third chip pad 131 and the third connector 133 of the third semiconductor chip 130 can be disposed closer to the first side S1 of the packaging substrate 10.

[0031] The semiconductor chip stack 100 may include semiconductor dies 119, 129, 139, and 149 stacked in a vertical zigzag stacking structure. A second semiconductor die 129 may be stacked on the first semiconductor die 119 offset in a first direction D1. A third semiconductor die 139 may be stacked on the second semiconductor die 129 offset in a second direction D2, and a fourth semiconductor die 149 may be stacked on the third semiconductor die 139 offset in the second direction D2.

[0032] The first adhesive layer 115 may have a first thickness t1. The second adhesive layer 125, the third adhesive layer 135, and the fourth adhesive layer 145 may have a second thickness t2. That is, the thicknesses of the second adhesive layer 125, the third adhesive layer 135, and the fourth adhesive layer 145 may be equal to each other. The first thickness t1 may be greater than the second thickness t2. In an embodiment, the second thickness t2 may be equal to or less than half of the first thickness t1. In an embodiment, the first thickness t1 may be greater than 10 micrometers (μm), and the second thickness t2 may be equal to or less than 10 μm. In an embodiment, the thickness may be a vertical thickness, whereby the vertical direction used to measure the vertical thickness is, for example, the stacking direction of the semiconductor chip (i.e., 110, 120, 130, and 140).

[0033] In semiconductor packaging manufacturing processes, the top surface of the packaging substrate can become contaminated. For example, foreign matter may separate from the packaging manufacturing equipment or raw materials and remain on the surface of the packaging substrate. Foreign matter between 5 μm and 10 μm in size can affect the surrounding structure within the semiconductor package. When some foreign matter remains on the packaging substrate, the adhesion between the semiconductor die and the packaging substrate may weaken and decrease. When the size of the foreign matter is larger than the thickness of the adhesive layer, it may apply stress to the semiconductor die while simultaneously contacting both sides of the packaging substrate and the semiconductor die. As a result, defects such as die cracks may occur. Therefore, the adhesive layer should have sufficient thickness to completely bury the foreign matter.

[0034] In this implementation, the thickness of the adhesive layer in the semiconductor package must be limited. In this implementation, the adhesive layer is needed to attach one semiconductor die to another. In this implementation, as the number of stacked semiconductor dies increases, the thickness of the semiconductor package due to the adhesive layer also increases. Therefore, in this implementation, in order to stack many semiconductor dies within a limited space and thickness, the thickness of the adhesive layer must be limited.

[0035] According to an embodiment, the thickness of the first adhesive layer 115 is greater than the size of the foreign matter on the surface of the package substrate 10, but the thicknesses of the second adhesive layer 125, the third adhesive layer 135, and the fourth adhesive layer 145, which are not in contact with the package substrate, are thinner than the thickness of the first adhesive layer 115. Therefore, in this embodiment, the thickness of the semiconductor package 1000A can be minimized.

[0036] Figure 2 This is a schematic side view of a semiconductor package 1000B according to an embodiment of the present disclosure. (Refer to...) Figure 2 The semiconductor package 1000B may include a semiconductor chip stack 100 laminated on a package substrate 10 and an additional semiconductor chip stack 200 laminated on the semiconductor chip stack 100. (The last part, "omitted," is a typo and can be left as is.) Figures 1A to 1C Description of repeating components. The semiconductor package 1000B may also include additional connectors 253, 263, 273, and 283 for electrically connecting the package substrate 10 to an additional semiconductor chip stack 200. Additional connectors 253, 263, 273, and 283 may include a fifth connector 253, a sixth connector 263, a seventh connector 273, and an eighth connector 283. Each of additional connectors 253, 263, 273, and 283 may include bonding leads.

[0037] The packaging substrate 10 may further include additional substrate pads 25, 26, 27, and 28. The additional substrate pads 25, 26, 27, and 28 may include a fifth substrate pad 25, a sixth substrate pad 26, a seventh substrate pad 27, and an eighth substrate pad 28. The fifth substrate pad 25 and the eighth substrate pad 28 may be positioned near the second side S2 of the packaging substrate 10. The sixth substrate pad 26 and the seventh substrate pad 27 may be positioned near the first side S1 of the packaging substrate 10.

[0038] The additional semiconductor chip stack 200 may include additional semiconductor dies 259, 269, 279, and 289. Additional semiconductor dies 259, 269, 279, and 289 may each include additional semiconductor chips 250, 260, 270, and 280 and additional adhesive layers 255, 265, 275, and 285. Additional semiconductor chips 250, 260, 270, and 280 may include a fifth semiconductor chip 250, a sixth semiconductor chip 260, a seventh semiconductor chip 270, and an eighth semiconductor chip 280. Additional adhesive layers 255, 265, 275, and 285 may include a fifth adhesive layer 255, a sixth adhesive layer 265, a seventh adhesive layer 275, and an eighth adhesive layer 285.

[0039] A fifth semiconductor die 259 may be offset and stacked on the fourth semiconductor die 149 in a first direction D1. A fifth semiconductor chip 250 may be directly adhered to and stacked on the fourth semiconductor chip 140 using a fifth adhesive layer 255. The horizontal length of the fifth adhesive layer 255 may be substantially equal to the horizontal length of the fifth semiconductor chip 250. The fifth semiconductor die 259 may be offset in the first direction D1 to extend beyond the fourth semiconductor die 149 to approach the first side S1 of the package substrate 10. One side end of the fifth semiconductor die 259 may protrude laterally from the side end of the first semiconductor die 119 in the first direction D1. A portion of the upper surface of the fourth semiconductor chip 140 near the second side S2 of the package substrate 10 may be exposed to expose the fourth chip pad 141 of the fourth semiconductor chip 140. Another portion of the upper surface of the fourth semiconductor chip 140 near the first side S1 of the package substrate 10 may not be exposed by the fifth semiconductor die 259. Therefore, by shifting or offsetting the fourth semiconductor die 149 in the second direction D2, a space Sp2 can be formed between the third semiconductor die 139 and the fifth semiconductor die 259.

[0040] The fifth semiconductor chip 250 of the third semiconductor die 259 may include a fifth chip pad 251. The fifth chip pad 251 may be disposed on the exposed upper surface of the fifth semiconductor chip 250 close to the second side S2 of the package substrate 10. The fifth chip pad 251 may be electrically connected to the fifth substrate pad 25 of the package substrate 10 via a fifth connector 253. The fifth connector 253 may be disposed close to the second side S2 of the package substrate 10.

[0041] The sixth semiconductor die 269 may be further offset and stacked on the fifth semiconductor die 259 in the first direction D1. The sixth semiconductor chip 260 may be directly adhered and stacked on the fifth semiconductor chip 250 using a sixth adhesive layer 265. The horizontal length of the sixth adhesive layer 265 may be substantially equal to the horizontal length of the sixth semiconductor chip 260. The sixth semiconductor die 269 may be offset in the first direction D1 to extend beyond the fifth semiconductor die 259 to approach the first side S1 of the package substrate 10. One side end of the sixth semiconductor die 269 may protrude laterally from the side end of the fifth semiconductor die 259 in the first direction D1. A portion of the upper surface of the fifth semiconductor chip 250 near the second side S2 of the package substrate 10 may be exposed to expose the fifth chip pad 251 of the fifth semiconductor chip 250. Another portion of the upper surface of the fifth semiconductor chip 250 near the first side S1 of the package substrate 10 may not be exposed by the sixth semiconductor die 269.

[0042] The sixth semiconductor chip 260 of the sixth semiconductor die 269 may include a sixth chip pad 261. The sixth chip pad 261 may be disposed on the exposed upper surface of the sixth semiconductor chip 260 close to the first side S1 of the package substrate 10. The sixth chip pad 261 may be electrically connected to the sixth substrate pad 26 of the package substrate 10 via a sixth connector 263. The sixth connector 263 may be disposed close to the first side S1 of the package substrate 10.

[0043] A seventh semiconductor die 279 may be offset and stacked on the sixth semiconductor die 269 in the second direction D2. A seventh semiconductor chip 270 may be directly adhered to and stacked on the sixth semiconductor chip 260 using a seventh adhesive layer 275. The horizontal length of the seventh adhesive layer 275 may be substantially equal to the horizontal length of the seventh semiconductor chip 270. The seventh semiconductor die 279 may be offset in the second direction D2 to extend beyond the sixth semiconductor die 269 to approach the second side S2 of the package substrate 10. One side end of the seventh semiconductor die 279 may protrude laterally from the side end of the sixth semiconductor die 269 in the second direction D2. A portion of the upper surface of the sixth semiconductor chip 260 near the first side S1 of the package substrate 10 may be exposed to expose the sixth chip pad 261 of the sixth semiconductor chip 260. Another portion of the upper surface of the sixth semiconductor chip 260 near the second side S2 of the package substrate 10 may not be exposed by the seventh semiconductor die 279. Therefore, by shifting or offsetting the sixth semiconductor die 269 in the first direction D1, a space Sp3 can be formed between the fifth semiconductor die 259 and the seventh semiconductor die 279.

[0044] The seventh semiconductor chip 270 of the seventh semiconductor die 279 may include a seventh chip pad 271. The seventh chip pad 271 may be disposed on the exposed upper surface of the seventh semiconductor chip 270 close to the first side S1 of the package substrate 10. The seventh chip pad 271 may be electrically connected to the seventh substrate pad 27 of the package substrate 10 via a seventh connector 273. The seventh connector 273 may be disposed close to the first side S1 of the package substrate 10.

[0045] The eighth semiconductor die 289 may be further offset and stacked on the seventh semiconductor die 279 in the second direction D2. The eighth semiconductor chip 280 may be directly adhered and stacked on the seventh semiconductor chip 270 using an eighth adhesive layer 285. The horizontal length of the eighth adhesive layer 285 may be substantially equal to the horizontal length of the eighth semiconductor chip 280. The eighth semiconductor die 289 may be offset in the second direction D2 to extend beyond the seventh semiconductor die 279 to approach the second side S2 of the package substrate 10. One side end of the eighth semiconductor die 289 may laterally protrude from the side ends of the first semiconductor die 119, the third semiconductor die 139, the fifth semiconductor die 259, and the seventh semiconductor die 279 in the second direction D2. A portion of the upper surface of the seventh semiconductor chip 270 near the first side S1 of the package substrate 10 may be exposed to expose the seventh chip pad 271 of the seventh semiconductor chip 270. Another portion of the upper surface of the seventh semiconductor chip 270 near the second side S2 of the package substrate 10 may not be exposed by the eighth semiconductor die 289.

[0046] The eighth semiconductor chip 280 of the eighth semiconductor die 289 may include an eighth chip pad 281. The eighth chip pad 281 may be disposed on the exposed upper surface of the eighth semiconductor chip 280, close to the second side S2 of the package substrate 10. The eighth chip pad 281 may be electrically connected to the eighth substrate pad 28 of the package substrate 10 via an eighth connector 283. The eighth connector 283 may be disposed close to the second side S2 of the package substrate 10.

[0047] The fourth semiconductor die 149, the fifth semiconductor die 259, and the sixth semiconductor die 269 can be stacked on the third semiconductor die 139 in a three-layer stepped configuration (i.e., cascaded configuration) that rises sequentially from the second side S2 to the first side S1 of the packaging substrate 10. The sixth semiconductor die 269, the seventh semiconductor die 279, and the eighth semiconductor die 289 can be stacked on the fifth semiconductor die 259 in a three-layer stepped configuration (i.e., cascaded configuration) that rises sequentially from the first side S1 to the second side S2 of the packaging substrate 10 in the second direction D2. In this embodiment, the first semiconductor die 119, the third semiconductor die 139, the fifth semiconductor die 259, and the seventh semiconductor die 279 can be perpendicular to each other and accurately aligned and overlapped. In this embodiment, the second semiconductor die 129 and the sixth semiconductor die 269 can be perpendicular to each other and accurately aligned and overlapped. In this embodiment, the fourth semiconductor die 149 and the eighth semiconductor die 289 can be perpendicular to each other and accurately aligned and overlapped.

[0048] The first chip pad 111, the first connector 113, the first substrate pad 11, the fourth chip pad 141, the fourth connector 143, the fourth substrate pad 14, the fifth chip pad 251, the fifth connector 253, the fifth substrate pad 25, the eighth chip pad 281, the eighth connector 283, and the eighth substrate pad 28 may be disposed close to the second side S2 of the packaging substrate 10. The second chip pad 121, the second connector 123, the second substrate pad 12, the third chip pad 131, the third connector 133, the third substrate pad 13, the sixth chip pad 261, the sixth connector 263, the sixth substrate pad 26, the seventh chip pad 271, the seventh connector 273, and the seventh substrate pad 27 may be disposed close to the first side S1 of the packaging substrate 10.

[0049] The additional semiconductor chip stack 200 may include semiconductor dies 259, 269, 279, and 289 stacked in a vertically zigzag stack structure. A fifth semiconductor die 259 may be stacked on top of a fourth semiconductor die 149 offset in a first direction D1. A sixth semiconductor die 269 may be stacked on top of the fifth semiconductor die 259 offset in the first direction D1. A seventh semiconductor die 279 may be stacked on top of the sixth semiconductor die 269 offset in a second direction D2. An eighth semiconductor die 289 may be stacked on top of the seventh semiconductor die 279 offset in the second direction D2. In the vertical zigzag stacked structure, the fifth semiconductor die 259 and the eighth semiconductor die 289 are offset stacked such that the fifth chip pad 251 and the eighth chip pad 281 are disposed close to the second side S2 of the package substrate 10, and the sixth semiconductor die 269 and the seventh semiconductor die 279 are offset stacked such that the sixth chip pad 261 and the seventh chip pad 271 are disposed close to the first side S1 of the package substrate 10.

[0050] In one embodiment, the fifth to eighth adhesive layers 255, 265, 275, and 285 may include a WBL. In another embodiment, the fifth adhesive layer 255, the sixth adhesive layer 265, the seventh adhesive layer 275, and the eighth adhesive layer 285 may have a second thickness t2. In yet another embodiment, the fifth to eighth adhesive layers 255, 265, 275, and 285 may include a DAF.

[0051] Figures 3A to 3F This is a view illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0052] Reference Figure 3A The method may include the following steps: fabricating a first wafer W1 and a second wafer W2; forming a first adhesive film L1 on the back side BS1 (i.e., the passive surface) of the first wafer W1; and forming a second adhesive film L2 on the back side BS2 (i.e., the passive surface) of the second wafer W2. The first wafer W1 and the second wafer W2 may respectively include transistors, electrical interconnects, and bonding pads formed on the front sides FS1 and FS2. The first wafer W1 and the second wafer W2 may be wafers thinned by performing a backside polishing process. The first adhesive film L1 and the second adhesive film L2 may include a wafer blank (WBL). In an embodiment, the first adhesive film L1 and the second adhesive film L2 may include a die bonded atomizer (DAF). The first adhesive film L1 may have a first thickness t1, and the second adhesive film L2 may have a second thickness t2. The first thickness t1 may be thicker than the second thickness t2. For example, the first thickness t1 may be equal to or greater than 15 μm, more specifically, about equal to or greater than 20 μm. The second thickness t2 may be equal to or less than 15 μm, more specifically, about equal to or less than 10 μm.

[0053] Reference Figure 3B The method may further include the following steps: performing a dicing process to separate a first wafer W1 and a first adhesive film L1 to manufacture a plurality of first semiconductor dies 119, and separating a second wafer W2 and a second adhesive film L2 to manufacture a plurality of second to fourth semiconductor dies 129, 139 and 149. The dicing process may include a stealth dicing process. In an embodiment, the dicing process may include a sawing process. The first semiconductor die 119 may include a first semiconductor chip 110 and a first adhesive layer 115 on the lower surface (i.e., back surface) of the first semiconductor chip 110. The second semiconductor die 129 may include a second semiconductor chip 120 and a second adhesive layer 125 on the lower surface (i.e., back surface) of the second semiconductor chip 120. The third semiconductor die 139 may include a third semiconductor chip 130 and a third adhesive layer 135 on the lower surface (i.e., back surface) of the third semiconductor chip 130. The fourth semiconductor die 149 may include a fourth semiconductor chip 140 and a fourth adhesive layer 145 on the lower surface (i.e., back surface) of the fourth semiconductor chip 140.

[0054] Reference Figure 3C The method may further include the following steps: performing a first chip stacking process to mount a first semiconductor die 119 onto a packaging substrate 10. The first semiconductor chip 110 may be adhered to and mounted on the packaging substrate 10 using a first adhesive layer 115. The packaging substrate 10 may have a first side S1 and a second side S2. The first side S1 and the second side S2 may be opposite to each other. The packaging substrate 10 may include a first substrate pad 11, a second substrate pad 12, a third substrate pad 13, and a fourth substrate pad 14 disposed on the upper surface of the packaging substrate 10. The first substrate pad 11 and the fourth substrate pad 14 may be disposed near the second side S2 of the packaging substrate 10, and the second substrate pad 12 and the third substrate pad 13 may be disposed near the first side S1 of the packaging substrate 10. The first semiconductor chip 110 may include a first chip pad 111 disposed on the upper surface of the first semiconductor chip 110 near the second side S2 of the packaging substrate 10.

[0055] Reference Figure 3D The method may further include the following steps: performing a first connection process to form a first connector 113 that electrically connects a first chip pad 111 of the first semiconductor chip 110 to a first substrate pad 11 of the package substrate 10. The first connector 113 may include bonding leads. The first connector 113 may be disposed near a second side S2 of the package substrate 10. The first connection process may include a first wire bonding process.

[0056] Reference Figure 3EThe method may further include the following steps: sequentially stacking a second semiconductor die 129, a third semiconductor die 139, and a fourth semiconductor die 149 on a first semiconductor die 119 by performing a second chip stacking process. The second semiconductor die 129 may be offset in a first direction D1 from the first semiconductor chip 110 toward a first side S1 of the package substrate 10, such that a portion of the upper surface on which the first chip pad 111 is disposed is exposed. The second semiconductor chip 120 may include a second chip pad 121 disposed on the upper surface of the second semiconductor chip 120 close to the first side S1 of the package substrate 10. The third semiconductor die 139 may be offset in a second direction D2 from the second semiconductor chip 120 toward a second side S2 of the package substrate 10, such that a portion of the upper surface on which the second chip pad 121 is disposed is exposed. The third semiconductor chip 130 may include a third chip pad 131 disposed on the upper surface of the third semiconductor chip 130 close to the first side S1 of the package substrate 10. The fourth semiconductor die 149 may be offset from the third semiconductor chip 130 in the second direction D2, such that a portion of the upper surface on which the third chip pad 131 is disposed is exposed. The fourth semiconductor chip 140 may include a fourth chip pad 141 disposed on its upper surface close to the second side S2 of the package substrate 10. The first direction D1 and the second direction D2 may be opposite to each other.

[0057] Reference Figure 3FThe method may further include the following steps: performing a second connection process to form a second connector 123 electrically connecting a second chip pad 121 of a second semiconductor chip 120 to a second substrate pad 12 of a package substrate 10, a third connector 133 electrically connecting a third chip pad 131 of a third semiconductor chip 130 to a third substrate pad 13 of a package substrate 10, and a fourth connector 143 electrically connecting a fourth chip pad 141 of a fourth semiconductor chip 140 to a fourth substrate pad 14 of a package substrate 10. Each of the second connector 123, the third connector 133, and the fourth connector 143 may include bonding leads. The second connection process may include a second wire bonding process. The second connection process may include the sequential formation of the second connector 123, the third connector 133, and the fourth connector 143. The second connector 123 and the third connector 133 may be formed near a first side S1 of the package substrate 10, and the fourth connector 143 may be formed near a second side S2 of the package substrate 10. The second chip pad 121 of the second semiconductor chip 120, the third chip pad 131 of the third semiconductor chip 130, and the third chip pad 131 of the fourth semiconductor chip 140 are all exposed, so that the second connector 123, the third connector 133, and the fourth connector 143 can be continuously formed in the second connection process. A semiconductor chip stack 100 including the first semiconductor die 119, the second semiconductor die 129, the third semiconductor die 139, and the fourth semiconductor die 149 can be mounted and stacked on the packaging substrate 10.

[0058] Subsequently, refer to Figure 1A The method may further include the following steps: performing a molding process to form a molded component 90 covering the semiconductor chip stack 100; and performing a solder ball mounting process to form an external connector 19.

[0059] A method for manufacturing a semiconductor package according to embodiments of the present disclosure may include the following steps: sequentially performing a first chip stacking process, a first interconnection process, a second chip stacking process, and a second interconnection process. The first chip stacking process may include stacking a lowermost first semiconductor die 119 on a package substrate 10. The first interconnection process may include forming a first connector 113 that electrically connects a first chip pad 111 of the first semiconductor chip 110 of the first semiconductor die 119 to a first substrate pad 11 of the package substrate 10. The second chip stacking process may include sequentially stacking second to fourth semiconductor dies 129, 139, and 149 on the first semiconductor die 119. The second interconnection process may include electrically connecting second to fourth chip pads 121, 131, and 141 of the second to fourth semiconductor dies 129, 139, and 149 to second to fourth substrate pads 12, 13, and 14 of the package substrate 10, respectively. In the first chip stacking process, the first semiconductor die 119 may be adhered to and stacked using a first adhesive layer 115 having a first thickness t1. In the second chip stacking process, the second to fourth semiconductor dies 129, 139, and 149 can be adhered and stacked using second to fourth adhesive layers 125, 135, and 145, each having a second thickness t2. That is, referring to... Figures 1A to 1C The first thickness t1 may be thicker than the second thickness t2. The first to fourth semiconductor chips 110, 120, 130, and 140 may have substantially the same thickness Tc. In this embodiment, because the lamination process is performed very precisely, if the thicknesses of the semiconductor dies 119, 129, 139, and 149 (i.e., the adhesive layers 115, 125, 135, and 145) are not the same, then the semiconductor dies 119, 129, 139, and 149 cannot be laminated by performing the same lamination process. In this embodiment, if the thicknesses of the adhesive layers 115, 125, 135, and 145 are different from each other, then the pressure, temperature, process time, and other process conditions performed on the chip stack are not the same, so the semiconductor dies 119, 129, 139, and 149 cannot be stably laminated. In embodiments of this disclosure, the second to fourth adhesive layers 125, 135, and 145 of the second to fourth semiconductor dies 129, 139, and 149 stacked in the second chip stacking process have substantially the same thickness t2. Therefore, according to the various embodiments described in this disclosure, semiconductor dies 119, 129, 139, and 149 with different thicknesses T1 and T2 can be stably stacked.

[0060] Figures 4A to 4E This is a view illustrating a method of manufacturing a semiconductor package according to an embodiment of the present disclosure.

[0061] Reference Figure 4A A method for manufacturing a semiconductor package may include the following steps: performing a reference... Figure 3AThe described process involves separating a first wafer W1 and a first adhesive film L1 to fabricate a plurality of first semiconductor dies 119; and separating a second wafer W2 and a second adhesive film L2 to fabricate a plurality of second to eighth semiconductor dies 129, 139, 259, 269, 279, and 289, respectively. A fifth semiconductor die 259 may include a fifth semiconductor chip 250 and a fifth adhesive layer 255 on the lower surface (back side) of the fifth semiconductor chip 250. A sixth semiconductor die 269 may include a sixth semiconductor chip 260 and a sixth adhesive layer 265 on the lower surface (back side) of the sixth semiconductor chip 260. A seventh semiconductor die 279 may include a seventh semiconductor chip 270 and a seventh adhesive layer 275 on the lower surface (back side) of the seventh semiconductor chip 270. An eighth semiconductor die 289 may include an eighth semiconductor chip 280 and an eighth adhesive layer 285 on the lower surface (back side) of the eighth semiconductor chip 280.

[0062] Reference Figure 4B The method may further include the following steps: by executing a reference Figures 3C to 3F The described process involves sequentially stacking a fifth semiconductor die 259 and a sixth semiconductor die 269 on a fourth semiconductor die 149 of a first semiconductor chip stack 100. The fifth semiconductor die 259 may be offset from the fourth semiconductor chip 140 in a first direction D1 of the package substrate 10, such that a portion of the upper surface on which the fourth chip pad 141 is disposed is exposed. The fifth semiconductor chip 250 may include a fifth chip pad 251 disposed on the upper surface near the second side S2 of the package substrate 10. The sixth semiconductor die 269 may be offset from the fifth semiconductor chip 250 in the first direction D1, such that a portion of the upper surface on which the fifth chip pad 251 is disposed is exposed. The sixth semiconductor chip 260 may include a sixth chip pad 261 disposed on the upper surface near the first side S1 of the package substrate 10.

[0063] Reference Figure 4C The method may further include the following steps: performing a third connection process to electrically connect the fifth chip pad 251 of the fifth semiconductor chip 250 to the fifth substrate pad 25 of the package substrate 10 using a fifth connector 253, and electrically connecting the sixth chip pad 261 of the sixth semiconductor chip 260 to the sixth substrate pad 26 of the package substrate 10 using a sixth connector 263. Each of the fifth connector 253 and the sixth connector 263 may include a bonding lead. The third connection process may include a third lead bonding process. The third connection process may include continuously forming the fifth connector 253 and the sixth connector 263. The fifth connector 253 may be formed near the second side S2 of the package substrate 10, and the sixth connector 263 may be formed near the first side S1 of the package substrate 10.

[0064] Reference Figure 4D The method may further include the following steps: performing a fourth chip stacking process to sequentially stack a seventh semiconductor die 279 and an eighth semiconductor die 289 on a sixth semiconductor die 269. The seventh semiconductor die 279 may be offset from the sixth semiconductor die 260 in a second direction D2, such that a portion of the upper surface of the sixth chip pad 261 on which the sixth semiconductor die 260 is disposed is exposed. The seventh semiconductor die 270 may include a seventh chip pad 271 disposed on an upper surface near a first side S1 of the package substrate 10. The eighth semiconductor die 289 may be offset from the seventh semiconductor die 270 in a second direction D2, such that a portion of the upper surface of the seventh chip pad 271 on which the seventh semiconductor die 270 is disposed is exposed. The eighth semiconductor die 280 may include an eighth chip pad 281 disposed on an upper surface near a second side S2 of the package substrate 10.

[0065] Reference Figure 4E The method may further include the following steps: performing a fourth connection process to electrically connect the seventh chip pad 271 of the seventh semiconductor chip 270 of the seventh semiconductor die 279 to the seventh substrate pad 27 of the package substrate 10 using a seventh connector 273, and electrically connecting the eighth chip pad 281 of the eighth semiconductor chip 280 of the eighth semiconductor die 289 to the eighth substrate pad 28 of the package substrate 10 using an eighth connector 283. Each of the seventh connector 273 and the eighth connector 283 may include a bonding lead. The fourth connection process may include a fourth wire bonding process. The fourth connection process may include sequentially forming the seventh connector 273 and the eighth connector 283. The seventh connector 273 may be disposed near a first side S1 of the package substrate 10, and the eighth connector 283 may be disposed near a second side S2 of the package substrate 10. An additional semiconductor chip stack 200 including a fifth semiconductor die 259, a sixth semiconductor die 269, a seventh semiconductor die 279, and an eighth semiconductor die 289 may be mounted and stacked on the semiconductor chip stack 100.

[0066] Subsequently, refer to Figure 2 The method may further include the following steps: performing a molding process to form a molded component 90 covering the semiconductor chip stack 100 and 200; and performing a solder ball mounting process to form an external connector 19.

[0067] According to embodiments of this disclosure, even if foreign matter is present on the packaging substrate, it can be covered by an adhesive layer of sufficient thickness. According to embodiments of this disclosure, by forming a thick adhesive layer only on the bottommost semiconductor die, the total height of the space between the stacked semiconductor dies can be kept to a minimum.

[0068] According to embodiments of this disclosure, by sequentially stacking three semiconductor dies in a single stacking process, the number of chip stacking processes can be prevented from increasing.

[0069] Although this disclosure has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of this disclosure as defined in the following claims.

[0070] Cross-references to related applications

[0071] This application claims priority to Korean Patent Application No. 10-2024-0130881, filed with the Korean Intellectual Property Office on September 26, 2024, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor package, the semiconductor package comprising: a package substrate; a first semiconductor die mounted over the package substrate; a second semiconductor die offset-stacked over the first semiconductor die in a first direction; a third semiconductor die offset-stacked over the second semiconductor die in a second direction, wherein the first direction is opposite to the second direction; and a fourth semiconductor die offset-stacked over the third semiconductor die in the second direction, wherein, the first semiconductor die comprises a first semiconductor chip and a first adhesive layer, the second semiconductor die comprises a second semiconductor chip and a second adhesive layer, the third semiconductor die comprises a third semiconductor chip and a third adhesive layer, the fourth semiconductor die comprises a fourth semiconductor chip and a fourth adhesive layer, the first adhesive layer has a first thickness, each of the second, third, and fourth adhesive layers has a second thickness, and the first thickness is thicker than the second thickness.

2. The semiconductor package of claim 1, wherein the package substrate comprises: a first side and a second side opposite to the first side; a first substrate pad disposed closer to the second side than to the first side; a second substrate pad and a third substrate pad disposed closer to the first side than to the second side; and a fourth substrate pad disposed closer to the second side than to the first side, wherein, the first semiconductor die comprises a first chip pad disposed over an upper surface of the first semiconductor chip closer to the second side than to the first side, the second semiconductor die comprises a second chip pad disposed over an upper surface of the second semiconductor chip closer to the first side than to the second side, the third semiconductor die comprises a third chip pad disposed over an upper surface of the third semiconductor die closer to the first side than to the second side, and the fourth semiconductor die comprises a fourth chip pad disposed over an upper surface of the fourth semiconductor die closer to the second side than to the first side.

3. The semiconductor package of claim 2, wherein, the first chip pad is electrically connected to the first substrate pad by a first connector, the second chip pad is electrically connected to the second substrate pad by a second connector, the third chip pad is electrically connected to the third substrate pad by a third connector, the fourth chip pad is electrically connected to the fourth substrate pad by a fourth connector, the first and fourth connectors are disposed closer to the second side than to the first side, and the second and third connectors are disposed closer to the first side than to the second side.

4. The semiconductor package of claim 1, wherein the first thickness is equal to or greater than 20 pm, and the second thickness is equal to or less than 10 pm.

5. The semiconductor package of claim 1, wherein a vertical thickness of each of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip is equal to or less than 60 pm.

6. The semiconductor package of claim 1, further comprising: a fifth semiconductor die offset-stacked in the first direction over the fourth semiconductor die; a sixth semiconductor die offset-stacked in the first direction over the fifth semiconductor die; a seventh semiconductor die offset-stacked in the second direction over the sixth semiconductor die; and an eighth semiconductor die offset-stacked in the second direction over the seventh semiconductor die.

7. The semiconductor package of claim 6, wherein the second semiconductor die, the third semiconductor die, and the fourth semiconductor die are offset-stacked to form a first three-tiered staircase form, the fourth semiconductor die, the fifth semiconductor die, and the sixth semiconductor die are offset-stacked to form a second three-tiered staircase form, and the sixth semiconductor die, the seventh semiconductor die, and the eighth semiconductor die are offset-stacked to form a third three-tiered staircase form.

8. The semiconductor package of claim 6, wherein the fifth semiconductor die includes a fifth semiconductor chip and a fifth adhesive layer over a lower surface of the fifth semiconductor chip, the sixth semiconductor die includes a sixth semiconductor chip and a sixth adhesive layer over a lower surface of the sixth semiconductor chip, the seventh semiconductor die includes a seventh semiconductor chip and a seventh adhesive layer over a lower surface of the seventh semiconductor chip, the eighth semiconductor die includes an eighth semiconductor chip and an eighth adhesive layer over a lower surface of the eighth semiconductor chip, wherein each of the fifth adhesive layer, the sixth adhesive layer, the seventh adhesive layer, and the eighth adhesive layer has the second thickness.

9. The semiconductor package of claim 8, the package substrate includes: wherein, a first side and a second side opposite the first side; a first substrate pad, a fourth substrate pad, a fifth substrate pad, and an eighth substrate pad disposed closer to the second side than the first side; and a second substrate pad, a third substrate pad, a sixth substrate pad, and a seventh substrate pad disposed closer to the first side than the second side, wherein the first semiconductor die includes a first chip pad disposed over an upper surface of the first semiconductor chip closer to the second side than the first side, the second semiconductor die includes a second chip pad disposed over an upper surface of the second semiconductor chip closer to the first side than the second side, the third semiconductor die includes a third chip pad disposed over an upper surface of the third semiconductor chip closer to the first side than the second side, the fourth semiconductor die includes a fourth chip pad disposed over an upper surface of the fourth semiconductor chip closer to the first side than the second side, the fifth semiconductor die includes a fifth chip pad disposed over an upper surface of the fifth semiconductor chip closer to the first side than the second side, the sixth semiconductor die includes a sixth chip pad disposed over an upper surface of the sixth semiconductor chip closer to the first side than the second side, the seventh semiconductor die includes a seventh chip pad disposed over an upper surface of the seventh semiconductor chip closer to the first side than the second side, and the eighth semiconductor die includes an eighth chip pad disposed over an upper surface of the eighth semiconductor chip closer to the first side than the second side. the fourth semiconductor die includes a fourth chip pad disposed over an upper surface of the fourth semiconductor die closer to the second side than to the first side, the fifth semiconductor die includes a fifth chip pad disposed over an upper surface of the fifth semiconductor die closer to the second side than to the first side, the sixth semiconductor die includes a sixth chip pad disposed over an upper surface of the sixth semiconductor die closer to the first side than to the second side, the seventh semiconductor die includes a seventh chip pad disposed over an upper surface of the seventh semiconductor die closer to the first side than to the second side, and the eighth semiconductor die includes an eighth chip pad disposed over an upper surface of the eighth semiconductor die closer to the second side than to the first side, wherein the first chip pad, the second chip pad, the third chip pad, the fourth chip pad, the fifth chip pad, the sixth chip pad, the seventh chip pad, and the eighth chip pad are electrically connected to the first substrate pad, the second substrate pad, the third substrate pad, the fourth substrate pad, the fifth substrate pad, the sixth substrate pad, the seventh substrate pad, and the eighth substrate pad, respectively, using a first connector, a second connector, a third connector, a fourth connector, a fifth connector, a sixth connector, a seventh connector, and an eighth connector, wherein the first connector, the fourth connector, the fifth connector, and the eighth connector are disposed closer to the second side than to the first side, wherein the second connector, the third connector, the sixth connector, and the seventh connector are disposed closer to the first side than to the second side.

10. The semiconductor package of claim 6, wherein a first space between the third semiconductor die and the fifth semiconductor die is formed by displacing the fourth semiconductor die, and a second space between the fifth semiconductor die and the seventh semiconductor die is formed by displacing the sixth semiconductor die.

11. A semiconductor package, comprising: a package substrate; a first semiconductor chip mounted over the package substrate; a second semiconductor chip offset stacked over the first semiconductor chip in a first direction; a third semiconductor chip offset stacked over the second semiconductor chip in a second direction; and a fourth semiconductor chip offset stacked over the third semiconductor chip in the second direction, wherein the package substrate includes a first side, a second side, and a first substrate pad, a second substrate pad, a third substrate pad, and a fourth substrate pad, wherein the first side is opposite the second side, wherein the first substrate pad and the fourth substrate pad are disposed closer to the second side than to the first side, wherein the second substrate pad and the third substrate pad are disposed closer to the first side than to the second side. wherein the second substrate pad and the third substrate pad are disposed closer to the first side than to the second side, wherein the first semiconductor chip includes a first chip pad disposed closer to the second side than to the first side, wherein the second semiconductor chip includes a second chip pad disposed closer to the first side than to the second side, wherein the third semiconductor chip includes a third chip pad disposed closer to the first side than to the second side, and wherein the fourth semiconductor chip includes a fourth chip pad disposed closer to the second side than to the first side.

12. The semiconductor package of claim 11, wherein the first chip pad and the first substrate pad are electrically connected to each other by a first connector, wherein the second chip pad and the second substrate pad are electrically connected to each other by a second connector, wherein the third chip pad and the third substrate pad are electrically connected to each other by a third connector, wherein the fourth chip pad and the fourth substrate pad are electrically connected to each other by a fourth connector, wherein the first connector and the fourth connector are disposed closer to the second side than to the first side, and wherein the second connector and the third connector are disposed closer to the first side than to the second side.

13. The semiconductor package of claim 11, wherein the first semiconductor chip is directly mounted on the package substrate using a first adhesive layer, wherein the second semiconductor chip is directly stacked on the first semiconductor chip using a second adhesive layer, wherein the third semiconductor chip is directly stacked on the second semiconductor chip using a third adhesive layer, wherein the fourth semiconductor chip is directly stacked on the third semiconductor chip using a fourth adhesive layer, wherein the first adhesive layer has a first thickness, wherein each of the second, third, and fourth adhesive layers has a second thickness, and wherein the first thickness is thicker than the second thickness.

14. The semiconductor package of claim 13, further comprising: a fifth semiconductor chip directly offset stacked on the fourth semiconductor chip in the first direction; a sixth semiconductor chip directly offset stacked on the fifth semiconductor chip in the first direction; a seventh semiconductor chip directly offset stacked on the sixth semiconductor chip in the second direction; and an eighth semiconductor chip directly offset stacked on the seventh semiconductor chip in the second direction, wherein the fifth semiconductor chip includes a fifth chip pad disposed closer to the second side than to the first side, wherein the sixth semiconductor chip includes a sixth chip pad disposed closer to the first side than to the second side, wherein the seventh semiconductor chip includes a seventh chip pad disposed closer to the first side than to the second side, ​ wherein the eighth semiconductor chip includes an eighth chip pad disposed closer to the second side than to the first side, wherein the package substrate further includes a fifth substrate pad disposed closer to the second side than to the first side, a sixth substrate pad disposed closer to the first side than to the second side, a seventh substrate pad disposed closer to the first side than to the second side, and an eighth substrate pad disposed closer to the second side than to the first side, wherein the fifth chip pad and the fifth substrate pad are electrically connected to each other by a fifth connector, wherein the sixth chip pad and the sixth substrate pad are electrically connected to each other by a sixth connector, wherein the seventh chip pad and the seventh substrate pad are electrically connected to each other by a seventh connector, and wherein the eighth chip pad and the eighth substrate pad are electrically connected to each other by an eighth connector.

15. The semiconductor package of claim 13, wherein the first thickness is equal to or greater than 20 pm, and the second thickness is equal to or less than 10 pm.

16. The semiconductor package of claim 13, wherein a vertical thickness of each of the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip is equal to or less than 60 pm.

17. A method of manufacturing a semiconductor package, the method comprising the steps of: mounting a first semiconductor die over a package substrate, forming first connectors electrically connecting the first semiconductor die to the package substrate, stacking a second semiconductor die offset in a first direction over the first semiconductor die, stacking a third semiconductor die offset in a second direction over the second semiconductor die, stacking a fourth semiconductor die offset in the second direction over the third semiconductor die, forming second connectors electrically connecting the second semiconductor die to the package substrate, forming third connectors electrically connecting the third semiconductor die to the package substrate, and forming fourth connectors electrically connecting the fourth semiconductor die to the package substrate.

18. The method of claim 17, wherein, the package substrate includes; a first side and a second side; and a first substrate pad, a second substrate pad, a third substrate pad, and a fourth substrate pad, wherein, the first substrate pad and the fourth substrate pad are disposed closer to the first side than to the second side, the second substrate pad and the third substrate pad are disposed closer to the second side than to the first side, and the first substrate pad to the fourth substrate pad are electrically connected to the first semiconductor die to the fourth semiconductor die, respectively, by the first connector to the fourth connector.

19. The method of claim 18, wherein, the first semiconductor die includes a first semiconductor chip and a first adhesive layer over a lower surface of the first semiconductor chip, the second semiconductor die includes a second semiconductor chip and a second adhesive layer over a lower surface of the second semiconductor chip, the third semiconductor die includes a third semiconductor chip and a third adhesive layer over a lower surface of the third semiconductor chip, and the fourth semiconductor die includes a fourth semiconductor chip and a fourth adhesive layer over a lower surface of the fourth semiconductor chip. the third semiconductor die includes a third semiconductor chip and a third adhesive layer over a lower surface of the third semiconductor chip, and the fourth semiconductor die includes a fourth semiconductor chip and a fourth adhesive layer over a lower surface of the fourth semiconductor chip, the first adhesive layer has a first thickness, each of the second adhesive layer to the fourth adhesive layer has a second thickness, the first thickness is thicker than the second thickness.

20. The method of claim 19, wherein the first semiconductor die includes a first chip pad disposed over an upper surface of the first semiconductor chip closer to the second side than to the first side, wherein the second semiconductor die includes a second chip pad disposed over an upper surface of the second semiconductor chip closer to the first side than to the second side, wherein the third semiconductor die includes a third chip pad disposed over an upper surface of the third semiconductor chip closer to the first side than to the second side, wherein the fourth semiconductor die includes a fourth chip pad disposed over an upper surface of the fourth semiconductor chip closer to the second side than to the first side, and wherein the first chip pad to the fourth chip pad are respectively electrically connected to the first substrate pad to the fourth substrate pad through the first connector to the fourth connector.

21. The method of claim 19, wherein the first thickness is equal to or greater than 20 pm, and the second thickness is equal to or less than 10 pm.

22. The method of claim 19, wherein a vertical thickness of each of the first semiconductor chip to the fourth semiconductor chip is equal to or less than 60 pm.

23. The method of claim 17, stacking a fifth semiconductor die over the fourth semiconductor die offset in the first direction, stacking a sixth semiconductor die over the fifth semiconductor die offset in the first direction, forming a fifth connector electrically connecting the fifth semiconductor die to the package substrate, forming a sixth connector electrically connecting the sixth semiconductor die to the package substrate, stacking a seventh semiconductor die over the sixth semiconductor die offset in the second direction, stacking an eighth semiconductor die over the seventh semiconductor die offset in the second direction, forming a seventh connector electrically connecting the seventh semiconductor die to the package substrate, and forming an eighth connector electrically connecting the eighth semiconductor die to the package substrate.

24. The method of claim 23, wherein the fifth semiconductor die includes a fifth semiconductor chip and a fifth adhesive layer disposed over a lower surface of the fifth semiconductor chip, the sixth semiconductor die includes a sixth semiconductor chip and a sixth adhesive layer disposed over a lower surface of the sixth semiconductor chip, the seventh semiconductor die includes a seventh semiconductor chip and a seventh adhesive layer disposed over a lower surface of the seventh semiconductor chip, the eighth semiconductor die includes an eighth semiconductor chip and an eighth adhesive layer disposed over a lower surface of the eighth semiconductor chip, wherein each of the fifth adhesive layer to the eighth adhesive layer has a second thickness.

25. A method of manufacturing a semiconductor package, the method comprising: forming a first adhesive film having a first thickness over a back surface of a first wafer, forming a second adhesive film having a second thickness over a back surface of a second wafer, dicing the first wafer and the first adhesive film to form a first semiconductor die having a first semiconductor chip and a first adhesive layer, dicing the second wafer and the second adhesive film to form a second semiconductor die, a third semiconductor die, and a fourth semiconductor die having a second semiconductor chip, a third semiconductor chip, and a fourth semiconductor chip, and a second adhesive layer, a third adhesive layer, and a fourth adhesive layer, respectively, mounting the first semiconductor die on a package substrate, and stacking the second semiconductor die, the third semiconductor die, and the fourth semiconductor die over the first semiconductor die in order, wherein the first adhesive film has a first thickness, the second adhesive film has a second thickness, and the first thickness is thicker than the second thickness.

26. The method of claim 25, wherein the second semiconductor die is offset stacked in a first direction on the first semiconductor die, the third semiconductor die is offset stacked in a second direction on the second semiconductor die, the fourth semiconductor die is offset stacked in the second direction on the third semiconductor die, and the first direction and the second direction are opposite to each other.

27. The method of claim 25, wherein, the package substrate includes: a first side and a second side; and a first substrate pad, a second substrate pad, a third substrate pad, and a fourth substrate pad, wherein the first substrate pad and the fourth substrate pad are disposed closer to the first side than the second side, the second substrate pad and the third substrate pad are disposed closer to the second side than the first side, and the first substrate pad, the second substrate pad, the third substrate pad, and the fourth substrate pad are electrically connected to the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die using a first connector, a second connector, a third connector, and a fourth connector, respectively.

28. The method of claim 27, wherein the first semiconductor die includes a first semiconductor chip and a first adhesive layer over a lower surface of the first semiconductor chip, the second semiconductor die includes a second semiconductor chip and a second adhesive layer over a lower surface of the second semiconductor chip, the third semiconductor die includes a third semiconductor chip and a third adhesive layer over a lower surface of the third semiconductor chip, the fourth semiconductor die includes a fourth semiconductor chip and a fourth adhesive layer over a lower surface of the fourth semiconductor chip, the first adhesive layer has the first thickness, and the second adhesive layer has the second thickness. Each of the second to fourth adhesive layers has the second thickness.

29. The method of claim 28, wherein, the first semiconductor die includes first chip pads disposed over an upper surface of the first semiconductor chip closer to the second side than to the first side, the second semiconductor die includes second chip pads disposed over an upper surface of the second semiconductor chip closer to the first side than to the second side, the third semiconductor die includes third chip pads disposed over an upper surface of the third semiconductor chip closer to the first side than to the second side, the fourth semiconductor die includes fourth chip pads disposed over an upper surface of the fourth semiconductor chip closer to the second side than to the first side, and the first to fourth chip pads are electrically connected to the first to fourth substrate pads, respectively, by the first to fourth connectors.

30. The method of claim 25, further comprising the steps of: stacking a fifth semiconductor die offset in a first direction over the fourth semiconductor die, stacking a sixth semiconductor die offset in the first direction over the fifth semiconductor die, forming fifth connectors electrically connecting the fifth semiconductor die to the package substrate, forming sixth connectors electrically connecting the sixth semiconductor die to the package substrate, stacking a seventh semiconductor die offset in a second direction over the sixth semiconductor die, stacking an eighth semiconductor die offset in the second direction over the seventh semiconductor die, forming seventh connectors electrically connecting the seventh semiconductor die to the package substrate, and forming eighth connectors electrically connecting the eighth semiconductor die to the package substrate.

31. The method of claim 30, wherein, the fifth, sixth, seventh, and eighth semiconductor dies respectively include: fifth, sixth, seventh, and eighth semiconductor chips; and fifth, sixth, seventh, and eighth adhesive layers disposed over lower surfaces of the fifth, sixth, seventh, and eighth semiconductor chips, respectively, wherein each of the fifth, sixth, seventh, and eighth adhesive layers has the second thickness.

32. The method of claim 25, wherein, the first thickness is equal to or greater than 20 pm, and the second thickness is equal to or less than 10 pm.

33. The method of claim 25, wherein a vertical thickness of each of the first to fourth semiconductor chips is equal to or less than 60 pm.

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