Driving chip, display device and driving method thereof

Abstract

The invention discloses a driving chip, a display device and a driving method thereof. The driving chip includes: a data signal transmission circuit configured to sequentially output a plurality of data signal groups; each data signal group comprises a plurality of data signals; n data signal groups continuously output in the plurality of data signal groups form a driving signal group, and n is an integer greater than 1; the charging compensation circuit is electrically connected with the data signal transmission circuit; the charging compensation circuit is configured to sequentially input a plurality of data signal groups in response to a first charging control signal; for each data signal group, responding to a second charging control signal, and outputting the data signal group after a preset duration at the starting moment of a data input period corresponding to the data signal group; wherein in the charging compensation mode, in each driving signal group, the preset duration corresponding to the first data signal group in the transmission sequence is smaller than the preset duration corresponding to each of the rest data signal groups.

Description

Driving chip, display device and driving method thereof TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a driving chip, a display device and a driving method thereof. BACKGROUND

[0002] With the increasing of display resolution, the power consumption of display products is increasing. For a red or green or blue picture, the power consumption can be reduced by sequentially turning on multiple rows of same color sub-pixels. However, the sequential turning on of multiple rows of same color sub-pixels will cause the first row to have no pre-charge and the other rows to have pre-charge, that is, the first row charging is worse than the other rows, which causes the pixel charging to be non-uniform and affects the display effect.

[0003] SUMMARY

[0004] The driving chip provided by the embodiments of the present disclosure comprises:

[0005] The data signal transmission circuit is configured to sequentially output a plurality of data signal groups; each data signal group comprises a plurality of data signals; n data signal groups that are sequentially output in the plurality of data signal groups form a driving signal group, and n is an integer greater than 1;

[0006] The charging compensation circuit is electrically connected to the data signal transmission circuit; the charging compensation circuit is configured to: in response to a first charging control signal, sequentially input a plurality of data signal groups; for each data signal group, in response to a second charging control signal, output the data signal group after a preset time length at the start time of the data input period corresponding to the data signal group; wherein in the charging compensation mode, the preset time length corresponding to the first data signal group in the transmission sequence in each driving signal group is less than the preset time length corresponding to each of the remaining data signal groups.

[0007] In some embodiments, the charging compensation circuit comprises: m cascaded sub-circuits; wherein m is an integer greater than or equal to 3; the sub-circuit comprises:

[0008] a control signal input end; the control signal input end of the first-stage sub-circuit is configured to input the first charging control signal, and the control signal input end of each of the remaining sub-circuits except the first-stage sub-circuit is configured to input the second charging control signal;

[0009] a data signal input end; the first-stage sub-circuit comprises one data signal input end configured to input a plurality of serial data signals; each of the remaining sub-circuits except the first-stage sub-circuit comprises a plurality of data signal input ends configured to input a plurality of data signals in parallel;

[0010] a plurality of data signal output terminals; the plurality of data signal output terminals of the i-th stage sub-circuit are configured to output the data signals in parallel at the i-th time point after the start time point of the data input period corresponding to the data signal group; wherein i is an integer greater than or equal to 1 and less than or equal to m; the data signal input terminals of the sub-circuits other than the first stage sub-circuit are electrically connected to the data signal output terminals of the previous stage sub-circuit one by one;

[0011] the first stage sub-circuit is configured to, in each data input period, in response to the first charge control signal, shift and output the data signals of the data signal group at the first time point after the start time point of the data input period;

[0012] the i-th stage sub-circuit with i greater than 1 is configured to, in each data input period, in response to the second charge control signal, latch and output the plurality of data signals output by the previous stage sub-circuit at the i-th time point after the start time point of the data input period; wherein when i is greater than 1, the first time point is earlier than or equal to the i-th time point; and when i is less than m, the i-th time point corresponding to the i-th stage sub-circuit is earlier than the i+1-th time point corresponding to the i+1-th stage sub-circuit; the time interval between the m-th time point and the start time point of the data input period is the preset time interval corresponding to the data signal group.

[0013] In some embodiments, the first stage sub-circuit includes a serial shift register;

[0014] The serial shift register includes a first data input terminal, a first control signal input terminal, and a plurality of first data output terminals;

[0015] The serial shift register is configured to, in response to the first charge control signal input by the first control signal input terminal, shift and output the plurality of data signals input in series by the first data input terminal in parallel through the plurality of first data output terminals at the first time point after the start time point of the data input period.

[0016] In some embodiments, at least one of the second stage sub-circuit to the m-th stage sub-circuit includes a latch;

[0017] The latch includes a plurality of second data input terminals, a second control signal input terminal, and a plurality of second data output terminals; the plurality of second data input terminals of the latch are electrically connected to the plurality of data output terminals of the previous stage sub-circuit corresponding to the latch one by one;

[0018] The i-th stage sub-circuit with i greater than 1 includes a latch, and the latch included in the i-th stage sub-circuit is configured to, in response to the second charge control signal input by the second control signal input terminal, latch the plurality of data signals input in parallel by the plurality of second data input terminals at the i-th time point after the start time point of the data input period, and output the plurality of data signals through the plurality of second data output terminals.

[0019] In some embodiments, the driving chip further comprises: a control signal generation circuit; the control signal generation circuit comprises: a high-low level control signal generation circuit;

[0020] The high-low level control signal generation circuit comprises: a first control signal output end, and m-1 second charging control signal output ends; the first control signal output end is electrically connected with the control signal input end of the first-stage sub-circuit, and the m-1 second control signal output ends are respectively electrically connected with the control signal input ends of the second-stage sub-circuit to the m-stage sub-circuit;

[0021] The high-low level control signal generation circuit is configured to: generate m high-low level signals as the first charging control signal and the m-1 second charging control signals respectively, output the first charging control signal through the first control signal output end, and output the m-1 second charging control signals through the m-1 second control signal output ends respectively; wherein, the high-low level signal comprises alternating high level signals and low level signals, and the voltage of the high level signal is greater than the voltage of the low level signal;

[0022] The sub-circuit inputs the data signal in response to the high level signal or the low level signal.

[0023] In some embodiments, at least one of the second-stage sub-circuit to the m-stage sub-circuit comprises a D flip-flop;

[0024] The D flip-flop comprises: a plurality of third data input ends, a third control signal input end, and a plurality of third data output ends;

[0025] The plurality of third data input ends of the D flip-flop are electrically connected one by one with the plurality of data output ends of the corresponding previous-stage sub-circuit of the D flip-flop;

[0026] The i-stage sub-circuit with i greater than 1 comprises a D flip-flop, and the D flip-flop of the i-stage sub-circuit is configured to: in response to the second charging control signal input by the third control signal input end, at the i time instant after the data input period start time, latch the plurality of data signals input in parallel by the plurality of third data input ends, and output the plurality of data signals through the plurality of third data output ends.

[0027] In some embodiments, the driving chip further comprises: a control signal generation circuit; the control signal generation circuit comprises: a clock signal generation circuit; the clock signal generation circuit comprises: a first clock signal output end, and m-1 second clock signal output ends; the first clock signal output end is electrically connected with the control signal input end of the first-stage sub-circuit, and the m-1 second clock signal output ends are respectively electrically connected with the control signal input ends of the second-stage sub-circuit to the m-stage sub-circuit;

[0028] The clock signal generation circuit is configured to generate m clock signals as the first charging control signal and m-1 second charging control signals respectively, and output the first charging control signal through the first clock signal output end and output the m-1 second charging control signals through the m-1 second clock signal output ends.

[0029] In some embodiments, the i-th level sub-circuit with i greater than 1 is further configured to maintain the cache state of the latched plurality of data signals in response to the second charging control signal.

[0030] In some embodiments, in the charging compensation mode, in one driving signal group, the output duration of the first data signal group in the transmission sequence output by the charging compensation circuit is greater than the output duration of the remaining data signal groups output by the charging compensation circuit, and the output duration of the charging compensation circuit output for the remaining data signal groups except the first data signal group is equal.

[0031] In some embodiments, in the non-charging compensation mode, in one driving signal group, the output duration of each data signal group output by the charging compensation circuit is equal.

[0032] The display device provided by the embodiments of the present disclosure includes:

[0033] The display panel includes a display area and a peripheral area surrounding the display area; the display panel includes: a plurality of data lines arranged along a first direction and extending from the display area to the peripheral area along a second direction, a plurality of pixel island rows located in the display area and arranged along the second direction, and a plurality of binding terminals located in the peripheral area; the first direction intersects the second direction; the plurality of binding terminals include a plurality of first binding terminals, and each first binding terminal is electrically connected to a data line at one end of the data line in the extension direction; each of the plurality of pixel island rows includes: a plurality of pixel islands arranged along the first direction; each pixel island includes: a plurality of sub-pixel units arranged along the second direction, and each sub-pixel unit includes a plurality of sub-pixels arranged along the first direction; the plurality of sub-pixel units arranged along the first direction form a sub-pixel row, and the plurality of sub-pixel units arranged along the second direction form a sub-pixel column; the sub-pixel column is electrically connected to the data line; the sub-pixels in the same sub-pixel row have the same color, and the sub-pixels in any two adjacent sub-pixel rows have different colors; in adjacent n rows of pixel island rows, the sub-pixel rows including sub-pixels of the same color form a driving unit group.

[0034] The driving chip provided by the embodiment of the present disclosure is bound with a plurality of binding terminals in the peripheral area; the charging compensation circuit is electrically connected with the plurality of first binding terminals; in the charging compensation mode, the charging compensation circuit is configured to: sequentially provide a data signal group to each of the n sub-pixel rows in the driving unit group through the plurality of first binding terminals and the plurality of data lines, and the n data signal groups corresponding to one driving unit group are one driving signal group.

[0035] In some embodiments, the display panel further comprises:

[0036] The plurality of scan lines extend from the display area to the peripheral area along the first direction; and one row of sub-pixel rows is electrically connected with the same scan line;

[0037] The gate drive circuit comprises at least one group of cascaded shift register units; the cascaded shift register units are located in the peripheral area on one side of the display area in the first direction; and the plurality of scan lines electrically connected with each driving unit group are electrically connected with the same shift register unit;

[0038] The plurality of binding terminals further comprise: a plurality of second binding terminals; and the plurality of second binding terminals are electrically connected with the gate drive circuit;

[0039] The charging compensation circuit is further configured to: provide a gate drive signal to the gate drive circuit; and the gate drive circuit is configured to: in the charging compensation mode, provide a scan signal to the plurality of scan lines in response to the gate drive signal, scan the driving unit group according to a preset scan order, and sequentially scan to turn on each sub-pixel row in the driving unit group.

[0040] In some embodiments, in the charging compensation mode, for each driving unit group, the gate drive circuit sequentially scans to turn on each sub-pixel row in the driving unit group, specifically comprising:

[0041] The time of scanning to turn on the first row of sub-pixel rows in the preset scan order is equal to the time of outputting the data signal group corresponding to the first row of sub-pixel rows from the charging compensation circuit;

[0042] The time of scanning to turn on each sub-pixel row other than the first row of sub-pixel rows is earlier than the time of outputting the data signal group corresponding to the sub-pixel row from the charging compensation circuit.

[0043] In some embodiments, in the non-charging compensation mode, the gate drive circuit is further configured to: for each driving unit group, the time of scanning to turn on the sub-pixel row is earlier than the time of outputting the data signal group corresponding to the sub-pixel row from the charging compensation circuit.

[0044] The driving method of the display device provided by the embodiment of the present disclosure comprises:

[0045] According to the image to be displayed and the display mode, the control data signal transmission circuit outputs a plurality of data signal groups in a preset data transmission sequence; the display mode includes a first resolution mode, and the first resolution mode includes a charge compensation mode;

[0046] According to the display mode, the first charge control signal is loaded to the charge compensation circuit to control the charge compensation circuit to input a data signal group in each data input period in a preset data transmission sequence; and for each data signal group, the second charge control signal is loaded to the charge compensation circuit to control the charge compensation circuit to output the data signal group after a preset time length at the start time of the data input period corresponding to the data signal group; in the charge compensation mode, the preset time length corresponding to the first data signal group in the transmission sequence in each drive signal group is less than the preset time length corresponding to each of the remaining data signal groups.

[0047] In some embodiments, the charge compensation circuit includes m cascaded sub-circuits; in each data input period, the first charge control signal is loaded to the charge compensation circuit to control the charge compensation circuit to output the data signal group after a preset time length at the start time of the data input period corresponding to the data signal group, and specifically includes:

[0048] The first charge control signal is loaded to the control signal input end of the first-stage sub-circuit to control the first-stage sub-circuit to shift and output in parallel the plurality of data signals included in the data signal group at the first time after the start time of the data input period.

[0049] The second charge control signal is loaded to the control signal input end of the i-th stage sub-circuit when i is greater than 1 to control the i-th stage sub-circuit to latch and output the plurality of data signals output by the previous-stage sub-circuit at the i-th time after the start time of the data input period; when i is greater than 1, the first time is earlier than or equal to the i-th time, and when i is less than m, the i-th time corresponding to the i-th stage sub-circuit is earlier than or equal to the i+1-th time corresponding to the i+1-th stage sub-circuit.

[0050] In some embodiments, the second charge control signal is loaded to the control signal input end of the i-th stage sub-circuit when i is greater than 1 to control the i-th stage sub-circuit to latch and output the plurality of data signals output by the previous-stage sub-circuit at the i-th time after the start time of the data input period, and specifically includes:

[0051] The high-low level signal is loaded to the control signal input end of the i-th stage sub-circuit when i is greater than 1, and the i-th stage sub-circuit latches and outputs the plurality of data signals output by the previous-stage sub-circuit at the i-th time after the start time of the data input period in response to the high-low level signal.

[0052] In some embodiments, the control signal input end of the i-th stage sub-circuit with i greater than 1 is loaded with the second charging control signal, and the i-th stage sub-circuit is controlled to latch and output the plurality of data signals output by the previous stage sub-circuit at the i-th time instant after the opening time instant of the data input period, specifically comprising:

[0053] The control signal input end of the i-th stage sub-circuit with i greater than 1 is loaded with a clock signal, and the i-th stage sub-circuit latches and outputs the plurality of data signals output by the previous stage sub-circuit at the i-th time instant after the opening time instant of the data input period in response to the clock signal.

[0054] In some embodiments, each data input period is divided into a first period and a second period after the first period, and the first time instant is the start time instant of the second period; the first stage sub-circuit is controlled to shift and register the plurality of serial data signals included in the data signal group and output the plurality of data signals in parallel at the first time instant, specifically comprising:

[0055] The first stage sub-circuit is controlled to shift and register the plurality of serial data signals included in the data signal group in the first period; and the first stage sub-circuit is controlled to output the plurality of data signals in parallel at the start time instant of the second period.

[0056] In some embodiments, for each data signal group, the interval between the i-th time instant and the start time instant of the data input period corresponding to the data signal group is the i-th time length, and i is an integer greater than 1 and less than m;

[0057] In the charging compensation mode, the first time lengths corresponding to different data signal groups are equal; and in the same driving signal group, the m-th time lengths corresponding to different data signal groups are not completely equal.

[0058] In some embodiments, in the driving signal group, the time length of the r-th data signal group in the data signal transmission sequence output by the charging compensation circuit is the r-th continuous time length Jr; r is an integer greater than or equal to 1 and less than or equal to n;

[0059] In the charging compensation mode, in the driving signal group, when r is greater than 1, the r-th continuous time lengths Jr of the r-th data signal groups in the data signal transmission sequence are equal, and the first continuous time length J1 of the first data signal group in the data signal transmission sequence is greater than the r-th continuous time lengths Jr of the r-th data signal groups in the data signal transmission sequence.

[0060] In some embodiments, in the charging compensation mode, at least the first charging control signal is a clock signal with a fixed period, and at least the second charging control signal corresponding to the m-th stage sub-circuit is a clock signal with a period varying.

[0061] In some embodiments, the first resolution mode further includes a non-charging compensation mode, and in the non-charging compensation mode, the i-th time lengths corresponding to different data signal groups are all the same.

[0062] In some embodiments, in the non-charge compensation mode, the rth time duration Jr of the rth data signal group in the data signal transmission sequence in the driving signal group is equal.

[0063] In some embodiments, in the non-charge compensation mode, the first charge control signal and the second charge control signal are clock signals with fixed periods.

[0064] In some embodiments, the display panel further comprises a plurality of scan lines and a gate driving circuit; and the method further comprises:

[0065] controlling the driving chip to load a gate driving signal to the gate driving circuit;

[0066] controlling the gate driving circuit to provide a scan signal to the plurality of scan lines in response to the gate driving signal, scan the driving unit groups in a preset scan sequence, and sequentially scan to turn on each sub-pixel row in the driving unit group.

[0067] In some embodiments, in the charge compensation mode, the turning-on time of the first row of sub-pixel rows in the preset scan sequence in the driving unit group is equal to the time when the data signal group corresponding to the first row of sub-pixel rows is output from the charge compensation circuit; and the turning-on time of each sub-pixel row other than the first row of sub-pixel rows in the driving unit group is earlier than the time when the data signal group corresponding to the sub-pixel row is output from the charge compensation circuit.

[0068] In some embodiments, in the non-charge compensation mode, the turning-on time of the sub-pixel row is earlier than the time when the data signal group corresponding to the sub-pixel row is output from the charge compensation circuit.

[0069] In some embodiments, the display mode further comprises a second resolution mode, and the resolution corresponding to the second resolution mode is lower than the resolution corresponding to the first resolution mode; and the method further comprises:

[0070] determining the scan signal of each sub-pixel row in the second resolution mode;

[0071] controlling the gate driving circuit to provide a scan signal to the plurality of scan lines, scan the plurality of driving unit groups in a preset scan sequence, and simultaneously scan to turn on n sub-pixel rows in the driving unit group. BRIEF DESCRIPTION OF DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, a brief introduction will be given below to the drawings needed to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0073] FIG. 1 is a structural schematic diagram of a driving chip according to an embodiment of the present disclosure;

[0074] FIG. 2 is a structural schematic diagram of another driving chip according to an embodiment of the present disclosure;

[0075] FIG. 3 is a structural schematic diagram of another driving chip according to an embodiment of the present disclosure;

[0076] FIG. 4 is a structural schematic diagram of another driving chip according to an embodiment of the present disclosure;

[0077] FIG. 5 is a structural schematic diagram of another driving chip according to an embodiment of the present disclosure;

[0078] FIG. 6 is a structural schematic diagram of another driving chip according to an embodiment of the present disclosure;

[0079] FIG. 7 is a structural schematic diagram of another driving chip according to an embodiment of the present disclosure;

[0080] FIGS. 8-10 are timing diagrams of a charging compensation mode of a driving chip according to an embodiment of the present disclosure;

[0081] FIGS. 11-13 are timing diagrams of a non-charging compensation mode of a driving chip according to an embodiment of the present disclosure;

[0082] FIG. 14 is a structural schematic diagram of a display device according to an embodiment of the present disclosure;

[0083] FIG. 15 is a schematic diagram of a driving chip, a binding terminal and a data line according to an embodiment of the present disclosure;

[0084] FIG. 16 is a timing diagram of a charging compensation mode of a display device according to an embodiment of the present disclosure;

[0085] FIG. 17 is a timing diagram of a non-charging compensation mode of a display device according to an embodiment of the present disclosure;

[0086] FIG. 18 is a flowchart of a driving method of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0088] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. The terms "first", "second", and similar terms in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0089] It should be noted that the size and shape of the figures in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. Throughout, the same or similar reference numerals and designations refer to the same or similar elements or elements having the same or similar functions.

[0090] In the related art, one of the longitudinal RGB pixel arrangement rules is that the display rows from top to bottom are arranged in a cycle of red sub-pixel row, green sub-pixel row, and blue sub-pixel row. In a conventional charging scheme, taking a pure red color picture as an example, the red sub-pixel row is charged, the data line is charged to a high gray level, and the blue and green sub-pixel rows are not charged, and the data line is discharged to a low gray level, that is, the data line is charged and discharged once every 3 rows, and the power consumption is high. If charging is performed in a manner that n rows of sub-pixels of the same color are charged at the same time (n rows of sub-pixels of the same color are charged and then discharged), the charging and discharging times of the pure color picture can be reduced to 1 / n, greatly reducing the power consumption. However, taking n = 4 as an example, when a red picture is displayed, the first row of red sub-pixels is charged together with the data line, and the charging is slow, while the second row of red sub-pixels is charged together with the data line that has been charged for 1 row of time, and the data line itself is close to being fully charged, so the second row of red sub-pixels is charged well, and the last two rows of red sub-pixels are also charged well, that is, the first row of red sub-pixels only has its own data writing time without data pre-charging time, while the second, third, and fourth rows of red sub-pixels have both their own data writing time and the data pre-charging time of the previous row, that is, the charging times of the last three rows of sub-pixels are equal and greater than that of the first row of sub-pixels, which will result in the problem of uneven charging, that is, the first row of red sub-pixels is charged poorly, and the last three rows of red sub-pixels are charged well, and the brightness of the first row of red sub-pixels is weaker than that of the other rows of red sub-pixels, resulting in uneven brightness and affecting the display effect.

[0091] Therefore, the present embodiment provides a driving chip, as shown in FIG. 1, which comprises:

[0092] The data signal transmission circuit 1 is configured to sequentially output a plurality of data signal groups Z; each data signal group Z includes a plurality of data signals, and in FIG. 1, each data signal group Z includes 960 data signals D1-D960 as an example; n data signal groups Z that are sequentially output in the plurality of data signal groups Z are a driving signal group Q, and n is an integer greater than 1;

[0093] The charging compensation circuit 2 is electrically connected with the data signal transmission circuit 1; the charging compensation circuit 2 is configured to: in response to a first charging control signal C1, sequentially input a plurality of data signal groups Z; for each data signal group Z, in response to a second charging control signal C2, output the data signal group Z after a preset time length at a starting moment of a data input period corresponding to the data signal group Z; wherein in the charging compensation mode, a preset time length corresponding to a first data signal group Z in a transmission sequence in each driving signal group Q is less than a preset time length corresponding to each of the remaining data signal groups Z.

[0094] It should be noted that the driving chip provided by the embodiments of the present disclosure can be applied to a display device, that is, can be used as a driving chip for providing a driving signal to a display panel, and an output end of the charging compensation circuit is electrically connected with a data line of the display panel, so as to provide a data signal to the data line. Among them, the data signals included in one data signal group correspond to the number of data lines one by one, and the data signals included in one data signal group are the data signals of one sub-pixel row of the display panel. The n data signal groups included in one driving signal group correspond to n rows of sub-pixels that are continuously charged, that is, the n rows of sub-pixels are discharged after being charged.

[0095] The driving chip provided by the embodiments of the present disclosure includes a charging compensation circuit, which inputs a data signal group in response to a first charging control signal and outputs the data signal group after buffering for a preset time length in response to a second charging control signal. In the charging compensation mode, a preset time length corresponding to a first data signal group in a transmission sequence in each driving signal group Q is less than a preset time length corresponding to each of the remaining data signal groups Z, so that the output time length of the data signal in the first data signal group is greater than the output time length of the data signal in each of the remaining data signal groups except the first data signal group. When the driving chip is applied to a display product, in the charging compensation mode, the output time length of the first data signal group can be increased and the output time length of the remaining data signal groups can be reduced when the driving chip provides a data signal to the data line for charging, so that the charging time length of the self data signal of the sub-pixel row corresponding to the first data signal group is greater than the charging time length of the self data signal of the sub-pixel row corresponding to the remaining data signal groups, that is, even if the sub-pixel row corresponding to the first data signal group has no pre-charging, the charging time lengths of the sub-pixel rows can be the same, and the brightness unevenness caused by insufficient charging of the sub-pixel row corresponding to the first data signal group can be avoided.

[0096] It should be noted that the driving chip provided by the embodiments of the present disclosure can also be applied to a non-charge compensation mode. In the non-charge compensation mode, the preset time length corresponding to the first data signal group Z in the transmission sequence in each driving signal group Q is equal to the preset time length corresponding to each data signal group Z.

[0097] In some embodiments, as shown in FIG. 1 and FIG. 2, the plurality of data signals of one data signal group Z output by the data signal transmission circuit 1 are serial data signals. Taking the example that the data signal group Z includes 960 data signals D1-D960, the D1-D960 data signals output by the data signal transmission circuit 1 are serial data signals. Correspondingly, the charging compensation circuit 2 inputs serial data signals.

[0098] In some embodiments, as shown in FIG. 2, the charging compensation circuit 2 includes: m cascaded sub-circuits 201; wherein m is an integer greater than or equal to 3; the sub-circuit 201 includes:

[0099] a control signal input end 2012; the control signal input end 2012 of the first-stage sub-circuit 201 is configured to input a first charging control signal C1, and the control signal input end 2012 of each sub-circuit 201 except the first-stage sub-circuit 201 is configured to input a second charging control signal C2;

[0100] a data signal input end 2011; the first-stage sub-circuit 201-1 includes one data signal input end 2011 configured to input serial data signals D1-D960; each sub-circuit 201 except the first-stage sub-circuit 201-1 includes a plurality of data signal input ends 2011 configured to input a plurality of data signals D1-D960 in parallel;

[0101] a plurality of data signal output ends 2013; the plurality of data signal output ends 2013 of the i-th stage sub-circuit 201 are configured to output the data signals D1-D960 in parallel at the i-th time after the data input period of the data signal group Z is opened; wherein i is an integer greater than or equal to 1 and less than or equal to m; the data signal input end 2011 of each sub-circuit 201 except the first-stage sub-circuit 201 is electrically connected to the data signal output end 2013 of the previous-stage sub-circuit 201 in one-to-one correspondence;

[0102] the first-stage sub-circuit 201-1 is configured to: in each data input period, input the data signal group Z in response to the first charging control signal C1, shift and store the data signals D1-D960 of the data signal group Z, and output the data signals D1-D960 in parallel at the first time after the data input period is opened;

[0103] The i-th stage sub-circuit 201, where i is greater than 1, is configured to: in each data input period, in response to the second charge control signal C2, latch and output, at an i-th time point after a start time point of the data input period, the plurality of data signals D1-D960 output by the previous stage sub-circuit 201; when i is greater than 1, the first time point is earlier than or equal to the i-th time point; and when i is less than m, the i-th time point corresponding to the i-th stage sub-circuit 201 is earlier than an (i+1)-th time point corresponding to the (i+1)-th stage sub-circuit 201; and a time length between the m-th time point and the start time point of the data input period is a preset time length corresponding to the data signal group Z.

[0104] The driving chip provided in the embodiments of the present disclosure includes m cascaded sub-circuits, that is, after the data signals D1-D960 of one data signal group are input into the charge compensation circuit, the serial data signals D1-D960 are shifted and stored by the first stage sub-circuit and then output in parallel, and then sequentially output by the second stage sub-circuit to the m-th stage sub-circuit. In this way, under the control of the second charge control signal, the data signals D1-D960 of the previous stage sub-circuit are latched and output at the required time point, that is, the storage time length of the data signals D1-D960 by the second stage sub-circuit to the (m-1)-th stage sub-circuit can be controlled through the second charge control signal, and correspondingly, the data signals D1-D960 of the previous stage sub-circuit are latched and output at the required time point by the m-th stage sub-circuit under the control of the second charge control signal. That is, by loading the corresponding control signal through the m cascaded sub-circuits, the time point at which the m-th stage sub-circuit outputs the data signals D1-D960 can be controlled. In the charge compensation mode, for each driving signal group, the time length between the m-th time point of the first data signal group and the start time point of the data input period is less than the time length between the m-th time point of each of the remaining data signal groups and the start time point of the data input period, that is, the preset time length corresponding to the first data signal group is less than the preset time length corresponding to each of the remaining data signal groups, so that the output time length of the data signals in the first data signal group is greater than the output time length of the data signals in each of the remaining data signal groups except the first data signal group. The charging time length of the self data signals of the sub-pixel row corresponding to the first data signal group is greater than the charging time length of the self data signals of the sub-pixel row corresponding to each of the remaining data signal groups, that is, even if the sub-pixel row corresponding to the first data signal group is not pre-charged, the charging time lengths of the sub-pixel rows can be the same, and the brightness unevenness caused by insufficient charging of the sub-pixel row corresponding to the first data signal group can be avoided.

[0105] In some embodiments, the i-th stage sub-circuit 201, where i is greater than 1, is further configured to: in response to the second charge control signal, maintain the cache state of the latched plurality of data signals D1-D960.

[0106] It should be noted that the two data signal groups Z1 and Z2 transmitted in sequence are taken as an example to explain the maintaining of the cache state of the latched plurality of data signals D1-D960: the i-th sub-circuit has latched the plurality of data signals D1-D960 included in the data signal group Z1, when the upper sub-circuit (i.e. the (i-1)-th sub-circuit) of the i-th sub-circuit outputs in parallel the plurality of data signals D1-D960 included in the data signal group Z2, the i-th sub-circuit does not latch the plurality of data signals D1-D960 included in the data signal group Z2, but maintains the plurality of data signals D1-D960 included in the data signal group Z1. That is, the i-th sub-circuit causes the plurality of data signals output by the upper sub-circuit (i.e. the (i-1)-th sub-circuit) of the i-th sub-circuit not to be transmitted to the lower sub-circuit (i.e. the (i+1)-th sub-circuit) of the i-th sub-circuit through the current sub-circuit in response to the second charge control signal. For the 2nd sub-circuit to the m-th sub-circuit, the plurality of data signals are in the state of being cached by the upper latch after the plurality of data signals are latched by the upper sub-circuit, and before the plurality of data signals are latched by the lower latch.

[0107] It should be noted that the 1st sub-circuit is an input sub-circuit, the m-th sub-circuit is an output sub-circuit, and the 2nd sub-circuit to the (m-1)-th sub-circuit are intermediate sub-circuits. The larger m is, the more intermediate sub-circuits m-2 there are, so that the data signal group can be cached through more levels of intermediate sub-circuits. Since the preset time length corresponding to each data signal group can be controlled by the time length of caching the data signal group, compared with the case where the intermediate sub-circuit does not cache the data signal group, the preset time length corresponding to the data signal group can be increased as long as there is one level of intermediate sub-circuit caching the data signal group, and the preset time length corresponding to the data signal group can be increased by m-2 data cache time lengths if each level of intermediate sub-circuit caches the data signal group.

[0108] It should be noted that in the non-charge compensation mode, the intermediate sub-circuit is set not to cache the data signal group, so that in each drive signal group Q, the preset time length corresponding to the first data signal group Z in the transmission sequence is equal to the preset time length corresponding to each of the remaining data signal groups Z.

[0109] In some embodiments, as shown in FIG. 1 and FIG. 2, the driving chip further comprises a control signal generation circuit 3.

[0110] As shown in FIG. 2, the control signal generation circuit 3 comprises a first output end and m-1 second output ends; the first output end is electrically connected with the control signal input end 2012 of the 1st sub-circuit 201-1, and the m-1 second output ends are respectively electrically connected with the control signal input ends 2012 of the 2nd sub-circuit 201-2 to the m-th sub-circuit 201-m.

[0111] The control signal generation circuit is configured to generate the first charging control signal C1 and m-1 second charging control signals C2 (including C22-C2m), and output the first charging control signal C1 through the first output end and output the m-1 second charging control signals C2 (including C22-C2m) through m-1 second output ends respectively.

[0112] In some embodiments, as shown in FIG. 2, the first-stage sub-circuit 201-1 includes a serial shift register;

[0113] The serial shift register includes a first data input end 20111, a first control signal input end 20121, and a plurality of first data output ends 20131;

[0114] The serial shift register is configured to, in response to the first charging control signal C1 input by the first control signal input end 20121, register a plurality of data signals D input in series by the first data input end 20111, and output in parallel through the plurality of first data output ends 20131 at the first time after the start time of the data input period;

[0115] In some embodiments, as shown in FIG. 2, at least one of the second-stage sub-circuit 201-2 to the m-th sub-circuit 201-m includes a latch;

[0116] The latch includes a plurality of second data input ends 20112, a second control signal input end 20122, and a plurality of second data output ends 20132; the plurality of second data input ends 20112 of the latch are in one-to-one correspondence with the plurality of data output ends 2013 included in the corresponding upper-stage sub-circuit 201 of the latch;

[0117] The i-th stage sub-circuit 201 with i greater than 1 includes a latch, and the latch included in the i-th stage sub-circuit 201 is configured to, in response to the second charging control signal C2 input by the second control signal input end 20122, latch a plurality of data signals D input in parallel by the plurality of second data input ends 20112 at the i-th time after the start time of the data input period, and output the plurality of data signals D through the plurality of second data output ends 20132.

[0118] In some embodiments, as shown in FIG. 2, each sub-circuit 201 except the first-stage sub-circuit 201-1 includes a latch;

[0119] The plurality of second data inputs 20112 of the latch included in the second stage sub-circuit 201 are electrically connected in one-to-one correspondence with the plurality of first data outputs 20131 of the serial shift register, and the plurality of second data inputs 20112 of the latch included in the third stage sub-circuit 201 to the mth stage sub-circuit 201 are electrically connected in one-to-one correspondence with the plurality of second data outputs 20132 of the latch of the previous stage.

[0120] In some embodiments, the first stage sub-circuit 201-1 includes a serial shift register, and each of the remaining sub-circuits 201 except the first stage sub-circuit 201-1 includes a latch, as shown in FIG. 3,

[0121] The control signal generation circuit 3 includes a high-low level control signal generation circuit 301.

[0122] The high-low level control signal generation circuit 301 includes a first control signal output end and m-1 second charging control signal output ends; the first control signal output end is electrically connected with the control signal input end 2012 of the first stage sub-circuit 201-1, and the m-1 second control signal output ends are respectively electrically connected with the control signal input ends 2012 of the second stage sub-circuit 201-2 to the mth stage sub-circuit 201-m; that is, the first control signal output end is the first output end of the control signal generation circuit 3, and the m-1 second control signal output ends are respectively the m-1 second output ends of the control signal generation circuit 3.

[0123] The high-low level control signal generation circuit 301 is configured to generate m high-low level signals, which are respectively a first charging control signal C1 and m-1 second charging control signals C2 (including C22-C2m); the first charging control signal C1 is output through the first control signal output end, and the m-1 second charging control signals C2 (including C22-C2m) are respectively output through the m-1 second control signal output ends; wherein the high-low level signal includes alternating high level signals and low level signals, and the voltage of the high level signal is greater than the voltage of the low level signal.

[0124] The sub-circuit inputs the data signal in response to the high level signal or the low level signal.

[0125] In specific implementation, the sub-circuit can input the data signal in response to the rising edge or the falling edge of the high level signal, or the sub-circuit can input the data signal in response to the rising edge or the falling edge of the low level signal.

[0126] Alternatively, in some embodiments, the first stage sub-circuit 201-1 includes a serial shift register, and each of the remaining sub-circuits 201 except the first stage sub-circuit 201-1 includes a latch, as shown in FIG. 4,

[0127] The control signal generation circuit 3 comprises a clock signal generation circuit 302; the clock signal generation circuit 302 comprises a first clock signal output end and m-1 second clock signal output ends; the first clock signal output end is electrically connected with the control signal input end 2012 of the first-stage sub-circuit, and the m-1 second clock signal output ends are respectively electrically connected with the control signal input ends 2012 of the second-stage sub-circuit to the m-stage sub-circuit;

[0128] The clock signal generation circuit is configured to generate m clock signals as the first charging control signal C1 and m-1 second charging control signals C2 (including C22-C2m) respectively, and output the first charging control signal C1 through the first clock signal output end and output the m-1 second charging control signals C2 (including C22-C2m) through the m-1 second clock signal output ends respectively.

[0129] In a specific implementation, one period of the clock signal comprises a high-level signal and a low-level signal, and the sub-circuit inputs the data signal in response to the rising edge or the falling edge of the high-level signal of the clock signal, or the sub-circuit inputs the data signal in response to the rising edge or the falling edge of the low-level signal of the clock signal.

[0130] In some embodiments, as shown in FIGS. 2-4, the first data input end 20111 of the serial shift register is the data signal input end 2011 of the first-stage sub-circuit 201-1, the first control signal input end 20121 of the serial shift register is the control signal input end 2012 of the first-stage sub-circuit 201-1, and the first data output end 20131 of the serial shift register is the data signal output end 2013 of the first-stage sub-circuit 201-1.

[0131] The second data input end 20112 of the latch of the second-stage sub-circuit 201-2 to the m-stage sub-circuit 201-m is the data signal input end 2011 of the second-stage sub-circuit 201-2 to the m-stage sub-circuit 201-m, the second control signal input end 20122 of the latch of the second-stage sub-circuit 201-2 to the m-stage sub-circuit 201-m is the control signal input end 2012 of the second-stage sub-circuit 201-2 to the m-stage sub-circuit 201-m, and the second data output end 20132 of the latch of the second-stage sub-circuit 201-2 to the m-stage sub-circuit 201-m is the data signal output end 2013 of the second-stage sub-circuit 201-2 to the m-stage sub-circuit 201-m.

[0132] In a specific implementation, the serial shift register as the first-stage sub-circuit serially shifts a plurality of data signals D1-D960 included in a data signal group in response to the first charging control signal C1.

[0133] The latch included in the 2nd to (m-1)th sub-circuits is a latch of an intermediate stage sub-circuit, and the latch included in any one of the 2nd to (m-1)th sub-circuits parallelly latches the plurality of data signals output by the previous stage sub-circuit at the corresponding time in response to the corresponding second charge control signal C2, and by controlling the time at which the plurality of data signals are parallelly latched, the time at which the plurality of data signals D1 to D960 are finally written into the mth sub-circuit can be buffered, that is, the 2nd to (m-1)th sub-circuits also function as buffers.

[0134] The latch included in the mth sub-circuit is a latch of an output stage sub-circuit, and the latch parallelly latches and outputs the plurality of data signals output by the previous stage sub-circuit at the mth time after the start time of the data input period in response to the corresponding second charge control signal C2, and maintains the plurality of data signals until the next data signal group is latched into the mth sub-circuit, and the interval between the output of the current data signal group by the mth sub-circuit and the latching of the next data signal group into the mth sub-circuit is the output time length of one data signal group.

[0135] In some embodiments, in the charge compensation mode, in one driving signal group, the output time length of the first data signal group in the transmission order through the charge compensation circuit is greater than the output time length of the remaining data signal groups through the charge compensation circuit, and the output time lengths of the remaining data signal groups through the charge compensation circuit are equal.

[0136] In specific implementation, the interval between the mth time and the start time of the data input period is the preset time length corresponding to the data signal group Z, and the greater the preset time length, the later the current data signal group relative to the output time. In each driving signal group, the preset time length corresponding to the first data signal group in the transmission order is less than the preset time length corresponding to each of the remaining data signal groups, and the output time length of the first data signal group is greater than the output time length of the remaining data signal groups.

[0137] In some embodiments, in the non-charge compensation mode, in one driving signal group, the output time length of each data signal group through the charge compensation circuit is equal.

[0138] Specifically, in the cascaded m sub-circuits, for one data signal group, the difference between the time at which the adjacent two sub-circuits latch and output the data signal group is the buffering time length of the data signal group by the former one of the adjacent two sub-circuits. In some embodiments, in the cascaded m sub-circuits, for one data signal group, the difference between the time at which the adjacent two sub-circuits latch and output the data signal group is greater than or equal to 0.

[0139] In a specific implementation, in the charging compensation mode, any one of the first to the m-2th sub-circuits has equal cache time lengths for the n different data signal groups in a drive signal group, and the m-1th sub-circuit has unequal cache time lengths for the n different data signal groups in a drive signal group, so that the preset time length between the time at which the mth sub-circuit latches and outputs the mth moment of the n different data signal groups in a drive signal group and the start moment of the data input period corresponding to each data signal group is not the same. In the charging compensation mode, in a drive signal group, the difference between the time at which the mth sub-circuit latches and outputs the first data signal group and the time at which the m-1th sub-circuit latches and outputs the first data signal group is less than the difference between the time at which the mth sub-circuit latches and outputs any other data signal group and the time at which the m-1th sub-circuit latches and outputs the any other data signal group, so that the output time length of the first data signal group can be increased. In the charging compensation mode, for the data signal groups other than the first data signal group, the difference between the time at which the mth sub-circuit latches and outputs a data signal group and the time at which the m-1th sub-circuit latches and outputs the data signal group can not be equal.

[0140] In a specific implementation, in the non-charging compensation mode, any one of the first to the m-1th sub-circuits has equal cache time lengths for the n different data signal groups in a drive signal group.

[0141] In some embodiments, m = 3, as shown in FIG. 5, the charging compensation circuit 2 includes three sub-circuits 201. Among them, the first stage sub-circuit 201-1 is an input stage sub-circuit 201, the third stage sub-circuit 201-3 is an output stage sub-circuit 201, and the second stage sub-circuit 201-2 is an intermediate stage sub-circuit 201. The preset time length corresponding to each data signal group can be controlled by adjusting the cache time length of the second stage sub-circuit 201-2 for the data signal group. Thus, with the least number of sub-circuits, the output time length of the first data signal group can be increased, and the output time length of the remaining data signal groups can be reduced, so that the charging time length of the self data signal of the sub-pixel row corresponding to the first data signal group is greater than the charging time length of the self data signal of the sub-pixel row corresponding to the remaining data signal group, and the brightness uniformity of different sub-pixel rows is improved.

[0142] In some embodiments, the latch included in the ith stage sub-circuit 201 where i is greater than 1 is further configured to, in response to a second charging control signal, maintain the cache state of the latched plurality of data signals D1-D960.

[0143] In some embodiments, the latch included in the i-th stage sub-circuit 201 with i greater than 1 is configured to: in response to a rising edge of the second charging control signal C2 input by the second control signal input end 20122, latch the plurality of data signals D input in parallel by the plurality of second data input ends 20112 at the i-th time after the data input period start time, and output the plurality of data signals D through the plurality of second data output ends 20132; and in response to other phases of the second charging control signal C2 except the rising edge time, maintain the cache state of the latched plurality of data signals D1-D960 by the latch included in the i-th stage sub-circuit with i greater than 1. Alternatively, the latch included in the i-th stage sub-circuit 201 with i greater than 1 is configured to: in response to a falling edge of the second charging control signal C2 input by the second control signal input end 20122, latch the plurality of data signals D input in parallel by the plurality of second data input ends 20112 at the i-th time after the data input period start time, and output the plurality of data signals D through the plurality of second data output ends 20132; and in response to other phases of the second charging control signal C2 except the falling edge time, maintain the cache state of the latched plurality of data signals D1-D960 by the latch included in the i-th stage sub-circuit with i greater than 1.

[0144] The above are all described by taking the second stage sub-circuit to the m-th stage sub-circuit as an example, and of course, the second stage sub-circuit to the m-th stage sub-circuit can also include other elements in specific implementation.

[0145] In some embodiments, as shown in FIG. 6, at least one of the second stage sub-circuit to the m-th stage sub-circuit includes a D flip-flop;

[0146] The D flip-flop includes: a plurality of third data input ends 20113, a third control signal input end 20123, and a plurality of third data output ends 20133;

[0147] The plurality of third data input ends 20113 of the D flip-flop are in one-to-one correspondence with the plurality of data output ends 2013 included in the corresponding previous stage sub-circuit 201 of the D flip-flop and are electrically connected in one-to-one correspondence;

[0148] The i-th stage sub-circuit with i greater than 1 includes a D flip-flop, and the D flip-flop of the i-th stage sub-circuit is configured to: in response to the second charging control signal C2 input by the third control signal input end 20123, latch the plurality of data signals D input in parallel by the plurality of third data input ends 20113 at the i-th time after the data input period start time, and output the plurality of data signals D through the plurality of third data output ends 20133.

[0149] In some embodiments, as shown in FIG. 6, each sub-circuit 201 except the first stage sub-circuit 201-1 includes a D flip-flop;

[0150] The plurality of third data inputs 20113 of the D flip-flops included in the second stage sub-circuit 201 are electrically connected one by one with the plurality of first data outputs 20131 of the serial shift register, and the plurality of third data inputs 20113 of the D flip-flops included in the third stage sub-circuit 201 to the mth stage sub-circuit 201 are electrically connected one by one with the plurality of third data outputs 20133 of the D flip-flops of the previous stage.

[0151] In some embodiments, as shown in FIG. 6, the first data input 20111 of the serial shift register is the data signal input 2011 of the first stage sub-circuit 201-1, the first control signal input 20121 of the serial shift register is the control signal input 2012 of the first stage sub-circuit 201-1, and the first data output 20131 of the serial shift register is the data signal output 2013 of the first stage sub-circuit 201-1.

[0152] The third data input 20113 of the D flip-flop of the second stage sub-circuit 201-2 to the mth stage sub-circuit 201-m is the data signal input 2011 of the second stage sub-circuit 201-2 to the mth stage sub-circuit 201-m, the third control signal input 20123 of the D flip-flop of the second stage sub-circuit 201-2 to the mth stage sub-circuit 201-m is the control signal input 2012 of the second stage sub-circuit 201-2 to the mth stage sub-circuit 201-m, and the third data output 20133 of the D flip-flop of the second stage sub-circuit 201-2 to the mth stage sub-circuit 201-m is the data signal output 2013 of the second stage sub-circuit 201-2 to the mth stage sub-circuit 201-m.

[0153] In specific implementation, the serial shift register as the first stage sub-circuit serially shifts a plurality of data signals D1-D960 included in a data signal group in response to a first charging control signal C1;

[0154] The D flip-flops included in the second stage sub-circuit to the m-1th stage sub-circuit are the D flip-flops of the intermediate stage sub-circuit. The D flip-flop included in any of the second stage sub-circuit to the m-1th stage sub-circuit parallelly latches a plurality of data signals output by the previous stage sub-circuit at a corresponding time in response to a corresponding second charging control signal C2. By controlling the time of parallel latching of the data signals, the time when the plurality of data signals D1-D960 are finally written into the mth stage sub-circuit can be buffered. That is, the second stage sub-circuit to the m-1th stage sub-circuit also functions as a buffer.

[0155] The D flip-flop included in the mth stage sub-circuit is a D flip-flop of the output stage sub-circuit, and in response to the corresponding second charging control signal C2, the plurality of data signals output by the previous stage sub-circuit are parallelly latched and output at the mth moment after the start moment of the data input period, and the plurality of data signals are maintained until the next data signal group is latched to the mth stage sub-circuit; the interval length between the output of the current data signal group to the mth stage sub-circuit and the latching of the next data signal group to the mth stage sub-circuit is the output length of one data signal group.

[0156] In some embodiments, the first stage sub-circuit 201-1 includes a serial shift register, and each of the remaining sub-circuits 201 except the first stage sub-circuit 201-1 includes a latch, as shown in FIG. 6,

[0157] The control signal generation circuit 3 includes a clock signal generation circuit 302; the clock signal generation circuit 302 includes a first clock signal output end and m-1 second clock signal output ends; the first clock signal output end is electrically connected with the control signal input end 2012 of the first stage sub-circuit, and the m-1 second clock signal output ends are respectively electrically connected with the control signal input ends 2012 of the second stage sub-circuit to the mth stage sub-circuit;

[0158] The clock signal generation circuit 3 is configured to generate m clock signals as the first charging control signal C1 and the m-1 second charging control signals C2 (including C22-C2m) respectively, and output the first charging control signal C1 through the first clock signal output end and output the m-1 second charging control signals C2 (including C22-C2m) through the m-1 second clock signal output ends respectively.

[0159] In a specific implementation, one period of the clock signal includes a high level signal and a low level signal, the sub-circuit inputs the data signal in response to the rising edge or the falling edge of the high level signal of the clock signal, or the sub-circuit inputs the data signal in response to the rising edge or the falling edge of the low level signal of the clock signal.

[0160] In some embodiments, the D flip-flop included in the ith stage sub-circuit 201 with i greater than 1 is further configured to maintain the cache state of the latched plurality of data signals D1-D960 in response to the second charging control signal.

[0161] In some embodiments, the D flip-flop included in the i-th stage sub-circuit 201 with i greater than 1 is configured to: in response to a rising edge of the second charging control signal C2 input by the third control signal input end 20123, latch the plurality of data signals D input in parallel by the plurality of third data input ends 20113 at the i-th time after the data input period start time, and output the plurality of data signals D through the plurality of third data output ends 20133; in response to other phases of the second charging control signal C2 except the rising edge time, the D flip-flop included in the i-th stage sub-circuit with i greater than 1 maintains the cache state of the latched plurality of data signals D1-D960. Alternatively, the D flip-flop included in the i-th stage sub-circuit 201 with i greater than 1 is configured to: in response to a falling edge of the second charging control signal C2 input by the third control signal input end 20123, latch the plurality of data signals D input in parallel by the plurality of third data input ends 20113 at the i-th time after the data input period start time, and output the plurality of data signals D through the plurality of third data output ends 20133; in response to other phases of the second charging control signal C2 except the falling edge time, the D flip-flop included in the i-th stage sub-circuit with i greater than 1 maintains the cache state of the latched plurality of data signals D1-D960.

[0162] Alternatively, in some embodiments, as shown in FIG. 7, in the 2nd stage sub-circuit to the m-th stage sub-circuit, part of the sub-circuits include latches and the rest of the sub-circuits include D flip-flops.

[0163] In some embodiments, as shown in FIG. 7, when in the 2nd stage sub-circuit to the m-th stage sub-circuit, part of the sub-circuits include latches and the rest of the sub-circuits include D flip-flops, the control signal generation circuit 3 includes a clock signal generation circuit 302.

[0164] It should be noted that in FIG. 7, m=3 is taken as an example for illustration, the 2nd stage sub-circuit includes a latch and the 3rd stage sub-circuit includes a D flip-flop;

[0165] The 2nd stage sub-circuit serves as an intermediate stage sub-circuit, the latch included in the 2nd stage sub-circuit latches the plurality of data signals output by the previous stage sub-circuit in parallel at the corresponding time in response to the corresponding second charging control signal C2, and by controlling the time of parallel latching of the data signals, the time for the plurality of data signals D1-D960 to be finally written into the 3rd stage sub-circuit can be buffered, and the latch included in the 2nd stage sub-circuit functions as a buffer;

[0166] The D flip-flop included in the third stage sub-circuit is a D flip-flop of an output stage sub-circuit, which, in response to the corresponding second charging control signal C2, latches and outputs the plurality of data signals output by the previous stage sub-circuit in parallel at the third time point after the start time point of the data input period, and maintains the plurality of data signals until the next data signal group is latched to the third stage sub-circuit. The interval between the output of the current data signal group to the third stage sub-circuit and the latching of the next data signal group to the third stage sub-circuit is the output duration of a data signal group.

[0167] In specific implementation, when some of the second stage sub-circuit to the mth stage sub-circuit include latches and the rest include D flip-flops, the specific settings of which sub-circuits include latches and which sub-circuits include D flip-flops can be made according to actual needs.

[0168] In some embodiments, when the control signal generation circuit includes the clock signal generation circuit, the clock signal generation circuit can be integrated into a clock sub-chip, that is, the driving chip includes the clock sub-chip, and the clock sub-chip includes the clock signal generation circuit.

[0169] In some embodiments, in the charging compensation mode, at least the first charging control signal is a clock signal with a fixed period, and the second charging control signal corresponding to at least the mth stage sub-circuit is a clock signal with a period varying.

[0170] In some embodiments, in the charging compensation mode, the second charging control signal corresponding to the second stage sub-circuit to the m-1th stage sub-circuit is a clock signal with a fixed period.

[0171] In some embodiments, in the non-charging compensation mode, the first charging control signal and the second charging control signal are clock signals with a fixed period.

[0172] In specific implementation, in one clock period of the first charging control signal, the duration of the high level is equal to the duration of the low level; the duration of the high level in one clock period of the second charging control signal corresponding to the second stage sub-circuit and the third stage sub-circuit can be set to be not equal to the duration of the low level.

[0173] In some embodiments, the data signal transmission circuit includes a data receiving and decoding circuit and a serial data transmission circuit.

[0174] The data receiving and decoding circuit is configured to receive image data and decode the image data to obtain a plurality of data signals.

[0175] The serial data transmission circuit is used for serially outputting the plurality of data signals.

[0176] In a specific implementation, when the driving chip is applied to a display device, the driving chip can be electrically connected with a driving element such as a flexible circuit board, so as to receive image data output by the driving element such as the flexible circuit board.

[0177] Next, taking m=3 and n=4 as an example, the working process of the charging compensation circuit provided in the embodiment of the present disclosure is illustrated.

[0178] In the charging compensation mode, the timing diagram of the charging compensation circuit is shown in FIGS. 8-10, and in the non-charging compensation mode, the timing diagram of the charging compensation circuit is shown in FIGS. 11-13.

[0179] Fig. 8-10 respectively show different groups of driving signals Q inputted continuously, respectively Q1-Q3, Fig. 11-13 also respectively show different groups of driving signals Q inputted continuously, respectively Q1-Q3, Fig. 8, 11 show the timing corresponding to complete Q1, Q1 includes 4 groups of data signals of sub-pixel rows of the first color, respectively Z11, Z12, Z13, Z14; Fig. 9, 12 show the timing corresponding to complete Q2, Q2 includes 4 groups of data signals of sub-pixel rows of the second color, respectively Z21, Z22, Z23, Z24; Fig. 10, 11 show the timing corresponding to complete Q3, Q3 includes 4 groups of data signals of sub-pixel rows of the third color, respectively Z31, Z32, Z33, Z34; Fig. 10, 11 also show the group of driving signals Q1' after the group of driving signals Q3, Q1' also includes 4 groups of data signals of sub-pixel rows of the first color, Fig. 10, 11 only show the first group of data signals of Q1' and mark as Z11'. L1 represents the first stage sub-circuit, L2 represents the second stage sub-circuit, L3 represents the third stage sub-circuit, DO represents the signal outputted by the output end of the charging compensation circuit, when m=3, the signal outputted by DO is the signal outputted by the third stage sub-circuit. C1 is the first charging control signal inputted by the control signal input end of the first stage sub-circuit, C22 is the second charging control signal inputted by the control signal input end of the second stage sub-circuit, C23 is the second charging control signal inputted by the control signal input end of the third stage sub-circuit; C1, C22, C23 are all clock signals, the second stage sub-circuit latches the data signal outputted by the previous stage sub-circuit in response to the falling edge of the clock signal, the third stage sub-circuit latches the data signal outputted by the previous stage sub-circuit in response to the rising edge of the clock signal. Each data input period T is divided into: a first period H1 and a second period H2 after the first period H1; it is to be noted that one data input period T refers to the period that the group of data signals is inputted into the charging compensation circuit. The time that the group of data signals is outputted from the charging compensation circuit can not be in the data input period where the group of data signals is located. One data input period T includes 195 clocks S1-S195, wherein the first period H1 includes 160 clocks S1-S160, then 960 data signals are divided into 160 groups ZD, respectively ZD1-ZD160, 6 data signals are written into each clock, i.e. each group ZD includes 6 data signals. The working process of the charging compensation circuit is as follows:

[0180] In the first period H1 of one data input period T, the first stage sub-circuit shifts and registers 960 data signals in response to the first charging control signal C1, and outputs 960 data signals in parallel at the first time t1 after the starting time of the data input period T, i.e. the starting time of the second period H2;

[0181] In the second time period H2 after the first time period H1, the second stage sub-circuit latches and outputs the 960 data signals outputted by the first stage sub-circuit in parallel at the second time t2 after the opening time t0 of the data input period T in response to the falling edge of the corresponding second charge control signal C22;

[0182] In the second time period H2 after the first time period H1, and at the third time t3 after t1, the third stage sub-circuit latches and outputs the 960 data signals outputted by the second stage sub-circuit in parallel in response to the falling edge of the corresponding second charge control signal C23; after the time t3, and before the data signals of the next data signal group are written, the third stage sub-circuit maintains outputting the 960 data signals included in the current data signal group in response to the corresponding second charge control signal C23.

[0183] For the convenience of distinction, in FIGS. 8-13, the opening time t0 of the data input period Tf is denoted as t0f, the ith time ti corresponding to the data signal group Zjk is denoted as tijk, the ith time ti corresponding to the data signal group Zjk' is denoted as tijk', i is an integer greater than or equal to 1 and less than or equal to 3, f is an integer greater than or equal to 1, j is an integer greater than or equal to 1 and less than or equal to 3, and k is an integer greater than or equal to 1 and less than or equal to 4.

[0184] In some embodiments, for each data signal group, the interval between the ith time and the starting time t0 of the data input period corresponding to the data signal group is the ith time length hi, i is an integer greater than or equal to 1 and less than m;

[0185] In the driving signal group, the output time length of the rth data signal group in the data signal transmission sequence through the charge compensation circuit is the rth duration length Jr; r is an integer greater than or equal to 1 and less than or equal to n;

[0186] The interval time length between the data signal group output times of two adjacent sub-circuits is the data signal output interval time length E.

[0187] For the convenience of distinction, in FIGS. 8-13, the ith time length hi corresponding to the data signal group Zjk is denoted as hijk, and the ith time length hi corresponding to the data signal group Zjk' is denoted as hijk'. In the driving signal group, the rth duration length Jr corresponding to the data signal group Zjk is denoted as Jrjk. In the Q1-Q3 driving signal group, the interval time length between the third time and the second time corresponding to the rth data signal group in the data signal transmission sequence is denoted as Erjk, and in the driving signal group after Q3, the interval time length between the third time and the second time corresponding to the first data signal group is denoted as E111'.

[0188] In some embodiments, in the charging compensation mode, the first time length corresponding to different data signal groups is the same, and the mth time length corresponding to different data signal groups is not completely the same.

[0189] In some embodiments, in the charging compensation mode, the first time length corresponding to different data signal groups is the same, and the second time length corresponding to different data signal groups is the same; in the same driving signal group, when i is greater than or equal to 3 and less than or equal to m, the ith time length corresponding to different data signal groups is not completely the same.

[0190] In the charging compensation mode, in the driving signal group, when r is greater than 1, the rth duration time Jr of the rth data signal group in the data signal transmission sequence is equal, and the first duration time J1 of the first data signal group in the data signal transmission sequence is greater than the rth duration time Jr of the rth data signal group in the data signal transmission sequence.

[0191] Taking the Q1 driving signal group with m=3 as an example, in the charging compensation mode, as shown in FIG. 8:

[0192] In the first time period H1 of the T1 data input period, the first subcircuit, i.e., the serial shift register, serially shifts the plurality of data signals included in the Z11 data signal group in response to the first charging control signal C1, and outputs the Z11 data signal group in parallel at the first time t111 corresponding to the Z11 data signal group; the second subcircuit, i.e., the latch or D flip-flop, latches and outputs the Z11 data signal group at the second time t211 after the first time t111 corresponding to the Z11 data signal group in response to the second charging control signal C22 corresponding to the second subcircuit; the third subcircuit, i.e., the latch or D flip-flop, latches and outputs the Z11 data signal group at the third time t311 after the second time t211 corresponding to the Z11 data signal group in response to the second charging control signal C23 corresponding to the third subcircuit, and the interval time E111 between the second time t211 and the third time t311 is greater than 0.

[0193] In the first period H1 of the T2 data input period, the first sub-circuit, i.e., the serial shift register, serially shifts a plurality of data signals included in the Z12 data signal group in response to the first charging control signal C1, and outputs the Z12 data signal group in parallel at the first time t112 corresponding to the Z12 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z12 data signal group at the second time t212 after the first time t112 corresponding to the Z12 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z12 data signal group at the third time t312 after the second time t212 corresponding to the Z12 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; before latching the Z12 data signal group, the third sub-circuit maintains output of the Z11 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; the interval time E112 between the second time t212 corresponding to the Z12 data signal group and the third time t312 corresponding to the Z12 data signal group is greater than 0, and E112 is greater than E111; the interval time between the third time t311 corresponding to the Z11 data signal group and the third time t312 corresponding to the Z12 data signal group, i.e., the duration of maintaining output of the Z11 data signal group by the third sub-circuit, is J111.

[0194] In the first period H1 of the T3 data input period, the first sub-circuit, i.e., the serial shift register, serially shifts a plurality of data signals included in the Z13 data signal group in response to the first charging control signal C1, and outputs the Z13 data signal group in parallel at the first time t113 corresponding to the Z13 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z13 data signal group at the second time t213 after the first time t113 corresponding to the Z13 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z13 data signal group at the third time t313 after the second time t213 corresponding to the Z13 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; before latching the Z13 data signal group, the third sub-circuit maintains output of the Z12 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; the interval time E113 between the second time t213 corresponding to the Z13 data signal group and the third time t313 corresponding to the Z13 data signal group is greater than 0, and E113 is greater than E111; the interval time between the third time t312 corresponding to the Z12 data signal group and the third time t313 corresponding to the Z13 data signal group, i.e., the duration of outputting the Z12 data signal group by the third sub-circuit, is J212; the duration J212 of output of the Z12 data signal group is less than the duration J111 of output of the Z11 data signal group.

[0195] In the first period H1 of the T4 data input cycle, the first sub-circuit, i.e., the serial shift register, serially shifts the plurality of data signals included in the Z14 data signal group in response to the first charge control signal C1, and outputs the Z14 data signal group in parallel at the first time t114 corresponding to the Z14 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z14 data signal group at the second time t214 after the first time t114 corresponding to the Z14 data signal group in response to the second charge control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z14 data signal group at the third time t314 after the second time t214 corresponding to the Z14 data signal group in response to the second charge control signal C23 corresponding to the third sub-circuit; before latching the Z14 data signal group, the third sub-circuit maintains the output of the Z13 data signal group in response to the second charge control signal C23 corresponding to the third sub-circuit; the interval E114 between the second time t214 corresponding to the Z14 data signal group and the third time t314 corresponding to the Z14 data signal group is greater than 0, and E114 is greater than E111; the interval between the third time t313 corresponding to the Z13 data signal group and the third time t314 corresponding to the Z14 data signal group, i.e., the duration J313 of the output of the Z13 data signal group by the third sub-circuit, is greater than 0; the duration J313 of the output of the Z13 data signal group is less than the duration J111 of the output of the Z11 data signal group, and the duration J313 of the output of the Z13 data signal group is equal to the duration J212 of the output of the Z12 data signal group.

[0196] In the first time period H1 of the T5 data input period, the first sub-circuit, i.e., the serial shift register, serially shifts the plurality of data signals included in the Z21 data signal group in response to the first charging control signal C1, and outputs the Z21 data signal group in parallel at the first time t121 corresponding to the Z21 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z21 data signal group at the second time t221 after the first time t121 corresponding to the Z21 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z21 data signal group at the third time t321 after the second time t2121 corresponding to the Z21 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; before latching the Z21 data signal group, the third sub-circuit maintains the output of the Z14 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; the interval time E121 between the second time t221 corresponding to the Z21 data signal group and the third time t321 corresponding to the Z21 data signal group is greater than 0, and E121 is equal to E111; the interval time between the third time t314 corresponding to the Z14 data signal group and the third time t321 corresponding to the Z21 data signal group, i.e., the duration of the output of the Z14 data signal group by the third sub-circuit, is J414; the duration J414 of the output of the Z14 data signal group is less than the duration J111 of the output of the Z11 data signal group, and the duration J414 of the output of the Z14 data signal group is equal to the duration J313 of the output of the Z13 data signal group, which is equal to the duration J212 of the output of the Z12 data signal group.

[0197] T5-T8 correspond to the Q2 driving signal group, T9-T12 correspond to the Q3 driving signal group, and T13 corresponds to the Q1' driving signal group. The working process of the charging compensation circuit corresponding to each driving signal group is similar to that of the Q1 driving signal group, which will not be described here.

[0198] In some embodiments, in the charging compensation mode, as shown in FIGS. 8-10, for each driving signal group, the first time h1 corresponding to each data signal group is equal, the second time h2 corresponding to each data signal group is equal, and the third time h3 corresponding to each data signal group is not equal. The third time h3 corresponding to the first data signal group in the driving signal group is greater than the third time h3 corresponding to the remaining data signal groups, and the third time h3 corresponding to the remaining data signal groups can be set to be unequal.

[0199] Taking the Q1 driving signal group with m=3 as an example, in the non-charging compensation mode, as shown in FIG. 11:

[0200] In the first period H1 of the T1 data input period, the first sub-circuit, i.e., the serial shift register, serially shifts the multiple data signals included in the Z11 data signal group in response to the first charging control signal C1, and outputs the Z11 data signal group in parallel at the first time t111 corresponding to the Z11 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z11 data signal group at the second time t211 after the first time t111 corresponding to the Z11 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z11 data signal group at the third time t311 after the second time t211 corresponding to the Z11 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit, and the interval E111 between the second time t211 and the third time t311 is greater than 0;

[0201] In the first period H1 of the T2 data input period, the first sub-circuit, i.e., the serial shift register, serially shifts the multiple data signals included in the Z12 data signal group in response to the first charging control signal C1, and outputs the Z12 data signal group in parallel at the first time t112 corresponding to the Z12 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z12 data signal group at the second time t212 after the first time t112 corresponding to the Z12 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z12 data signal group at the third time t312 after the second time t212 corresponding to the Z12 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit, and before latching the Z12 data signal group, the third sub-circuit maintains the output of the Z11 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; the interval E112 between the second time t212 corresponding to the Z12 data signal group and the third time t312 corresponding to the Z12 data signal group is greater than 0, and E112 is equal to E111, and the interval J111, i.e., the duration of maintaining the output of the Z11 data signal group by the third sub-circuit, between the third time t311 corresponding to the Z11 data signal group and the third time t312 corresponding to the Z12 data signal group;

[0202] In the first period H1 of the T3 data input cycle, the first sub-circuit, i.e., the serial shift register, serially shifts the plurality of data signals included in the Z13 data signal group in response to the first charging control signal C1, and outputs the Z13 data signal group in parallel at the first time t113 corresponding to the Z13 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z13 data signal group at the second time t213 after the first time t113 corresponding to the Z13 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z13 data signal group at the third time t313 after the second time t213 corresponding to the Z13 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; before latching the Z13 data signal group, the third sub-circuit maintains the output of the Z12 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; the interval time E113 between the second time t213 corresponding to the Z13 data signal group and the third time t313 corresponding to the Z13 data signal group is greater than 0, and E113 is equal to or greater than E111; the interval time between the third time t312 corresponding to the Z12 data signal group and the third time t313 corresponding to the Z13 data signal group, i.e., the duration of the output of the Z12 data signal group by the third sub-circuit, is J212; the duration J212 of the output of the Z12 data signal group is equal to the duration J111 of the output of the Z11 data signal group.

[0203] In the first period H1 of the T4 data input cycle, the first sub-circuit, i.e. the serial shift register, serially shifts the plurality of data signals included in the Z14 data signal group in response to the first charging control signal C1, and outputs the Z14 data signal group in parallel at the first time t114 corresponding to the Z14 data signal group; the second sub-circuit, i.e. the latch or D flip-flop, latches and outputs the Z14 data signal group at the second time t214 after the first time t114 corresponding to the Z14 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e. the latch or D flip-flop, latches and outputs the Z14 data signal group at the third time t314 after the second time t214 corresponding to the Z14 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; before latching the Z14 data signal group, the third sub-circuit maintains the output of the Z13 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; the interval E114 between the second time t214 corresponding to the Z14 data signal group and the third time t314 corresponding to the Z14 data signal group is greater than 0, and E114 is equal to E111; the interval between the third time t313 corresponding to the Z13 data signal group and the third time t314 corresponding to the Z14 data signal group, i.e. the duration of the output of the Z13 data signal group by the third sub-circuit, is J313; the duration J313 of the output of the Z13 data signal group is equal to the duration J111 of the output of the Z11 data signal group, and the duration J313 of the output of the Z13 data signal group is equal to the duration J212 of the output of the Z12 data signal group.

[0204] In the first time period H1 of the T5 data input period, the first sub-circuit, i.e., the serial shift register, serially shifts the plurality of data signals included in the Z21 data signal group in response to the first charging control signal C1, and outputs the Z21 data signal group in parallel at the first time t121 corresponding to the Z21 data signal group; the second sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z21 data signal group at the second time t221 after the first time t121 corresponding to the Z21 data signal group in response to the second charging control signal C22 corresponding to the second sub-circuit; the third sub-circuit, i.e., the latch or D flip-flop, latches and outputs the Z21 data signal group at the third time t321 after the second time t2121 corresponding to the Z21 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; before latching the Z21 data signal group, the third sub-circuit maintains the output of the Z14 data signal group in response to the second charging control signal C23 corresponding to the third sub-circuit; the interval E121 between the second time t221 corresponding to the Z21 data signal group and the third time t321 corresponding to the Z21 data signal group is greater than 0, and E121 is equal to E111; the interval between the third time t314 corresponding to the Z14 data signal group and the third time t321 corresponding to the Z21 data signal group, i.e., the duration J414 of the output of the Z14 data signal group by the third sub-circuit; the duration J414 of the output of the Z14 data signal group is equal to the duration J111 of the output of the Z11 data signal group, and the duration J414 of the output of the Z14 data signal group is equal to the duration J313 of the output of the Z13 data signal group and the duration J212 of the output of the Z12 data signal group.

[0205] T5-T8 correspond to the Q2 driving signal group, T9-T12 correspond to the Q3 driving signal group, and T13 corresponds to the Q1' driving signal group. The working process of the charging compensation circuit corresponding to one driving signal group is similar to that of the Q1 driving signal group, which will not be described here.

[0206] In some embodiments, in the non-charging compensation mode, the output durations of the data signal groups in one driving signal group are equal. That is, as shown in FIGS. 11-13, J1=J2=J3=J4.

[0207] In some embodiments, in the non-charging compensation mode, for each driving signal group, the ith duration hi corresponding to each data signal group is equal. As shown in FIGS. 11-13, for each driving signal group, the first duration h1 corresponding to each data signal group is equal, the second duration h2 corresponding to each data signal group is equal, and the third duration h3 corresponding to each data signal group is equal.

[0208] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure is shown in FIGS. 14-15, which comprises:

[0209] The display panel 4 includes a display area AA and a peripheral area NA surrounding the display area AA; the display panel 4 includes a plurality of data lines DA arranged along a first direction X and extending from the display area AA to the peripheral area NA along a second direction Y, a plurality of pixel island rows PX located in the display area AA and arranged along the second direction Y, and a plurality of binding terminals 401 located in the peripheral area NA; the first direction X and the second direction Y intersect, and the first direction X and the second direction Y are perpendicular in FIG. 14; the plurality of binding terminals 401 includes a plurality of first binding terminals 4011, and each first binding terminal 4011 is electrically connected to a data line DA at one end of the data line DA in the extension direction; each pixel island row PX in the plurality of pixel island rows PX includes a plurality of pixel islands PX-1 arranged along the first direction X; each pixel island PX-1 includes a plurality of sub-pixel units PX-101 arranged along the second direction Y, and each sub-pixel unit PX-101 includes a plurality of sub-pixels PZ arranged along the first direction X; a plurality of sub-pixel unit groups PX-101 arranged along the first direction X form a sub-pixel row PXH, and a plurality of sub-pixel unit groups PX-101 arranged along the second direction Y form a sub-pixel column PXL; the sub-pixel column PXL is electrically connected to the data line DA; sub-pixels PZ in a same sub-pixel row PXH are of a same color, and sub-pixels PZ in any two adjacent sub-pixel rows PXH are of different colors; in n adjacent pixel island rows PX, sub-pixel rows PXH including sub-pixels PZ of the same color form a driving unit group P.

[0210] The driving chip 5 provided by the embodiment of the present disclosure is bound to the plurality of binding terminals 401 in the peripheral area NA; the charging compensation circuit 2 is electrically connected to the plurality of first binding terminals 4011; in the charging compensation mode, the charging compensation circuit 2 is configured to: sequentially provide a plurality of data signal groups to n sub-pixel rows PXH in a driving unit group through the plurality of first binding terminals 4011 and the plurality of data lines DA, and n data signal groups corresponding to one driving unit group form one driving signal group.

[0211] It should be noted that only the area occupied by the binding of the driving chip 5 is shown in FIG. 14, and the charging compensation circuit included in the driving chip 5 is not shown; the electrical connection relationship between the charging compensation circuit 2 and the plurality of first binding terminals 4011 and the data lines DA is shown in FIG. 15. In FIG. 14, n = 4. In specific implementation, n can be selected according to actual needs.

[0212] The display device provided by the embodiments of the present disclosure comprises the driving chip provided by the embodiments of the present disclosure. Since the driving chip comprises the charging compensation circuit, the charging compensation circuit inputs the data signal group in response to the first charging control signal, and outputs the data signal group after buffering for a preset time length in response to the second charging control signal. In the charging compensation mode, the preset time length corresponding to the first data signal group in the transmission sequence in each driving signal group is less than the preset time length corresponding to each of the remaining data signal groups, so that the output time length of the data signal in the first data signal group is greater than the output time length of the data signal in each of the remaining data signal groups. When the driving chip provides the data signal to the data line for charging in the charging compensation mode, the output time length of the first data signal group can be increased, and the output time length of the remaining data signal groups can be reduced, so that the charging time length of the self data signal of the sub-pixel row corresponding to the first data signal group is greater than the charging time length of the self data signal of the sub-pixel row corresponding to the remaining data signal groups. Even if the sub-pixel row corresponding to the first data signal group is not pre-charged, the charging time length of each sub-pixel row in the driving unit group can be the same, and the uneven brightness caused by insufficient charging of the sub-pixel row corresponding to the first data signal group in the driving unit group can be avoided.

[0213] In some embodiments, the pixel island row PX comprises 3 rows of sub-pixel rows arranged in sequence along the second direction Y, which are a first sub-pixel row, a second sub-pixel row, and a third sub-pixel row, respectively. The first sub-pixel row comprises a plurality of first sub-pixels, the second sub-pixel row comprises a plurality of second sub-pixels, and the third sub-pixel row comprises a plurality of third sub-pixels. As shown in FIG. 14, the first sub-pixel is a red sub-pixel R, the second sub-pixel is a green sub-pixel G, and the third sub-pixel is a blue sub-pixel B. That is, the first sub-pixel row is a red sub-pixel row, the second sub-pixel row is a green sub-pixel row, and the third sub-pixel row is a blue sub-pixel row. The n red sub-pixel rows in the continuous n pixel island rows PX form a driving unit group, the n green sub-pixel rows in the continuous n pixel island rows PX form a driving unit group, and the n green sub-pixel rows in the continuous n pixel island rows PX form a driving unit group.

[0214] In specific implementation, the display device provided by the embodiments of the present disclosure can be applied to three-dimensional (3D) display and can be switched between 3D display and two-dimensional (2D) display. The pixel island can be used as a sub-pixel of 2D display. Since a pixel island includes a plurality of sub-pixels, the same resolution as 2D display can be maintained in 3D display mode. In combination with an eye-tracking system, multi-view display with a large viewing angle can be realized, and 3D display with a higher pixel density (ppi) can also be realized, which has a larger amount of information and lower color crosstalk between adjacent view points. On the light-emitting side of the display panel, the display device further includes a plurality of light splitting structures extending in the column direction Y; the light splitting structure may, for example, be a cylindrical lens; the cylindrical lens may, for example, be a geometric lens, a diffractive lens, a liquid crystal lens, or a liquid lens.

[0215] In specific implementation, the display panel can be a liquid crystal display panel (LCD) or an electroluminescent display panel; the electroluminescent display panel may, for example, be one of an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED), a micro inorganic light-emitting diode (micro LED) display panel, or a mini light-emitting diode (mini LED) display panel.

[0216] In some embodiments, the display panel is a liquid crystal display panel, and the display panel includes: an array substrate and a counter substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the counter substrate.

[0217] The array substrate includes: a thin film transistor corresponding to each sub-pixel, and a pixel electrode electrically connected to the thin film transistor; the source of the thin film transistor is electrically connected to a data line, and the drain of the thin film transistor is electrically connected to the pixel electrode; and the display panel can further include a common electrode.

[0218] The counter substrate includes a black matrix and a plurality of color resistors; the black matrix includes a plurality of opening regions, and the color resistors are located at least in the opening regions; the opening region of the black matrix is a sub-pixel opening region, and the color of the color resistor corresponds to the color of the sub-pixel.

[0219] Alternatively, in some embodiments, the display panel is an electroluminescent display panel; taking an OLED display panel as an example, the display panel includes: a thin film transistor corresponding to each sub-pixel, and a light-emitting device electrically connected to the thin film transistor; the light-emitting device includes an anode, a light-emitting layer, and a cathode arranged in layers; and the anode is electrically connected to the drain of the thin film transistor.

[0220] In some embodiments, as shown in FIG. 14, the display panel further includes:

[0221] A plurality of scan lines GA extend from the display area AA to the peripheral area NA in the first direction; and a row of sub-pixel rows PXH is electrically connected to the same scan line GA.

[0222] The gate drive circuit 402 includes at least one group of cascaded shift register units GOA; the cascaded shift register units GOA are located on the side of the display area AA of the peripheral area NA in the first direction X; each group of drive units is electrically connected to the same shift register unit GOA through a plurality of scan lines GA.

[0223] The plurality of binding terminals 401 further include a plurality of second binding terminals 4012; the plurality of second binding terminals 4012 are electrically connected to the gate drive circuit 402.

[0224] The charging compensation circuit is further configured to provide a gate drive signal to the gate drive circuit 402; the gate drive circuit 402 is configured to, in the charging compensation mode, provide a scan signal to the plurality of scan lines GA in response to the gate drive signal, scan the groups of drive units in a preset scan order, and sequentially scan each sub-pixel row PXH in the group of drive units that is turned on.

[0225] The display device provided by the embodiments of the present disclosure has the advantages that n scan lines corresponding to one group of drive units are electrically connected to the same shift register unit GOA, so that n rows of sub-pixels can be simultaneously driven by one shift register unit GOA to reduce power consumption.

[0226] Specifically, when the pixel island row includes a red sub-pixel row, a green sub-pixel row, and a blue sub-pixel row, n rows of red sub-pixel rows, n rows of green sub-pixel rows, and n rows of blue sub-pixel rows are sequentially driven.

[0227] Specifically, the scan line is electrically connected to the gate of the thin film transistor.

[0228] It should be noted that only one signal line through which the gate drive circuit 402 is electrically connected to the second binding terminal 4012 is shown in FIG. 14. In specific implementation, a plurality of second binding terminals can be electrically connected to the gate drive circuit through a plurality of signal lines, and the gate drive circuit can be provided with a plurality of gate drive signals through the second binding terminals. The plurality of gate drive signals include, for example, a clock signal, an initialization signal, a reset signal, a high-level power supply signal, a low-level power supply signal, and the like.

[0229] In some embodiments, the display panel includes a number of sub-pixel rows greater than the number of shift register units GOA in one group of cascaded shift register units GOA, and the ratio of the number of sub-pixel rows to the number of shift register units GOA in one group of cascaded shift register units GOA is an integer.

[0230] In some embodiments, in the charging compensation mode, for each driving unit group, the gate driving circuit sequentially scans to turn on each sub-pixel row in the driving unit group, as shown in FIG. 16, specifically including:

[0231] At the turning-on moment tt01 of the first row of sub-pixel rows in the preset scanning order, tm1, which is the moment when the data signal group corresponding to the first row of sub-pixel rows is output from the charging compensation circuit.

[0232] The turning-on moment tt0r (r is greater than 1 and less than or equal to n) of each sub-pixel row other than the first row of sub-pixel rows is earlier than tmr (r is greater than 1 and less than or equal to n), which is the moment when the data signal group corresponding to the sub-pixel row is output from the charging compensation circuit.

[0233] In some embodiments, when charging in the charging compensation mode by providing data signals to the data lines through the driving chip, the output duration of the first data signal group in the driving signal group is greater than the output duration of the remaining data signal groups. On this basis, the moment of scanning to turn on the first row of sub-pixel rows in the preset scanning order is equal to the moment when the data signal group corresponding to the first row of sub-pixel rows is output from the charging compensation circuit, and the moment of scanning to turn on each sub-pixel row other than the first row of sub-pixel rows is earlier than the moment when the data signal group corresponding to the sub-pixel row is output from the charging compensation circuit, that is, the data signal input duration of the first row of sub-pixels in a driving unit group is greater than the data signal input duration of the remaining rows of sub-pixels. Even if the first data signal group corresponds to a sub-pixel row without pre-charging, the charging duration of each sub-pixel row in the driving unit group can be the same, avoiding the brightness unevenness caused by insufficient charging of the sub-pixel row corresponding to the first data signal group in the driving unit group.

[0234] It should be noted that in the charging compensation mode, the working process of the charging compensation circuit is described in the previous driving chip section and will not be repeated here. The rth duration Jr of the data signal group in the driving signal group is the data signal writing duration of one sub-pixel row in the driving unit group.

[0235] In some embodiments, as shown in FIG. 16, the turn-on duration HG of the sub-pixel rows is the same. In each driving unit group, the charging duration of the first sub-pixel row is equal to the duration of the data signal written to the first sub-pixel row (equal to the first duration J1 of the first data signal group in the driving signal group corresponding to the driving unit group), and the charging duration of the remaining sub-pixel rows includes the pre-charging duration after the scan is turned on and before the data signal is written to the sub-pixel row, and the duration of the data signal written to the sub-pixel row (when r is greater than 1, the rth duration Jr of the rth data signal group in the driving signal group corresponding to the driving unit group). Since the turn-on duration HG of the sub-pixel rows in each driving unit group is the same, the charging duration of the first sub-pixel row in the driving unit group is equal to the charging duration of the remaining sub-pixel rows, thereby avoiding insufficient charging of the sub-pixel row corresponding to the first data signal group in the driving unit group, which leads to uneven brightness.

[0236] It should be noted that FIG. 16 takes n = 4 as an example for illustration, G1, G2, G3, and G4 are scan signals of four sub-pixel rows, and the four sub-pixel rows input data signal groups Z11, Z12, Z13, and Z14 in turn.

[0237] In some embodiments, the duration of the data signal written to the rth sub-pixel row in the driving unit group, that is, the rth duration Jr of the rth data signal group in the driving signal group corresponding to the driving unit group, is greater than 0 and less than or equal to HG.

[0238] In some embodiments, as shown in FIG. 16, J1 = HG, J2 = J3 = J4 = HG / 3.

[0239] In some embodiments, in the non-charging compensation mode, the gate driving circuit is further configured to: for each driving unit group, the turn-on time tt0r (r is greater than or equal to 1 and less than or equal to n) of the sub-pixel row is earlier than the time tmr (r is greater than or equal to 1 and less than or equal to n) at which the data signal group corresponding to the sub-pixel row is output from the charging compensation circuit.

[0240] It should be noted that FIG. 17 takes n = 4 as an example for illustration, G1, G2, G3, and G4 are scan signals of four sub-pixel rows, and the four sub-pixel rows input data signal groups Z11, Z12, Z13, and Z14 in turn.

[0241] In some embodiments, as shown in FIG. 17, the turn-on duration HG of the sub-pixel rows is the same. In each driving unit group, the duration of the data signal written to the sub-pixel row is equal to the rth duration Jr of the data signal group in the driving signal group corresponding to the driving unit group, r is greater than or equal to 1 and less than or equal to n; J1 = J2 = J3 = J4 = HG / 2.

[0242] It should be noted that the charging compensation mode can be applied to a scene with high requirement on display brightness uniformity, for example. The non-charging compensation mode can be applied to a scene with low requirement on display brightness uniformity, for example.

[0243] It should be noted that the charging compensation mode and the non-charging compensation mode are both first resolution modes. In some embodiments, the display mode further includes a second resolution mode, and the resolution corresponding to the second resolution mode is lower than the resolution corresponding to the first resolution mode. In the second resolution mode, the gate driving circuit is further configured to: in response to the gate driving signal, provide the scanning signal to the plurality of scanning lines GA, scan the plurality of driving unit groups in the preset scanning order, and simultaneously scan the n sub-pixel rows in the driving unit group that is turned on.

[0244] In some embodiments, as shown in FIG. 14, in the peripheral area NA, the plurality of binding terminals bound 401 bound to the driving chip 5 further include a plurality of third binding terminals bound 4013, and the display panel further includes a plurality of fourth binding terminals 403 located on the side of the plurality of third binding terminals bound 4013 away from the display area AA; the fourth binding terminals 403 are electrically connected to the third binding terminals bound 4013.

[0245] The display device further includes a driving element 6 bound to the plurality of fourth binding terminals 403. The driving element 6 can be a flexible circuit board, for example, which is used to output image data. The image data is transmitted to the driving chip 5 through the fourth binding terminals 403 and the third binding terminals bound 4013. The driving chip 5 receives the image data and decodes the image data to obtain a plurality of data signals, and serially outputs the plurality of data signals.

[0246] The display device provided by the embodiments of the present disclosure is any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those skilled in the art, and are not described here in detail, nor should they be regarded as a limitation on the present disclosure.

[0247] Based on the same inventive concept, the embodiments of the present disclosure further provide a driving method of a display device, as shown in FIG. 18, which includes:

[0248] S101, according to the image to be displayed and the display mode, controlling the data signal transmission circuit to output a plurality of data signal groups in a preset data transmission order; the display mode includes a first resolution mode, and the first resolution mode includes a charging compensation mode;

[0249] S102, according to the display mode, the first charging control signal is loaded to the charging compensation circuit, the charging compensation circuit is controlled to input a data signal group in each data input period according to a preset data transmission sequence; and for each data signal group, the second charging control signal is loaded to the charging compensation circuit, the charging compensation circuit is controlled to output the data signal group after a preset time length at the start time of the data input period corresponding to the data signal group; in the charging compensation mode, the preset time length corresponding to the first data signal group in the transmission sequence in each drive signal group is less than the preset time length corresponding to each data signal group.

[0250] It should be noted that the charging compensation circuit is electrically connected to the plurality of data lines through the first binding terminal, and the data signal group output by the charging compensation circuit is transmitted to the plurality of data lines.

[0251] The driving method of the display device provided by the embodiments of the present disclosure is that the charging compensation circuit inputs the data signal group in response to the first charging control signal, and outputs the data signal group after buffering for a preset time length in response to the second charging control signal. In the charging compensation mode, the preset time length corresponding to the first data signal group in the transmission sequence in each drive signal group is less than the preset time length corresponding to each data signal group, so that the output time length of the data signal in the first data signal group is greater than the output time length of the data signal in each data signal group except the first data signal group. When the data signal is provided to the data line by the driving chip in the charging compensation mode to charge, the output time length of the first data signal group can be increased, and the output time length of the remaining data signal groups can be reduced, so that the charging time length of the self data signal of the sub-pixel row corresponding to the first data signal group is greater than the charging time length of the self data signal of the sub-pixel row corresponding to the remaining data signal groups. Even if the sub-pixel row corresponding to the first data signal group is not pre-charged, the charging time length of each sub-pixel row in the drive unit group can be the same, and the uneven brightness caused by insufficient charging of the sub-pixel row corresponding to the first data signal group in the drive unit group can be avoided.

[0252] In some embodiments, the charging compensation circuit includes m cascaded sub-circuits; in each data input period, the first charging control signal is loaded to the charging compensation circuit to control the charging compensation circuit to output the data signal group after a preset time length at the start time of the data input period corresponding to the data signal group, as shown in FIGS. 8-13, which specifically includes:

[0253] The first charging control signal C1 is loaded to the control signal input end of the first-stage sub-circuit to control the first-stage sub-circuit to shift and store the plurality of data signals included in the data signal group Z in series and output in parallel at the first time t1 after the start time t0 of the data input period;

[0254] The control signal input end of the i-th sub-circuit with i greater than 1 is loaded with the second charge control signal C2, so as to control the i-th sub-circuit to latch and output the multiple data signals output by the previous sub-circuit at the i-th time ti after the start time t0 of the data input period; wherein, when i is greater than 1, the first time t1 is earlier than or equal to the i-th time ti, and when i is less than m, the i-th time ti corresponding to the i-th sub-circuit is earlier than or equal to the (i+1)-th time ti+1 corresponding to the (i+1)-th sub-circuit.

[0255] In some embodiments, as shown in FIGS. 8-13, the control signal input end of the i-th sub-circuit with i greater than 1 is loaded with the second charge control signal, so as to control the i-th sub-circuit to latch and output the multiple data signals output by the previous sub-circuit at the i-th time after the start time of the data input period, specifically including:

[0256] The control signal input end of the i-th sub-circuit with i greater than 1 is loaded with a high-low level signal, and the i-th sub-circuit latches and outputs the multiple data signals output by the previous sub-circuit at the i-th time ti after the start time t0 of the data input period in response to the high-low level signal.

[0257] Alternatively, in some embodiments, as shown in FIGS. 8-13, the control signal input end of the i-th sub-circuit with i greater than 1 is loaded with the second charge control signal, so as to control the i-th sub-circuit to latch and output the multiple data signals output by the previous sub-circuit at the i-th time after the start time of the data input period, specifically including:

[0258] The control signal input end of the i-th sub-circuit with i greater than 1 is loaded with a clock signal, and the i-th sub-circuit latches and outputs the multiple data signals output by the previous sub-circuit at the i-th time ti after the start time t0 of the data input period in response to the clock signal.

[0259] In some embodiments, as shown in FIGS. 8-13, each data input period T is divided into a first period H1 and a second period H2 after the first period H1, and the first time t1 is the start time of the second period H2; the first sub-circuit is controlled to shift and register the serial multiple data signals included in the data signal group and output in parallel at the first time, specifically including:

[0260] The first sub-circuit is controlled to shift and register the serial multiple data signals included in the data signal group in the first period H1; the first sub-circuit is controlled to output the multiple data signals in parallel at the start time of the second period H2.

[0261] It should be noted that FIGS. 8-13 take m=3 as an example for illustration, and the specific working process of the charge compensation circuit can be referred to the description of the driving chip part, which will not be repeated here.

[0262] In some embodiments, as shown in Figures 8 to 13, for each data signal group, the interval between the i-th time ti and the start time t0 of the data input period corresponding to the data signal group is the i-th time duration hi, where i is an integer greater than or equal to 1 and less than m.

[0263] In the drive signal group Q, the duration of the r-th data signal group output by the charging compensation circuit in the data signal transmission sequence is the r-th duration Jr; r is an integer greater than or equal to 1 and less than or equal to n.

[0264] In some embodiments, as shown in Figures 8 to 10, in the charging compensation mode, the first duration h1 corresponding to different data signal groups is equal; in the same drive signal group, the m duration corresponding to different data signal groups is not completely equal.

[0265] In some embodiments, under the charging compensation mode, when i is greater than or equal to 1 and less than m, the i-th duration hi corresponding to different data signal groups is the same. For example, as shown in Figures 8 to 10, when m = 3, under the charging compensation mode, the second duration h2 corresponding to different data signal groups is the same.

[0266] In some embodiments, under the charging compensation mode, as shown in Figures 8 to 10, the third duration h3 corresponding to each data signal group is not equal. The third duration h3 corresponding to the first data signal group in the drive signal group is greater than the third duration h3 corresponding to the other data signal groups. The third duration h3 corresponding to the other data signal groups can be set to be unequal.

[0267] In some embodiments, under the charging compensation mode, as shown in Figures 8 to 10, in the drive signal group, when r is greater than 1, the r-th duration Jr of the r-th data signal group in the data signal transmission sequence is equal, and the first duration J1 of the first data signal group in the data signal transmission sequence is greater than the r-th duration Jr of the remaining data signal groups in the data signal transmission sequence.

[0268] In some embodiments, when r is greater than 1, 3J1 = Jr. As shown in Figures 8 to 10, 3J1 = J2 = J3 = J4.

[0269] In some embodiments, under the charging compensation mode, as shown in Figures 8 to 10, at least the first charging control signal C1 is a clock signal with a fixed period, and at least the second charging control signal C2m corresponding to the m-th sub-circuit is a periodically changing clock signal.

[0270] In some embodiments, in the charging compensation mode, the second charging control signal corresponding to the second-level sub-circuit to the (m-1)th-level sub-circuit is a clock signal with a fixed period. For example, as shown in Figures 8 to 10, the second charging control signal C22 corresponding to the second-level sub-circuit is a clock signal with a fixed period.

[0271] In some embodiments, the first resolution mode further includes a non-charging compensation mode. In the non-charging compensation mode, as shown in Figures 11 to 13, the i-th duration hi corresponding to different data signal groups is the same, where i is an integer greater than or equal to 1 and less than or equal to m.

[0272] In some embodiments, under non-charging compensation mode, as shown in Figures 11 to 13, the duration Jr of the r-th data signal group in the data signal transmission sequence is equal.

[0273] In some embodiments, under non-charging compensation mode, as shown in Figures 11 to 13, the first charging control signal C1 and the second charging control signal C2 are clock signals with a fixed period.

[0274] In some embodiments, the display panel further includes: multiple scan lines and a gate driving circuit; the method further includes:

[0275] The control driver chip applies a gate drive signal to the gate drive circuit;

[0276] The control gate drive circuit responds to the gate drive signal to provide scan signals to multiple scan lines, scans the drive unit group according to the preset scan order, and sequentially scans each sub-pixel row in the turn-on drive unit group.

[0277] The display device provided in this disclosure has n scan lines corresponding to a driving unit group electrically connected to the same shift register unit GOA, thereby reducing power consumption by driving n rows of sub-pixels simultaneously through a shift register unit GOA.

[0278] In some embodiments, as shown in FIG16, in the charging compensation mode, in the driving unit group, the opening time tt01 of the first row of sub-pixel rows in the preset scanning order is equal to the time tm1 when the data signal group corresponding to the first row of sub-pixel rows is output from the charging compensation circuit; in the driving unit group, the opening time tt0r (r is greater than 1 and less than or equal to n) of each sub-pixel row other than the first row of sub-pixel rows is earlier than the time tmr (r is greater than 1 and less than or equal to n) when the data signal group corresponding to the sub-pixel row is output from the charging compensation circuit.

[0279] The driving method for the display device provided in this disclosure, when charging in charging compensation mode by providing data signals to the data line through the driving chip, has an output duration of the first data signal group greater than the output duration of the other data signal groups in the driving signal group. Based on this, the moment the scan starts in the first row of sub-pixel rows in a preset scanning order is equal to the moment the data signal group corresponding to the first row of sub-pixel rows is output from the charging compensation circuit, and the moment the scan starts in each of the remaining sub-pixel rows (excluding the first row) is earlier than the moment the data signal group corresponding to that sub-pixel row is output from the charging compensation circuit. That is, the data signal input duration of the first row of sub-pixels in a driving unit group is greater than the data signal input duration of the other rows of sub-pixels. Even if the sub-pixel row corresponding to the first data signal group has no pre-charging, the charging duration of each sub-pixel row in the driving unit group can be made the same, avoiding uneven brightness caused by insufficient charging of the sub-pixel row corresponding to the first data signal group in the driving unit group.

[0280] It should be noted that, in charging compensation mode, the operation of the charging compensation circuit is explained in the previous section on the driver chip, and will not be repeated here. The r-th duration Jr corresponding to the data signal group in the driving signal group is the data signal writing duration of a sub-pixel row in the driving unit group.

[0281] In some embodiments, as shown in Figure 16, the on-time HG of the sub-pixel rows is the same. In each driving unit group, the charging time of the first sub-pixel row is the duration of its own data signal writing (equal to the first duration J1 of the data signal group in the driving signal group corresponding to the driving unit group). The charging time of the remaining sub-pixels includes: the pre-charging time after scanning is started and before writing its own data signal, and the duration of its own data signal writing (when r is greater than 1, the r-th duration Jr of the r-th data signal group in the driving signal group corresponding to the driving unit group). Since the on-time HG of the sub-pixel rows is the same in each driving unit group, the charging time of the first sub-pixel row in the driving unit group is equal to the charging time of the remaining sub-pixel rows, avoiding insufficient charging of the sub-pixel row corresponding to the first data signal group in the driving unit group, which would lead to uneven brightness.

[0282] It should be noted that Figure 16 uses n=4 as an example for illustration. G1, G2, G3, and G4 are the scanning signals of the four sub-pixel rows, and the data signal groups input to the four sub-pixel rows are Z11, Z12, Z13, and Z14 respectively.

[0283] In some embodiments, the duration of writing the data signal of the r-th sub-pixel row in the driving unit group, that is, the duration Jr of the r-th data signal group in the driving signal group corresponding to the driving unit group, is greater than 0 and less than or equal to HG.

[0284] In some embodiments, as shown in FIG16, J1 = HG, J2 = J3 = J4 = HG / 3.

[0285] In some embodiments, in the non-charging compensation mode, as shown in FIG17, the sub-pixel row opening time tt0r (r is greater than or equal to 1 and less than or equal to n) is earlier than the time tmr (r is greater than or equal to 1 and less than or equal to n) when the data signal group corresponding to the sub-pixel row is output from the charging compensation circuit.

[0286] It should be noted that Figure 17 uses n=4 as an example for illustration. G1, G2, G3, and G4 are the scanning signals of the four sub-pixel rows, and the data signal groups input to the four sub-pixel rows are Z11, Z12, Z13, and Z14 respectively.

[0287] In some embodiments, as shown in FIG17, the on-time HG of the sub-pixel rows is the same. In each driving unit group, the duration of writing the data signal of the sub-pixel row itself is equal to the r-th duration Jr of the data signal group in the driving signal group corresponding to the driving unit group, where r is greater than or equal to 1 and less than or equal to n; J1 = J2 = J3 = J4 = HG / 2.

[0288] In some embodiments, the display mode further includes a second resolution mode, wherein the resolution of the second resolution mode is lower than the resolution of the first resolution mode; and further includes:

[0289] Determine the scan signal for each sub-pixel row in the second resolution mode;

[0290] The control gate drive circuit provides scan signals to multiple scan lines, scans multiple drive unit groups according to a preset scan order, and simultaneously scans n sub-pixel rows in the activated drive unit group.

[0291] The display device driving method provided in this disclosure, in the second resolution mode, i.e. the lower resolution mode, can further reduce power consumption by simultaneously scanning n sub-pixel rows in the turn-on driving unit group through a gate driving unit.

[0292] In summary, the driving chip, display device, and driving method provided in this disclosure include a charging compensation circuit. The charging compensation circuit, in response to a first charging control signal inputting a data signal group, buffers the data signal group for a preset duration before outputting it in response to a second charging control signal. In charging compensation mode, the preset duration corresponding to the first data signal group in the transmission sequence within each driving signal group is less than the preset duration corresponding to each of the other data signal groups. This results in the output duration of the data signal in the first data signal group being greater than the output duration of the data signal in the other data signal groups. When the driving chip is applied to a display product, in charging compensation mode, when the driving chip provides data signals to the data line for charging, the output duration of the first data signal group can be increased, and the output duration of the other data signal groups can be decreased. This ensures that the charging duration of the data signal of the sub-pixel row corresponding to the first data signal group is greater than the charging duration of the data signal of the sub-pixel rows corresponding to the other data signal groups. Even if the sub-pixel row corresponding to the first data signal group has no pre-charging, the charging duration of each sub-pixel row can be made the same, avoiding uneven brightness caused by insufficient charging of the sub-pixel row corresponding to the first data signal group.

[0293] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0294] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0295] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0296] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0297] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0298] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A driver chip, wherein, The driving chip comprises: a data signal transmission circuit configured to sequentially output a plurality of data signal groups; each of the data signal groups comprises a plurality of data signals; n data signal groups sequentially outputted in the plurality of data signal groups are a driving signal group, and n is an integer greater than 1; a charging compensation circuit electrically connected with the data signal transmission circuit; the charging compensation circuit is configured to: in response to a first charging control signal, sequentially input the plurality of data signal groups; for each of the data signal groups, in response to a second charging control signal, output the data signal group after a preset time length at a start time of a data input period corresponding to the data signal group; wherein in a charging compensation mode, a preset time length corresponding to a first data signal group in a transmission sequence in each of the driving signal groups is less than a preset time length corresponding to each of the remaining data signal groups.

2. The drive chip of claim 1, wherein, The charging compensation circuit comprises: m cascaded sub-circuits; wherein m is an integer greater than or equal to 3; the sub-circuit comprises: a control signal input end; the control signal input end of the first-stage sub-circuit is configured to input the first charging control signal, and the control signal input end of each of the remaining sub-circuits except the first-stage sub-circuit is configured to input the second charging control signal; a data signal input end; the first-stage sub-circuit comprises one data signal input end configured to input a plurality of data signals in series; each of the remaining sub-circuits except the first-stage sub-circuit comprises a plurality of data signal input ends configured to input a plurality of data signals in parallel; a plurality of data signal output ends; the plurality of data signal output ends of the i-th stage sub-circuit are configured to output the data signals in parallel at the i-th time after the start time of the data input period corresponding to the data signal group; wherein i is an integer greater than or equal to 1 and less than or equal to m; the data signal input end of each of the remaining sub-circuits except the first-stage sub-circuit is electrically connected with the data signal output end of the previous-stage sub-circuit in one-to-one correspondence; the first-stage sub-circuit is configured to: in each data input period, in response to the first charging control signal inputting the data signal group, shifting and registering the data signals of the data signal group and outputting the data signals in parallel at the first time after the start time of the data input period; the i-th stage sub-circuit with i greater than 1 is configured to: in each data input period, in response to the second charging control signal, at the i-th time after the start time of the data input period, latch and output a plurality of data signals outputted by the previous-stage sub-circuit; wherein when i is greater than 1, the first time is earlier than or equal to the i-th time; and when i is less than m, the i-th time corresponding to the i-th stage sub-circuit is earlier than the i+1-th time corresponding to the i+1-th stage sub-circuit; a time length between the m-th time and the start time of the data input period is the preset time length corresponding to the data signal group. the first-stage sub-circuit comprises a serial shift register; 3. The drive chip of claim 2, wherein, ​ The serial shift register comprises a first data input end, a first control signal input end, and a plurality of first data output ends; The serial shift register is configured to, in response to the first charging control signal input by the first control signal input end, register a plurality of data signals input in series by the first data input end, and output the plurality of data signals in parallel by the plurality of first data output ends at the first time after the data input period starts.

4. The drive chip according to claim 2 or 3, wherein, At least one of the second-level sub-circuit to the mth sub-circuit comprises a latch; The latch comprises a plurality of second data input ends, a second control signal input end, and a plurality of second data output ends; The plurality of second data input ends of the latch are in one-to-one correspondence with the plurality of data output ends of the corresponding previous-level sub-circuit of the latch; The i-level sub-circuit, where i is greater than 1, comprises the latch, and the latch of the i-level sub-circuit is configured to, in response to the second charging control signal input by the second control signal input end, latch a plurality of data signals input in parallel by the plurality of second data input ends at the i time after the data input period starts, and output the plurality of data signals by the plurality of second data output ends. The driving chip further comprises a control signal generation circuit; the control signal generation circuit comprises a high-low level control signal generation circuit; 5. The drive chip of claim 4, wherein, The high-low level control signal generation circuit comprises a first control signal output end and m-1 second charging control signal output ends; the first control signal output end is electrically connected to the control signal input end of the first-level sub-circuit, and the m-1 second control signal output ends are respectively electrically connected to the control signal input ends of the second-level sub-circuit to the mth sub-circuit; The high-low level control signal generation circuit is configured to generate m high-low level signals, which are respectively the first charging control signal and m-1 second charging control signals, output the first charging control signal by the first control signal output end, and output the m-1 second charging control signals by the m-1 second control signal output ends respectively; wherein the high-low level signal comprises an alternating high level signal and a low level signal, and the voltage of the high level signal is greater than the voltage of the low level signal; The sub-circuit inputs the data signal in response to the high level signal or the low level signal. At least one of the second-level sub-circuit to the mth sub-circuit comprises a D flip-flop; 6. The driver chip according to any one of claims 2 to 4, wherein The D flip-flop comprises a plurality of third data input ends, a third control signal input end, and a plurality of third data output ends; The plurality of third data input ends of the D flip-flop are in one-to-one correspondence with the plurality of data output ends of the corresponding previous-level sub-circuit of the D flip-flop; ​ The i-th stage sub-circuit (i>1) includes the D flip-flop, and the D flip-flop of the i-th stage sub-circuit is configured to: in response to the second charging control signal input by the third control signal input end, latch the plurality of data signals input in parallel by the plurality of third data input ends at the i-th time point after the opening time point of the data input period, and output the plurality of data signals by the plurality of third data output ends.

7. The driving chip according to any one of claims 2 to 4, 6, wherein, The driving chip further includes a control signal generation circuit; the control signal generation circuit includes a clock signal generation circuit; the clock signal generation circuit includes a first clock signal output end and m-1 second clock signal output ends; the first clock signal output end is electrically connected with the control signal input end of the first stage sub-circuit, and the m-1 second clock signal output ends are respectively electrically connected with the control signal input ends of the second stage sub-circuit to the m-th stage sub-circuit; The clock signal generation circuit is configured to generate m clock signals as the first charging control signal and m-1 second charging control signals respectively, and output the first charging control signal by the first clock signal output end and output the m-1 second charging control signals by the m-1 second clock signal output ends respectively.

8. The driver chip according to any one of claims 2 to 7, wherein The i-th stage sub-circuit (i>1) is further configured to: in response to the second charging control signal, maintain the cache state of the plurality of data signals that have been latched.

9. The driver chip according to any one of claims 2 to 8, wherein In the charging compensation mode, in one driving signal group, the output duration of the first data signal group in the transmission sequence output by the charging compensation circuit is greater than the output duration of the remaining data signal groups output by the charging compensation circuit, and the output duration of the charging compensation circuit output for the remaining data signal groups except the first data signal group is equal.

10. The driver chip according to any one of claims 2 to 8, wherein In the non-charging compensation mode, in one driving signal group, the output duration of each data signal group output by the charging compensation circuit is equal.

11. A display device, wherein, The display device includes: The display panel includes a display area and a peripheral area surrounding the display area; the display panel includes: a plurality of data lines arranged along a first direction and extending from the display area to the peripheral area along a second direction, a plurality of pixel island rows located in the display area and arranged along the second direction, and a plurality of binding terminals located in the peripheral area; the first direction intersects the second direction; the plurality of binding terminals include a plurality of first binding terminals, and the first binding terminals are electrically connected with the data lines at one end of the data line extension direction; each of the plurality of pixel island rows includes: a plurality of pixel islands arranged along the first direction; each of the pixel islands includes: a plurality of sub-pixels arranged along the second direction A plurality of sub-pixel units, the sub-pixel units include a plurality of sub-pixels arranged along the first direction; a plurality of the sub-pixel units arranged along the first direction form a sub-pixel row, and a plurality of the sub-pixel units arranged along the second direction form a sub-pixel column; the sub-pixel column is electrically connected with the data line; the sub-pixels in the same sub-pixel row are of the same color, and the sub-pixels in any two adjacent sub-pixel rows are of different colors; in adjacent n rows of the pixel island rows, the sub-pixel rows including the sub-pixels of the same color form a driving unit group; The driving chip according to any one of claims 1-10 is bound with the plurality of binding terminals in the peripheral area; the charging compensation circuit is electrically connected with the plurality of first binding terminals; in the charging compensation mode, the charging compensation circuit is configured to sequentially provide the n sub-pixel rows in the driving unit group with the data signal groups through the plurality of first binding terminals and the plurality of data lines, and the n data signal groups corresponding to one driving unit group are one driving signal group.

12. The display device of claim 11, wherein, The display panel further includes: A plurality of scan lines extending from the display area to the peripheral area along the first direction; one row of the sub-pixel rows is electrically connected with the same scan line; A gate drive circuit including at least one group of cascaded shift register units; the cascaded shift register units are located in the peripheral area on one side of the display area in the first direction; the plurality of scan lines electrically connected with the same shift register unit corresponding to each driving unit group are electrically connected with the same shift register unit; The plurality of binding terminals further include a plurality of second binding terminals; the plurality of second binding terminals are electrically connected with the gate drive circuit; The charging compensation circuit is further configured to provide the gate drive circuit with a gate drive signal; the gate drive circuit is configured to, in the charging compensation mode, provide the plurality of scan lines with a scan signal in response to the gate drive signal, scan the driving unit groups in a preset scan order, and sequentially scan to turn on each sub-pixel row in the driving unit groups.

13. The display device of claim 12, wherein, In the charging compensation mode, for each driving unit group, the gate drive circuit sequentially scans to turn on each sub-pixel row in the driving unit group, specifically including: The time of scanning and turning on the first row of sub-pixel rows in the preset scan order is equal to the time of outputting the data signal group corresponding to the first row of sub-pixel rows from the charging compensation circuit; The time of scanning and turning on each sub-pixel row except the first row of sub-pixel rows is earlier than the time of outputting the data signal group corresponding to the sub-pixel row from the charging compensation circuit.

14. The display device of claim 12, wherein, In the non-charging compensation mode, the gate drive circuit is further configured to, for each driving unit group, scan and turn on the sub-pixel row at a time earlier than the time of outputting the data signal group corresponding to the sub-pixel row from the charging compensation circuit.

15. A driving method of a display device according to any one of claims 11 to 14, wherein, The method includes: According to the image to be displayed and the display mode, the data signal transmission circuit is controlled to output a plurality of data signal groups in a preset data transmission sequence; the display mode includes a first resolution mode, and the first resolution mode includes a charge compensation mode; According to the display mode, a first charge control signal is loaded to the charge compensation circuit to control the charge compensation circuit to input a data signal group in each data input period in the preset data transmission sequence; and for each data signal group, a second charge control signal is loaded to the charge compensation circuit to control the charge compensation circuit to output the data signal group after a preset time length from the start time of the data input period corresponding to the data signal group; in the charge compensation mode, the preset time length corresponding to the first data signal group in the transmission sequence in each drive signal group is less than the preset time length corresponding to each of the remaining data signal groups.

16. The method of claim 15, wherein, The charge compensation circuit includes m cascaded sub-circuits; in each data input period, a first charge control signal is loaded to the charge compensation circuit to control the charge compensation circuit to output the data signal group after a preset time length from the start time of the data input period corresponding to the data signal group, and the control specifically includes: The first charge control signal is loaded to the control signal input end of the first-stage sub-circuit to control the first-stage sub-circuit to shift and output in parallel a plurality of data signals included in the data signal group in series at the first time after the start time of the data input period; The second charge control signal is loaded to the control signal input end of the i-th stage sub-circuit to control the i-th stage sub-circuit to latch and output a plurality of data signals output by the previous-stage sub-circuit at the i-th time after the start time of the data input period; when i is greater than 1, the first time is earlier than or equal to the i-th time, and when i is less than m, the i-th time corresponding to the i-th stage sub-circuit is earlier than or equal to the i+1-th time corresponding to the i+1-th stage sub-circuit. The second charge control signal is loaded to the control signal input end of the i-th stage sub-circuit to control the i-th stage sub-circuit to latch and output a plurality of data signals output by the previous-stage sub-circuit at the i-th time after the start time of the data input period, and the control specifically includes:

17. The method of claim 16, wherein, The high-low level signal is loaded to the control signal input end of the i-th stage sub-circuit, and the i-th stage sub-circuit latches and outputs a plurality of data signals output by the previous-stage sub-circuit at the i-th time after the start time of the data input period in response to the high-low level signal. The second charge control signal is loaded to the control signal input end of the i-th stage sub-circuit to control the i-th stage sub-circuit to latch and output a plurality of data signals output by the previous-stage sub-circuit at the i-th time after the start time of the data input period, and the control specifically includes:

18. The method of claim 16, wherein, ​ The control signal input end of the i-th stage sub-circuit is loaded with a clock signal, and the i-th stage sub-circuit latches and outputs the plurality of data signals output by the previous stage sub-circuit at the i-th time point after the start time of the data input period in response to the clock signal.

19. The method according to any one of claims 16 to 18, wherein, Each data input period is divided into a first time period and a second time period after the first time period, and the first time point is the start time of the second time period; the first stage sub-circuit is controlled to shift register and output in parallel the plurality of serial data signals included in the data signal group at the first time point, specifically comprising: In the first time period, the first stage sub-circuit is controlled to shift register and output in parallel the plurality of serial data signals included in the data signal group; in the second time period, the first stage sub-circuit is controlled to output in parallel the plurality of data signals.

20. The method of any one of claims 16-19, wherein, For each data signal group, the interval between the i-th time point and the start time of the data input period corresponding to the data signal group is the i-th time length, and i is an integer greater than 1 and less than m; In the charge compensation mode, the first time length corresponding to different data signal groups in the driving signal group is equal; in the same driving signal group, the m-th time length corresponding to different data signal groups is not completely equal.

21. The method of claim 20, wherein, In the driving signal group, the time length of the r-th data signal group in the data signal transmission sequence output by the charge compensation circuit is the r-th continuous time length Jr; r is an integer greater than or equal to 1 and less than or equal to n; In the charge compensation mode, in the driving signal group, when r is greater than 1, the r-th continuous time length Jr of the r-th data signal group in the data signal transmission sequence is equal, and the first continuous time length J1 of the first data signal group in the data signal transmission sequence is greater than the r-th continuous time length Jr of the r-th data signal group in the data signal transmission sequence.

22. The method of claim 21, wherein, In the charge compensation mode, at least the first charge control signal is a signal with a fixed period, and at least the second charge control signal corresponding to the m-th stage sub-circuit is a signal with a period.

23. The method of any one of claims 16-22, wherein, The first resolution mode further includes a non-charge compensation mode, and in the non-charge compensation mode, the i-th time length corresponding to different data signal groups is the same.

24. The method of claim 23, wherein, In the non-charge compensation mode, in the driving signal group, the r-th continuous time length Jr of the r-th data signal group in the data signal transmission sequence is equal.

25. The method of claim 24, wherein, In the non-charge compensation mode, the first charge control signal and the second charge control signal are clock signals with a fixed period.

26. The method of any one of claims 15-25, wherein, The display panel further comprises a plurality of scan lines and a gate drive circuit; the method further comprises: controlling the driving chip to load a gate drive signal to the gate drive circuit; controlling the gate drive circuit to provide a scan signal to the plurality of scan lines in response to the gate drive signal, scanning the driving unit group in a preset scan order, and sequentially scanning to turn on each sub-pixel row in the driving unit group. ​ 27. The method of claim 26, wherein, In the charging compensation mode, the turning-on time of the first row of the sub-pixel rows in the preset scanning sequence in the driving unit group is equal to the time when the data signal group corresponding to the first row of the sub-pixel rows is output from the charging compensation circuit; and the turning-on time of each of the remaining sub-pixel rows in the driving unit group, except the first row of the sub-pixel rows, is earlier than the time when the data signal group corresponding to the sub-pixel row is output from the charging compensation circuit.

28. The method of claim 26, wherein, In the non-charging compensation mode, the turning-on time of the sub-pixel row is earlier than the time when the data signal group corresponding to the sub-pixel row is output from the charging compensation circuit.

29. The method of any one of claims 15-28, wherein, The display mode further includes a second resolution mode, the resolution corresponding to the second resolution mode being lower than the resolution corresponding to the first resolution mode; and the method further includes: determining a scanning signal of each of the sub-pixel rows in the second resolution mode; controlling the gate driving circuit to provide a scanning signal to the plurality of scanning lines, scan the plurality of driving unit groups according to a preset scanning sequence, and simultaneously scan and turn on n sub-pixel rows in the driving unit group.

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