Digital processing integrated board effector for radiation damage detection

Abstract

The invention discloses a digital processing integrated board effector for radiation damage detection. The digital processing integrated board effector comprises a circuit board, the circuit board is provided with an FPGA chip, and a digital interface circuit, an analog interface circuit, a reconstruction refresh circuit and a power distribution circuit which are electrically connected with the FPGA chip. The digital interface circuit receives the test remote control instruction, transmits the test remote control instruction to the FPGA chip for execution, and feeds back an execution result; the analog interface circuit receives the test analog signal, converts the test analog signal, transmits the converted test analog signal to the FPGA chip, converts a test digital signal sent by the FPGA chip, and feeds back the converted test digital signal; the reconstruction refresh circuit comprises a refresh control circuit and a storage circuit, the FPGA chip receives a refresh test instruction, and data erasing, data writing and verification starting operation are carried out on data stored in the storage circuit through the refresh control circuit; and the power supply distribution circuit performs secondary voltage division distribution on the power supply and feeds back a power supply current value, so that centralized radiation damage effect detection on various types of electronic components is realized.

Description

Technical Field

[0001] This invention relates to the field of spaceborne equipment testing technology, and in particular to a digital processing integrated plate effect for radiation damage detection. Background Technology

[0002] In outer space, various circuit boards and electronic components in spaceborne equipment are exposed to radiation from multiple sources, such as electromagnetic radiation and X-ray ionization radiation. These radiations can affect the normal operation of electronic components to varying degrees.

[0003] In the existing technology, there is a lack of universal test board effect materials, and it is not possible to complete the centralized radiation damage effect detection of multiple types of electronic components under the same test conditions. Summary of the Invention

[0004] The main technical problem solved by this invention is to provide a digital processing integrated board effect material for radiation damage detection, which solves the problem that the existing technology lacks a universal board effect material for testing, making it difficult to perform centralized radiation damage effect detection on various types of electronic components.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention includes: A digital processing integrated board effector for radiation damage detection, comprising a digital processing integrated board effector circuit board and a test device electrically connected to the digital processing integrated board effector circuit board. The digital processing integrated circuit board is equipped with an FPGA chip, and a digital interface circuit, an analog interface circuit, a reconfiguration and refresh circuit, and a power distribution circuit that are electrically connected to the FPGA chip. The digital interface circuit is used to receive test remote control commands from the test equipment, transmit them to the FPGA chip for execution, and then return the execution result to the test equipment as test telemetry information for verification. The analog interface circuit is used to receive test analog signals from the test equipment, perform analog-to-digital conversion, and transmit them to the FPGA chip to verify the correctness of the test analog signals; it also performs digital-to-analog conversion on the test digital signals sent by the FPGA chip and transmits them to the test equipment to verify the correctness of the test digital signals. The reconstructed refresh circuit includes a refresh control circuit and a storage circuit, which is used for the FPGA chip to receive refresh test commands from the test equipment, and under the action of the refresh control circuit, to perform data erasure, data writing and start verification operations on the data stored in the storage circuit. The power distribution circuit is used to perform secondary voltage division and distribution of the power supply from the test equipment to the circuit board, and to feed back the power supply current value to the test equipment.

[0006] Optionally, the digital interface circuit includes an RS422 receiver chip, an RS422 transmitter chip, and a CAN bus chip, which are electrically connected to the FPGA chip respectively. The RS422 receiver chip is used to receive test remote control commands and transmit them to the FPGA chip for execution. The RS422 transmitting chip is used to send the execution result to the test equipment; The CAN bus chip is used to receive test remote control commands, transmit them to the FPGA chip for execution, and send the execution results to the test equipment.

[0007] Optionally, the analog interface circuit includes an ADC chip and a DAC chip, which are electrically connected to the FPGA chip respectively. The ADC chip is used to receive ADC test simulation signals sent from the test equipment, perform analog-to-digital conversion, and then transmit them to the FPGA chip to verify the correctness of the test simulation signals. The DAC chip is used to receive the DAC test digital signal sent from the FPGA chip, perform digital-to-analog conversion, and send it to the test equipment to verify the correctness of the test digital signal.

[0008] Optionally, the refresh control circuit includes a refresh chip, which is electrically connected to the FPGA chip and is used to reload the FPGA chip.

[0009] Optionally, the storage circuit includes a NOR FLASH memory chip and a PROM memory chip. The NOR FLASH memory chip and the PROM memory chip are electrically connected to the FPGA chip respectively. The PROM memory chip is used to store the original startup file, and the NOR FLASH memory chip is used to store the reconstruction file and for debugging by the test equipment.

[0010] Optionally, the power distribution circuit includes a first power chip, a second power chip, a first low-dropout regulator, a second low-dropout regulator, and a third power chip. The power supply is converted by the first power chip to power the FPGA chip; The power supply is divided into three branches after passing through the second power chip. One branch provides digital power voltage to the digital interface circuit, the analog interface circuit, the reconfiguration and refresh circuit, and the FPGA chip; another branch is electrically connected to the first low-dropout regulator to power the FPGA chip; and the third branch is electrically connected to the second low-dropout regulator to power the FPGA chip. The power supply, after being converted by the third power chip, provides analog power voltage to the analog interface circuit.

[0011] Optionally, the reconfiguration refresh circuit further includes a watchdog control circuit, which is electrically connected to the refresh control circuit and is used to reset the refresh control circuit.

[0012] Optionally, the reconstruction method of the reconstructed refresh circuit includes a FLASH erasure step, a data writing step, and a startup verification step. The FLASH erasure step includes: the test device sends a FLASH erasure command, the FPGA chip sends an erasure command to the refresh chip after receiving the command, and at the same time modifies the telemetry of the reconstructed FLASH status to "erasing in progress", and modifies it to "erased" after the erasure is completed. The test device confirms whether the erasure operation is completed through telemetry. The data writing steps include: the test device sends a reconstructed data write command, the FPGA chip enters the data receiving and writing FLASH mode, modifies the reconstructed FLASH status telemetry to "writing", and starts waiting for data; after receiving the data, it performs verification. If the verification passes, it is sent to the refresh chip; otherwise, an error is recorded; after all data is sent, the test device checks to confirm whether there are any missing frames. If there are any missing frames, it polls the missing frame number through telemetry and resends the missing frames; after completing the missing frames, it sends a data writing completion command. The startup verification step includes: the test device sends a reconstruction startup command, the FPGA chip receives the command and sends a command to the refresh chip, the refresh chip receives the command and reloads the FPGA chip, and the test device confirms whether the reconstruction program has been successfully started based on telemetry information.

[0013] Optionally, the test equipment 2 provides power supply voltage to the digital processing integrated circuit board effect circuit board, and the digital interface of the digital processing integrated circuit board effect circuit board includes one set of synchronous RS422 receiving interface and one set of synchronous RS422 transmitting interface, and one set of CAN bus interface. The analog interface includes ADC clock input, DAC clock input, 140MHz intermediate frequency input, and 140MHz intermediate frequency output. The 5V power supply and digital interface use a J30J connector, while the analog interface uses an SMA interface. The 5V power supply and digital interface are connected to test equipment 2 via a J30J connector, and the analog interface is connected to test equipment 2 via an SMA interface.

[0014] Optionally, the storage circuit uses two NOR FLASH memory chips and six PROM memory chips. The PROM memory chip is used to store the original boot file, one NOR FLASH memory chip is used to store the reconstruction file, and one NOR FLASH memory chip 1421 is used for debugging the test device 2. Among them, the NOR FLASH memory chip uses the JFM29LV641 chip, and the PROM memory chip 1422 uses the B17V16RH chip. The on-orbit reconfiguration process of the reconfiguration and refresh circuit is implemented by FPGA chip 11 of model JFM7K325T-C, and RS422 receiver chip of model JSR26C32 and RS22 transmitter chip of model JSR26C31A are used for reconfiguration control and data transmission.

[0015] The beneficial effects of this invention are: The present invention relates to a digital processing integrated board effect device for radiation damage detection, comprising a circuit board on which an FPGA chip is mounted, and a digital interface circuit, an analog interface circuit, a reconfiguration and refresh circuit, and a power distribution circuit electrically connected to the FPGA chip. The digital interface circuit receives test remote control commands from the test equipment, transmits them to the FPGA chip for execution, and returns the execution result to the test equipment for verification as test telemetry information. The analog interface circuit receives test analog signals from the test equipment, performs analog-to-digital conversion, and transmits them to the FPGA chip to verify the correctness of the test analog signals; it also performs digital-to-analog conversion on test digital signals sent by the FPGA chip and transmits them to the test equipment to verify the correctness of the test digital signals. The reconfiguration and refresh circuit includes a refresh control circuit and a storage circuit. The FPGA chip receives refresh test commands from the test equipment and, under the action of the refresh control circuit, performs data erasure, data writing, and verification initiation operations on the data stored in the storage circuit. The power distribution circuit performs secondary voltage division and distribution on the power supply from the test equipment and feeds back the power supply current value to the test equipment, thereby realizing centralized radiation damage effect detection for various types of electronic components. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the circuit composition of the digital processing integrated board effector for radiation damage detection according to the present invention; Figure 2 This is a schematic diagram showing the connection relationship between the circuit board and the testing equipment of the digital processing integrated board effector for radiation damage detection according to the present invention; Figure 3 This is a schematic diagram of the components in the circuit board of the digital processing integrated board effector for radiation damage detection according to the present invention; Figure 4 This is a schematic diagram illustrating the principle of the on-orbit reconstruction process of the digital processing integrated plate effector for radiation damage detection according to the present invention. Figure 5 This is a schematic diagram of the reconstruction steps of the digital processing integrated board effector for radiation damage detection according to the present invention; Figure 6 This is a schematic diagram of the power distribution circuit of the digital processing integrated board effect device for radiation damage detection according to the present invention. Figure 7 This is a schematic diagram of the power supply voltage sequence for the digital processing integrated board effector used for radiation damage detection according to the present invention. Detailed Implementation

[0017] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0018] It should be noted that, unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0019] Figure 1 The present invention illustrates a digital processing integrated board effect device for radiation damage detection, comprising a digital processing integrated board effect device circuit board 1, an FPGA chip 11 disposed on the digital processing integrated board effect device circuit board 1, and a digital interface circuit 12, an analog interface circuit 13, a reconfiguration refresh circuit 14, and a power distribution circuit 15 electrically connected to the FPGA chip 11.

[0020] In this embodiment, the FPGA chip 11 can be a JFM7K325T-C chip. The JFM7K325T-C chip is a high-performance SRAM-type FPGA chip that internally includes programmable logic modules (CLBs), general-purpose input / output modules (IOBs), as well as IP resources such as multipliers, block RAM (BRAM), and digital clock manager (DCM). It can be field-configured via JTAG, serial mode, or parallel mode to flexibly implement various required functions. This FPGA chip has a total radiation dose withstand capability greater than 100 krad (Si) and a single-event lockout (SEL) rating of 81 MeV-cm. 2 / mg, meeting construction specifications.

[0021] The digital interface circuit 12 is used to receive test remote control commands from the test equipment 2, transmit them to the FPGA chip 11 for execution, and then return the execution result to the test equipment 2 as test telemetry information for verification.

[0022] The analog interface circuit 13 is used to receive the test analog signal from the test equipment 2, perform analog-to-digital conversion and transmit it to the FPGA chip 11 to verify the correctness of the test analog signal; and to perform digital-to-analog conversion on the test digital signal sent by the FPGA chip 11 and transmit it to the test equipment 2 to verify the correctness of the test digital signal.

[0023] The reconfiguration refresh circuit 14 includes a refresh control circuit 141 and a storage circuit 142. It is used for the FPGA chip 11 to receive refresh test instructions from the test device 2, and under the action of the refresh control circuit 141, to perform data erasure, data writing and start verification operations on the data stored in the storage circuit 142.

[0024] The power distribution circuit 15 is used to perform secondary voltage division and distribution on the power supply from the test equipment 2, and to feed back the power supply current value to the test equipment 2.

[0025] Test equipment 2 uses the SEM module integrated within the FPGA chip 11 to detect single-event upsets in real time and records the number of upsets. The CAN bus interface and RS422 interface of the digital interface circuit 12 are used as remote control interfaces. The FPGA chip 11 executes any remote control command received from either interface, and the remote control interface simultaneously feeds back telemetry information. The ADC test module of the analog interface circuit 13 receives analog test signals, verifies their correctness, and then feeds back the results. The DAC test module of the analog interface circuit 13 sends digital test signals and judges their correctness. The RS422 interface includes a synchronous RS422 receiving interface and a synchronous RS422 transmitting interface. The synchronous RS422 receiving interface can send specific test data to verify its normal operation, while the synchronous RS422 transmitting interface can send specific test data, which is received by test equipment 2 to determine its normal operation. This digital processing integrated board effect device can also feed back parameters such as the temperature and core voltage of the FPGA chip 11 through the remote control interface.

[0026] Combination Figure 2 As shown, test equipment 2 provides a 5V power supply to the digital processing integrated circuit board effect (DSP). The DSP's digital interfaces include one set each of synchronous RS422 receive and transmit interfaces, and one CAN bus interface. The analog interfaces include ADC clock input, DAC clock input, 140MHz intermediate frequency input, and 140MHz intermediate frequency output. The power supply and digital interfaces use a single J30J connector, while the analog interfaces use SMA connectors.

[0027] The 5V power supply and digital interface are connected to test device 2 via a J30J connector, while the analog interface is connected to test device 2 via an SMA connector. Test device 2 is connected to the main control computer 3 via a network cable. The main control computer 3 has control software installed on it, which controls the tested device 2 and displays the test results.

[0028] Combination Figure 3 As shown, in some embodiments, the digital interface circuit 12 includes an RS422 receiver chip 121, an RS422 transmitter chip 122, and a CAN bus chip 123, which are electrically connected to the FPGA chip 11 respectively.

[0029] RS422 receiver chip 121 is used to receive test remote control commands and transmit them to FPGA chip 11 for execution; RS422 transmitter chip 122 is used to send the execution results to test device 2; CAN bus chip 123 is used to receive test remote control commands, transmit them to FPGA chip 11 for execution, and send the execution results to test device 2.

[0030] In this embodiment, the RS422 receiver chip 121 can be a JSR26C32 chip, and the RS422 transmitter chip 122 can be a JSR26C31A chip. Both the JSR26C32 and JSR26C31A chips have a total ionization dose resistance of ≥100 krad (Si) and a maximum voltage rating of 75 MeV·cm⁻¹. 2 The single-particle latch-up threshold (SEL) is set at / mg. The CAN bus chip can be model JR82C250J, which has an ionization total dose resistance of ≥100 krad(Si) and a strength of 75 MeV·cm⁻¹. 2 Single-particle latch-up threshold SEL (LET) / mg, 15MeV·cm 2 The single-particle flip threshold LETth is 1 mg.

[0031] In some embodiments, the analog interface circuit 13 includes an ADC chip 131 and a DAC chip 132, which are electrically connected to the FPGA chip 11 respectively. The ADC chip 131 is used to receive a 140MHz ADC test analog signal from the test device 2, perform analog-to-digital conversion, and transmit it to the FPGA chip 11. The FPGA chip 11 verifies the correctness of the converted test analog signal. The DAC chip 132 is used to receive a DAC test digital signal sent from the FPGA chip 11, perform digital-to-analog conversion, and send it to the test device 2 as a 140MHz analog signal. The test device 2 verifies the correctness of the 140MHz analog signal.

[0032] In this embodiment, the ADC chip 131 needs to receive ADC test analog signals. According to the channel design requirements, the center frequency of the received test analog signals is 140MHz, while the processing clock for the received test analog signals is approximately 80MHz, and the signal bandwidth is less than 20MHz. Furthermore, considering the large dynamic range of the processed received test analog signals, in order to ensure the quality of the received test analog signals under interference conditions, the ADC chip 131 needs to have the largest possible dynamic range; that is, the sampling bit depth of the ADC chip 131 needs to be sufficiently high.

[0033] Considering both requirements and the aerospace component selection criteria, the ADC chip 131 can be a chip from the SAD2208MQRH series. The SAD2208MQRH-T type radiation-hardened 16-bit 100MSPS A / D converter is a monolithic integrated circuit manufactured using CMOS technology. This product has a pipelined structure, internally containing a high-precision reference, clock stabilization circuit, pipelined signal processing circuit, output digital correction circuit, and digital output interface circuit. It is specifically designed for high-frequency, wide dynamic range signal digital processing. The analog input must be driven by a differential input signal, and the analog input range is controlled and set by an external FPGA chip 11. The digital output has three modes: LVDS, full-speed CMOS, and half-speed CMOS. The clock input can be differentially or single-ended driven using sine wave, PECL, and LVDS input signals. This device can realize input amplitude control, reference selection control, low power consumption, and normal LVDS mode control, meeting the functional requirements of this embodiment.

[0034] In this embodiment, the DAC chip 132 can be a B9122 chip. The B9122 chip is a dual-channel, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a 1 GSPS sampling rate and can generate multi-carrier signals up to the Nyquist frequency. The B9122 chip supports a maximum sampling frequency of 1 GSPS, supports intermediate frequency (IF) sampling, and allows for input IF signal frequencies up to 1 GSPS, which meets the requirements of the input signal frequency and sampling frequency in this embodiment.

[0035] In some embodiments, the refresh control circuit 141 includes a refresh chip 1411, which is electrically connected to the FPGA chip 11 and is used to reload the FPGA chip 11; the storage circuit 142 includes a NOR FLASH memory chip 1421 and a PROM memory chip 1422, which are electrically connected to the FPGA chip 11 respectively. The PROM memory chip 1422 is used to store the original startup file, and the NOR FLASH memory chip 1421 is used to store the reconstruction file and for debugging by the test device 2.

[0036] In some embodiments, the reconfiguration refresh circuit 14 further includes a watchdog control circuit 143, which is electrically connected to the refresh chip 1411. The watchdog control circuit 143 is used to periodically check the internal status of the refresh chip 1411, and sends a reset signal to the refresh chip 1411 to reset the refresh chip 1411 if an error occurs.

[0037] In this embodiment, the refresh chip 1411 in the refresh control circuit 141 can be a JFMRS01 chip. The JFMRS01 chip is a chip specifically designed for refreshing the configuration memory of SRAM-type FPGA chips. The JFMRS01 chip adopts highly reliable anti-single-event upset hardening design technology and has the ability to configure the FPGA chip 11 in serial mode and refresh the FPGA chip 11 in JTAG mode.

[0038] The storage circuit 142 employs two NOR FLASH memory chips 1421 and six PROM memory chips 1422. The PROM memory chips 1421 store the original boot file, one NOR FLASH memory chip 1422 stores the reconstruction file, and one NOR FLASH memory chip 1421 is used for debugging the test equipment 2. The NOR FLASH memory chip 1421 can be a JFM29LV641 chip, and the PROM memory chips 1422 can be a B17V16RH chip. The B17V16RH chip is an aerospace-grade PROM memory chip 1422 with a storage capacity of 16Mb, capable of configuring various FPGA chips 11, and supporting both serial and parallel configuration modes. The B17V16RH has strong radiation resistance; when used to configure FPGA chips 11 in conjunction with a timed refresh scheme, it can significantly improve the on-orbit adaptability of digital signal processing.

[0039] In addition, placing the JFMRS01 chip between the FPGA chip 11 and the PROM memory chip 1422 also serves as a data exchange bridge.

[0040] Combination Figure 4 As shown, the on-orbit reconstruction process of the reconfiguration and refresh circuit 14 is implemented by the FPGA chip 11 of model JFM7K325T-C, and the RS422 receiver chip 121 of model JSR26C32 and the RS22 transmitter chip 122 of model JSR26C31A are used for reconstruction control and data transmission.

[0041] Furthermore, combined with Figure 5 As shown, the reconstruction is divided into three steps: FLASH erasure step S1, data writing step S2, and startup verification step S3.

[0042] Specifically, the FLASH erasure step S1 is as follows: Test device 2 sends a FLASH erasure command. After receiving the command, FPGA chip 11 sends an erasure command to refresh chip 1411. At the same time, it modifies the telemetry status of the reconstructed FLASH to "erasing in progress". After the erasure is completed, it is modified to "erased". Test device 2 confirms whether the erasure operation is completed through telemetry.

[0043] The data writing step S2 is as follows: S21: Test device 2 sends a reconstructed data write command, and FPGA chip 11 enters the data receiving and writing FLASH mode, modifying the reconstructed FLASH status telemetry to "writing". At the same time, it begins waiting for data.

[0044] S22: After receiving the data, perform verification (frame number and CRC). If the verification passes, send it to the refresh chip 1411; otherwise, record the error.

[0045] S23: After all data transmission is completed, test device 2 checks the telemetry to confirm whether there are any missing frames (missing frames or erroneous frames). If there are missing frames, the missing frame number is polled via telemetry, and the missing frame is retransmitted.

[0046] S24: After completing the missing frame, send the data writing completion command.

[0047] The verification step S3 is as follows: Test device 2 sends a reconstruction start command. After receiving the command, FPGA chip 11 sends a command to refresh chip 1411. After receiving the command, refresh chip 1411 reloads FPGA chip 11. Test device 2 confirms whether the reconstruction program has been successfully started based on telemetry information.

[0048] Combination Figure 6 As shown, in some embodiments, the power distribution circuit 15 includes a first power chip 151, a second power chip 152, a first low-dropout regulator 154, a second low-dropout regulator 155, and a third power chip 153. The power supply, after being converted by the first power chip 151, provides a specific voltage value to the FPGA chip 11. The power supply, after being converted by the second power chip 152, is divided into three branches: one branch provides digital power voltage to the digital interface circuit 12, the analog interface circuit 13, the reconfiguration and refresh circuit 14, and the FPGA chip 11; another branch, electrically connected to the first low-dropout regulator 154, provides a specific voltage value to the FPGA chip 11; and the third branch, electrically connected to the second low-dropout regulator 155, provides a specific voltage value to the FPGA chip 11. The power supply, after being converted by the third power chip 153, provides analog power voltage to the analog interface circuit 13.

[0049] In this embodiment, the power distribution circuit 15 is mainly responsible for supplying power to the entire circuit board 1. The power supply voltage required by the FPGA chip 11 includes 1.0V, 1.8V, 3.3V, 2.5V, etc., the power supply voltage of the DAC chip 131 includes a digital power supply voltage of 3.3V and an analog power supply voltage of 3.3V, the power supply voltage of the ADC chip 132 includes a digital power supply voltage of 3.3V and an analog power supply voltage of 3.3V, the power supply voltage of the refresh chip 1411 includes a digital power supply voltage of 3.3V, and the interface chips of other digital interface circuits 12 require a 3.3V power supply voltage.

[0050] Among them, the first power chip 151, the second power chip 152 and the third power chip 153 can be the RSS0508HRH power chip. The RSS0508HRH power chip is a synchronous buck converter with internally integrated dual N-channel MOSFETs. It uses peak current mode control at a fixed switching frequency to improve transient response performance, simplifies external frequency compensation, and reduces the size of the inductor and the capacity of the filter capacitor by increasing the switching frequency, thus saving board space.

[0051] The first low-dropout regulator 154 and the second low-dropout regulator 155 can employ the RSW1101HRH radiation-resistant linear regulator. The RSW1101HRH radiation-resistant linear regulator is a positive-output, adjustable-voltage, high-voltage, high-current, low-dropout linear power supply. The power input voltage range is 0.95V to 5.5V, the control input voltage is 3.3V to 5.5V, and the output voltage range is 0.6V to 3.3V. Its high rated output current of up to 5A and excellent radiation resistance enable it to meet the power supply requirements of various satellite payloads, and the extremely low dropout voltage helps improve power conversion efficiency.

[0052] Specifically, the first power supply chip 151 converts the 5V supply voltage to 1V to provide 1V for the FPGA chip 11; the second power supply chip 152 converts the 5V supply voltage to a digital power supply voltage of 3.3V to provide 3.3V for the FPGA chip 11, refresh chip 1411, NOR FLASH memory chip 1421, PROM memory chip 1422, DAC chip 132, and ADC chip 131; the first low-dropout regulator 154 converts the 3.3V digital power supply voltage to 1.8V to provide 1.8V for the FPGA chip 11; the second low-dropout regulator 155 converts the 3.3V digital power supply voltage to 2.5V to provide 2.5V for the FPGA chip 11; and the third power supply chip 153 converts the 5V supply voltage to an analog power supply voltage of 3.3V to provide 3.3V analog power supply for the DAC chip 132 and ADC chip 131.

[0053] In addition, combined Figure 7 As shown, in this embodiment, the FPGA chip 11 requires the core power supply voltage of 1.0V to be powered on first, followed by the digital power supply voltage of 3.3V and the analog power supply voltage of 3.3V, and finally the 2.5V and 1.8V power-on sequence. Therefore, the PG function of the first power supply chip 151RSS0508HRH is used to drive the enable pins of the remaining second power supply chips 152, third power supply chips 153, first low-dropout regulator 154, and second low-dropout regulator 155, thereby achieving the following power-on sequence: 1V first, followed by the digital power supply voltage of 3.3V and the analog power supply voltage of 3.3V, and finally the 2.5V and 1.8V power-on sequence.

[0054] Therefore, this invention discloses a digital processing integrated board effect device for radiation damage detection, including a circuit board with an FPGA chip mounted on it, and a digital interface circuit, an analog interface circuit, a reconstruction and refresh circuit, and a power distribution circuit electrically connected to the FPGA chip. The digital interface circuit receives test remote control commands from the test equipment, transmits them to the FPGA chip for execution, and returns the execution result to the test equipment as test telemetry information for verification. The analog interface circuit receives test analog signals from the test equipment, performs analog-to-digital conversion, and transmits them to the FPGA chip to verify the correctness of the test analog signals; it also performs digital-to-analog conversion on the test digital signals sent by the FPGA chip and transmits them to the test equipment to verify the correctness of the test digital signals. The reconstruction and refresh circuit includes a refresh control circuit and a storage circuit. The FPGA chip receives refresh test commands from the test equipment and, under the action of the refresh control circuit, performs data erasure, data writing, and verification start operations on the data stored in the storage circuit. The power distribution circuit performs secondary voltage division and distribution on the power supply from the test equipment and feeds back the power supply current value to the test equipment, thereby realizing centralized radiation damage effect detection of various types of electronic components.

[0055] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A digital processing integrated board effect material for radiation damage detection, characterized in that, A test device is set up to be electrically connected to the digital processing integrated circuit board effector circuit board. The digital processing integrated circuit board is equipped with an FPGA chip, and a digital interface circuit, an analog interface circuit, a reconfiguration and refresh circuit, and a power distribution circuit that are electrically connected to the FPGA chip. The digital interface circuit is used to receive test remote control commands from the test equipment, transmit them to the FPGA chip for execution, and then return the execution result to the test equipment as test telemetry information for verification. The analog interface circuit is used to receive test analog signals from the test equipment, perform analog-to-digital conversion, and transmit them to the FPGA chip to verify the correctness of the test analog signals; it also performs digital-to-analog conversion on the test digital signals sent by the FPGA chip and transmits them to the test equipment to verify the correctness of the test digital signals. The reconstructed refresh circuit includes a refresh control circuit and a storage circuit, which is used for the FPGA chip to receive refresh test commands from the test equipment, and under the action of the refresh control circuit, to perform data erasure, data writing and start verification operations on the data stored in the storage circuit. The power distribution circuit is used to perform secondary voltage division and distribution of the power supply from the test equipment to the circuit board, and to feed back the power supply current value to the test equipment.

2. The digital processing integrated board effect material for radiation damage detection according to claim 1, characterized in that, The digital interface circuit includes an RS422 receiver chip, an RS422 transmitter chip, and a CAN bus chip, which are electrically connected to the FPGA chip respectively. The RS422 receiver chip is used to receive test remote control commands and transmit them to the FPGA chip for execution. The RS422 transmitting chip is used to send the execution result to the test equipment; The CAN bus chip is used to receive test remote control commands, transmit them to the FPGA chip for execution, and send the execution results to the test equipment.

3. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The analog interface circuit includes an ADC chip and a DAC chip, which are electrically connected to the FPGA chip respectively. The ADC chip is used to receive ADC test simulation signals sent from the test equipment, perform analog-to-digital conversion, and then transmit them to the FPGA chip to verify the correctness of the test simulation signals. The DAC chip is used to receive the DAC test digital signal sent from the FPGA chip, perform digital-to-analog conversion, and send it to the test equipment to verify the correctness of the test digital signal.

4. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The refresh control circuit includes a refresh chip, which is electrically connected to the FPGA chip. The refresh chip is used to reload the FPGA chip.

5. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The storage circuit includes a NOR FLASH memory chip and a PROM memory chip. The NOR FLASH memory chip and the PROM memory chip are electrically connected to the FPGA chip respectively. The PROM memory chip is used to store the original startup file, and the NOR FLASH memory chip is used to store the reconstruction file and for debugging the test equipment.

6. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The power distribution circuit includes a first power chip, a second power chip, a first low-dropout regulator, a second low-dropout regulator, and a third power chip. The power supply is converted by the first power chip to power the FPGA chip; The power supply is divided into three branches after passing through the second power chip. One branch provides digital power voltage to the digital interface circuit, the analog interface circuit, the reconfiguration and refresh circuit, and the FPGA chip; another branch is electrically connected to the first low-dropout regulator to power the FPGA chip; and the third branch is electrically connected to the second low-dropout regulator to power the FPGA chip. The power supply, after being converted by the third power chip, provides analog power voltage to the analog interface circuit.

7. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The reconfiguration refresh circuit also includes a watchdog control circuit, which is electrically connected to the refresh control circuit and is used to reset the refresh control circuit.

8. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The reconstruction method for the reconstructed refresh circuit includes a FLASH erasure step, a data writing step, and a startup verification step. The FLASH erasure step includes: the test device sends a FLASH erasure command, the FPGA chip sends an erasure command to the refresh chip after receiving the command, and at the same time modifies the telemetry status of the reconstructed FLASH to "erasing in progress", and modifies it to "erased" after the erasure is completed. The test device confirms whether the erasure operation is completed through telemetry. The data writing steps include: the test device sends a reconstructed data write command, the FPGA chip enters the data receiving and writing FLASH mode, modifies the reconstructed FLASH status telemetry to "writing", and starts waiting for data; after receiving the data, it performs verification. If the verification passes, it is sent to the refresh chip; otherwise, an error is recorded; after all data is sent, the test device checks to confirm whether there are any missing frames. If there are any missing frames, it polls the missing frame number through telemetry and resends the missing frames; after completing the missing frames, it sends a data writing completion command. The startup verification step includes: the test device sends a reconstruction startup command, the FPGA chip receives the command and sends a command to the refresh chip, the refresh chip receives the command and reloads the FPGA chip, and the test device confirms whether the reconstruction program has been successfully started based on telemetry information.

9. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The test equipment 2 provides power voltage to the digital processing integrated circuit board effect circuit board. The digital interface of the digital processing integrated circuit board effect circuit board includes one set of synchronous RS422 receiving interface and one set of synchronous RS422 transmitting interface, and one set of CAN bus interface. The analog interface includes ADC clock input, DAC clock input, 140MHz intermediate frequency input, and 140MHz intermediate frequency output. The 5V power supply and digital interface use a J30J connector, while the analog interface uses an SMA interface. The 5V power supply and digital interface are connected to test equipment 2 via a J30J connector, and the analog interface is connected to test equipment 2 via an SMA interface.

10. The digital processing integrated board effect material for radiation damage detection according to claim 1 or 2, characterized in that, The storage circuit uses two NOR FLASH memory chips and six PROM memory chips. The PROM memory chip is used to store the original boot file, one NOR FLASH memory chip is used to store the reconstruction file, and one NOR FLASH memory chip 1421 is used for debugging the test device 2. Among them, the NOR FLASH memory chip uses the JFM29LV641 chip, and the PROM memory chip 1422 uses the B17V16RH chip. The on-orbit reconfiguration process of the reconfiguration and refresh circuit is implemented by FPGA chip 11 of model JFM7K325T-C, and RS422 receiver chip of model JSR26C32 and RS22 transmitter chip of model JSR26C31A are used for reconfiguration control and data transmission.

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