Three-dimensional integrated circuit fault detection method and system

Abstract

The invention discloses a three-dimensional integrated circuit fault detection method and system, and relates to the field of circuit fault detection, and the system comprises a sensing module which is used for carrying out the cross-layer coupling signal synchronous sensing of interlayer interconnection nodes and a core unit based on the stacking density of a three-dimensional integrated circuit, and capturing the fault correlation original features in signals; the reconstruction module is used for carrying out hierarchical enhancement and three-dimensional interference shielding processing on the extracted fault associated original features so as to output a structured three-dimensional feature data set; the method can be adapted to circuits with different stacking densities, accurately capture fault correlation original features, improve feature data quality through hierarchical enhancement and interference shielding processing, accurately extract interlayer coupling distortion features through dynamic modeling, quickly lock fault positions and conduction paths by means of bidirectional mapping of space coordinates and interconnection topology, and improve fault positioning accuracy. And determining a fault type and a diffusion boundary by combining a three-dimensional fault equivalent field and double verification.

Description

Technical Field

[0001] This invention relates to the field of circuit fault detection technology, specifically to a three-dimensional integrated circuit fault detection method and system. Background Technology

[0002] Three-dimensional integrated circuits (3DICs) rely on a stacked architecture and TSV interconnects, which are prone to bonding failures, open / short circuits in interconnects, and thermal failures due to stacking stress, heat dissipation bottlenecks, and process deviations. These types of failures directly affect the chip's performance stability and long-term reliability, and are core issues in high-density integration scenarios.

[0003] The invention patent application with application number 202410824930.2 discloses a method for detecting through-silicon via (TSV) faults in three-dimensional integrated circuits. This method aims to solve the problem that "there may be some structural defects in the manufacturing process of TSVs. If there are gaps and pinholes in the TSV, the performance of the TSV will be significantly affected."

[0004] However, existing technologies for fault detection in 3D integrated circuits mainly focus on fault type identification and fault location, and usually lack the function of fault propagation boundary analysis, and the accuracy of fault type identification and fault location is poor.

[0005] To address this, we propose a three-dimensional integrated circuit fault detection method and system. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the existing technology, the present invention provides a three-dimensional integrated circuit fault detection method and system, which can effectively solve the problems of the existing technology.

[0007] To achieve the above objectives, the present invention is implemented through the following technical solutions; This invention discloses a three-dimensional integrated circuit fault detection system, comprising: The system comprises the following modules: a perception module for synchronously sensing cross-layer coupling signals of interconnect nodes and core units based on the 3D integrated circuit stacking density, capturing original fault-related features; a reconstruction module for performing layered enhancement and 3D interference shielding on the extracted original fault-related features to output a structured 3D feature dataset; an extraction module for dynamically modeling the 3D integrated circuit interconnect paths and extracting feature vectors of inter-layer coupling distortion caused by faults from the structured 3D feature dataset; a localization module for matching the inter-layer coupling distortion feature vectors with the physical structure through bidirectional mapping of 3D spatial coordinates and interconnect path topology to pinpoint the fault layer, unit, and cross-layer propagation path; a verification module for constructing a 3D fault equivalent field and performing double verification based on the fault localization results to determine the fault type and propagation boundary; and an output module for collecting fault localization, type, and propagation trajectory information to generate a 3D fault map and a detection report containing the complete fault link. The sensing module is interconnected with the reconstruction module via a wireless network. The reconstruction module is interconnected with the extraction module via a wireless network. The extraction module is interconnected with the positioning module via a wireless network. The positioning module is interconnected with the verification module via a wireless network. The verification module is interconnected with the output module via a wireless network.

[0008] Furthermore, the core unit of the three-dimensional integrated circuit includes a logic operation unit, a storage unit, an inter-layer interconnection interface unit, a power management unit, and a signal conditioning unit; The cross-layer coupling signal synchronous sensing process of the sensing module follows the following: ; In the formula: The synchronous sensing signal strength between the interconnection nodes of layer i and layer j at time t; This refers to the stacking density coefficient of three-dimensional integrated circuits. The coupling capacitance of the interconnection node between layer i and layer j; The physical distance between the interconnecting nodes of layer i and layer j; The original excitation signal; The signal transmission delay between the i-th and j-th layers; This represents the total number of interference sources. Let be the interference intensity coefficient of the k-th interference source; The correlation degree of the influence of the k-th interference source on the i-th layer node; Through real-time data collection And compare it with the preset signal reference value to capture the original characteristics of the fault association: Based on the normal operating state of the three-dimensional integrated circuit, preset signal reference values ​​are obtained through calibration for different inter-layer interconnection nodes and working conditions. The sensing module collects data at a preset sampling frequency. After filtering and denoising, the amplitude, trend of change and phase are compared with the corresponding preset signal reference value in multiple dimensions. When the comparison deviation exceeds the allowable fluctuation range or reaches the preset deviation threshold, it is determined that there are signs of fault association. The signal distortion parameters and corresponding node and timing information are recorded simultaneously to form the original features of fault association.

[0009] Furthermore, the hierarchical enhancement and three-dimensional interference shielding logic for the original fault-related features in the reconstruction module is as follows: ; In the formula: The enhanced feature data is from the l-th layer. The original fault association features extracted from layer l; Enhance the weights of the features in the l-th layer; The number of stereo interference types existing in the l-th layer; Let be the amplitude of the m-th type of stereo interference in the l-th layer; The preset interference suppression threshold; The reconstruction module, through The calculation formula outputs a structured 3D feature dataset after removing stereo interference and layering enhancement.

[0010] Furthermore, the dynamic modeling of inter-layer interconnection paths in the extraction module is achieved by constructing a path association matrix, wherein the matrix elements... This represents the dynamic correlation between the p-th interconnection path and the q-th interconnection path; Extracting fault-induced interlayer coupling distortion feature vectors from a structured 3D feature dataset: ; In the formula, K represents the total number of inter-layer interconnection paths; Let be the impedance distortion value of the k-th path; The standard impedance of the k-th path; Let be the phase distortion value of the k-th path; The standard phase of the k-th path; Let be the power loss distortion value of the k-th path; Let be the standard power loss of the k-th path.

[0011] Furthermore, the bidirectional mapping between the three-dimensional spatial coordinates of the positioning module and the interconnection path topology is represented as follows: ; In the formula: These are the physical space coordinates of a cell or node in a three-dimensional integrated circuit. This represents the forward mapping function; t is the topology dynamic update time. This is the adjacency matrix of the interconnection path topology; This represents the number of topologically related nodes. This represents the inverse mapping function; Let be the weight coefficient of the s-th topologically related node; Let be the local adjacency matrix corresponding to the s-th topologically associated node; Let be the update sequence of the s-th topologically related node; The coordinate-topology mapping coefficient matrix is ​​based on the physical layout preset of the three-dimensional integrated circuit. The positioning module uses the above bidirectional mapping model to match the distortion position corresponding to the interlayer coupling distortion feature vector V with the physical structure.

[0012] Furthermore, the field strength distribution of the three-dimensional fault equivalent field constructed in the verification module follows: ; In the formula: Let be the field strength of the three-dimensional fault equivalent field at coordinates (x, y, z); The electric field strength coefficient; This represents the fault equivalent charge. The equivalent dielectric constant of a three-dimensional integrated circuit; This is the field strength attenuation correction factor; The coordinates of the core fault location are shown in the preliminary diagram.

[0013] Furthermore, during the positive signal excitation process of the dual verification, the excitation signal strength is: ; In the reverse fault tracing process of the dual verification, the fault propagation coefficient is: ; In the formula: The strength of the basic excitation signal; This is the excitation gain coefficient; This represents the maximum withstand field strength of the system. For verification duration; For temporal field strength; The strength of the timing excitation signal; The verification module determines the fault type and propagation boundary by comparing the results of forward excitation and reverse tracing.

[0014] Furthermore, the logical expression for the output module to generate a three-dimensional fault map is as follows: ; In the formula: The grid model matrix of the three-dimensional fault map; This is the standard mesh model matrix for three-dimensional integrated circuits; Adjust the matrix for grid weights; This represents the mesh distortion matrix caused by the fault. The detection report includes the fault core coordinates, fault layer and unit number, cross-layer propagation path parameters, fault type, diffusion boundary range, fault equivalent field strength distribution data, eigenvector distortion peak value and corresponding time series information.

[0015] On the other hand, a three-dimensional integrated circuit fault detection method includes: Based on the 3D integrated circuit stacking density, cross-layer coupling signals of inter-layer interconnect nodes and core units are synchronously sensed. By comparing with preset signal benchmark values ​​in multiple dimensions, the original features of fault association are captured. Layered enhancement and three-dimensional interference shielding are performed on the original features of fault association to remove three-dimensional interference and enhance effective features, outputting a structured 3D feature dataset. The path association matrix is ​​constructed by dynamically modeling the inter-layer interconnect path. The inter-layer coupling distortion feature vector caused by the fault is extracted from the structured 3D feature dataset. Through bidirectional mapping of 3D spatial coordinates and interconnect path topology, the inter-layer coupling distortion feature vector is accurately matched with the physical structure to locate the fault layer, unit, and cross-layer propagation path. A 3D fault equivalent field is constructed. Based on the dual verification of forward signal excitation and reverse fault tracing, combined with feature matching and propagation coefficient analysis, the fault type and propagation boundary are determined. All information such as fault location, type, and propagation trajectory is collected to generate a 3D fault map and output a detection report containing the complete fault link.

[0016] Compared with the known prior art, the technical solution provided by this invention has the following beneficial effects: This invention provides a three-dimensional integrated circuit fault detection method and system. During execution, this method and system can adapt to circuits with different stacking densities, accurately capture original fault-related features, and improve the quality of feature data through layered enhancement and interference shielding. Simultaneously, it accurately extracts inter-layer coupling distortion features through dynamic modeling, quickly locates the fault position and propagation path using bidirectional mapping of spatial coordinates and interconnect topology, and clarifies the fault type and propagation boundary by combining a three-dimensional fault equivalent field and dual verification. This generates an intuitive three-dimensional stereoscopic map and a complete fault link report, significantly improving the accuracy and efficiency of fault detection, effectively reducing the impact of interference on detection results, shortening the fault investigation and repair cycle, reducing losses caused by circuit malfunctions, ensuring the stable and reliable operation of three-dimensional integrated circuits, and providing support for circuit design optimization and subsequent maintenance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a three-dimensional integrated circuit fault detection system; Figure 2 This is a flowchart illustrating a three-dimensional integrated circuit fault detection method. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] The present invention will be further described below with reference to embodiments.

[0021] Example 1: This embodiment provides a three-dimensional integrated circuit fault detection system, such as... Figure 1 As shown, it includes: The sensing module is used to synchronously sense cross-layer coupled signals of inter-layer interconnect nodes and core units based on the three-dimensional integrated circuit stacking density, and to capture the original fault correlation features in the signals. The core units of a 3D integrated circuit include a logic operation unit, a storage unit, an inter-layer interconnection interface unit, a power management unit, and a signal conditioning unit. The logic operation unit is used to perform arithmetic operations and logical judgments on the data. The storage unit is used to cache the data and instructions during the operation of the 3D integrated circuit. The inter-layer interconnection interface unit is used to realize signal transmission and data interaction between core units of different layers. The power management unit is used to provide stable operating voltage and current for each core unit. The signal conditioning unit is used to filter, amplify, and impedance match the input / output signals of the core unit. The cross-layer coupling signal synchronous sensing process of the sensing module follows the following rules: ; In the formula: The interconnection nodes of layer i and layer j are used to sense the signal strength at time t. The interconnection nodes are signal interaction nodes between core units of different layers, including inter-layer connection nodes between logic operation units and storage units, transfer nodes between storage units and inter-layer interconnection interface units, power supply nodes between power management units and various functional core units, etc. This refers to the stacking density coefficient of three-dimensional integrated circuits. The coupling capacitance of the interconnection node between layer i and layer j; The physical distance between the interconnecting nodes of layer i and layer j; The original excitation signal is output by the built-in excitation source of the sensing module and is adapted to the working signal type of the core unit; The signal transmission delay between the i-th and j-th layers; This represents the total number of interference sources. Let be the interference intensity coefficient of the k-th interference source; The correlation degree of the influence of the k-th interference source on the i-th layer node; The above formula fully considers the impact of three-dimensional integrated circuit stacking density on signal transmission. By combining the relationship between coupling capacitance and physical spacing, and the original excitation signal and transmission delay, it accurately describes the signal strength of interconnection nodes between different layers at a specific time. At the same time, it introduces the interference source strength coefficient and the influence correlation to offset the interference of various interferences on signal perception. By comparing with the preset benchmark value in multiple dimensions, it ensures the accurate capture of the original characteristics of fault correlation. Through real-time data collection And compare it with the preset signal reference value to capture the original characteristics of the fault association: Based on the normal operating state of the three-dimensional integrated circuit, preset signal reference values ​​are obtained through calibration for different inter-layer interconnection nodes and working conditions. The sensing module collects data at a preset sampling frequency. After filtering and denoising, the amplitude, trend of change and phase are compared with the corresponding preset signal reference value in multiple dimensions. When the comparison deviation exceeds the allowable fluctuation range or reaches the preset deviation threshold, it is determined that there are signs of fault association. The signal distortion parameters and corresponding node and timing information are recorded simultaneously to form the original characteristics of fault association. in, The preset value range is [0.1, 1]. The more layers a 3D integrated circuit has, the smaller the inter-layer spacing, the higher the core unit density, and the greater the inter-layer interconnect density... The larger the value, the lower the value. The smaller the value, The preset value range is [0,1]. The higher the output power of the interference source, the closer the physical distance to the target interconnection node, and the higher the overlap between the interference frequency and the target signal frequency, the better. The larger the value, the lower the value. The smaller the value, ∈[0,1], which is determined based on the physical distance between the interference source and the i-th layer node and the matching degree between the interference source type and the node's working frequency band / function. The closer the distance and the higher the matching degree, the larger the value; the farther the distance and the lower the matching degree, the smaller the value. The filtering and denoising operation is performed using a preset filtering and denoising algorithm; The reconstruction module is used to perform hierarchical enhancement and three-dimensional interference masking on the extracted fault association original features to output a structured three-dimensional feature dataset. The logic for layered enhancement and three-dimensional interference shielding of the original fault-related features in the reconstruction module is as follows: ; In the formula: The enhanced feature data is from the l-th layer. The original fault association features extracted from layer l; Enhance the weights of the features in the l-th layer; The number of stereo interference types existing in the l-th layer; Let be the amplitude of the m-th type of stereo interference in the l-th layer; The preset interference suppression threshold; The above formula sets enhancement weights based on the differences in the importance of features at each layer, and specifically enhances the identification of original features of fault association between different layers. At the same time, it counts the types and corresponding amplitudes of three-dimensional interference in each layer, and combines them with preset interference suppression thresholds to effectively eliminate the interference of three-dimensional interference on feature data. This allows the layered enhancement of fault features and interference shielding to proceed simultaneously, providing data support for subsequent feature extraction. The refactoring module passes through The calculation formula outputs a structured 3D feature dataset that has been freed from stereo interference and enhanced in layers; in, The value range is preset to [0.1, 1.5], and the value is larger when the interlayer interconnection density is higher and smaller when the interlayer interconnection density is lower. The extraction module is used to dynamically model the inter-layer interconnection path of three-dimensional integrated circuits and extract the feature vector of inter-layer coupling distortion caused by faults from the structured three-dimensional feature dataset. The dynamic modeling of inter-layer interconnection paths in the extraction module is achieved by constructing a path association matrix, where the matrix elements... This represents the dynamic correlation between the p-th interconnection path and the q-th interconnection path; Extracting fault-induced interlayer coupling distortion feature vectors from a structured 3D feature dataset: ; In the formula, K represents the total number of inter-layer interconnection paths; Let be the impedance distortion value of the k-th path; The standard impedance of the k-th path; Let be the phase distortion value of the k-th path; The standard phase of the k-th path; Let be the power loss distortion value of the k-th path; The standard power loss of the k-th path; The above formula takes the standard impedance, standard phase and standard power loss of each interconnection path as the benchmark. By calculating the deviation of the actual impedance time-varying value, phase time-varying value and power loss distortion value relative to the standard value, the system integrates the distortion information of each path and constructs a feature vector that can comprehensively reflect the interlayer coupling distortion state caused by the fault, providing support for subsequent fault location. Among them, feature vector Each component is calculated using the corresponding parameters in the structured 3D feature dataset; The positioning module is used to match the interlayer coupling distortion feature vector with the physical structure through a two-way mapping of three-dimensional spatial coordinates and interconnection path topology, so as to locate the fault layer, unit and cross-layer transmission path; The bidirectional mapping between the three-dimensional spatial coordinates of the positioning module and the interconnection path topology is represented as follows: ; In the formula: These are the physical space coordinates of a cell or node in a three-dimensional integrated circuit. This represents the forward mapping function; t is the topology dynamic update time. This is the adjacency matrix of the interconnection path topology; This represents the number of topologically related nodes. This represents the inverse mapping function; Let be the weight coefficient of the s-th topologically related node; Let be the local adjacency matrix corresponding to the s-th topologically associated node; Let be the update sequence of the s-th topologically related node; The coordinate-topology mapping coefficient matrix is ​​based on the physical layout preset of the three-dimensional integrated circuit. In the above formula, the forward mapping transforms topological information into physical spatial coordinates of units or nodes through the adjacency matrix of the interconnected path topology, the weight coefficients of topologically related nodes, and the update sequence; the reverse mapping, on the other hand, uses the coordinate-topological mapping coefficient matrix and the relevant parameters of the topologically related nodes to realize the reverse transformation of physical spatial coordinates into topological information. The bidirectional mapping mechanism enables the precise correspondence between topological information and physical structure, ensuring that the interlayer coupling distortion feature vector can be quickly matched to the specific physical location, thereby improving the accuracy and efficiency of fault location. The localization module uses the above bidirectional mapping model to match the distortion position corresponding to the interlayer coupling distortion feature vector V with the physical structure; Among them, the adjacency matrix of the interconnection path topology Based on the physical layout of nodes between / within the layer of the three-dimensional integrated circuit, the actual interconnection relationship between nodes and the functional attributes of nodes, the matrix is ​​constructed. When the element in the matrix takes a value of 1, it means that the two corresponding interconnection paths are directly connected, and when it takes a value of 0, it means that the two corresponding interconnection paths are not directly connected. The value range is preset to [0,1]. The higher the coupling strength between the topologically associated node and the inter-layer interconnection path, and the stronger its core position in the interconnection topology, the larger the value. The lower the coupling strength and the weaker its core position, the smaller the value. The verification module is used to construct a three-dimensional fault equivalent field and perform dual verification based on the fault location results to determine the fault type and propagation boundary. The field strength distribution of the three-dimensional fault equivalent field constructed in the verification module follows: ; In the formula: Let be the field strength of the three-dimensional fault equivalent field at coordinates (x, y, z); The electric field strength coefficient; This represents the fault equivalent charge. The equivalent dielectric constant of a three-dimensional integrated circuit; This is the field strength attenuation correction factor; The initial coordinates of the fault location; The above formula combines the equivalent charge of the fault with the equivalent dielectric constant of the three-dimensional integrated circuit. Based on the coordinates of the initially located fault core, it accurately simulates the distribution of the equivalent field strength caused by the fault in three-dimensional space through spatial coordinates and field strength attenuation correction factor. The field strength coefficient is adapted to the difference in conductivity and interlayer density of the integrated circuit material, and the attenuation correction factor is dynamically adjusted according to the fault type and dielectric homogeneity to reflect the intensity of the fault's influence on different spatial locations. in, The preset value range is [1.2 × 10]. 9 3.8×10 9 V・m / C, the value is larger when the material equivalent conductivity of the three-dimensional integrated circuit is higher and the interlayer structure is more compact, and the value is smaller when the material equivalent conductivity is lower and the interlayer structure is less compact. The preset value range is [0.01mm]. 2 0.5mm 2 The value is smaller when the fault type is short circuit and the equivalent dielectric uniformity of the three-dimensional integrated circuit is better; the value is larger when the fault type is open circuit and the equivalent dielectric uniformity of the three-dimensional integrated circuit is worse. During the positive signal excitation process with double verification, the excitation signal strength is: ; The above formula is based on the basic excitation signal strength and refers to the ratio of the three-dimensional fault equivalent field strength to the system's maximum withstand field strength. The excitation signal strength is dynamically adjusted through the excitation gain coefficient, so that the excitation signal can be adaptively optimized according to the field strength distribution of the fault area. The excitation intensity is automatically increased in areas with weak field strength to ensure the detectability of the response signal, and the excitation intensity is reasonably controlled in areas with strong field strength to avoid system overload. This achieves efficient acquisition of excitation response characteristics in the fault area and provides response data for fault type judgment. In the reverse fault tracing process of double verification, the fault propagation coefficient is: ; The above formula quantifies the energy change relationship during fault propagation by calculating the ratio of the integral of the three-dimensional fault equivalent temporal field strength to the integral of the temporal excitation signal strength within the verification time. It intuitively reflects the intensity and trend of fault propagation. This ratio can effectively correlate the response characteristics of positive excitation with the propagation characteristics of reverse tracing, providing a key quantitative indicator for fault type determination and improving the accuracy and reliability of fault type identification. In the formula: The strength of the basic excitation signal; This is the excitation gain coefficient; This represents the maximum withstand field strength of the system. For verification duration; For temporal field strength; The strength of the timing excitation signal; The verification module determines the fault type and propagation boundary by comparing the results of forward excitation and reverse fault tracing. The module obtains the excitation response characteristics of the fault region through forward excitation, including response amplitude, response delay, and phase shift. It also obtains the attenuation characteristics, branching characteristics, and time-series characteristics of the fault propagation path through reverse fault tracing. These two types of features are then matched with a pre-defined feature template library corresponding to different fault types, and the fault propagation coefficient is calculated simultaneously. The deviation from a preset threshold, combined with the similarity matching result and the deviation value, determines the fault type according to preset judgment rules, including short-circuit fault, open-circuit fault, leakage fault, or interlayer coupling fault, and is based on the three-dimensional fault equivalent field strength. The spatial coordinate range corresponding to the field strength threshold when it drops to the preset field strength threshold is used to determine the fault propagation boundary; in, The preset value range is [0.1, 2.0], and its magnitude varies with the three-dimensional fault equivalent field strength. The decrease increases with the three-dimensional fault equivalent field strength. The increase is reduced; The output module is used to collect fault location, type and transmission trajectory information, and generate a three-dimensional fault map and a detection report containing the complete fault chain. The logical expression for the output module to generate a three-dimensional fault map is as follows: ; In the formula: The grid model matrix of the three-dimensional fault map; This is the standard mesh model matrix for three-dimensional integrated circuits; Adjust the matrix for grid weights; This represents the mesh distortion matrix caused by the fault. The above formula uses the physical layout parameters of the integrated circuit design stage and the structural size under fault-free conditions as a basis to preset a standard grid model matrix. The grid weight adjustment matrix is ​​dynamically adjusted according to the fault influence range and the degree of correlation between each grid node and the fault influence. The grid distortion matrix is ​​calculated by combining the fault core coordinates, diffusion boundary and field strength distribution data. By integrating the three, a three-dimensional map that can intuitively present the fault core location, diffusion range and influence degree is constructed, thereby realizing the visualization of fault information. The test report includes the fault core coordinates, fault layer and unit number, cross-layer propagation path parameters, fault type, diffusion boundary range, fault equivalent field strength distribution data, eigenvector distortion peak value and corresponding time series information; in, The dimensions are determined based on the physical layout parameters during the design phase and the pre-set structural dimensions under fault-free conditions. The determination is dynamically adjusted based on the size of the fault's impact range and the degree of correlation between each grid node and the fault's impact. The location is determined based on the fault core coordinates, diffusion boundary, and field strength distribution data of the three-dimensional fault equivalent field output by the positioning module. Among them, dual verification includes positive signal excitation and reverse fault tracing; The sensing module interacts with the reconstruction module via a wireless network. The reconstruction module interacts with the extraction module via a wireless network. The extraction module interacts with the positioning module via a wireless network. The positioning module interacts with the verification module via a wireless network. The verification module interacts with the output module via a wireless network.

[0022] In this embodiment, the perception module operates based on the 3D integrated circuit stacking density, synchronously sensing cross-layer coupling signals of inter-layer interconnect nodes and core units, capturing the original fault-related features in the signals. The reconstruction module then performs layered enhancement and three-dimensional interference shielding processing on the extracted original fault-related features to output a structured 3D feature dataset. The extraction module then dynamically models the 3D integrated circuit inter-layer interconnect path, extracting the feature vector of inter-layer coupling distortion caused by the fault from the structured 3D feature dataset. The localization module further matches the inter-layer coupling distortion feature vector with the physical structure through bidirectional mapping of 3D spatial coordinates and interconnect path topology to lock the fault layer, unit, and cross-layer propagation path. The verification module constructs a 3D fault equivalent field and performs double verification based on the fault localization results to determine the fault type and propagation boundary. Finally, the output module collects fault localization, type, and propagation trajectory information to generate a 3D fault map and a detection report containing the complete fault link.

[0023] In the above embodiments, the system can accurately capture the fault correlation characteristics of three-dimensional integrated circuits, quickly locate the fault location, conduction path and diffusion boundary, accurately determine the fault type, and generate an intuitive three-dimensional map and a complete test report. After implementation, it can greatly improve the efficiency and accuracy of fault detection, shorten the troubleshooting and maintenance cycle, reduce operation and maintenance costs, and ensure the stable and reliable operation of integrated circuits.

[0024] Example 2: At the implementation level, based on Example 1, this example refers to... Figure 2 A more detailed description of the three-dimensional integrated circuit fault detection system in Example 1 is provided below: A three-dimensional integrated circuit fault detection method, comprising: Based on the three-dimensional integrated circuit stacking density, cross-layer coupling signals of inter-layer interconnection nodes and core units are synchronously sensed. By comparing with preset signal reference values ​​in multiple dimensions, the original characteristics of fault association are captured. The original fault-related features are subjected to hierarchical enhancement and three-dimensional interference masking processing to remove three-dimensional interference and enhance effective features, and output a structured three-dimensional feature dataset. Dynamically model the inter-layer interconnection path to construct the path association matrix, and extract the inter-layer coupling distortion feature vector caused by the fault from the structured three-dimensional feature dataset; By mapping three-dimensional spatial coordinates to the interconnection path topology, the interlayer coupling distortion feature vector is accurately matched with the physical structure to pinpoint the fault location, unit, and cross-layer propagation path. A three-dimensional fault equivalent field is constructed. Based on the dual verification of forward signal excitation and reverse fault source tracing, combined with feature matching and propagation coefficient analysis, the fault type and propagation boundary are determined. Collect all information such as fault location, type, and transmission trajectory, generate a three-dimensional fault map, and output a detection report containing the complete fault chain.

[0025] In summary, the system and method described in the above embodiments can adapt to circuits with different stacking densities during execution, accurately capture the original features associated with faults, and improve the quality of feature data through layered enhancement and interference shielding. At the same time, through dynamic modeling, the interlayer coupling distortion features are accurately extracted, and the fault location and propagation path are quickly located by means of bidirectional mapping of spatial coordinates and interconnect topology. Combined with three-dimensional fault equivalent field and double verification, the fault type and propagation boundary are clarified, and an intuitive three-dimensional map and a complete fault link report are generated, which greatly improves the accuracy and efficiency of fault detection, effectively reduces the impact of interference on the detection results, shortens the fault investigation and repair cycle, reduces the losses caused by circuit operation failures, ensures the stable and reliable operation of three-dimensional integrated circuits, and provides support for circuit design optimization and subsequent maintenance.

[0026] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-dimensional integrated circuit fault detection system, characterized in that, include: The sensing module is used to synchronously sense cross-layer coupled signals of inter-layer interconnect nodes and core units based on the three-dimensional integrated circuit stacking density, and to capture the original fault correlation features in the signals. The reconstruction module is used to perform hierarchical enhancement and three-dimensional interference masking on the extracted fault association original features to output a structured three-dimensional feature dataset. The extraction module is used to dynamically model the inter-layer interconnection path of three-dimensional integrated circuits and extract the feature vector of inter-layer coupling distortion caused by faults from the structured three-dimensional feature dataset. The positioning module is used to match the interlayer coupling distortion feature vector with the physical structure through a two-way mapping of three-dimensional spatial coordinates and interconnection path topology, so as to locate the fault layer, unit and cross-layer transmission path; The verification module is used to construct a three-dimensional fault equivalent field and perform dual verification based on the fault location results to determine the fault type and propagation boundary. The output module is used to collect fault location, type and transmission trajectory information, and generate a three-dimensional fault map and a detection report containing the complete fault chain. The dual verification includes positive signal excitation and reverse fault tracing.

2. The three-dimensional integrated circuit fault detection system according to claim 1, characterized in that, The core units of the three-dimensional integrated circuit include a logic operation unit, a storage unit, an inter-layer interconnection interface unit, a power management unit, and a signal conditioning unit; The cross-layer coupling signal synchronous sensing process of the sensing module follows the following: ； In the formula: The synchronous sensing signal strength between the interconnection nodes of layer i and layer j at time t; This refers to the stacking density coefficient of three-dimensional integrated circuits. The coupling capacitance of the interconnection node between layer i and layer j; The physical distance between the interconnecting nodes of layer i and layer j; The original excitation signal; The signal transmission delay between the i-th and j-th layers; This represents the total number of interference sources. Let be the interference intensity coefficient of the k-th interference source; The correlation degree of the influence of the k-th interference source on the i-th layer node; Through real-time data collection And compare it with the preset signal reference value to capture the original characteristics of the fault association: Based on the normal operating state of the three-dimensional integrated circuit, preset signal reference values ​​are obtained through calibration for different inter-layer interconnection nodes and working conditions. The sensing module collects data at a preset sampling frequency. After filtering and denoising, the amplitude, trend of change and phase are compared with the corresponding preset signal reference value in multiple dimensions. When the comparison deviation exceeds the allowable fluctuation range or reaches the preset deviation threshold, it is determined that there are signs of fault association. The signal distortion parameters and corresponding node and timing information are recorded simultaneously to form the original features of fault association.

3. The three-dimensional integrated circuit fault detection system according to claim 1, characterized in that, The logic for layered enhancement and three-dimensional interference shielding of the original fault-related features in the reconstruction module is as follows: ； In the formula: The enhanced feature data is from the l-th layer. The original fault association features extracted from layer l; Enhance the weights of the features in the l-th layer; The number of stereo interference types existing in layer l; Let be the amplitude of the m-th type of stereo interference in the l-th layer; The preset interference suppression threshold; The reconstruction module, through The calculation formula outputs a structured 3D feature dataset after removing stereo interference and layering enhancement.

4. The three-dimensional integrated circuit fault detection system according to claim 1, characterized in that, The dynamic modeling of inter-layer interconnection paths in the extraction module is achieved by constructing a path association matrix, wherein the matrix elements This represents the dynamic correlation between the p-th interconnection path and the q-th interconnection path; Extracting fault-induced interlayer coupling distortion feature vectors from a structured 3D feature dataset: ； In the formula, K represents the total number of inter-layer interconnection paths; Let be the impedance distortion value of the k-th path; The standard impedance of the k-th path; Let be the phase distortion value of the k-th path; The standard phase of the k-th path; Let be the power loss distortion value of the k-th path; Let be the standard power loss of the k-th path.

5. A three-dimensional integrated circuit fault detection system according to claim 1, characterized in that, The bidirectional mapping between the three-dimensional spatial coordinates of the positioning module and the interconnection path topology is represented as follows: ； In the formula: These are the physical space coordinates of a cell or node in a three-dimensional integrated circuit. This represents the forward mapping function; t is the topology dynamic update time. This is the adjacency matrix of the interconnection path topology; This represents the number of topologically related nodes. This represents the inverse mapping function; Let be the weight coefficient of the s-th topologically related node; Let be the local adjacency matrix corresponding to the s-th topologically associated node; Let be the update sequence of the s-th topologically related node; The coordinate-topology mapping coefficient matrix is ​​based on the physical layout preset of the three-dimensional integrated circuit. The positioning module uses the above bidirectional mapping model to match the distortion position corresponding to the interlayer coupling distortion feature vector V with the physical structure.

6. The three-dimensional integrated circuit fault detection system according to claim 1, characterized in that, The field strength distribution of the three-dimensional fault equivalent field constructed in the verification module follows: ； In the formula: Let be the field strength of the three-dimensional fault equivalent field at coordinates (x, y, z); This is the electric field strength coefficient; This represents the fault equivalent charge. The equivalent dielectric constant of a three-dimensional integrated circuit; This is the field strength attenuation correction factor; The coordinates of the core fault location are shown in the preliminary diagram.

7. A three-dimensional integrated circuit fault detection system according to claim 6, characterized in that, During the positive signal excitation process of the dual verification, the excitation signal strength is: ； In the reverse fault tracing process of the dual verification, the fault propagation coefficient is: ； In the formula: The strength of the basic excitation signal; This is the excitation gain coefficient; This represents the maximum withstand field strength of the system. For verification duration; For temporal field strength; The strength of the timing excitation signal; The verification module determines the fault type and propagation boundary by comparing the results of forward excitation and reverse tracing.

8. A three-dimensional integrated circuit fault detection system according to claim 1, characterized in that, The logical expression for the output module to generate a three-dimensional fault map is as follows: ； In the formula: The grid model matrix of the three-dimensional fault map; This is the standard mesh model matrix for three-dimensional integrated circuits; Adjust the matrix for grid weights; This represents the mesh distortion matrix caused by the fault. The detection report includes the fault core coordinates, fault layer and unit number, cross-layer propagation path parameters, fault type, diffusion boundary range, fault equivalent field strength distribution data, eigenvector distortion peak value and corresponding time series information.

9. A three-dimensional integrated circuit fault detection system according to claim 1, characterized in that, The sensing module is interconnected with the reconstruction module via a wireless network. The reconstruction module is interconnected with the extraction module via a wireless network. The extraction module is interconnected with the positioning module via a wireless network. The positioning module is interconnected with the verification module via a wireless network. The verification module is interconnected with the output module via a wireless network.

10. A method for detecting faults in a three-dimensional integrated circuit, wherein the method is an implementation method of a three-dimensional integrated circuit fault detection system as described in any one of claims 1-9, characterized in that, include: Based on the three-dimensional integrated circuit stacking density, cross-layer coupling signals of inter-layer interconnection nodes and core units are synchronously sensed. By comparing with preset signal reference values ​​in multiple dimensions, the original characteristics of fault association are captured. The original fault-related features are subjected to hierarchical enhancement and three-dimensional interference masking processing to remove three-dimensional interference and enhance effective features, and output a structured three-dimensional feature dataset. Dynamically model the inter-layer interconnection path to construct the path association matrix, and extract the inter-layer coupling distortion feature vector caused by the fault from the structured three-dimensional feature dataset; By mapping three-dimensional spatial coordinates to the interconnection path topology, the interlayer coupling distortion feature vector is accurately matched with the physical structure to pinpoint the fault location, unit, and cross-layer propagation path. A three-dimensional fault equivalent field is constructed. Based on the dual verification of forward signal excitation and reverse fault source tracing, combined with feature matching and propagation coefficient analysis, the fault type and propagation boundary are determined. Collect all information such as fault location, type, and transmission trajectory, generate a three-dimensional fault map, and output a detection report containing the complete fault chain.

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