Acceleration unit, dedicated data processor, host and read-write signal transmission method
By introducing an acceleration unit between the host and a dedicated data processor and utilizing a doorbell signal transmission mechanism, the problem of excessive processor resource consumption was solved, achieving efficient storage system access and improved computing performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-21
- Publication Date
- 2026-04-03
AI Technical Summary
When the host's processor handles read and write requests for storage devices, it consumes too many computing resources, resulting in less time for the processor to run its main tasks.
An acceleration unit is employed, including a first register, a forwarding subunit, and a second register. Signal transmission between the host and a dedicated data processor is achieved through a doorbell signal. The dedicated data processor handles read and write requests to offload the host's computational burden.
This reduces the complexity of accessing different storage systems and the overhead of running storage system clients, while improving the computing performance of the host processor.
Smart Images
Figure CN121785955A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to an acceleration unit, a dedicated data processor, a host, and a read / write signal transmission method. Background Technology
[0002] NVMe storage devices refer to storage devices that support the Non-Volatile Memory Express (NVMe) protocol. Because the NVMe protocol employs simplified instructions, a lower-latency software stack, queue parallelism, and a large queue depth, it can significantly reduce hardware-level I / O overhead and latency. This results in NVMe-enabled storage devices possessing high bandwidth and low latency hardware characteristics, making them widely used in computing devices.
[0003] Currently, read and write requests to storage devices are processed by the processor in the host, thereby enabling functions such as establishing connections with storage devices and reading and writing data.
[0004] However, when the host's processor handles read and write requests to the storage device, it consumes too much of the processor's computing resources, resulting in less time for the processor to run its main tasks. Summary of the Invention
[0005] In view of this, embodiments of this application provide an acceleration unit, a dedicated data processor, a host, and a read / write signal transmission method to at least solve or alleviate the above-mentioned problems.
[0006] According to a first aspect of the present application, an acceleration unit is provided, the acceleration unit being disposed in a dedicated data processor connected to a host, the acceleration unit comprising: a first register, a forwarding subunit, and a second register; the first register being used to store a doorbell signal written by the host, wherein the doorbell signal is used to instruct the host to request read / write access to a storage system; the forwarding subunit being used to, after detecting that the doorbell signal has been written to the first register, read the doorbell signal from the first register and write the read doorbell signal to the second register, so that a processing unit included in the dedicated data processor reads the doorbell signal from the second register and obtains a read / write request from the host to read / write access to the storage system based on the doorbell signal.
[0007] In one possible implementation, the acceleration unit includes at least two first registers and at least two second registers, with different first registers corresponding to different second registers, and different first registers corresponding to different transmission queues in the host; the first register is used to store a doorbell signal written by the host after a read / write request is made to the transmission queue corresponding to the first register, wherein the read / write request is used to read and write to the storage system; the forwarding subunit is used to read the doorbell signal from the first register after detecting that the doorbell signal has been written to the first register, and write the read doorbell signal into the second register corresponding to the first register.
[0008] In one possible implementation, the first register communicates with the host via a register interface-based connection bus.
[0009] According to a second aspect of the embodiments of this application, a dedicated data processor is provided, including: a processing unit and an acceleration unit as described in the first aspect of this application; the processing unit is configured to, after detecting that a doorbell signal has been written into a second register included in the acceleration unit, read the doorbell signal from the second register, and obtain a read / write request from the host to read and write to the storage system based on the read doorbell signal.
[0010] In one possible implementation, the processing unit is configured to determine, based on the doorbell signal, the sending queue in the host where read / write requests are written, and to obtain the read / write requests from the sending queue.
[0011] In one possible implementation, the processing unit is configured to read from the storage system when the read / write request is a read request and send the read data to the host, and to obtain write data from the host and write the write data to the storage system when the read / write request is a write request.
[0012] In one possible implementation, when the acceleration unit includes at least two first registers and at least two second registers, different first registers correspond to different second registers, and different first registers correspond to different transmission queues in the host; the processing unit is configured to traverse the at least two second registers according to a preset traversal period to detect whether each second register has been written with a doorbell signal.
[0013] In one possible implementation, the processing unit is configured to acquire the recording signal of the second register, and if the signal currently stored in the second register is different from the recording signal, determine that the second register has been written with a doorbell signal by the host, and update the recording signal of the second register to the signal currently stored in the second register.
[0014] According to a third aspect of the embodiments of this application, a host is provided, comprising: a processor; the host is connected to a dedicated data processor as described in the second aspect of this application; the processor is configured to write a doorbell signal into a first register included in the dedicated data processor after writing a read / write request for a storage system into a transmission queue, so that the dedicated data processor obtains a read / write request for reading and writing to the storage system from the host according to the doorbell signal.
[0015] According to a fourth aspect of the embodiments of this application, a read / write signal transmission method is provided, applied to a dedicated data processor, comprising: storing a doorbell signal written by a host in a first register, wherein the doorbell signal is used to instruct the host to request read / write access to a storage system; after detecting that the doorbell signal has been written to the first register, reading the doorbell signal from the first register and writing the read doorbell signal to a second register; after detecting that the doorbell signal has been written to the second register, reading the doorbell signal from the second register and obtaining a read / write request to access the storage system from the host based on the read doorbell signal.
[0016] According to the solution provided in the embodiments of this application, the acceleration unit includes a first register, a forwarding subunit, and a second register. The first register stores the doorbell signal sent by the host, and the forwarding subunit forwards the doorbell signal to the second register. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. The host can then read / write to the storage system through a dedicated data processor. Since the host processes read / write requests through a dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0018] Figure 1This is a schematic diagram of an acceleration unit provided in an embodiment of this application;
[0019] Figure 2 This is a schematic diagram of another acceleration unit provided in an embodiment of this application;
[0020] Figure 3 This is a schematic diagram of a dedicated data processor provided in an embodiment of this application;
[0021] Figure 4 This is a schematic diagram of a host provided in an embodiment of this application;
[0022] Figure 5 This is a flowchart of a read / write signal transmission method provided in an embodiment of this application. Detailed Implementation
[0023] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.
[0024] As mentioned earlier, NVMe storage devices refer to storage devices that support the Non-Volatile Memory Express (NVMe) protocol. Because the NVMe protocol employs simplified instructions, a lower-latency software stack, queue parallelism, and a larger queue depth, it can significantly reduce hardware-level I / O overhead and latency. This results in NVMe-enabled storage devices possessing high bandwidth and low latency hardware characteristics, making them widely used in computing devices.
[0025] When an application running on the host needs to read or write to a storage device, it issues a read / write request. Currently, the host's processor handles these requests, enabling functions such as establishing a connection with the storage device and reading / writing data. However, processing these read / write requests consumes excessive processor resources, resulting in less time for the processor to run its primary tasks.
[0026] This application provides an acceleration unit, which includes a first register, a forwarding subunit, and a second register. The first register stores a doorbell signal sent by the host, and the forwarding subunit forwards the doorbell signal to the second register. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. The host can then read / write to the storage system through a dedicated data processor. Since the host processes read / write requests through the dedicated data processor, it can access any storage system, thereby offloading the complexity of accessing different storage systems and the overhead of running storage system clients. The processor utilization is low, improving the computing performance of the processor in the host.
[0027] The specific implementation of the embodiments of this application will be further described below with reference to the accompanying drawings.
[0028] Figure 1 This is a schematic diagram of an acceleration unit provided in an embodiment of this application. The acceleration unit 100 is disposed on a dedicated data processor connected to a host computer, such as... Figure 1 As shown, the acceleration unit 100 includes: a first register 101, a forwarding subunit 102, and a second register 103.
[0029] The first register 101 can store a doorbell signal written by the host, wherein the doorbell signal is used to indicate that the host requests to read or write to the storage system. The forwarding subunit 102 can read the doorbell signal from the first register 101 after detecting that a doorbell signal has been written to the first register 101, and write the read doorbell signal to the second register 103, so that the processing unit included in the dedicated data processor reads the doorbell signal from the second register 103 and obtains a read / write request from the host to read or write to the storage system based on the doorbell signal.
[0030] When a program in the host needs to read or write to the storage system, the NVMe driver running in the host writes a doorbell signal to the first register 101 included in the dedicated data processor. The first register 101 stores the doorbell signal written by the host. After the forwarding subunit 102 detects that a doorbell signal has been written to the first register 101, it reads the doorbell signal in the first register 101 according to the preset forwarding rules and writes the doorbell signal to the second register 103. After the processing unit in the dedicated data processor detects that a doorbell signal has been written to the second register 103, it reads the doorbell signal in the second register 103 and processes the doorbell signal.
[0031] The processing unit processes the doorbell signal and can obtain read / write requests for the storage system from the host based on the doorbell signal. Thus, the host can read and write to the storage system through this dedicated data processor.
[0032] In this embodiment, the acceleration unit 100 includes a first register 101, a forwarding subunit 102, and a second register 103. The first register 101 stores the doorbell signal sent by the host, and the forwarding subunit 102 forwards the doorbell signal to the second register 103. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. The host can then read / write to the storage system through a dedicated data processor. Since the host processes read / write requests through a dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0033] Figure 2 This is a schematic diagram of another acceleration unit provided in an embodiment of this application, as shown below. Figure 2 As shown, the acceleration unit 100 includes at least two first registers 101 and at least two second registers 103, with different first registers 101 corresponding to different second registers 103, and different first registers 101 corresponding to different transmission queues in the host.
[0034] The first register 101 can store the doorbell signal written by the host after the corresponding transmission queue of the first register 101 is written with a read / write request. The read / write request is used to read and write to the storage system. The forwarding subunit 102 can read the doorbell signal from the first register 101 after detecting that the first register 101 has been written with a doorbell signal, and write the read doorbell signal into the second register 103 corresponding to the first register 101.
[0035] The acceleration unit 100 may include multiple first registers 101 and multiple second registers 103. The multiple first registers 101 correspond one-to-one with the transmission queues in the host, and the multiple first registers 101 and multiple second registers 103 correspond one-to-one. For example, if the host has 10 transmission queues, the acceleration unit 100 includes 10 first registers 101 and 10 second registers 103. The 10 first registers 101 correspond one-to-one with the 10 transmission queues, and different transmission queues correspond to different first registers 101. The 10 first registers 101 and 10 second registers 103 correspond one-to-one, and different first registers 101 correspond to different second registers 103.
[0036] When a read / write request is written to the transmission queue corresponding to the first register 101, the first register 101 receives the doorbell signal sent by the host and stores the doorbell signal. At this time, the forwarding subunit 102 detects that the doorbell signal has been written to the first register 101. The forwarding subunit 102 reads the doorbell signal and writes the doorbell signal to the second register 103 corresponding to the first register 101. For example, if a read / write request is written to the first transmission queue in the host, the doorbell signal written by the host is stored in register 1 corresponding to the first transmission queue. The forwarding subunit 102 detects that the host has written the doorbell signal to register 1 and forwards the doorbell signal to register 2 corresponding to register 1.
[0037] It should be understood that the acceleration unit 100 can be configured with multiple first registers 101 and multiple second registers 103. The number of first registers 101 and second registers 103 that are enabled can be determined according to the transmission queues in the host. For example, if the acceleration unit 100 is configured with 20 first registers 101 and 20 second registers 103, and the host has 10 transmission queues, then 10 first registers 101 and 10 second registers 103 will be enabled. It should be noted that the forwarding subunit 102 can display a preset correspondence between the first registers 101 and the second registers 103, thereby allowing the doorbell signal in the first register 101 to be read and written to the corresponding second register 103.
[0038] In this embodiment, the acceleration unit 100 is provided with multiple first registers 101 and multiple second registers 103. Different first registers 101 correspond to different transmission queues in the host, and different first registers 101 correspond to different second registers 103. This allows multiple doorbell signals sent by the host to be stored in multiple first registers 101 when read / write requests are being written to multiple transmission queues. This enables parallel processing of doorbell signals corresponding to multiple read / write requests. Furthermore, since the first registers 101 and second registers 103 correspond one-to-one, the corresponding first register 101 can be located through the second register 103, thereby locating the transmission queue to which the read / write request is being written, thus improving the efficiency of data read / write.
[0039] In one possible implementation, the first register 101 communicates with the host via a register interface-based connection bus.
[0040] The first register 101 communicates with the host via a register interface-based connection bus, for example, by communicating with the host via the PCIe bus, or by transmitting doorbell signals via the PCIe bus.
[0041] In this embodiment, the first register 101 communicates with the host via a register interface-based connection bus, thus making it applicable to a variety of dedicated data processors connected to the host via different buses, and thus having high applicability.
[0042] Figure 3 This is a schematic diagram of a dedicated data processor provided in an embodiment of this application, as shown below. Figure 3 As shown, the dedicated data processor 200 includes a processing unit 201 and an acceleration unit 100 as described in any of the above embodiments. After detecting that a doorbell signal has been written into the second register 103 included in the acceleration unit 100, the processing unit 201 can read the doorbell signal from the second register 103 and obtain a read / write request from the host to read and write to the storage system based on the read doorbell signal.
[0043] The dedicated data processor 200 can be a smart network card connected to the host. For example, the dedicated data processor 200 can be a data processing unit (DPU). After detecting that a doorbell signal has been written into the second register 103, the processing unit 201 in the dedicated data processor 200 can read the doorbell signal and process it, thereby establishing a read / write channel between the dedicated data processor 200 and the storage system based on the doorbell signal.
[0044] In this embodiment, the dedicated data processor 200 includes an acceleration unit 100 and a processing unit 201. The first register 101 in the acceleration unit 100 can store the doorbell signal sent by the host. The forwarding subunit 102 in the acceleration unit 100 forwards the doorbell signal to the second register 103. The processing unit 201 of the dedicated data processor 200 can read the doorbell signal stored in the second register 103 in the acceleration unit 100. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. Therefore, the host can read / write to the storage system through the dedicated data processor. Since the host processes the read / write requests through the dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0045] In one possible implementation, the processing unit 201 can determine the sending queue of read / write requests written in the host based on the doorbell signal, and obtain the read / write requests from the sending queue.
[0046] The processing unit 201 processes the doorbell signal and determines the sending queue of the read / write request, that is, the storage area in the host where the read / write request is stored. After determining the storage area, the processing unit 201 reads the read / write request stored in the storage area, so that the storage system can be read and written through the read / write request.
[0047] In this embodiment of the application, the processing unit 201 can determine the sending queue of read and write requests written in the host according to the doorbell signal, and obtain the read and write requests from the sending queue. This realizes the processing of read and write requests by a dedicated data processor. Since the host processes read and write requests through a dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0048] In one possible implementation, the processing unit 201 can read from the storage system when the read / write request is a read request and send the read data to the host, and when the read / write request is a write request, it can obtain write data from the host and write the write data to the storage system.
[0049] After the processing unit 201 in the dedicated data processor 200 obtains the read / write request from the host according to the doorbell signal, it analyzes the read / write request. If the read / write request is to read data from the storage system, the data is read from the storage system according to the read / write request and written to the corresponding storage location in the host according to the read / write request. If the read / write request is to write data to the storage system, the data to be written is read from the host according to the read / write request and written to the storage system. In this way, the dedicated data processor 200 can read and write data in the storage system.
[0050] In this embodiment of the application, the dedicated data processor 200 processes read and write requests, enabling read and write access to the storage system. Since the host processes read and write requests through the dedicated data processor 200, the host can access any storage system through the dedicated data processor 200, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, improving the computing performance of the processor in the host.
[0051] In one possible implementation, when the acceleration unit 100 includes at least two first registers 101 and at least two second registers 103, different first registers 101 correspond to different second registers 103, and different first registers 101 correspond to different transmission queues in the host, the processing unit 201 can traverse at least two second registers 103 according to a preset traversal period to detect whether each second register 103 has been written with a doorbell signal.
[0052] When the acceleration unit 100 includes at least two first registers 101 and at least two second registers 103, the multiple first registers 101 correspond one-to-one with the transmission queues in the host, and the multiple first registers 101 and the multiple second registers 103 correspond one-to-one. For example, if the host has 10 transmission queues, the acceleration unit 100 includes 10 first registers 101 and 10 second registers 103. The 10 first registers 101 correspond one-to-one with the 10 transmission queues, and different transmission queues correspond to different first registers 101. The 10 first registers 101 and the 10 second registers 103 correspond one-to-one, and different first registers 101 correspond to different second registers 103.
[0053] The processing unit 201 in the dedicated data processor 200 traverses all the second registers 103 according to a preset traversal period. For example, the processing unit 201 traverses at least two of the second registers 103 included in the acceleration unit 100 every 1 second to detect whether the doorbell signal has been written into the at least two second registers 103 included in the acceleration unit 100. It should be understood that the doorbell signal in the second register 103 is written by the forwarding subunit 102 in the acceleration unit 100 according to the doorbell signal written by the host in the corresponding first register 101.
[0054] In this embodiment of the application, the processing unit 201 can traverse at least two second registers 103 according to a preset traversal period, thereby enabling the detection of whether each second register 103 in the acceleration unit 100 has been written with a doorbell signal, and enabling timely response to the doorbell signal when a doorbell signal is written to the second register 103, thus improving the efficiency of processing the doorbell signal.
[0055] In one possible implementation, the processing unit 201 can obtain the recording signal of the second register 103. If the signal currently stored in the second register 103 is different from the recording signal, it is determined that the second register 103 has been written with a doorbell signal by the host, and the recording signal of the second register 103 is updated to the signal currently stored in the second register 103.
[0056] The processing unit 201 can obtain the recording signal of the second register 103. The recording signal is the signal stored in the second register 103 last time it was read. After obtaining the recording signal, the processing unit 201 will detect the second register 103 and compare whether the signal stored in the second register 103 is the same as the recording signal. If they are the same, it proves that no new doorbell signal has been written into the second register 103. If they are different, it proves that a new doorbell signal has been written into the second register 103. At this time, the new doorbell signal is read and the recording signal of the second register 103 is updated to the new doorbell signal.
[0057] It should be understood that when the acceleration unit 100 has multiple second registers 103, the processing unit 201 will acquire the recording signal of each second register 103 and compare the signal stored in each second register 103 with the corresponding recording signal, thereby traversing each second register 103. This will not be elaborated further here.
[0058] In this embodiment, the processing unit 201 traverses the second register 103 according to the recording signal. This allows the doorbell signal to be processed promptly after a new doorbell signal is written into the second register 103. This enables the traversal of the second register 103. After reading the new doorbell signal stored in the second register 103, the recording signal corresponding to the second register 103 is updated to the new doorbell signal. This avoids repeatedly reading the signal stored in the second register 103, improving the accuracy of the doorbell signal and the efficiency of processing the doorbell signal.
[0059] Figure 4 This is a schematic diagram of a host provided in an embodiment of this application, such as... Figure 4 As shown, the host 300 includes a processor 301. The host 300 is connected to the dedicated data processor 200 in any of the above embodiments. After writing the read / write request for the storage system into the transmission queue, the processor 301 can write the doorbell signal into the first register 101 included in the dedicated data processor 200, so that the dedicated data processor 200 can obtain the read / write request for reading and writing to the storage system from the host 300 according to the doorbell signal.
[0060] When the host 300's processor 301 needs to read or write to the storage system, it can write the read / write request to the sending queue. After the processor 301 writes the read / write request to the sending queue, the host 300 generates a doorbell signal and sends the doorbell signal to the first register 101.
[0061] In one example, host 300 includes multiple sending queues. After writing a read / write request to a sending queue, host 300 sends a doorbell signal to the first register 101 corresponding to that sending queue. The interaction process is shown in the above embodiment and will not be repeated here.
[0062] In this embodiment, the processor 301 included in the host 300 can write the doorbell signal into the first register 101 included in the dedicated data processor 200 after writing the read / write request into the sending queue. This allows the dedicated data processor 200 to obtain the read / write request for reading and writing to the storage system from the host 300 based on the doorbell signal. Thus, the host 300 can read and write to the storage system through the dedicated data processor 200, thereby realizing the read and write of the storage system. Since the host 300 offloads the task to the dedicated data processor 200 for execution, the occupancy of the processor 301 in the host 300 can be reduced, and the computing efficiency of the host 300 can be improved.
[0063] The specific application of the dedicated data processor is described below through a specific embodiment.
[0064] Figure 5 This is a flowchart of a read / write signal transmission method provided in an embodiment of this application, such as... Figure 5 As shown, the read / write signal transmission method includes the following steps 501 to 503:
[0065] Step 501: Store the doorbell signal written by the host in the first register.
[0066] The first register receives and stores the doorbell signal written by the host. This doorbell signal is generated after the host writes the read / write request into the sending queue. In other words, the doorbell signal is used to indicate that the host requests to read or write to the storage system.
[0067] In one example, multiple doorbell signals written by the host can be stored in multiple first registers.
[0068] Step 502: After detecting that the doorbell signal has been written to the first register, read the doorbell signal from the first register and write the read doorbell signal to the second register.
[0069] In one example, if the acceleration unit has multiple first registers and multiple second registers, the doorbell signal in the first register can be read and written to the second register corresponding to the first register.
[0070] Step 503: After detecting that the doorbell signal has been written into the second register, read the doorbell signal from the second register and obtain a read / write request from the host to read and write to the storage system based on the read doorbell signal.
[0071] In this embodiment, the doorbell signal sent by the host is stored in the first register, and then the doorbell signal is forwarded to the second register. The doorbell signal in the second register is read, so that the host can obtain read and write requests to the storage system through the doorbell signal. Thus, the host can read and write to the storage system through a dedicated data processor. Since the host processes the read and write requests through the dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0072] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. The focus of each embodiment is to describe the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and the relevant parts can be referred to the descriptions of other embodiments.
[0073] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0074] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.
[0075] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.
Claims
1. An acceleration unit, wherein the acceleration unit is disposed on a dedicated data processor connected to a host computer, characterized in that, The acceleration unit includes: a first register, a forwarding subunit, and a second register; The first register is used to store a doorbell signal written by the host, wherein the doorbell signal is used to instruct the host to request read or write access to the storage system; The forwarding subunit is configured to read the doorbell signal from the first register after detecting that the doorbell signal has been written to the first register, and write the read doorbell signal to the second register, so that the processing unit included in the dedicated data processor reads the doorbell signal from the second register and obtains a read / write request for reading and writing to the storage system from the host according to the doorbell signal.
2. The acceleration unit according to claim 1, characterized in that, The acceleration unit includes at least two first registers and at least two second registers, with different first registers corresponding to different second registers, and different first registers corresponding to different transmission queues in the host. The first register is used to store the doorbell signal written by the host after the corresponding sending queue is written with a read / write request, wherein the read / write request is used to read and write to the storage system; The forwarding subunit is configured to read the doorbell signal from the first register after detecting that the doorbell signal has been written into the first register, and write the read doorbell signal into the second register corresponding to the first register.
3. The acceleration unit according to any one of claims 1-2, characterized in that, The first register communicates with the host via a register interface-based connection bus.
4. A dedicated data processor, characterized in that, include: The processing unit and the acceleration unit as described in any one of claims 1-3; The processing unit is configured to, after detecting that a doorbell signal has been written into the second register included in the acceleration unit, read the doorbell signal from the second register, and obtain a read / write request from the host to read and write to the storage system based on the read doorbell signal.
5. The dedicated data processor according to claim 4, characterized in that, The processing unit is configured to determine the sending queue of read / write requests written in the host based on the doorbell signal, and obtain the read / write request from the sending queue.
6. The dedicated data processor according to claim 4, characterized in that, The processing unit is configured to read from the storage system when the read / write request is a read request and send the read data to the host, and to obtain write data from the host when the read / write request is a write request and write the write data to the storage system.
7. The dedicated data processor according to claim 4, characterized in that, When the acceleration unit includes at least two first registers and at least two second registers, different first registers correspond to different second registers, and different first registers correspond to different transmission queues in the host. The processing unit is used to traverse the at least two second registers according to a preset traversal period to detect whether each second register has been written with a doorbell signal.
8. The dedicated data processor according to any one of claims 5-7, characterized in that, The processing unit is configured to acquire the recording signal of the second register, and if the signal currently stored in the second register is different from the recording signal, determine that the second register has been written with a doorbell signal by the host, and update the recording signal of the second register to the signal currently stored in the second register.
9. A host computer, characterized in that, include: processor; The host is connected to a dedicated data processor as described in any one of claims 5-8; The processor is configured to write a doorbell signal into a first register included in the dedicated data processor after writing a read / write request for the storage system into a transmission queue, so that the dedicated data processor can obtain a read / write request for the storage system from the host according to the doorbell signal.
10. A read / write signal transmission method, applied to a dedicated data processor, characterized in that, include: The doorbell signal written by the host is stored in the first register, wherein the doorbell signal is used to indicate that the host requests to read or write to the storage system; After detecting that the doorbell signal has been written to the first register, the doorbell signal is read from the first register and written to the second register. After detecting that a doorbell signal has been written into the second register, the doorbell signal is read from the second register, and a read / write request for reading and writing to the storage system is obtained from the host based on the read doorbell signal.