Acceleration unit, dedicated data processor, host and read-write signal transmission method
By introducing an acceleration unit and a dedicated data processor into the host, and using the first register to store and forward the doorbell signal, the problem of excessive processor resource consumption is solved, and efficient storage system access and improved computing performance are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-21
- Publication Date
- 2026-04-03
AI Technical Summary
When the host's processor handles read and write requests for storage devices, it consumes too many computing resources, resulting in less time for the processor to run its main tasks.
An acceleration unit, including a first register and a forwarding subunit, is used to store the doorbell signal of the host and forward it to the memory of a dedicated data processor, which then processes read and write requests.
It reduces the complexity of accessing different storage systems and the overhead of running storage system clients, thereby reducing processor utilization and improving the computing performance of the processor in the host.
Smart Images
Figure CN121785956A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to an acceleration unit, a dedicated data processor, a host, and a read / write signal transmission method. Background Technology
[0002] NVMe storage devices refer to storage devices that support the Non-Volatile Memory Express (NVMe) protocol. Because the NVMe protocol employs simplified instructions, a lower-latency software stack, queue parallelism, and a large queue depth, it can significantly reduce hardware-level I / O overhead and latency. This results in NVMe-enabled storage devices possessing high bandwidth and low latency hardware characteristics, making them widely used in computing devices.
[0003] Currently, read and write requests to storage devices are processed by the processor in the host, thereby enabling functions such as establishing connections with storage devices and reading and writing data.
[0004] However, when the host's processor handles read and write requests to the storage device, it consumes too much of the processor's computing resources, resulting in less time for the processor to run its main tasks. Summary of the Invention
[0005] In view of this, embodiments of this application provide an acceleration unit, a dedicated data processor, a host, and a read / write signal transmission method to at least solve or alleviate the above-mentioned problems.
[0006] According to a first aspect of the embodiments of this application, an acceleration unit is provided, the acceleration unit being disposed in a dedicated data processor connected to a host, the acceleration unit comprising: a first register and a forwarding subunit; the first register being used to store a doorbell signal written by the host, wherein the doorbell signal is used to instruct the host to request read / write access to a storage system; the forwarding subunit being used to, after detecting that the doorbell signal has been written to the first register, read the doorbell signal from the first register and write the read doorbell signal to the memory of the dedicated data processor, so that a processing unit included in the dedicated data processor reads the doorbell signal from the memory and obtains a read / write request from the host to read / write access to the storage system based on the doorbell signal.
[0007] In one possible implementation, the acceleration unit includes at least two first registers, the memory includes at least two doorbell memories, different first registers correspond to different doorbell memories, and different first registers correspond to different transmission queues in the host; the first register is used to store the doorbell signal written by the host after a read / write request is written to the transmission queue corresponding to the first register, wherein the read / write request is used to read and write to the storage system; the forwarding subunit is used to read the doorbell signal from the first register after detecting that the doorbell signal has been written to the first register, and write the read doorbell signal to the doorbell memory corresponding to the first register.
[0008] In one possible implementation, the acceleration unit further includes: a second register; the second register is used to store the memory base address of the at least two doorbell memories, wherein the memory base address is written to the second register by the processing unit, and the memory addresses of the at least two doorbell memories are sequentially connected; the forwarding subunit is used to, after detecting that the first register has been written with the doorbell signal, read the memory base address from the second register, and determine the memory address of the doorbell memory corresponding to the first register according to the memory base address, the sequence number of the first register in the at least two first registers, and the capacity of the first register, and write the doorbell signal read from the first register into the doorbell memory corresponding to the first register according to the memory address.
[0009] In one possible implementation, the capacity of the storage space in the first register used to store the doorbell signal is equal to the capacity of the doorbell memory.
[0010] In one possible implementation, the first register communicates with the host via a register interface-based connection bus.
[0011] According to a second aspect of the embodiments of this application, a dedicated data processor is provided, including: a processing unit and an acceleration unit as described in the first aspect of this application; the processing unit is configured to read the doorbell signal from the memory when a doorbell signal is detected being written to the memory of the dedicated data processor, and to obtain a read / write request from the host to read and write to the storage system based on the read doorbell signal.
[0012] In one possible implementation, the processing unit reads from the storage system when the read / write request is a read request and sends the read data to the host, and obtains write data from the host when the read / write request is a write request and writes the write data to the storage system.
[0013] In one possible implementation, when the acceleration unit includes at least two first registers, the memory includes at least two doorbell memories, different first registers correspond to different doorbell memories, and different first registers correspond to different transmission queues in the host; the processing unit is configured to traverse the at least two doorbell memories according to a preset traversal period to detect whether each doorbell memory has been written with a doorbell signal.
[0014] According to a third aspect of the embodiments of this application, a host is provided, comprising: a processor; the host is connected to a dedicated data processor as described in the second aspect of this application; the processor is configured to write a doorbell signal into a first register included in the dedicated data processor after writing a read / write request for a storage system into a transmission queue, so that the dedicated data processor obtains a read / write request for reading and writing to the storage system from the host according to the doorbell signal.
[0015] According to a fourth aspect of the embodiments of this application, a read / write signal transmission method is provided, applied to a dedicated data processor, comprising: storing a doorbell signal written by a host in a first register, wherein the doorbell signal is used to instruct the host to request read / write access to a storage system; after detecting that the doorbell signal has been written to the first register, reading the doorbell signal from the first register and writing the read doorbell signal into memory; reading the doorbell signal from the memory and obtaining a read / write request from the host to read / write access to the storage system based on the doorbell signal.
[0016] According to the solution provided in the embodiments of this application, the acceleration unit includes a first register and a forwarding subunit. The first register stores the doorbell signal sent by the host, and the forwarding subunit forwards the doorbell signal to the memory of the dedicated data processor. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. The host can then read / write to the storage system through the dedicated data processor. Since the host processes the read / write requests through the dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0018] Figure 1 This is a schematic diagram of an acceleration unit provided in an embodiment of this application;
[0019] Figure 2 This is a schematic diagram of another acceleration unit provided in an embodiment of this application;
[0020] Figure 3 This is a schematic diagram of another acceleration unit provided in an embodiment of this application;
[0021] Figure 4 This is a schematic diagram of a dedicated data processor provided in an embodiment of this application;
[0022] Figure 5 This is a schematic diagram of a host provided in an embodiment of this application;
[0023] Figure 6 This is a flowchart of a read / write signal transmission method provided in an embodiment of this application. Detailed Implementation
[0024] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the essence of the present application, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.
[0025] As mentioned earlier, NVMe storage devices refer to storage devices that support the Non-Volatile Memory Express (NVMe) protocol. Because the NVMe protocol employs simplified instructions, a lower-latency software stack, queue parallelism, and a larger queue depth, it can significantly reduce hardware-level I / O overhead and latency. This results in NVMe-enabled storage devices possessing high bandwidth and low latency hardware characteristics, making them widely used in computing devices.
[0026] When an application running on the host needs to read or write to a storage device, it issues a read / write request. Currently, the host's processor handles these requests, enabling functions such as establishing a connection with the storage device and reading / writing data. However, processing these read / write requests consumes excessive processor resources, resulting in less time for the processor to run its primary tasks.
[0027] In this embodiment, the acceleration unit includes a first register and a forwarding subunit. The first register stores the doorbell signal sent by the host, and the forwarding subunit forwards the doorbell signal to the memory of the dedicated data processor. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. The host can then read and write to the storage system through the dedicated data processor. Since the host processes the read / write requests through the dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0028] The specific implementation of the embodiments of this application will be further described below with reference to the accompanying drawings.
[0029] Figure 1 This is a schematic diagram of an acceleration unit provided in an embodiment of this application. The acceleration unit 100 is disposed on a dedicated data processor connected to a host computer, such as... Figure 1 As shown, the acceleration unit 100 includes a first register 101 and a forwarding subunit 102.
[0030] The first register 101 can store a doorbell signal written by the host, wherein the doorbell signal is used to indicate that the host requests to read or write to the storage system. The forwarding subunit 102 can read the doorbell signal from the first register 101 after detecting that a doorbell signal has been written to it, and write the read doorbell signal to the memory of the dedicated data processor. This enables the processing unit included in the dedicated data processor to read the doorbell signal from the memory and obtain a read / write request from the host to read or write to the storage system based on the doorbell signal.
[0031] When a program in the host needs to read or write to the storage system, the NVMe driver running in the host writes a doorbell signal to the first register 101 included in the dedicated data processor. The first register 101 stores the doorbell signal written by the host. After the forwarding subunit 102 detects that a doorbell signal has been written to the first register 101, it reads the doorbell signal in the first register 101 according to the preset forwarding rules and writes the doorbell signal to the memory in the dedicated data processor. After the processing unit in the dedicated data processor detects that a doorbell signal has been written to the memory, it reads the doorbell signal in the memory and processes the doorbell signal.
[0032] The processing unit processes the doorbell signal and can obtain read / write requests for the storage system from the host based on the doorbell signal. Thus, the host can read and write to the storage system through this dedicated data processor.
[0033] In this embodiment, the acceleration unit 100 includes a first register 101 and a forwarding subunit 102. The first register 101 stores the doorbell signal sent by the host, and the forwarding subunit 102 forwards the doorbell signal to the memory of the dedicated data processor. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. The host can then read / write to the storage system through the dedicated data processor. Since the host processes the read / write requests through the dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0034] Figure 2 This is a schematic diagram of another acceleration unit provided in an embodiment of this application, as shown below. Figure 2 As shown, the acceleration unit 100 includes at least two first registers 101, and the memory includes at least two doorbell memories. Different first registers 101 correspond to different doorbell memories, and different first registers 101 correspond to different transmission queues in the host.
[0035] The first register 101 can store the doorbell signal written by the host after a read / write request is written to the transmission queue corresponding to the first register 101. The read / write request is used to read and write to the storage system. The forwarding subunit 102 can read the doorbell signal from the first register 101 after detecting that a doorbell signal has been written to the first register 101, and write the read doorbell signal into the doorbell memory corresponding to the first register 101.
[0036] The acceleration unit 100 may include multiple first registers 101, each corresponding to a transmission queue in the host and a doorbell memory in the dedicated data processor. For example, if the host has 10 transmission queues, the acceleration unit 100 includes 10 first registers 101, and the dedicated data processor allocates 10 doorbell memories. The 10 first registers 101 correspond one-to-one with the 10 transmission queues, with different transmission queues corresponding to different first registers 101. The 10 first registers 101 correspond one-to-one with the 10 doorbell memories, with different first registers 101 corresponding to different doorbell memories.
[0037] When a read / write request is written to the transmission queue corresponding to the first register 101, the first register 101 receives the doorbell signal sent by the host and stores the doorbell signal. At this time, the forwarding subunit 102 detects that the doorbell signal has been written to the first register 101. The forwarding subunit 102 reads the doorbell signal and writes the doorbell signal to the doorbell memory corresponding to the first register 101. For example, if a read / write request is written to the first transmission queue in the host, the doorbell signal written by the host is stored in register 1 corresponding to the first transmission queue. The forwarding subunit 102 detects that the host has written the doorbell signal to register 1 and forwards the doorbell signal to the doorbell memory 1 corresponding to register 1.
[0038] It should be understood that the acceleration unit 100 can be configured with multiple first registers 101. The number of first registers 101 that are enabled can be determined based on the transmission queues in the host. For example, if the acceleration unit 100 is configured with 20 first registers 101, and the host has 10 transmission queues, then 10 first registers 101 will be enabled. It should be noted that the amount of doorbell memory in the dedicated data processor can be allocated by the processing unit in the dedicated data processor based on the number of transmission queues or the number of first registers 101, and is not limited here.
[0039] In this embodiment, the acceleration unit 100 is provided with multiple first registers 101. Different first registers 101 correspond to different transmission queues in the host and different doorbell memories. This allows multiple doorbell signals sent by the host to be stored in multiple first registers 101 when read / write requests are being written to multiple transmission queues. This enables parallel processing of doorbell signals corresponding to multiple read / write requests. Since the first registers 101 and doorbell memories are one-to-one, the corresponding first register 101 can be located through the doorbell memory, thereby locating the transmission queue to which the read / write request is being written, thus improving the efficiency of data read / write.
[0040] Figure 3 This is a schematic diagram of another acceleration unit provided in an embodiment of this application, as shown below. Figure 3As shown, the acceleration unit 100 further includes a second register 103, which can store the memory base addresses of at least two doorbell memories. The memory base addresses are written to the second register 103 by the processing unit, and the memory addresses of the at least two doorbell memories are sequentially connected. After detecting that a doorbell signal has been written to the first register 101, the forwarding subunit 102 can read the memory base address from the second register 103, and determine the memory address of the doorbell memory corresponding to the first register 101 based on the memory base address, the sequence number of the first register 101 in the at least two first registers 101, and the capacity of the first register 101. Based on the memory address, the doorbell signal read from the first register 101 is written to the doorbell memory corresponding to the first register 101.
[0041] The acceleration unit 100 also includes a second register 103, which stores the memory base addresses of at least two doorbell memories. For example, the starting address of the doorbell memory within the dedicated data processor's memory. It should be understood that since the doorbell memory is allocated by the processing unit within the dedicated data processor, and the dedicated data processor's memory is a single block of memory, the processing unit allocates a portion of this block as doorbell memory. This doorbell memory base address is the starting address of the first doorbell memory data stored in the contiguous doorbell memory. After allocating the doorbell memory, the processing unit writes the memory base address into the second register 103. The doorbell memory consists of contiguous memory addresses and contiguous memory blocks.
[0042] After detecting that a doorbell signal has been written to the first register 101 by the host, the forwarding subunit 102 determines the memory address of the doorbell memory corresponding to the first register 101 based on the memory base address stored in the second register 103, the sequence number of the first register 101 in at least two first registers 101, and the capacity of the first register 101. It should be understood that the capacity of the doorbell memory is greater than or equal to the capacity of the first register 101, thereby allowing the complete doorbell signal to be written. After determining the address of the doorbell memory, the forwarding subunit 102 writes the doorbell signal read from the first register 101 to the doorbell memory corresponding to the first register 101 according to the memory address of the doorbell memory, that is, writes it to the memory of the dedicated data processor. It should be understood that the forwarding subunit 102 can write the doorbell signal to the doorbell memory through Direct Memory Access (DMA).
[0043] In this embodiment, the acceleration unit 100 further includes a second register 103, which stores the base address of the doorbell memory. The forwarding subunit 102 can determine the doorbell memory corresponding to the first register 101 to which the doorbell signal is written based on the base address of the doorbell memory, thereby writing the doorbell signal to the memory of the dedicated data processor and realizing the forwarding of the doorbell signal. Since the doorbell base address is stored in the register in the acceleration unit 100, the time spent by the forwarding unit to read the doorbell base address is reduced, thus improving the efficiency of doorbell signal forwarding.
[0044] In one possible implementation, the capacity of the storage space in the first register 101 used to store the doorbell signal is equal to the capacity of the doorbell memory.
[0045] In one example, the starting address of the first doorbell memory is the memory base address, and the ending address is the memory base address plus the capacity of the storage space in the corresponding first register 101 used to store the doorbell signal. The starting address of the second doorbell memory is the ending address of the first doorbell memory, and the ending address is the ending address of the first doorbell memory plus the capacity of the storage space in the corresponding first register 101 used to store the doorbell signal. When the capacities of the first registers 101 are the same, the starting address of the doorbell memory is the memory base address plus the sequence number of the first register 101 in at least two first registers 101 multiplied by the capacity of the first register 101.
[0046] In this embodiment, the capacity of the storage space in the first register 101 used to store the doorbell signal is equal to the capacity of the doorbell memory. This ensures that the complete doorbell signal can be written into the doorbell memory, avoids wasting doorbell memory, and reduces the memory usage in the dedicated data processor.
[0047] In one possible implementation, the first register 101 communicates with the host via a register interface-based connection bus.
[0048] The first register 101 communicates with the host via a register interface-based connection bus, for example, by communicating with the host via the PCIe bus, or by transmitting doorbell signals via the PCIe bus.
[0049] In this embodiment, the first register 101 communicates with the host via a register interface-based connection bus, thus making it applicable to a variety of dedicated data processors connected to the host via different buses, and thus having high applicability.
[0050] Figure 4 This is a schematic diagram of a dedicated data processor provided in an embodiment of this application, as shown below. Figure 4As shown, the dedicated data processor 200 includes a processing unit 201 and an acceleration unit 100 as described in any of the above embodiments. The processing unit 201 can read the doorbell signal from the memory 202 after detecting that a doorbell signal has been written to the dedicated data processor's memory 202, and obtain a read / write request from the host to read and write to the storage system based on the read doorbell signal.
[0051] The dedicated data processor 200 can be a smart network card connected to the host. For example, the dedicated data processor 200 can be a data processing unit (DPU). The processing unit 201 in the dedicated data processor 200 can read the doorbell signal after detecting that a doorbell signal has been written to the memory 202, and process the doorbell signal, thereby establishing a read and write channel between the dedicated data processor 200 and the NVMe storage system based on the doorbell signal.
[0052] In this embodiment, the dedicated data processor 200 includes an acceleration unit 100 and a processing unit 201. The first register 101 in the acceleration unit 100 can store the doorbell signal sent by the host. The forwarding subunit 102 in the acceleration unit 100 forwards the doorbell signal to the memory 202 of the dedicated data processor. The processing unit 201 of the dedicated data processor 200 can read the doorbell signal in the memory 202. Thus, a read / write channel between the dedicated data processor 200 and the NVMe storage system can be established through the doorbell signal. Therefore, the host can read and write to the NVMe storage system through the dedicated data processor 200. Since the host offloads the task of processing the doorbell signal and the read / write request to the dedicated data processor 200, the processor utilization rate is lower than that of the prior art where the host processor processes the doorbell signal and the read / write request, thus improving the computing performance of the host processor.
[0053] In one possible implementation, the processing unit 201 can determine the sending queue of read / write requests written in the host based on the doorbell signal, and obtain the read / write requests from the sending queue.
[0054] The processing unit 201 processes the doorbell signal and determines the sending queue of the read / write request, that is, the storage area in the host where the read / write request is stored. After determining the storage area, the processing unit 201 reads the read / write request stored in the storage area, so that the storage system can be read and written through the read / write request.
[0055] In this embodiment of the application, the processing unit 201 can determine the sending queue of read and write requests written in the host according to the doorbell signal, and obtain the read and write requests from the sending queue. This realizes the processing of read and write requests by a dedicated data processor. Since the host processes read and write requests through a dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0056] In one possible implementation, the processing unit 201 can read from the storage system when the read / write request is a read request and send the read data to the host, and when the read / write request is a write request, it can obtain write data from the host and write the write data to the storage system.
[0057] After the processing unit 201 in the dedicated data processor 200 obtains the read / write request from the host according to the doorbell signal, it analyzes the read / write request. If the read / write request is to read data from the storage system, the data is read from the storage system according to the read / write request and written to the corresponding storage location in the host according to the read / write request. If the read / write request is to write data to the storage system, the data to be written is read from the host according to the read / write request and written to the storage system. In this way, the dedicated data processor 200 can read and write data in the storage system.
[0058] In this embodiment of the application, the dedicated data processor 200 processes read and write requests, enabling read and write access to the storage system. Since the host processes read and write requests through the dedicated data processor 200, the host can access any storage system through the dedicated data processor 200, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, improving the computing performance of the processor in the host.
[0059] In one possible implementation, when the acceleration unit 100 includes at least two first registers 101, the memory 202 includes at least two doorbell memories 202, different first registers 101 correspond to different doorbell memories 202, and different first registers 101 correspond to different transmission queues in the host, the processing unit 201 can traverse at least two doorbell memories 202 according to a preset traversal period to detect whether each doorbell memory 202 has been written with a doorbell signal.
[0060] When the acceleration unit 100 includes at least two first registers 101, the multiple first registers 101 correspond one-to-one with the transmission queues in the host, and the multiple first registers 101 correspond one-to-one with the multiple doorbell memories 202 in the dedicated data processor. For example, if the host has 10 transmission queues, then the acceleration unit 100 includes 10 first registers 101, and the dedicated data processor is allocated 10 doorbell memories 202. The 10 first registers 101 correspond one-to-one with the 10 transmission queues, and different transmission queues correspond to different first registers 101. The 10 first registers 101 correspond one-to-one with the 10 doorbell memories 202, and different first registers 101 correspond to different doorbell memories 202.
[0061] The processing unit 201 in the dedicated data processor 200 traverses all the doorbell memories 202 according to a preset traversal period. For example, the processing unit 201 traverses at least two doorbell memories 202 included in the dedicated data processor every 1 second to detect whether doorbell signals have been written to at least two doorbell memories 202. It should be understood that the doorbell signals in the doorbell memories 202 are written by the forwarding subunit 102 in the acceleration unit 100 according to the doorbell signals written by the host in the corresponding first register 101.
[0062] In this embodiment of the application, the processing unit 201 can traverse at least two doorbell memories 202 according to a preset traversal period, thereby enabling the detection of whether a doorbell signal has been written into the doorbell memory 202, and enabling timely response to the doorbell signal when a doorbell signal is written into the doorbell memory 202, thus improving the efficiency of doorbell signal processing.
[0063] Figure 5 This is a schematic diagram of a host provided in an embodiment of this application, such as... Figure 5 As shown, the host 300 includes a processor 301. The host 300 is connected to the dedicated data processor 200 in any of the above embodiments. After writing the read / write request for the storage system into the transmission queue, the processor 301 can write the doorbell signal into the first register 101 included in the dedicated data processor 200, so that the dedicated data processor 200 can obtain the read / write request for reading and writing to the storage system from the host 300 according to the doorbell signal.
[0064] When the host 300's processor 301 needs to read or write to the storage system, it can write the read / write request to the sending queue. After the processor 301 writes the read / write request to the sending queue, the host 300 generates a doorbell signal and sends the doorbell signal to the first register 101.
[0065] In one example, host 300 includes multiple sending queues. After writing a read / write request to a sending queue, host 300 sends a doorbell signal to the first register 101 corresponding to that sending queue. The interaction process is shown in the above embodiment and will not be repeated here.
[0066] In this embodiment, the processor 301 included in the host 300 can write the doorbell signal into the first register 101 included in the dedicated data processor 200 after writing the read / write request into the sending queue. This allows the dedicated data processor 200 to obtain the read / write request for reading and writing to the storage system from the host 300 based on the doorbell signal. Thus, the host 300 can read and write to the storage system through the dedicated data processor 200, thereby realizing the read and write of the storage system. Since the host 300 offloads the task to the dedicated data processor 200 for execution, the occupancy of the processor 301 in the host 300 can be reduced, and the computing efficiency of the host 300 can be improved.
[0067] The specific application of the dedicated data processor is described below through a specific embodiment.
[0068] Figure 6 This is a flowchart of a read / write signal transmission method provided in an embodiment of this application, such as... Figure 6 As shown, the read / write signal transmission method includes the following steps 601 to 603:
[0069] Step 601: Store the doorbell signal written by the host in the first register.
[0070] The first register receives and stores the doorbell signal written by the host. This doorbell signal is generated after the host writes the read / write request into the sending queue. In other words, the doorbell signal is used to indicate that the host requests to read or write to the storage system.
[0071] In one example, multiple doorbell signals written by the host can be stored in multiple first registers.
[0072] Step 602: After detecting that the doorbell signal has been written to the first register, read the doorbell signal from the first register and write the read doorbell signal into memory.
[0073] In one example, if the acceleration unit has multiple first registers and the memory includes multiple doorbell memories, the doorbell signal in the first register can be read and written to the doorbell memory corresponding to the first register.
[0074] Step 603: Read the doorbell signal from memory and obtain read / write requests for the storage system from the host based on the doorbell signal.
[0075] In this embodiment, the doorbell signal sent by the host is stored in the first register, then the doorbell signal is forwarded to memory, and the doorbell signal in memory is read. Thus, the host can obtain read / write requests to the storage system from the host through the doorbell signal. The host can then read and write to the storage system through a dedicated data processor. Since the host processes read / write requests through a dedicated data processor, the host can access any storage system through the dedicated data processor, thereby offloading the complexity of accessing different storage systems and the consumption of running storage system clients. The processor utilization rate is low, which improves the computing performance of the processor in the host.
[0076] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. The focus of each embodiment is to describe the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and the relevant parts can be referred to the descriptions of other embodiments.
[0077] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0078] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.
[0079] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.
Claims
1. An acceleration unit, wherein the acceleration unit is disposed on a dedicated data processor connected to a host computer, characterized in that, The acceleration unit includes: a first register and a forwarding subunit; The first register is used to store a doorbell signal written by the host, wherein the doorbell signal is used to instruct the host to request read or write access to the storage system; The forwarding subunit is configured to read the doorbell signal from the first register after detecting that the doorbell signal has been written to the first register, and write the read doorbell signal into the memory of the dedicated data processor, so that the processing unit included in the dedicated data processor reads the doorbell signal from the memory and obtains a read / write request for reading and writing to the storage system from the host according to the doorbell signal.
2. The acceleration unit according to claim 1, characterized in that, The acceleration unit includes at least two first registers, the memory includes at least two doorbell memories, different first registers correspond to different doorbell memories, and different first registers correspond to different transmission queues in the host; The first register is used to store the doorbell signal written by the host after a read / write request is written to the sending queue corresponding to the first register, wherein the read / write request is used to read and write to the storage system; The forwarding subunit is configured to read the doorbell signal from the first register after detecting that the doorbell signal has been written into the first register, and write the read doorbell signal into the doorbell memory corresponding to the first register.
3. The acceleration unit according to claim 2, characterized in that, The acceleration unit further includes: a second register; The second register is used to store the memory base address of the at least two doorbell memories, wherein the memory base address is written into the second register by the processing unit, and the memory addresses of the at least two doorbell memories are sequentially connected; The forwarding subunit is configured to, after detecting that the doorbell signal is written to the first register, read the memory base address from the second register, and determine the memory address of the doorbell memory corresponding to the first register based on the memory base address, the sequence number of the first register in the at least two first registers, and the capacity of the first register, and write the doorbell signal read from the first register into the doorbell memory corresponding to the first register based on the memory address.
4. The acceleration unit according to claim 3, characterized in that, The capacity of the storage space in the first register used to store the doorbell signal is equal to the capacity of the doorbell memory.
5. The acceleration unit according to any one of claims 1-4, characterized in that, The first register communicates with the host via a register interface-based connection bus.
6. A dedicated data processor, characterized in that, include: The processing unit and the acceleration unit as described in any one of claims 1-5; The processing unit is configured to read the doorbell signal from the memory when it detects that the memory of the dedicated data processor has been written with a doorbell signal, and obtain a read / write request from the host to read and write to the storage system based on the read doorbell signal.
7. The dedicated data processor according to claim 6, characterized in that, The processing unit is configured to read from the storage system when the read / write request is a read request and send the read data to the host, and to obtain write data from the host when the read / write request is a write request and write the write data to the storage system.
8. The dedicated data processor according to claim 6, characterized in that, When the acceleration unit includes at least two first registers, the memory includes at least two doorbell memories, different first registers correspond to different doorbell memories, and different first registers correspond to different sending queues in the host; The processing unit is used to traverse the at least two doorbell memories according to a preset traversal period to detect whether a doorbell signal has been written to each doorbell memory.
9. A host computer, characterized in that, include: processor; The host is connected to a dedicated data processor as described in any one of claims 6-8; The processor is configured to write a doorbell signal into a first register included in the dedicated data processor after writing a read / write request for the storage system into a sending queue, so that the dedicated data processor can obtain a read / write request for the storage system from the host according to the doorbell signal.
10. A read / write signal transmission method, applied to a dedicated data processor, characterized in that, include: The doorbell signal written by the host is stored in the first register, wherein the doorbell signal is used to instruct the host to request read and write to the storage system; After detecting that the doorbell signal has been written to the first register, the doorbell signal is read from the first register and written to memory; The doorbell signal is read from the memory, and a read / write request for reading and writing to the storage system is obtained from the host based on the doorbell signal.