Storage control circuit, storage control chip, system-on-chip and electronic equipment

Abstract

The invention relates to a storage control circuit, a storage control chip, a system-on-chip and electronic equipment. The first end of the storage control circuit is electrically connected with the control unit, and the second end of the storage control circuit is electrically connected with the memory; the storage control circuit is used for processing the first read-write information sent by the control unit to obtain a plurality of pieces of second read-write information, and each piece of second read-write information corresponds to one sub-channel in the memory; and the storage control circuit is also used for processing the plurality of pieces of second read-write information in sequence to obtain corresponding third read-write information, and sending each piece of third read-write information to the corresponding sub-channel. The storage control circuit sequentially processes the multiple pieces of second read-write information corresponding to the multiple sub-channels of the memory, so that only one read-write information processing circuit needs to be arranged in the storage control circuit, the area of the storage control circuit can be reduced, and the power consumption and the cost of the storage control circuit are reduced.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a storage control circuit, a storage control chip, a system-on-a-chip, and an electronic device. Background Technology

[0002] The storage control circuit processes the data flow between the control unit and the memory. Memory with multiple sub-channels communicates with the storage control circuit through multiple independent sub-channels, thereby increasing the memory's data transfer bandwidth. Currently, the storage control circuit for memory with multiple sub-channels includes multiple read / write information processing circuits, each corresponding to one of the sub-channels. These circuits process the read / write information corresponding to each sub-channel. The inclusion of multiple read / write information processing circuits results in a large storage control circuit with high power consumption and cost. Summary of the Invention

[0003] To overcome the problems existing in related technologies, this disclosure provides a storage control circuit, a storage control chip, a system-on-a-chip, and an electronic device.

[0004] According to a first aspect of the present disclosure, a storage control circuit is provided, wherein a first terminal of the storage control circuit is electrically connected to a control unit, and a second terminal of the storage control circuit is electrically connected to a memory; the storage control circuit is configured to process first read / write information sent by the control unit to obtain a plurality of second read / write information, each of the second read / write information corresponding to a sub-channel of the memory; the storage control circuit is further configured to process the plurality of second read / write information sequentially to obtain corresponding third read / write information, and send each of the third read / write information to the corresponding sub-channel.

[0005] In this embodiment, the storage control circuit processes multiple second read / write information corresponding to multiple sub-channels of the memory sequentially. Therefore, only one read / write information processing circuit needs to be set in the storage control circuit, which can reduce the area of ​​the storage control circuit and reduce its power consumption and cost.

[0006] In some exemplary embodiments of this disclosure, the storage control circuit includes: A first interface unit, wherein a first end of the first interface unit is used to be electrically connected to the control unit, and the first interface unit is used to process the first read / write information to obtain a plurality of second read / write information; The read / write processing circuit has each first terminal electrically connected to a second terminal of the first interface unit. The first terminals of the read / write processing circuit are electrically connected to different second terminals of the first interface circuit. The read / write processing circuit is used to process multiple second read / write information sequentially to obtain the corresponding third read / write information. The second interface unit has a first terminal that is electrically connected to a second terminal of the read / write processing circuit. The second terminals of the read / write processing circuits connected to different first terminals of the second interface unit are different. Each second terminal of the second interface unit is electrically connected to a sub-channel. The sub-channels connected to different second terminals of the second interface unit are different. The second interface unit is used to send each of the third read / write information to the corresponding sub-channel.

[0007] In this embodiment, the first interface unit processes the first read / write information to obtain multiple second read / write information, the read / write processing circuit processes the multiple second read / write information sequentially to obtain corresponding third read / write information, and the second interface unit sends the third read / write information to the corresponding sub-channel so that the storage control circuit can control the memory including multiple sub-channels.

[0008] In some exemplary embodiments of this disclosure, the first read / write information includes a target address; The first interface unit determines the sub-channel corresponding to each piece of the second read / write information based on the target address, and adds the flag information corresponding to the sub-channel to the second read / write information; The different sub-channels correspond to different flag information.

[0009] In this embodiment, the first interface unit determines the sub-channel corresponding to each second read / write information based on the target address in the first read / write information, adds the flag information corresponding to the sub-channel to the second read / write information, and can subsequently identify the sub-channel based on the flag information in the second read / write information.

[0010] In some exemplary embodiments of this disclosure, the third read / write information includes flag information; the second interface unit identifies the sub-channel corresponding to the third read / write information through the flag information.

[0011] In this embodiment, the third read / write information still includes flag information. The second interface unit can determine the sub-channel corresponding to the third read / write information based on the flag information and send the third read / write information to the corresponding sub-channel.

[0012] In some exemplary embodiments of this disclosure, the read / write processing circuit includes: A command processing circuit, wherein a first terminal of the command processing circuit is electrically connected to a second terminal of the first interface unit, and a second terminal of the command processing circuit is electrically connected to a first terminal of the second interface unit; A write data path, wherein a first end of the write data path is electrically connected to a second end of the first interface unit, a second end of the write data path is electrically connected to a first end of the second interface unit, and a third end of the write data path is electrically connected to a third end of the command processing circuit. A read data path, wherein a first end of the read data path is electrically connected to a second end of the first interface unit, a second end of the read data path is electrically connected to a first end of the second interface unit, and a third end of the read data path is electrically connected to a fourth end of the command processing circuit. The first terminal of the command processing circuit, the first terminal of the write data path, and the first terminal of the read data path are electrically connected to different terminals of the first interface unit, and the second terminal of the command processing circuit, the second terminal of the write data path, and the second terminal of the read data path are electrically connected to different terminals of the first interface unit.

[0013] In this embodiment, a single read / write processing circuit can process multiple second read / write messages sequentially, which can reduce the area of ​​the storage control circuit and lower its power consumption and cost.

[0014] In some exemplary embodiments of this disclosure, the command processing circuit includes: A priority control unit, wherein a first terminal of the priority control unit is electrically connected to a second terminal of the first interface unit; The scheduling unit has a first terminal electrically connected to the second terminal of the priority control unit, a second terminal electrically connected to the third terminal of the write data path, and a third terminal electrically connected to the third terminal of the read data path. The decoding unit has a first end electrically connected to the fourth end of the scheduling unit, and a second end electrically connected to the first end of the second interface unit.

[0015] In this embodiment, the priority control unit, scheduling unit, and decoding unit can be used to complete the command transmission in the second read / write information and control the corresponding data path to complete the data transmission.

[0016] In some exemplary embodiments of this disclosure, the second interface unit is electrically connected to the memory through a third interface unit, and the third interface unit is used to convert the third read / write information into digital data and send it to the corresponding sub-channel.

[0017] In this embodiment, by adding a third interface unit, the third read / write information can be electrically processed and converted into an electrical signal that the memory can recognize.

[0018] In some exemplary embodiments of this disclosure, each second end of the second interface unit is respectively used to be electrically connected to a first end of the third interface unit, and the first ends of the third interface unit electrically connected to different second ends of the second interface unit are different. Each second terminal of the third interface unit is electrically connected to one of the sub-channels, and the sub-channels electrically connected to different second terminals of the third interface unit are different.

[0019] In this embodiment, each sub-channel corresponds to a second end of the second interface unit and a first end and a second end of the third interface unit, and is used to transmit the third read / write information corresponding to the sub-channel.

[0020] In some exemplary embodiments of this disclosure, the second interface unit is a DFI interface unit, and the third interface unit is a PHY interface unit.

[0021] In this embodiment, the DFI interface unit, as the second interface unit, can define a standardized and efficient communication protocol between the storage control circuit and the PHY interface unit, enabling them to communicate efficiently and without errors. The PHY interface unit, as the third interface unit, is used to handle matters related to physical electrical signals. It can convert the third read / write information from digital to analog and send it to the corresponding sub-channel. It can also enhance the signal strength of the third read / write information, perform timing control, and perform voltage conversion.

[0022] In some exemplary embodiments of this disclosure, the number of sub-channels is two, and the number of read / write processing circuits is one.

[0023] In this embodiment, the memory includes two sub-channels. By using two independent sub-channels to communicate with the memory control circuit, the data transmission bandwidth of the memory is increased. The number of read / write processing circuits is reduced to one, which can decrease the area of ​​the memory control circuit and reduce its power consumption and cost.

[0024] In some exemplary embodiments of this disclosure, each of the sub-channels is a 32-bit sub-channel.

[0025] In this embodiment, the data transmission bandwidth of the memory is increased by using multiple independent 32-bit sub-channels to communicate with the memory control circuit.

[0026] In some exemplary embodiments of this disclosure, the storage control circuit is used to sequentially send the processed plurality of third read / write information to the corresponding sub-channels.

[0027] In this embodiment, by sequentially sending multiple third read / write messages, the speed can be matched with the speed of sequentially processing multiple second read / write messages.

[0028] According to a second aspect of the present disclosure, a memory control chip is provided, including any of the memory control circuits described in the first aspect of the present disclosure.

[0029] According to a third aspect of the present disclosure, a system-on-a-chip is provided, including a memory control chip as described in the second aspect of the present disclosure.

[0030] According to a fourth aspect of the present disclosure, an electronic device is provided, including a storage control chip as described in the second aspect of the present disclosure or a system-on-a-chip as described in the third aspect of the present disclosure.

[0031] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: The storage control circuit processes multiple second read / write information corresponding to multiple sub-channels of the memory sequentially. Therefore, only one read / write information processing circuit needs to be set in the storage control circuit, which can reduce the area of ​​the storage control circuit and reduce its power consumption and cost.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0034] Figure 1 This is a schematic diagram of a storage control circuit according to an exemplary embodiment.

[0035] Figure 2 This is a schematic diagram of a storage control circuit according to another exemplary embodiment.

[0036] Figure 3 This is a schematic diagram of a storage control circuit according to another exemplary embodiment.

[0037] Figure 4 This is a schematic diagram of a storage control circuit according to another exemplary embodiment.

[0038] Figure 5 This is a schematic diagram of a storage control circuit according to another exemplary embodiment.

[0039] Figure 6This is a block diagram of an electronic device according to an exemplary embodiment.

[0040] In the picture: 1-Storage control circuit; 2-Control unit; 3-Memory; 4-Third interface unit; 11-First interface unit; 12-Read / write processing circuit; 13-Second interface unit; 31-Sub-channel; 121-Command processing circuit; 122-Write data path; 123-Read data path; 600-Electronic device; 602-Processing component; 604-Memory; 606-Power supply component; 608-Multimedia component; 610-Audio component; 612-Input / output interface; 614-Sensor component; 616-Communication component; 620-Processor; 1211-Priority control unit; 1212-Scheduling unit; 1213-Decoding unit. Detailed Implementation

[0041] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0042] The storage control circuit processes the data flow between the control unit and the memory. Memory with multiple sub-channels communicates with the storage control circuit through multiple independent sub-channels, thereby increasing the memory's data transfer bandwidth. Currently, the storage control circuit for memory with multiple sub-channels includes multiple read / write information processing circuits, each corresponding to one of the sub-channels. These circuits process the read / write information corresponding to each sub-channel. The inclusion of multiple read / write information processing circuits results in a large storage control circuit with high power consumption and cost.

[0043] To address the aforementioned problems, this disclosure provides a storage control circuit. A first terminal of the storage control circuit is electrically connected to a control unit, and a second terminal is electrically connected to a memory. The storage control circuit processes first read / write information sent by the control unit to obtain multiple second read / write information entries, each corresponding to a sub-channel in the memory. The storage control circuit further processes the multiple second read / write information entries sequentially to obtain corresponding third read / write information entries, and sends each third read / write information entry to its corresponding sub-channel. Since the storage control circuit processes multiple second read / write information entries corresponding to multiple sub-channels of the memory sequentially, only one read / write information processing circuit needs to be included in the storage control circuit, which reduces the area of ​​the storage control circuit and lowers its power consumption and cost.

[0044] In some exemplary embodiments, such as Figure 1 As shown in the illustration, this embodiment depicts a storage control circuit 1. A first terminal of the storage control circuit 1 is electrically connected to a control unit 2, and a second terminal is electrically connected to a memory 3. In some examples, the storage control circuit 1 can be used to process the data flow between the control unit 2 and the memory 3. The control unit 2 can be a processor such as a central processing unit or a graphics processing unit. The memory 3 can be a memory comprising multiple independent sub-channels 31, for example, a fifth-generation Double Data Rate (DDR5) memory comprising two sub-channels 31, or a sixth-generation Low Power Double Data Rate (LPDDR6) memory comprising two sub-channels 31.

[0045] The storage control circuit 1 processes the first read / write information sent by the control unit 2 to obtain multiple second read / write information messages, each corresponding to a sub-channel 31 in the storage 3. In some examples, the control unit 2 can send the first read / write information to the storage control circuit 1 via a bus. The first read / write information may include a target address, which may include multiple consecutive addresses, for example, the target address may include consecutive addresses of a cache line. The storage control circuit 1 can use a mapping algorithm to map the portion of the first read / write information related to each of the multiple consecutive addresses to the corresponding sub-channel 31, forming a second read / write information message, thereby processing the first read / write information to obtain multiple second read / write information messages. For example, if a cache line is 64 bytes in size, the read / write information for the first 32 bytes is mapped to a sub-channel 31 to form one second read / write information message, and the read / write information for the last 32 bytes is mapped to another sub-channel 31 to form another second read / write information message. The storage control circuit 1 can also add the flag information corresponding to the sub-channel 31 to the corresponding second read / write information. The flag information corresponding to each sub-channel 31 is different. For example, the memory 3 includes two sub-channels 31, and the flag information is represented by 1 bit of data. The flag information corresponding to one sub-channel 31 is 0, and the flag information corresponding to the other sub-channel 31 is 1. In some examples, the storage control circuit 1 can convert the target address into a physical address that the memory 3 can recognize.

[0046] The storage control circuit 1 is also used to process multiple second read / write information sequentially to obtain corresponding third read / write information, and send each third read / write information to the corresponding sub-channel 31. In some examples, the storage control circuit 1 can process multiple second read / write information sequentially in a serial manner. The storage control circuit 1 can process each second read / write information to obtain third read / write information that the memory 3 can recognize. For example, it can decode the operation instructions in the second read / write information according to the truth table, and split the data to be written to the memory 3 according to the bit width of the memory 3. The processed third read / write information includes flag information. The storage control circuit 1 can determine the sub-channel 31 corresponding to a third read / write information based on the flag information, and determine the time to send a third read / write information to the corresponding sub-channel 31 through priority control and scheduling.

[0047] In this embodiment, the storage control circuit processes multiple second read / write information corresponding to multiple sub-channels of the memory sequentially. Therefore, only one read / write information processing circuit needs to be set in the storage control circuit, which can reduce the area of ​​the storage control circuit and reduce its power consumption and cost.

[0048] In some possible embodiments, such as Figure 2 As shown, the storage control circuit 1 in this embodiment includes a first interface unit 11, a read / write processing circuit 12, and a second interface unit 13.

[0049] The first end of the first interface unit 11 is used to be electrically connected to the control unit 2. The first interface unit 11 is used to process the first read and write information to obtain multiple second read and write information.

[0050] In some possible embodiments, the first read / write information includes a target address. The first interface unit 11 determines the sub-channel 31 corresponding to each piece of second read / write information based on the target address, and adds the flag information corresponding to the sub-channel 31 to the second read / write information. Different sub-channels 31 correspond to different flag information.

[0051] In some examples, the control unit 2 can send first read / write information to the first interface unit 11 via a bus. The first read / write information may include a target address, which may include multiple consecutive addresses, for example, the target address may include consecutive addresses of a cache line. The first interface unit 11 can use a mapping algorithm to map the portion of the first read / write information related to each of the multiple consecutive addresses to the corresponding sub-channel 31, forming a second read / write information, thereby processing the first read / write information to obtain multiple second read / write information entries. For example, if a cache line is 64 bytes in size, the read / write information for the first 32 bytes is mapped to a sub-channel 31 to form one second read / write information entry, and the read / write information for the last 32 bytes is mapped to another sub-channel 31 to form another second read / write information entry. The first interface unit 11 can also add flag information corresponding to the sub-channel 31 to the corresponding second read / write information entry. The flag information corresponding to each sub-channel 31 is different. For example, the memory 3 includes two sub-channels 31, and the flag information is represented using 1 bit of data; the flag information corresponding to one sub-channel 31 is 0, and the flag information corresponding to the other sub-channel 31 is 1.

[0052] In some examples, the first interface unit 11 can translate the target address into a physical address that the memory 3 can recognize.

[0053] Each first terminal of the read / write processing circuit 12 is electrically connected to a second terminal of the first interface unit 11. Different first terminals of the read / write processing circuit 12 are electrically connected to different second terminals of the first interface circuit 11. The read / write processing circuit 12 processes multiple second read / write messages sequentially to obtain corresponding third read / write messages. In some examples, each second terminal of the first interface circuit 11 sends the same second read / write message to the corresponding first terminal of the read / write processing circuit 12. In some examples, the read / write processing circuit 12 can process multiple second read / write messages sequentially in a serial manner. The read / write processing circuit 12 can process each second read / write message to obtain third read / write messages that the memory 3 can recognize. For example, it can decode the operation instructions in the second read / write message according to a truth table, and split the data to be written to the memory 3 according to the bit width of the memory 3. The read / write processing circuit 12 can determine the timing of sending a third read / write message to the corresponding sub-channel 31 through priority control and scheduling.

[0054] Each first terminal of the second interface unit 13 is electrically connected to a second terminal of the read / write processing circuit 12. The second terminals of the read / write processing circuit 12 connected to different first terminals of the second interface unit 13 are different. Each second terminal of the second interface unit 13 is used to be electrically connected to a sub-channel 31. The sub-channels 31 connected to different second terminals of the second interface unit 13 are different. The second interface unit 13 is used to send each third read / write information to the corresponding sub-channel 31.

[0055] In some possible embodiments, the third read / write information includes flag information. The second interface unit 13 identifies the sub-channel 31 corresponding to the third read / write information through the flag information.

[0056] In some examples, multiple second terminals of the read / write processing circuit 12 jointly send a third read / write message to multiple first terminals of the second interface unit 13. In some examples, the third read / write message includes flag information. The second interface unit 13 can determine the sub-channel 31 corresponding to the third read / write message based on the flag information, and send the third read / write message to the corresponding sub-channel 31 according to the time indicated by the read / write processing circuit 12.

[0057] In this embodiment, the first interface unit processes the first read / write information to obtain multiple second read / write information pieces, and determines the sub-channel corresponding to each second read / write information piece based on the target address in the first read / write information piece, adding the flag information corresponding to the sub-channel to the second read / write information piece. After the read / write processing circuit processes the multiple second read / write information pieces sequentially to obtain the corresponding third read / write information pieces, the third read / write information pieces still include flag information. The second interface unit can determine the sub-channel corresponding to the third read / write information piece based on the flag information and send the third read / write information piece to the corresponding sub-channel, so that the storage control circuit can control the memory including multiple sub-channels.

[0058] In some possible embodiments, such as Figure 3 As shown, the read / write processing circuit 12 in this embodiment includes a command processing circuit 121, a write data path 122, and a read data path 123.

[0059] The first terminal of the command processing circuit 121 is electrically connected to a second terminal of the first interface unit 11, and the second terminal of the command processing circuit 121 is electrically connected to a first terminal of the second interface unit 13. In some examples, the command processing circuit 121 is used for priority control, scheduling, and decoding. Priority control refers to determining which second read / write information should be sent to the scheduler for processing first based on the priority sent from upstream (such as control unit 2). Scheduling refers to determining the timing of generating and issuing a third read / write information. Decoding refers to decoding the operation instructions in the second read / write information according to the truth table.

[0060] The first end of the write data path 122 is electrically connected to a second end of the first interface unit 11, the second end of the write data path 122 is electrically connected to a first end of the second interface unit 13, and the third end of the write data path 122 is electrically connected to the third end of the command processing circuit 121. In some examples, the write data path 122 is used to transmit data that needs to be written to the memory 3 in the second read / write information. The write data path 122 can split the data that needs to be written to the memory 3 according to the bit width of the memory 3. The bit width refers to the number of bits of data that can be transmitted simultaneously when the memory 3 exchanges data with the outside world. The write data path 122 can send corresponding data according to the instructions issued by the command processing circuit 121.

[0061] The first end of the read data path 123 is electrically connected to a second end of the first interface unit 11, the second end of the read data path 123 is electrically connected to a first end of the second interface unit 13, and the third end of the read data path 123 is electrically connected to a fourth end of the command processing circuit 121. In some examples, the read data path 123 is used to transmit data read from the memory 3. The read data path 123 can merge the data read from the memory 3. The read data path 123 can read corresponding data according to the instructions issued by the command processing circuit 121.

[0062] The first terminals of the command processing circuit 121, the first terminal of the write data path 122, and the first terminal of the read data path 123 are electrically connected to different second terminals of the first interface unit 11. The second terminals of the command processing circuit 121, the write data path 122, and the read data path 123 are electrically connected to different first terminals of the second interface unit 13. In some instances, the first terminals of the command processing circuit 121, the write data path 122, and the read data path 123 respectively obtain the same second read / write information from different second terminals of the first interface unit 11. The second terminals of the command processing circuit 121, the write data path 122, and the read data path 123 jointly send a third read / write information to multiple first terminals of the second interface unit 13.

[0063] In this embodiment, a single read / write processing circuit can process multiple second read / write messages sequentially, which can reduce the area of ​​the storage control circuit and lower its power consumption and cost.

[0064] In some possible embodiments, such as Figure 4As shown, the command processing circuit 121 in this embodiment includes a priority control unit 1211, a scheduling unit 1212, and a decoding unit 1213. The first terminal of the priority control unit 1211 is electrically connected to the second terminal of the first interface unit 11. The first terminal of the scheduling unit 1212 is electrically connected to the second terminal of the priority control unit 1211, the second terminal of the scheduling unit 1212 is electrically connected to the third terminal of the write data path 122, and the third terminal of the scheduling unit 1212 is electrically connected to the third terminal of the read data path 123. The first terminal of the decoding unit 1213 is electrically connected to the fourth terminal of the scheduling unit 1212, and the second terminal of the decoding unit 1213 is electrically connected to the first terminal of the second interface unit 13.

[0065] In some examples, the priority control unit 1211 is used to determine, based on priority, which second read / write message to send to the scheduling unit 1212 first. The scheduling unit 1212 is used to determine the timing of generating and sending a third read / write message, and to instruct the write data path 122 to send the corresponding data, and to instruct the read data path 123 to read the corresponding data. The decoding unit 1213 is used to decode the operation instructions in the second read / write message according to the truth table.

[0066] In this embodiment, the priority control unit, scheduling unit, and decoding unit can be used to complete the command transmission in the second read / write information and control the corresponding data path to complete the data transmission.

[0067] In some possible embodiments, such as Figure 5 As shown, the second interface unit 13 is electrically connected to the memory 3 through the third interface unit 4. The third interface unit 4 is used to convert the third read / write information into digital and then send it to the corresponding sub-channel 31.

[0068] In some possible embodiments, such as Figure 5 As shown, each second terminal of the second interface unit 13 is electrically connected to a first terminal of the third interface unit 4, and the first terminals of the third interface unit 4 connected to different second terminals of the second interface unit 13 are different. Each second terminal of the third interface unit 4 is electrically connected to a sub-channel 31, and the sub-channels 31 connected to different second terminals of the third interface unit 4 are different.

[0069] In some possible embodiments, the second interface unit 13 is a DFI interface unit. The third interface unit 4 is a PHY interface unit.

[0070] In some examples, the DFI (DDR PHY Interface) unit, acting as the second interface unit 13, defines a standardized and efficient communication protocol between the memory control circuit 1 and the PHY (Physical Layer) interface unit, enabling efficient and error-free communication between the two to access the memory 3. The PHY interface unit, acting as the third interface unit 4, handles matters related to physical electrical signals. It can convert the third read / write information from digital to analog and send it to the corresponding sub-channel 31. It can also enhance the signal strength of the third read / write information, perform timing control, and perform voltage conversion.

[0071] In some examples, each sub-channel 31 corresponds to a second end of the second interface unit 13 and a first end and a second end of the third interface unit 4, for transmitting the third read / write information corresponding to the sub-channel 31.

[0072] In this embodiment, by adding a third interface unit, the third read / write information can be electrically processed and converted into an electrical signal that the memory can recognize.

[0073] In some possible embodiments, there are two sub-channels 31 and one read / write processing circuit 12.

[0074] In some possible embodiments, each subchannel 31 is a 32-bit subchannel.

[0075] In some examples, memory 3 includes two sub-channels 31, each of which is a 32-bit sub-channel. By using two independent 32-bit sub-channels 31 to communicate with the memory control circuit 1, the data transfer bandwidth of memory 3 is increased. The number of read / write processing circuits 12 is reduced to one, which can decrease the area of ​​the memory control circuit 1 and reduce its power consumption and cost.

[0076] In some possible embodiments, the storage control circuit 1 is used to sequentially send the processed third read / write information to the corresponding sub-channel 31.

[0077] In this embodiment, by sequentially sending multiple third read / write messages, the speed can be matched with the speed of sequentially processing multiple second read / write messages.

[0078] In some exemplary embodiments, such as Figure 4As shown, the storage control circuit 1 includes a first interface unit 11, a priority control unit 1211, a scheduling unit 1212, a decoding unit 1213, a write data path 122, a read data path 123, and a second interface unit 1213. The memory 3 includes two sub-channels 31. The first terminal of the first interface unit 11 is electrically connected to the control unit 2. The first terminals of the priority control unit 1211, the write data path 122, and the read data path 123 are each electrically connected to a different second terminal of the first interface unit 11. The first terminal of the scheduling unit 1212 is electrically connected to the second terminal of the priority control unit 1211, the second terminal of the scheduling unit 1212 is electrically connected to the third terminal of the write data path 122, and the third terminal of the scheduling unit 1212 is electrically connected to the third terminal of the read data path 123. The first terminal of the decoding unit 1213 is electrically connected to the fourth terminal of the scheduling unit 1212. The second terminal of the decoding unit 1213, the second terminal of the write data path 122, and the second terminal of the read data path 123 are each electrically connected to a different first terminal of the second interface unit 13. One second terminal of the second interface unit 13 is used to electrically connect to a sub-channel 31 of the memory 3. The other second terminal of the second interface unit 13 is used to electrically connect to another sub-channel 31 of the memory 3.

[0079] In some exemplary embodiments, a memory control chip is provided, including any of the memory control circuits described in the above embodiments. By employing the memory control circuits described in the above embodiments, the area of ​​the memory control chip can be reduced, and the power consumption and cost of the memory control chip can be lowered.

[0080] In some exemplary embodiments, a system-on-a-chip (SoC) is provided, including the memory control chip described in the above embodiments. By employing the memory control chip described in the above embodiments, the area of ​​the SoC can be reduced, and the power consumption and cost of the SoC can be lowered.

[0081] In some exemplary embodiments, an electronic device is provided, including a storage control chip or a system-on-a-chip (SoC) as described in the above embodiments. The electronic device is, for example, a mobile phone, a laptop computer, a tablet computer, and a wearable device. By employing the storage control chip or SoC described in the above embodiments, the chip area inside the electronic device can be reduced, thereby lowering the power consumption and cost of the electronic device.

[0082] Figure 6 This is a block diagram of an electronic device 600 according to an exemplary embodiment.

[0083] Reference Figure 6The electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0084] Processing component 602 typically controls the overall operation of electronic device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 602 may include one or more processors 620 to execute instructions. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.

[0085] Memory 604 is configured to store various types of data to support the operation of electronic device 600. Examples of such data include instructions for any application or method operating on electronic device 600, contact data, phonebook data, messages, pictures, videos, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0086] Power supply component 606 provides power to various components of electronic device 600. Power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 600.

[0087] Multimedia component 608 includes a screen that provides an output interface between electronic device 600 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When electronic device 600 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0088] Audio component 610 is configured to output and / or input audio signals. For example, audio component 610 includes a microphone (MIC) configured to receive external audio signals when electronic device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.

[0089] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, start buttons, and lock buttons.

[0090] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of electronic device 600. For example, sensor assembly 614 may detect the on / off state of electronic device 600, the relative positioning of components such as the display and keypad of electronic device 600, changes in position of electronic device 600 or a component of electronic device 600, the presence or absence of user contact with electronic device 600, orientation or acceleration / deceleration of electronic device 600, and temperature changes of electronic device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0091] Communication component 616 is configured to facilitate wired or wireless communication between electronic device 600 and other devices. Electronic device 600 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 616 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0092] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0093] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions that can be executed by a processor 620 of an electronic device 600. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0094] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

[0095] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A storage control circuit, characterized in that, The first terminal of the storage control circuit is used to be electrically connected to the control unit, and the second terminal of the storage control circuit is used to be electrically connected to the memory. The storage control circuit is used to process the first read / write information sent by the control unit to obtain a plurality of second read / write information, each of the second read / write information corresponding to a sub-channel in the memory. The storage control circuit is also used to process the plurality of second read / write information sequentially to obtain corresponding third read / write information, and send each of the third read / write information to the corresponding sub-channel.

2. The storage control circuit according to claim 1, characterized in that, The storage control circuit includes: A first interface unit, wherein a first end of the first interface unit is used to be electrically connected to the control unit, and the first interface unit is used to process the first read / write information to obtain a plurality of second read / write information; The read / write processing circuit has each first terminal electrically connected to a second terminal of the first interface unit. The first terminals of the read / write processing circuit are electrically connected to different second terminals of the first interface unit. The read / write processing circuit is used to process multiple second read / write information sequentially to obtain the corresponding third read / write information. The second interface unit has a first terminal that is electrically connected to a second terminal of the read / write processing circuit. The second terminals of the read / write processing circuits connected to different first terminals of the second interface unit are different. Each second terminal of the second interface unit is electrically connected to a sub-channel. The sub-channels connected to different second terminals of the second interface unit are different. The second interface unit is used to send each of the third read / write information to the corresponding sub-channel.

3. The storage control circuit according to claim 2, characterized in that, The first read / write information includes the target address; The first interface unit determines the sub-channel corresponding to each piece of the second read / write information based on the target address, and adds the flag information corresponding to the sub-channel to the second read / write information; The different sub-channels correspond to different flag information.

4. The storage control circuit according to claim 3, characterized in that, The third read / write information includes flag information; the second interface unit identifies the sub-channel corresponding to the third read / write information through the flag information.

5. The storage control circuit according to claim 2, characterized in that, The read / write processing circuit includes: A command processing circuit, wherein a first terminal of the command processing circuit is electrically connected to a second terminal of the first interface unit, and a second terminal of the command processing circuit is electrically connected to a first terminal of the second interface unit; A write data path, wherein a first end of the write data path is electrically connected to a second end of the first interface unit, a second end of the write data path is electrically connected to a first end of the second interface unit, and a third end of the write data path is electrically connected to a third end of the command processing circuit. A read data path, wherein a first end of the read data path is electrically connected to a second end of the first interface unit, a second end of the read data path is electrically connected to a first end of the second interface unit, and a third end of the read data path is electrically connected to a fourth end of the command processing circuit. The first terminal of the command processing circuit, the first terminal of the write data path, and the first terminal of the read data path are electrically connected to different terminals of the first interface unit, and the second terminal of the command processing circuit, the second terminal of the write data path, and the second terminal of the read data path are electrically connected to different terminals of the first interface unit.

6. The storage control circuit according to claim 5, characterized in that, The command processing circuit includes: A priority control unit, wherein a first terminal of the priority control unit is electrically connected to a second terminal of the first interface unit; The scheduling unit has a first terminal electrically connected to the second terminal of the priority control unit, a second terminal electrically connected to the third terminal of the write data path, and a third terminal electrically connected to the third terminal of the read data path. The decoding unit has a first end electrically connected to the fourth end of the scheduling unit, and a second end electrically connected to the first end of the second interface unit.

7. The storage control circuit according to claim 2, characterized in that, The second interface unit is electrically connected to the memory through the third interface unit, which is used to convert the third read / write information into digital and then send it to the corresponding sub-channel.

8. The storage control circuit according to claim 7, characterized in that, Each second terminal of the second interface unit is electrically connected to a first terminal of the third interface unit, and the first terminals of the third interface unit connected to different second terminals of the second interface unit are different. Each second terminal of the third interface unit is electrically connected to one of the sub-channels, and the sub-channels electrically connected to different second terminals of the third interface unit are different.

9. The storage control circuit according to claim 7, characterized in that, The second interface unit is a DFI interface unit, and the third interface unit is a PHY interface unit.

10. The storage control circuit according to claim 2, characterized in that, The number of sub-channels is two, and the number of read / write processing circuits is one.

11. The storage control circuit according to any one of claims 1 to 10, characterized in that, Each of the sub-channels is a 32-bit sub-channel.

12. The storage control circuit according to any one of claims 1 to 10, characterized in that, The storage control circuit is used to sequentially send the processed third read / write information to the corresponding sub-channel.

13. A storage control chip, characterized in that, Includes the storage control circuit as described in any one of claims 1 to 12.

14. A system-on-a-chip, characterized in that, Includes the memory control chip as described in claim 13.

15. An electronic device, characterized in that, This includes the memory control chip as described in claim 13 or the system-on-a-chip as described in claim 14.

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