CPLD (Complex Programmable Logic Device) supporting online upgrading and online upgrading method thereof

Abstract

The invention discloses a CPLD (Complex Programmable Logic Device) supporting online upgrading and an online upgrading method thereof. The CPLD comprises a plurality of multiplexing I / O (Input / Output); the Flash is provided with a storage area used for storing the feature control bits of the multiple multiplexing I / Os; the configuration control system is configured to obtain a feature control bit of the multiplexing I / O after a configuration reset pin of the CPLD is changed from low to high, configure the multiplexing I / O into a configuration mode according to a first control field, and output a configuration completion signal of an invalid level; after the initialization state of the CPLD indicates that the pin is changed from low to high and the configuration of the CPLD is completed, multiplexing the I / O into a user mode according to the second control field configuration, and outputting a configuration completion signal of an effective level; the mode selection module is used for configuring the multiplexing I / O as a slave parallel interface according to the first control field when the configuration completion signal is an invalid level; and when the configuration completion signal is the effective level, configuring the multiplexing I / O as the universal I / O according to the second control field. The problem that in the prior art, the I / O resource utilization rate and the upgrading efficiency are difficult to consider at the same time is solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a CPLD that supports online upgrades and its online upgrade method. Background Technology

[0002] Complex Programmable Logic Devices (CPLDs) rely on embedded Flash memory to operate immediately upon power-on. Their development, production, and maintenance all require reprogramming the Flash memory for functional upgrades. Traditional serial interfaces have limited bandwidth, and upgrade times are lengthy when dealing with large-capacity firmware, making it difficult to meet the demands of rapid delivery and quick field iteration.

[0003] To address the upgrade efficiency issue, existing technologies employ two solutions. One solution involves directly accessing the embedded Flash memory via an external multiplexed I / O interface, supporting white-chip programming during the initialization phase and subsequent online upgrades. The second solution involves accessing the Flash memory via a dedicated parallel bus within the CPLD, combined with user-written interface conversion logic to achieve data transmission.

[0004] However, existing technical solutions have significant limitations. The first solution requires dedicated I / O resources for upgrade operations, and these I / O resources cannot simultaneously serve user logic during online upgrades, resulting in wasted I / O resources. Furthermore, the inherently low bandwidth of serial interfaces limits upgrade speed. The second solution, while improving I / O utilization, requires additional programmable logic resources to implement interface conversion functions, increasing design complexity and resource overhead. These shortcomings make it difficult for existing technologies to achieve a balance between upgrade efficiency, resource utilization, and design complexity. Summary of the Invention

[0005] In view of the above problems, this application provides a CPLD that supports online upgrades and its online upgrade method to solve the above technical problems.

[0006] Firstly, this application provides a CPLD that supports online upgrades, comprising: Multiple multiplexed I / Os are configured as slave interfaces in a preset configuration mode and as general-purpose I / Os in a preset user mode. The Flash memory is provided with a storage area for storing the feature control bits of multiple multiplexed I / Os, wherein the feature control bits of the multiplexed I / Os include a first control field and a second control field. The configuration control system is configured to: after the configuration reset pin of the CPLD changes from an invalid level to an active level, retrieve the characteristic control bits of multiple multiplexed I / Os from the Flash, configure the multiple multiplexed I / Os to the configuration mode according to the first control field, and output an invalid level configuration completion signal; after the initialization status indicator pin of the CPLD changes from an invalid level to an active level and the CPLD configuration is completed, configure the multiple multiplexed I / Os to the user mode according to the second control field, and output an active level configuration completion signal. The mode selection module is used to configure multiple multiplexed I / Os as slave interfaces according to the first control field when the configuration completion signal is invalid, so as to receive the upgrade bit stream file of the CPLD and output it to the Flash to upgrade the CPLD; when the configuration completion signal is valid, it configures multiple multiplexed I / Os as general-purpose I / Os according to the second control field to communicate with the programmable logic resources of the CPLD. The configuration completion signal is used to control the configuration completion pin of the CPLD to indicate whether the CPLD configuration has been successfully completed. The configuration reset pin is used to trigger the CPLD to clear the configuration memory and restart the configuration process in response to a first external input. The initialization status indicator pin is used to indicate the initialization status of the CPLD in response to a second external input, and to delay the configuration of the CPLD in response to a second external input.

[0007] Secondly, this application provides a CPLD online upgrade method, applied to a CPLD supporting online upgrades as described in the first aspect, the CPLD online upgrade method comprising: In response to the initialization state indicator pin being pulled low, a delay configuration is applied. In response to the configuration reset pin being pulled low and released, the characteristic control bits of multiple multiplexed I / Os are retrieved from Flash, and an invalid level configuration completion signal is output. In response to the configuration completion signal at an invalid level, the multiple multiplexed I / Os are configured as slave interfaces according to the first control field to receive the upgrade bitstream file of the CPLD and output it to the Flash to upgrade the CPLD; In response to the released initialization state indicator pin, a configuration completion signal with an active level is output after configuration is completed; In response to the configuration completion signal at an active level, the multiplexed I / Os are configured as general-purpose I / Os according to the second control field to communicate with the programmable logic resources of the CPLD.

[0008] The CPLD and its online upgrade method provided in this application store 2-bit feature control bits of multiplexed I / O in the first control field and the second control field in Flash. The mode selection module works in coordination with the configuration control system of the CPLD to realize the function switching of multiplexed I / O in configuration mode and user mode. In the actual upgrade process of the CPLD in this application, it is only necessary to pull the initialization status indicator pin low to make the CPLD enter delayed configuration; then pull the configuration reset pin low and release it to trigger the CPLD to clear the configuration memory and restart the configuration process. When the CPLD restarts the configuration process, the configuration control system reads the 2-bit characteristic control bits of the multiplexed I / O from the FLASH, configures multiple multiplexed I / Os as slave parallel interfaces in configuration mode according to the first control field, and outputs an invalid level configuration completion signal. After the mode selection module detects the invalid level configuration completion signal, it configures the multiplexed I / O as a slave parallel interface according to the first control field, so that the CPLD's upgrade bitstream file can be transmitted to the FLASH for firmware update through the slave parallel interface. After the upgrade is completed, the initialization status indicator pin is released. When the CPLD completes the configuration process, the configuration control system configures the multiplexed I / O as user mode according to the second control field and outputs an effective level configuration completion signal. The mode selection module then switches the multiplexed I / O to general-purpose I / O, so that it can communicate normally with the CPLD's programmable logic resources, thereby completing the entire online upgrade of the CPLD. The CPLD that supports online upgrades provided in this application solves the technical problem of balancing I / O resource utilization and upgrade efficiency in the prior art. It achieves the goal of maintaining the high-efficiency upgrade capability of the parallel interface without consuming additional logic resources, while also allowing the upgrade-dedicated I / O to be used as general-purpose I / O during normal operation. This significantly improves the efficiency of CPLD online upgrades and the overall utilization of I / O resources.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a CPLD supporting online upgrades provided in an embodiment of this application is shown.

[0012] Figure 2The illustration shows a partial timing diagram of the CPLD supporting online upgrades during startup, as provided in an embodiment of this application.

[0013] Figure 3 The illustration shows a partial timing diagram of the CPLD upgrade that supports online upgrades, as provided in an embodiment of this application.

[0014] Figure 4 This illustration shows another module diagram of a CPLD that supports online upgrades, as provided in an embodiment of this application.

[0015] Figure 5 This illustration shows another module diagram of a CPLD that supports online upgrades, as provided in an embodiment of this application.

[0016] Figure 6 A flowchart of the CPLD online upgrade method provided in an embodiment of this application is shown.

[0017] Figure 7 Another flowchart of the CPLD online upgrade method provided in this application embodiment is shown.

[0018] Figure 8 This paper illustrates another flowchart of the CPLD online upgrade method provided in an embodiment of this application. Detailed Implementation

[0019] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0021] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0022] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0023] This application provides a CPLD that supports online upgrades. Figure 1 The diagram illustrates a module schematic of a CPLD supporting online upgrades provided in an embodiment of this application, as shown below. Figure 1 As shown, the CPLD includes: Multiple multiplexed I / Os are configured as slave interfaces in a preset configuration mode and as general-purpose I / Os in a preset user mode. Optionally, multiplexed I / Os are input / output ports on the CPLD with multiple functions, which can be dynamically configured to different functions according to the needs of the CPLD. In this embodiment, some or all of the multiplexed I / Os of the CPLD can be selected for online upgrade functions according to actual data transmission requirements. The slave interface refers to the parallel bus interface used by the CPLD when it acts as a "slave device". Compared with traditional serial interfaces (such as JTAG, I2C, SPI, etc.), the slave interface can provide higher data transmission efficiency in parallel transmission mode, which is suitable for rapid upgrades of large-capacity firmware. General-purpose I / Os are regular user pins. Under normal operating conditions, the CPLD can communicate with the programmable logic resources of the CPLD through general-purpose I / Os. In this embodiment, the CPLD power-on configuration process is defined as the configuration mode, at which time the CPLD has not yet executed user logic functions; the working state after the CPLD completes initialization and loads configuration data, and enters normal operation of user-defined logic functions, is defined as the user mode.

[0024] The Flash memory includes a storage area for storing feature control bits of multiple multiplexed I / Os. The feature control bits of the multiplexed I / Os include a first control field and a second control field. Optionally, the feature control bits are configuration parameters pre-stored in a specific storage area of ​​the CPLD's embedded Flash memory, used to control the functional state of the multiplexed I / Os in different operating modes. Unlike traditional CPLDs where each multiplexed I / O is controlled by only 1 feature control bit, this embodiment uses 2 feature control bits for each multiplexed I / O, including a first control field and a second control field. The first control field controls the functional state of the multiplexed I / O in configuration mode, and the second control field controls the functional state of the multiplexed I / O in user mode. This 2-bit feature control bit design in this embodiment allows the same group of multiplexed I / Os to perform different functions in different operating stages, thereby improving the utilization rate of I / O resources.

[0025] It is understood that in the embodiments of this application, multiple multiplexed I / Os can share a 2-bit storage area in Flash to store the first control field and the second control field, or each multiplexed I / O can choose to use a 2-bit storage area in Flash to store its corresponding first control field and second control field respectively. The embodiments of this application do not limit the storage method. As a preferred implementation, the embodiments of this application configure multiple multiplexed I / Os to share a 2-bit storage area in Flash to store the first control field and the second control field.

[0026] The configuration control system, i.e., the CPLD's CCS (Configuration Control System), is the embedded logic within the CPLD, responsible for the entire configuration management process after the CPLD is powered on. In this embodiment, the configuration control system is configured to: after the CPLD's configuration reset pin changes from an invalid level to an active level, retrieve the characteristic control bits of multiple multiplexed I / Os from Flash, configure the multiple multiplexed I / Os to configuration mode according to the first control field, and output an invalid level configuration completion signal; after the CPLD's initialization status indicator pin changes from an invalid level to an active level and the CPLD configuration is completed, configure the multiple multiplexed I / Os to user mode according to the second control field, and output a high level configuration completion signal. Optionally, Figure 2 The following is a partial timing diagram of the CPLD supporting online upgrades during startup, as provided in an embodiment of this application. Figure 2As shown, assuming that low level is set as invalid and high level is set as valid, the CPLD power-on configuration process includes three stages: initialization, loading configuration data from Flash, and wake-up. When the configuration reset pin detects a transition from low to high level, it indicates that an external input has triggered the CPLD to restart the configuration process, and the CPLD enters the power-on initialization stage. At this time, the configuration control system knows that the CPLD is in the power-on initialization stage by changing the timing PROGRAM corresponding to the configuration reset pin. Then, it reads 2 bits of feature control bits from Flash and configures the multiplexed I / O to configuration mode according to the value of the first control field. At the same time, it controls the timing DONE corresponding to the configuration completion pin to be low level, indicating that the CPLD has not yet completed the configuration process. That is, at this time, the CPLD outputs a low-level configuration completion signal. When the timing INIT corresponding to the initialization status indicator pin changes, it indicates that the initialization indicator pin changes from low level to high level. Then, after the internal configuration process of the CPLD is completed, the CPLD has completed power-on initialization, loading configuration data in Flash and wake-up. At this time, the configuration control system configures the multiplexed I / O to user mode according to the value of the second control field, and at the same time controls the timing DONE corresponding to the configuration completion pin to be high level, indicating that the CPLD has successfully completed the configuration and entered the normal working state, that is, outputs a high-level configuration completion signal.

[0027] The mode selection module is used to configure multiple multiplexed I / Os as slave-parallel interfaces according to a first control field when the configuration completion signal is invalid, so as to receive the upgrade bitstream file of the CPLD and output it to the Flash to upgrade the CPLD; when the configuration completion signal is valid, it configures multiple multiplexed I / Os as general-purpose I / Os according to a second control field to communicate with the programmable logic resources of the CPLD. Optionally, the mode selection module receives the configuration completion signal and feature control bits output by the configuration control module, and dynamically selects the signal flow direction of the multiplexed I / Os according to the level state of the configuration completion signal and the value of the feature control bits. When the configuration completion signal is invalid, it indicates that the CPLD is in the configuration process. At this time, the mode selection module configures the multiplexed I / Os as slave-parallel interfaces, so that the external upgrade bitstream file can be transmitted to the Flash memory of the CPLD through the slave-parallel interface to realize firmware upgrade. When the configuration completion signal is active, it indicates that the CPLD has successfully completed the configuration and entered user mode. At this time, the mode selection module will multiplex the I / O to connect to the programmable logic resources inside the CPLD, so that these I / O can execute the user-defined logic functions normally and interact with external circuits.

[0028] The configuration completion signal controls the CPLD's configuration completion pin to indicate whether the CPLD configuration has been successfully completed. The configuration reset pin responds to a first external input to trigger the CPLD to clear the configuration memory and restart the configuration process. The initialization status indicator pin responds to the CPLD's initialization status to indicate the CPLD's initialization status and responds to a second external input to delay the CPLD configuration. Optionally, the configuration completion pin is commonly referred to as the DONE pin in industry standards, and some manufacturers also name it the CDONE pin, CONFIG_DONE pin, etc.; the configuration reset pin is commonly referred to as the PROGRAM pin, and some manufacturers also name it the PROG pin, nCONFIG pin, etc.; the initialization status indicator pin is commonly referred to as the INIT pin, and some manufacturers also name it the INIT_B pin or INITN pin. However, the functional definitions of the configuration completion pin, configuration reset pin, and initialization status indicator pin are as described in the embodiments of this application. The first input refers to the active control signal from the external device to the configuration reset pin, which is typically provided by the external device when it needs to trigger CPLD reconfiguration. The second input refers to the active control signal from the external device to the initialization status indicator pin, which is typically provided by the external upgrade device when it needs to delay the CPLD configuration process. The level state of the configuration completion pin is controlled by the configuration completion signal of the configuration control module.

[0029] It is understood that the embodiments of this application only describe the hardware structure directly related to the online upgrade function, namely multiple multiplexed I / O, Flash, configuration control system, and mode selection module, and do not involve other hardware structures within the CPLD that are unrelated to the technical solution of this invention. This is intended to clearly demonstrate the technical features of this application, while avoiding redundant descriptions of conventional CPLD structures known to those skilled in the art and unrelated to the innovative points of this invention. Those skilled in the art should understand that the CPLD also includes other conventional components such as programmable logic arrays, interconnect resources, and clock management units. The specific implementation methods of these components are common knowledge in the art and will not be elaborated here.

[0030] The CPLD provided in this application supports online upgrades. It stores 2-bit characteristic control bits of the multiplexed I / O of the first and second control fields in Flash. The mode selection module works in conjunction with the configuration control system of the CPLD to realize the function switching of the multiplexed I / O between configuration mode and user mode. In the actual upgrade process of the CPLD in this embodiment, it is only necessary to pull the initialization status indicator pin low to make the CPLD enter delayed configuration; then pull the configuration reset pin low and release it to trigger the CPLD to clear the configuration memory and restart the configuration process. When the CPLD restarts the configuration process, the configuration control system reads the 2-bit characteristic control bits of the multiplexed I / O from the FLASH, configures multiple multiplexed I / Os as slave parallel interfaces in configuration mode according to the first control field, and outputs an invalid level configuration completion signal; after the mode selection module detects the invalid level configuration completion signal, it configures the multiplexed I / O as a slave parallel interface according to the first control field, so that the CPLD's upgrade bitstream file can be transmitted to the FLASH for firmware update through the slave parallel interface; after the upgrade is completed, the initialization status indicator pin is released. When the CPLD completes the configuration process, the configuration control system configures the multiplexed I / O as user mode according to the second control field and outputs an effective level configuration completion signal; the mode selection module then switches the multiplexed I / O to general-purpose I / O, so that it can communicate normally with the CPLD's programmable logic resources, thereby completing the entire online upgrade of the CPLD. The CPLD supporting online upgrades provided in this application solves the technical problem of balancing I / O resource utilization and upgrade efficiency in existing technologies. Specifically, in traditional solutions, if external multiplexed I / O is used for upgrades, these I / Os cannot be used by users during normal operation, resulting in wasted I / O resources. If an internal dedicated parallel bus is used for upgrades, additional programmable logic resources are required for interface conversion. The embodiments of this application, however, utilize multiplexed I / O as a slave parallel interface for upgrades in configuration mode and as general-purpose I / O for user use in user mode. This retains the high upgrade efficiency of parallel interfaces while avoiding I / O resource waste. Furthermore, the entire switching process is automatically completed by the configuration control system and mode selection module, requiring no additional logic resource overhead. This significantly improves the efficiency of CPLD online upgrades and the overall utilization of I / O resources, making it particularly suitable for application scenarios requiring frequent firmware updates and where I / O resources are scarce.

[0031] Specifically, Figure 3 The following is a partial timing diagram of the CPLD upgrade supporting online upgrades provided in an embodiment of this application, as shown in the figure. Figure 3 As shown, assuming that low level is set as invalid and high level is set as valid, the CPLD supporting online upgrades provided in this embodiment is configured as follows when used for online upgrades: The CPLD responds to the pulled-down initialization status indicator pin for delayed configuration. Optionally, the initialization status indicator pin has the function of controlling the CPLD delayed configuration according to external input. When performing CPLD online upgrade, the CPLD initialization status indicator pin is pulled low by an external input (i.e., the second input mentioned above). At this time, the timing INIT corresponding to the pin is pulled low, and the CPLD will not enter the configuration data loading Flash when restarting the configuration.

[0032] In response to the configuration reset pin being pulled low and then released, the CPLD retrieves the feature control bits of multiple multiplexed I / O from the Flash and outputs a low-level configuration complete signal. Optionally, the configuration reset pin is pulled low and then released through an external input (i.e., the first input mentioned above), thereby clearing the configuration memory and restarting the CPLD configuration process. At this time, the timing DONE corresponding to this pin goes low first and then high, and then the CPLD initialization stage is entered. The CPLD configuration control module reads 2 bits of feature control bits from the Flash and outputs a low-level configuration complete signal to control the timing DONE corresponding to the configuration complete pin to go low.

[0033] Furthermore, the CPLD's configuration control module also configures multiple multiplexed I / Os into configuration modes based on the characteristic control bits of the first control field.

[0034] In response to a low-level configuration completion signal, the CPLD configures multiple multiplexed I / Os as slave parallel interfaces according to the first control field to receive the CPLD's upgrade bitstream file and output it to the Flash to upgrade the CPLD. Optionally, when the configuration completion signal is low, the CPLD's mode selection module configures multiple multiplexed I / Os as slave parallel interfaces according to the first control field, and then transmits the upgrade bitstream file to the Flash through the slave parallel interface, thereby upgrading the CPLD.

[0035] In response to the released initialization status indicator pin, the CPLD outputs a high-level configuration completion signal after configuration is completed. Optionally, after the CPLD upgrade is completed, the initialization status indicator pin of the CPLD is actively released, and the timing INIT corresponding to this pin is pulled high. Subsequently, the CPLD loads configuration data and wakes up. After the CPLD is woken up, the CPLD configuration control module outputs a high-level configuration completion signal to control the timing DONE corresponding to the configuration completion pin to be pulled low, indicating that the CPLD can be used normally.

[0036] Furthermore, the CPLD's configuration control module also configures multiple multiplexed I / Os as user mode based on the characteristic control bits of the second control field.

[0037] In response to a high-level configuration completion signal, the CPLD configures multiple multiplexed I / Os as general-purpose I / Os according to the second control field to communicate with the CPLD's programmable logic resources. Optionally, the CPLD's mode selection module receives the configuration completion signal and configures multiple multiplexed I / Os as multiplexed I / Os according to the second control field when the configuration completion signal is high.

[0038] In some embodiments, Figure 4 This illustration shows another module diagram of a CPLD supporting online upgrades provided in an embodiment of this application, as shown below. Figure 4 As shown, the mode selection module includes a first selection unit and multiple second selection units. The first selection unit's selection terminal receives a configuration completion signal, its first input terminal and second input terminal receive a first control field and a second control field, respectively, and its output terminal outputs the first control field when the configuration completion signal is invalid and the second control field when the configuration completion signal is valid. Each second selection unit's selection terminal receives either the first or second control field, its input terminal receives an external input signal, its first output terminal outputs the input signal to Flash when the selection terminal receives the first control field, and its second output terminal outputs the input signal to the CPLD's programmable logic resources when the selection terminal receives the second control field. When the input signal is output to Flash, the input signal is the CPLD's upgrade bitstream file.

[0039] It is understood that in the embodiments of this application, the first selection unit and the second selection unit receive the logic signals corresponding to the first control field and the second control field. The first selection unit can be a multiplexer (MUX) or a combinational logic circuit built from basic logic gates that can realize signal selection. The second selection unit can be a demultiplexer (DEMUX) or a circuit module composed of transmission gates and control logic that can realize signal routing. The specific implementation of these circuit modules can be optimized according to the process characteristics and performance requirements of the CPLD, as long as the function of selecting the signal path according to the control signal can be realized. Those skilled in the art can use different circuit structures to achieve the same function according to actual needs, and these variations should all fall within the protection scope of this invention.

[0040] In some embodiments, Figure 5 This illustration shows another module diagram of a CPLD supporting online upgrades provided in an embodiment of this application, such as... Figure 5 As shown, the multiple multiplexed I / Os configured for CPLD upgrades include: The slave interface includes a clock function pin SP_CLK, an enable function pin SP_CS, a read / write control function pin SP_RDWR, a busy status indicator pin SP_BUSY, and a data bus function pin SP_D. Optionally, the clock function pin SP_CLK receives the clock signal from the upgrade bitstream file to control data transmission timing; the enable function pin SP_CS receives the chip select signal from the upgrade bitstream file, allowing the CPLD to access Flash when the chip select signal is valid; the read / write control function pin SP_RDWR indicates whether the current operation is a read or write operation; the busy status indicator pin SP_BUSY provides feedback on the CPLD's internal busy and idle states; and the data bus function pin SP_D is used to transmit the upgrade bitstream file to the CPLD.

[0041] In some embodiments, such as Figure 5 As shown, the number of data bus function pins of the slave-parallel interface corresponds to the bit width of the slave-parallel interface. The bit width of the slave-parallel interface can be configured to 4 bits, 8 bits, or 16 bits according to actual needs, and correspondingly, the number of data bus function pins SP_D is 4, 8, or 16. Different bit width configurations provide a balance between upgrade efficiency and I / O resource consumption. The larger the bit width, the larger the amount of data transmitted per unit time, and the higher the upgrade efficiency, but the more I / O resources are consumed; the smaller the bit width, the less I / O resources are consumed, but the upgrade efficiency is relatively reduced. Users can choose an appropriate bit width configuration according to the upgrade speed requirements and I / O resource constraints of specific application scenarios to achieve the best match between resource utilization and performance requirements.

[0042] In some embodiments, in the CPLD that supports online upgrades provided in this application, the first control field is logic 1 and the second control field is logic 0, or the first control field is logic 0 and the second control field is logic 1.

[0043] In some embodiments, in the CPLD supporting online upgrades provided in this application, the Flash storage area is further used to store the feature control bits of the configuration reset pin, the feature control bits of the initialization status indicator pin, and the feature control bits of the configuration completion pin. Each of these feature control bits includes a third control field and a fourth control field. The third control field and the fourth control field are logic 1 and logic 0 respectively; that is, the third control field is logic 1 and the fourth control field is logic 0, or the third control field is logic 0 and the fourth control field is logic 1.

[0044] The configuration control system is also configured to: after the configuration reset pin of the CPLD changes from an invalid level to an active level, retrieve the characteristic control bits of the configuration reset pin, the initialization status indicator pin, and the configuration completion pin from the Flash, configure the configuration reset pin, the initialization status indicator pin, and the configuration completion pin to configuration mode according to the third control field, so as to indicate that the CPLD is currently in the power-on configuration process; after the initialization status indicator pin of the CPLD changes from an invalid level to an active level and the CPLD configuration is completed, configure the configuration reset pin, the initialization status indicator pin, and the configuration completion pin to user mode according to the fourth control field, so as to indicate that the CPLD has now completed power-on configuration and entered normal working state.

[0045] Based on the configuration control system's mode configuration of the configuration reset pin, initialization status indicator pin, and configuration completion pin, the CPLD supporting online upgrades provided in this application embodiment is further configured as follows during online upgrades: In response to the configuration reset pin being pulled low and released, the CPLD configuration control module obtains the characteristic control bits of the configuration reset pin, the initialization status indicator pin, and the configuration completion pin from the Flash memory, and configures the configuration reset pin, the initialization status indicator pin, and the configuration completion pin to configuration mode according to the third control field.

[0046] In response to a valid configuration completion signal, the CPLD's mode selection module configures multiple multiplexed I / Os as general-purpose I / Os according to the second control field to communicate with the CPLD's programmable logic resources. Then, the CPLD's configuration control module configures the configuration reset pin, initialization status indicator pin, and configuration completion pin as user mode according to the fourth control field.

[0047] In one implementation, the configuration reset pin, configuration completion pin, and initialization status indicator pin are respectively stored in a 2-bit Flash memory area to store their corresponding third and fourth control fields.

[0048] In specific implementation, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0049] For example, for various devices and products applied to or integrated into chips, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into chip modules, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The unit can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, all of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0050] In some embodiments, this application also provides a CPLD online upgrade method, which is applied to the CPLD that supports online upgrades as described in the above embodiments. Figure 6 A flowchart of the CPLD online upgrade method provided in an embodiment of this application is shown, as follows: Figure 6 As shown, the method includes: The initialization status indicator pin is configured with a delay in response to being pulled low. Optionally, the initialization status indicator pin has the function of controlling the CPLD's delayed configuration according to an external input. When performing an online CPLD upgrade, the CPLD's initialization status indicator pin is pulled low by an external input (i.e., the second input mentioned above). At this time, the timing INIT corresponding to this pin is pulled low, and the CPLD will not enter the configuration data loading Flash when restarting the configuration.

[0051] In response to the configuration reset pin being pulled low and then released, the characteristic control bits of multiple multiplexed I / Os are retrieved from Flash, and an invalid level configuration complete signal is output. Optionally, the configuration reset pin is pulled low and then released via an external input, thereby clearing the configuration memory and restarting the CPLD configuration process. In this case, the timing DONE corresponding to this pin goes low first and then high, and then the CPLD initialization phase begins. The CPLD configuration control module reads 2 bits of characteristic control bits from Flash and outputs an invalid level configuration complete signal to control the timing DONE corresponding to the configuration complete pin to go low.

[0052] In response to an invalid configuration completion signal, multiple multiplexed I / Os are configured as slave parallel interfaces according to the first control field to receive the CPLD upgrade bitstream file and output it to Flash to upgrade the CPLD. Optionally, when the configuration completion signal is invalid, the CPLD mode selection module configures multiple multiplexed I / Os as slave parallel interfaces according to the first control field, and then transmits the upgrade bitstream file to Flash through the slave parallel interface to upgrade the CPLD.

[0053] In response to the released initialization status indicator pin, a valid configuration completion signal is output after configuration is complete. Optionally, after the CPLD upgrade is complete, the CPLD's initialization status indicator pin is actively released, and the corresponding timing INIT pin is pulled high. Subsequently, the CPLD loads configuration data and wakes up. After the CPLD wakes up, the CPLD's configuration control module outputs a valid configuration completion signal to control the timing DONE pin corresponding to the configuration completion pin to go low, indicating that the CPLD can be used normally.

[0054] In response to a valid configuration completion signal, multiple multiplexed I / Os are configured as general-purpose I / Os according to a second control field for communication with the programmable logic resources of the CPLD. Optionally, the CPLD's mode selection module receives the configuration completion signal and, when the configuration completion signal is valid, configures the multiple multiplexed I / Os as multiplexed I / Os according to the second control field.

[0055] The CPLD online upgrade method provided in this application solves the technical problem of the difficulty in balancing I / O resource utilization and upgrade efficiency in the prior art. It achieves the goal of maintaining the high-efficiency upgrade capability of the parallel interface without consuming additional logic resources, while also enabling the upgrade-dedicated I / O to be used as general-purpose I / O during normal operation. This significantly improves the efficiency of CPLD online upgrade and the overall utilization of I / O resources.

[0056] In some embodiments, Figure 7 Another flowchart of the CPLD online upgrade method provided in this application embodiment is shown, such as... Figure 7 As shown, the steps of retrieving the characteristic control bits of multiple multiplexed I / Os from Flash and outputting an invalid level configuration completion signal in response to a configuration reset pin that has been pulled low and released also include: The CPLD's configuration control module configures multiple multiplexed I / Os into configuration mode based on the characteristic control bits of the first control field.

[0057] In some embodiments, such as Figure 7 As shown, the step of outputting a configuration completion signal with an active level after configuration is completed in response to the released initialization status indicator pin further includes: The CPLD's configuration control module configures multiple multiplexed I / Os to user mode based on the characteristic control bits of the second control field.

[0058] In some embodiments, Figure 8 This illustration shows another flowchart of the CPLD online upgrade method provided in an embodiment of this application, such as... Figure 8 As shown, the steps of retrieving the characteristic control bits of multiple multiplexed I / Os from Flash and outputting an invalid level configuration completion signal in response to a configuration reset pin that has been pulled low and released also include: In response to the configuration reset pin being pulled low and released, the CPLD configuration control module also obtains the characteristic control bits of the configuration reset pin, the initialization status indicator pin, and the configuration completion pin from the Flash, and configures the configuration reset pin, the initialization status indicator pin, and the configuration completion pin to the configuration mode according to the characteristic control bits of the third control field. Following the step of configuring multiple multiplexed I / Os as general-purpose I / Os for communication with the programmable logic resources of the CPLD according to the second control field in response to a configuration completion signal at an active level, the method further includes: The CPLD configuration control module configures the configuration reset pin, initialization status indicator pin, and configuration completion pin to user mode based on the characteristic control bits of the fourth control field.

[0059] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A CPLD that supports online upgrades, characterized in that, include: Multiple multiplexed I / Os are configured as slave interfaces in a preset configuration mode and as general-purpose I / Os in a preset user mode. The Flash memory is provided with a storage area for storing the feature control bits of multiple multiplexed I / Os, wherein the feature control bits of the multiplexed I / Os include a first control field and a second control field. The configuration control system is configured to: after the configuration reset pin of the CPLD changes from an invalid level to an active level, retrieve the characteristic control bits of multiple multiplexed I / Os from the Flash, configure the multiple multiplexed I / Os to the configuration mode according to the first control field, and output an invalid level configuration completion signal; after the initialization status indicator pin of the CPLD changes from an invalid level to an active level and the CPLD configuration is completed, configure the multiple multiplexed I / Os to the user mode according to the second control field, and output an active level configuration completion signal. The mode selection module is used to configure multiple multiplexed I / Os as slave interfaces according to the first control field when the configuration completion signal is invalid, so as to receive the upgrade bit stream file of the CPLD and output it to the Flash to upgrade the CPLD; When the configuration completion signal is active, the multiple multiplexed I / Os are configured as general-purpose I / Os according to the second control field to communicate with the programmable logic resources of the CPLD; The configuration completion signal is used to control the configuration completion pin of the CPLD to indicate whether the CPLD configuration has been successfully completed. The configuration reset pin is used to trigger the CPLD to clear the configuration memory and restart the configuration process in response to a first external input. The initialization status indicator pin is used to indicate the initialization status of the CPLD in response to a second external input, and to delay the configuration of the CPLD in response to a second external input.

2. The CPLD supporting online upgrades as described in claim 1, characterized in that, The mode selection module includes a first selection unit and multiple second selection units; The selection terminal of the first selection unit is used to receive the configuration completion signal, the first input terminal and the second input terminal are used to receive the first control field and the second control field respectively, and the output terminal is used to output the first control field when the configuration completion signal is invalid and output the second control field when the configuration completion signal is valid. Each second selection unit has a selection terminal for receiving the first control field or the second control field, an input terminal for receiving an input signal from the outside, a first output terminal for outputting the input signal to the Flash when the selection terminal receives the first control field, and a second output terminal for outputting the input signal to the programmable logic resource of the CPLD when the selection terminal receives the second control field. When the input signal is output to the Flash, the input signal is the upgrade bitstream file of the CPLD.

3. The CPLD supporting online upgrades as described in claim 1, characterized in that, The multiple multiplexed I / Os configured for CPLD upgrades include: The clock function pin, enable function pin, read / write control function pin, busy status indication function pin, and data bus function pin of the slave interface.

4. The CPLD supporting online upgrades as described in claim 3, characterized in that, The number of data bus function pins of the slave interface corresponds to the bit width of the slave interface.

5. The CPLD supporting online upgrades as described in claim 1, characterized in that, The first control field is logic 1 and the second control field is logic 0, or the first control field is logic 0 and the second control field is logic 1.

6. The CPLD supporting online upgrades as described in claim 1, characterized in that, The Flash storage area is also used to store the feature control bits of the configuration reset pin, the feature control bits of the initialization status indicator pin, and the feature control bits of the configuration completion pin. The feature control bits of the configuration reset pin, the initialization status indicator pin, and the configuration completion pin all include a third control field and a fourth control field. The configuration control system is further configured to: after the configuration reset pin of the CPLD changes from an invalid level to an active level, obtain the characteristic control bit of the configuration reset pin, the characteristic control bit of the initialization status indicator pin, and the characteristic control bit of the configuration completion pin from the Flash, and configure the configuration reset pin, the initialization status indicator pin, and the configuration completion pin as configuration mode according to the third control field; and configure the configuration reset pin, the initialization status indicator pin, and the configuration completion pin as user mode according to the fourth control field after the initialization status indicator pin of the CPLD changes from an invalid level to an active level and the CPLD configuration is completed.

7. A method for online upgrading of a CPLD, characterized in that, Applied to a CPLD supporting online upgrades as described in any one of claims 1 to 6, the CPLD online upgrade method includes: In response to the initialization state indicator pin being pulled low, a delay configuration is applied. In response to the configuration reset pin being pulled low and released, the characteristic control bits of multiple multiplexed I / Os are retrieved from Flash, and an invalid level configuration completion signal is output. In response to the configuration completion signal at an invalid level, the multiple multiplexed I / Os are configured as slave interfaces according to the first control field to receive the upgrade bitstream file of the CPLD and output it to the Flash to upgrade the CPLD; In response to the released initialization state indicator pin, a configuration completion signal with an active level is output after configuration is completed; In response to the configuration completion signal at an active level, the multiplexed I / Os are configured as general-purpose I / Os according to the second control field to communicate with the programmable logic resources of the CPLD.

8. The CPLD online upgrade method as described in claim 7, characterized in that, The steps of retrieving the characteristic control bits of multiple multiplexed I / Os from Flash and outputting an invalid level configuration completion signal in response to a configuration reset pin that has been pulled low and released further include: Configure multiple multiplexed I / Os into a configuration mode according to the characteristic control bits of the first control field.

9. The CPLD online upgrade method as described in claim 7, characterized in that, The step of outputting a configuration completion signal with an active level after configuration is completed in response to the released initialization state indicator pin further includes: Configure multiple multiplexed I / Os as user mode according to the feature control bits of the second control field.

10. The CPLD online upgrade method as described in claim 7, characterized in that, The steps of retrieving the characteristic control bits of multiple multiplexed I / Os from Flash and outputting an invalid level configuration completion signal in response to a configuration reset pin that has been pulled low and released further include: Obtain the feature control bits of the configuration reset pin, the initialization status indicator pin, and the configuration completion pin from the Flash memory, and configure the configuration reset pin, the initialization status indicator pin, and the configuration completion pin to configuration mode according to the feature control bits of the third control field; Following the step of configuring the multiple multiplexed I / Os as general-purpose I / Os for communication with the programmable logic resources of the CPLD according to the second control field in response to the configuration completion signal at an active level, the method further includes: Configure the configuration reset pin, the initialization status indicator pin, and the configuration completion pin to user mode according to the feature control bits of the fourth control field.

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