PUF (Physical Unclonable Function) circuit based on memristor cellular automaton and use method thereof

Abstract

The invention discloses a PUF (Physical Unclonable Function) circuit based on a memristor cellular automaton and a use method thereof, and belongs to the technical field of integrated circuit design and information security, the circuit comprises a first cellular initialization module, a second cellular initialization module, 2N cellular node modules, 2N-bit excitation signal input terminals, 2N-bit response signal output terminals, and power supply terminals VCC, VDD, VEE and GND, the 2N cellular node modules are connected end to end to form an annular array, N is an integer which is a positive integer multiple of 4, and each cellular node module comprises a Rule30 logic module and a cellular module, so that the problems of high hardware overhead, poor expandability and insufficient attack resistance of a traditional PUF (Physical Unclonable Function) are effectively solved; the circuit structure is simplified; the hardware resource consumption is reduced; and the flexible expansion of response bits is supported.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and information security technology, and in particular to a PUF circuit based on memristor cellular automata and its usage method. Background Technology

[0002] PUF (Programmable Array) circuits are a type of circuit technology that enables secure authentication and key generation based on the physical characteristics of a chip. They utilize microscopic random differences in the semiconductor manufacturing process, such as changes in the threshold voltage of transistors and line delays, to generate unique digital fingerprints. These fingerprints are fixed after chip manufacturing and are virtually impossible to copy or predict. When a PUF circuit is specifically stimulated, it generates a unique response based on its internal physical structure. This response can serve as a device identifier or be used for key extraction. It is widely used in IoT devices, smart cards, and other fields, providing a reliable solution for security needs such as device authentication and data encryption.

[0003] In existing technologies, traditional PUF circuits generally suffer from the problem of separating the entropy source extraction module and the chaos confusion module, resulting in redundant hardware structure, large resource overhead, and the cell array is mostly of fixed size, making it difficult to increase the number of response bits by expanding the number of cells, resulting in poor scalability. At the same time, the nonlinear correlation between excitation and response is weak, making it vulnerable to machine learning modeling attacks, which seriously affects the security of PUF. Summary of the Invention

[0004] The purpose of this invention is to provide a PUF circuit based on memristor cellular automata and its usage method, so as to solve the technical problems of insufficient reliability, poor security, high hardware cost, weak nonlinear correlation between excitation and response, and susceptibility to machine learning modeling attacks in the traditional PUF circuit in the prior art.

[0005] This invention provides a PUF circuit based on memristor cellular automata, the circuit including a first cell initialization module, a second cell initialization module, 2N cell node modules, and an input terminal U. RESET U MEM_assign U Reverse_Control U Rule30_enable U MEM_Init U IN_enable U OUT_enable U D_FF_CLK U D_FF_RESETThe 2N-bit excitation signal input terminals Challenge[2N-1:0], 2N-bit response signal output terminals Response[2N-1:0], and power supply terminals VCC, VDD, VEE, and GND are connected end-to-end to form a ring array, where N is an integer multiple of 4. Each cell node module includes a Rule30 logic module and a cell module. The Rule30 logic module includes input terminals Reverse_Control, Cell_A_State, Cell_B_State, Cell_C_State, and Rule30_e. The cell module includes input terminals RESET, Reverse, MEM_assign, MEM_Select, MEM_L, and output terminals STATE and MEM_R. Both the first and second cell initialization modules include input terminals Bit[2N-1:0], IN_enable, OUT_enable, D_FF_CLK, D_FF_RESET, RESET, and output terminals Output[N-1:0]. The circuit structures of the first and second cell initialization modules are identical. RESET The terminal is connected to the RESET terminals of the 2N cell modules, the RESET terminals of the first cell initialization module and the second cell initialization module, respectively, and the U MEM_assign The terminal is connected to the MEM_assign terminal of each of the 2N cell modules, and the U Reverse_Control The terminal is connected to the Reverse_Control terminal of each of the 2N Rule30 logic modules, and the U Rule30_enable The terminal is connected to the Rule30_enable terminal of each of the 2N Rule30 logic modules, and the U MEM_Init The terminal is connected to the MEM_L terminal of the first to Nth cell modules respectively, and the U IN_enable The terminal is connected to the IN_enable terminal of the first cell initialization module and the second cell initialization module respectively, and the U OUT_enable The terminal is connected to the OUT_enable terminal of the first cell initialization module and the second cell initialization module respectively, and the U D_FF_CLK The terminal is connected to the D_FF_CLK terminal of the first cell initialization module and the second cell initialization module respectively, and the U D_FF_RESETThe terminals are connected to the D_FF_RESET terminals of the first and second cell initialization modules, respectively. The terminals Bit(8i), Bit(8i+1), Bit(8i+4), and Bit(8i+6) of the first cell initialization module are connected to the VCC terminal, and the terminals Bit(8i+2), Bit(8i+3), Bit(8i+5), and Bit(8i+7) of the first cell initialization module are connected to the GND terminal, respectively. Here, i is an integer from 0 to N / 4-1. The 2N-bit excitation signal input terminals Challenge[2N-1:0] are connected to the Bit[2N-1:0] terminals of the second cell initialization module, respectively. Corresponding connections are made: the STATE terminals of the 1st to 2Nth cell modules are respectively connected to the Response[2N-1:0] terminals of the 2Nth response signal output terminals; the Reverse terminals of the cell modules in the cell node modules are connected to the Reverse terminals of the Rule30 logic module; the MEM_Select terminals of the 1st to Nth cell modules are respectively connected to the Output[N-1:0] terminals of the first cell initialization module; and the MEM_Select terminals of the N+1th to 2Nth cell modules are respectively connected to the Output[N-1:0] terminals of the second cell initialization module. The MEM_R terminals of the first to the Nth cell module, and the MEM_L terminals of the (N+1)th to the 2Nth cell modules are all connected together. The MEM_R terminals of the (N+1)th to the 2Nth cell modules are respectively connected to the GND terminal. The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the yth cell node module are respectively connected to the STATE terminals of the (y-1)th, yth, and (y+1)th cell node modules, where y is an integer from 2 to 2N-1. The first cell node... The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the point module are respectively connected to the STATE terminals of the cell modules in the 2Nth, the first, and the second cell node modules. The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the 2Nth cell node module are respectively connected to the STATE terminals of the 2N-1th, the 2Nth, and the first cell node modules.In existing technologies, traditional PUF circuits generally suffer from the problem of separating the entropy source extraction module and the chaotic confusion module, resulting in redundant hardware structure, high resource overhead, and fixed-size cellular arrays, making it difficult to increase the response bit depth by expanding the number of cells, leading to poor scalability. Furthermore, the nonlinear correlation between excitation and response is weak, making it vulnerable to machine learning modeling attacks, severely impacting the security of the PUF. To address these issues, this invention adopts a ring array memristor cellular automaton integrated architecture. 2N cellular node modules are connected end-to-end to form a ring cellular space. Each cellular node module integrates a Rule30 logic module and a cellular module, achieving integrated chaotic evolution and state storage. The first cell initialization module selects the 1st to Nth cellular modules sequentially using a fixed bit terminal level combination. The second cell initialization module receives 2... The N-bit excitation signal selects the N+1 to 2Nth cell modules. The two modules work together to complete the initial resistive state configuration of the memristor. The Rule30 logic module obtains the STATE terminal state of the adjacent cell modules and generates a Reverse signal by combining it with the control signal to drive the state evolution of the cell modules. The STATE terminal is directly used as the response signal output without the need for an additional conversion module. The 2N-bit excitation signal is connected one-to-one with the Bit terminal of the second cell initialization module. The MEM_Select terminal of the cell module is connected one-to-one with the Output terminal of the initialization module to ensure the accuracy of signal transmission. This effectively solves the problems of high hardware overhead, poor scalability, and insufficient anti-attack capability of traditional PUF, and simplifies the circuit structure, reduces hardware resource consumption, and supports flexible expansion of the response bit width.

[0006] Furthermore, the cell module includes a first single-pole single-throw (SPS) to a fourth SPS, a first single-pole double-throw (SPS) CNC switch, a second single-pole double-throw (SPS) CNC switch, a first resistor, a second resistor, a threshold voltage type memristor, a current mirror, a first NOT gate, an SR latch, input terminals RESET, Reverse, MEM_assign, MEM_Select, MEM_L, output terminals MEM_R and STATE, wherein the STATE terminal serves as the cell state output terminal. The RESET input terminal of the cell module is connected to the "+" terminal of the third SPS, and the Reverse input terminal of the cell module is connected to the EN terminal of the SR latch. The input terminal MEM_assign is connected to the "+" terminal of the fourth single-pole single-throw CNC switch; the input terminal MEM_Select is connected to the "+" terminals of the first single-pole double-throw CNC switch and the second single-pole double-throw CNC switch, respectively; the input terminal MEM_L is connected to the S1 terminal of the first single-pole double-throw CNC switch; the output terminal MEM_R is connected to the S1 terminal of the second single-pole double-throw CNC switch; the output terminal STATE is connected to the output terminal of the first NOT gate and the R terminal of the SR latch, respectively; the "+" terminal of the first single-pole single-throw CNC switch is connected to the VCC terminal; and the "-" terminal of the first single-pole single-throw CNC switch is connected to the SR latch.

[0007] ˉ

[0008] The Q terminal of the latch is connected. The S1 terminal of the first single-pole single-throw CNC switch is connected to the VCC terminal. The S2 terminal of the first single-pole single-throw CNC switch is connected to the S2 terminal of the second single-pole single-throw CNC switch and the S1 terminal of the fourth single-pole single-throw CNC switch, respectively. The "+" terminal of the second single-pole single-throw CNC switch is connected to the VCC terminal. The "-" terminal of the second single-pole single-throw CNC switch is connected to the Q terminal of the SR latch. The S1 terminal of the second single-pole single-throw CNC switch is connected to the VEE terminal. The "-" terminal of the fourth single-pole single-throw CNC switch is connected to the GND terminal. The S2 terminal of the fourth single-pole single-throw CNC switch is connected to the S2 terminal of the first single-pole double-throw CNC switch. One end of the first resistor is connected to the VDD terminal, and the other end of the first resistor is connected to the S2 terminal of the first single-pole double-throw CNC switch. The "-" terminal of the third single-pole single-throw CNC switch is connected to... The terminal GND is connected. The S1 terminal of the third single-pole single-throw CNC switch is connected to the terminal VEE. The S2 terminal of the third single-pole single-throw CNC switch is connected to the S2 terminal of the first single-pole double-throw CNC switch. The "-" terminals of the first single-pole double-throw CNC switch and the second single-pole double-throw CNC switch are respectively connected to the terminal GND. One end of the threshold voltage type memristor is connected to the S3 terminal of the first single-pole double-throw CNC switch. The other end of the threshold voltage type memristor is connected to the S3 terminal of the second single-pole double-throw CNC switch. The S2 terminal of the second single-pole double-throw CNC switch is connected to one end of the current mirror. The other end of the current mirror is connected to one end of the second resistor, the input terminal of the first NOT gate, and the S terminal of the SR latch respectively. The other end of the second resistor is connected to the terminal VCC. The output terminal of the first NOT gate is connected to the R terminal of the SR latch.In existing technologies, traditional cellular modules typically design state storage and next-state control as independent units, resulting in large signal delays and poor state synchronization when they work together. Furthermore, the ambiguous resistance switching and state output logic of the memristor affects the response speed and reliability of the PUF. To address these issues, this invention employs a memristor-SR latch collaborative control cellular module technology. A threshold voltage type memristor serves as the core state storage component, connected to the circuit via first and second single-pole double-throw digital switches. The MEM_Select signal controls the switch's on / off state, enabling the selection and connection of the memristor. The SR latch stores the cell's next-moment state, and the Reverse signal acts as the latch's enable signal, controlling the Q-terminal state to flip. A Reverse value of 1 flips the state, while a value of 0 keeps it unchanged. The IGN signal drives the fourth single-pole single-throw digital switch to synchronize the Q-terminal state of the SR latch to the memristor, completing the resistance state update. The first NOT gate converts the resistance state of the memristor into the STATE terminal output signal, where the high resistance state of the memristor corresponds to the STATE terminal output "0", and the low resistance state corresponds to the output "1". The RESET signal resets the memristor to the high resistance state through the third single-pole single-throw digital switch, ensuring the consistency of the initial state. The current mirror and the second resistor constitute a signal detection circuit, accurately feeding back the resistance state of the memristor and providing a trigger signal for the SR latch. This achieves the technical effect of solving the problems of poor synchronization and response delay caused by the separation of state storage and control in traditional cell modules, integrating cell state storage and next state control, improving state switching speed and synchronization accuracy, and ensuring the stability of STATE terminal output.

[0009] Furthermore, the Rule30 logic module includes a second NOT gate to a fourth NOT gate, a first AND gate to a third AND gate, a first OR gate to a third OR gate, input terminals Cell_A_State, Cell_B_State, Cell_C_State, Rule30_enable, Reverse_Control, and an output terminal Reverse. The input terminal Cell_A_State is connected to the input of the second NOT gate and the A input of the second AND gate, respectively. The input terminal Cell_B_State is connected to the input of the third NOT gate and the A input of the first OR gate, respectively. The input terminal Cell_C_State is connected to the input of the fourth NOT gate and the C input of the first AND gate, respectively. The input terminal Rule30_enable... The output of the second NOT gate is connected to the B input of the third AND gate, the input terminal Reverse_Control is connected to the B input of the third OR gate, the output of the second NOT gate is connected to the A input of the first AND gate, the output of the third NOT gate is connected to the B input of the first AND gate, the output of the fourth NOT gate is connected to the B input of the first OR gate, the output of the first AND gate is connected to the A input of the second OR gate, the output of the first OR gate is connected to the B input of the second AND gate, the output of the second AND gate is connected to the B input of the second OR gate, the output of the second OR gate is connected to the A input of the third AND gate, the output of the third AND gate is connected to the A input of the third OR gate, and the output of the third OR gate is connected to the Reverse output terminal of the Rule30 logic module.In existing technologies, the implementation of chaotic confusion modules either relies on analog circuits, which are susceptible to temperature and voltage fluctuations and have unstable chaotic characteristics, or on complex digital circuits, such as floating-point arithmetic iterations, which have high hardware overhead and poor real-time performance, resulting in weak anti-interference capabilities and high hardware implementation difficulty for the PUF. To address these issues, this invention adopts a digitally integrated Rule30 chaotic logic module technology. This module integrates NOT gates, AND gates, and OR gates to implement the Rule30 evolution rules, eliminating the need for analog devices or complex arithmetic units. The Cell_A_State, Cell_B_State, and Cell_C_State terminals respectively receive the STATE signals from the left neighbor, current cell, and right neighbor cell modules. After being inverted by the second to fourth NOT gates, these signals are input to the first AND gate, the first OR gate, and the second AND gate, respectively, for logical operations. The Rule30_enable signal controls the third AND gate to conduct, ensuring that chaotic evolution only occurs at the specified stage. The Reverse_Control signal acts as the control terminal of the third OR gate. When Reverse_Control is "1", the Reverse terminal directly outputs "1", forcing the cell state to flip. When Reverse_Control is "0", the signal is output according to Rule30. That is, when Cell_A_State, Cell_B_State, and Cell_C_State are "111", "110", "101", or "000", Reverse outputs "1", otherwise it outputs "0". This logic module is directly integrated into the cell node module and works in conjunction with the cell module. The generated Reverse signal accurately controls the SR latch state, thus solving the problem of high hardware overhead in traditional chaos modules. It simplifies the chaos implementation architecture, improves the real-time performance of chaos characteristics, enhances the nonlinear correlation of stimulus-response, and improves the PUF's resistance to machine learning attacks.

[0010] Furthermore, the cell initialization module includes the first to the N / 4th selection units, 2N-bit input terminals Bit[2N-1:0], input terminals IN_enable, D_FF_CLK, OUT_enable, D_FF_RESET, RESET, and N-bit output terminals Output[N-1:0]. Each selection unit includes 8-bit input terminals Bit[7:0], input terminals IN_enable, D_FF_CLK, OUT_enable, EN_enable, D_FF_RESET, RESET, 4-bit output terminals Output[3:0] and NEXT_enable. The input terminals Bit[j×8-1:(j-1)×8] of the cell initialization module are respectively connected to the input terminals Bit[7:0] of the j-th selection unit, where j is an integer from 1 to N / 4. The input terminal IN_enable of the cell initialization module is respectively connected to the input terminals IN_enable of the N / 4 selection units. The input terminals D_FF_CLK, D_FF_RESET, and RESET of the cell initialization module are also connected to the N / 4 selection units. CLK is connected to the input terminals D_FF_CLK of N / 4 of the selection units respectively. The input terminal OUT_enable of the cell initialization module is connected to the input terminals OUT_enable of N / 4 of the selection units respectively. The input terminal D_FF_RESET of the cell initialization module is connected to the input terminals D_FF_RESET of N / 4 of the selection units respectively. The input terminal RESET of the cell initialization module is connected to the input terminals RESET of N / 4 of the selection units respectively. The output terminal Output[j×4-1:(j-1)×4] of the cell initialization module is connected to the output terminal Output[3:0] of the j-th selection unit respectively, where j is an integer from 1 to N / 4. The EN_enable terminal of the first selection unit is connected to the terminal VCC. The EN_enable terminal of the k-th selection unit is connected to the NEXT_enable terminal of the (k-1)-th selection unit, where k is an integer from 2 to N / 4. The NEXT_enable terminal of the N / 4-th selection unit is floating.In existing technologies, PUF cell selection initialization modules mostly use single control logic, which cannot flexibly adjust the selection object according to the excitation signal. Furthermore, control signal conflicts easily occur when multiple units are cascaded, resulting in low selection accuracy, poor initialization efficiency, and difficulty in adapting to large-scale cell arrays. To address these issues, this invention adopts a hierarchical cascaded cell selection initialization module technology. The cell initialization module consists of N / 4 selection units cascaded hierarchically. Each selection unit processes 8 bits of signal and outputs 4 bits of output signal. N bits of output signal are achieved through multi-unit cascading. The first and second cell initialization modules adapt to the selection requirements of 2N cell modules. The bit terminals of the first cell initialization module are connected to VCC or GND according to a fixed rule: Bit[8i], Bit[8i+1], Bit[8i+4], and Bit[8i+6] are connected to VCC, and the rest are connected to GND. No further information is needed. External excitation automatically selects the first to Nth cell modules according to the D_FF_CLK timing sequence. The bit terminals of the second cell initialization module are connected one-to-one with the 2N-bit excitation signals. Based on different combinations of excitation signals, the N+1 to 2Nth cell modules are selected. The selection unit is cascaded through the EN_enable and NEXT_enable terminals. The EN_enable of the first selection unit is connected to VCC for priority start. Subsequent selection units are started sequentially by receiving the NEXT_enable signal of the previous unit, realizing hierarchical timing control and avoiding signal conflicts. The IN_enable and OUT_enable signals control the input enable and output enable of the selection unit, respectively. The D_FF_RESET signal realizes the trigger reset, ensuring the reliability of initialization. This achieves the technical effects of precise cell selection, controllable initialization timing, support for large-scale cell array expansion, and adaptation to different excitation signals.

[0011] Furthermore, the selection unit includes the fourth to sixteenth AND gates, the fifth to ninth NOT gates, the fourth OR gate, the first to ninth D flip-flops, a 2-to-4 decoder, a 2-bit counter, 8-bit input terminals Bit[7:0], input terminals IN_enable, D_FF_CLK, OUT_enable, EN_enable, D_FF_RESET, RESET, 4-bit output terminals Output[3:0], and output terminal NEXT_enable; the 8-bit input terminals Bit[7:0] of the selection unit are respectively connected to the A input terminals of the fourth to eleventh AND gates, the IN_enable input terminal of the selection unit is respectively connected to the B input terminals of the fourth to eleventh AND gates, and the output terminals of the fourth to eleventh AND gates are respectively connected to the SET terminals of the first to eighth D flip-flops. The input terminal D_FF_CLK of the selection unit is connected to the CLK terminals of the first to eighth D flip-flops and the CLK terminal of the 2-bit counter, respectively. The Q terminal of the first D flip-flop is connected to the D terminal of the second D flip-flop. The Q terminal of the second D flip-flop is connected to the D terminal of the third D flip-flop. The Q terminal of the third D flip-flop is connected to the D terminal of the fourth D flip-flop. The Q terminal of the fourth D flip-flop is connected to the D terminal of the first D flip-flop and the IA terminal of the 2-to-4 decoder, respectively. The Q terminal of the fifth D flip-flop is connected to the D terminal of the sixth D flip-flop. The Q terminal of the sixth D flip-flop is connected to the D terminal of the seventh D flip-flop. The Q terminal of the seventh D flip-flop is connected to the D terminal of the eighth D flip-flop. The Q terminal of the eighth D flip-flop is connected to the D terminal of the fifth D flip-flop and the IB terminal of the 2-to-4 decoder, respectively.

[0012] ˉ

[0013] The Q terminal of the ninth D flip-flop is connected to the A input terminal of the twelfth AND gate. The EN_enable input terminal of the selection unit is connected to the B input terminal of the twelfth AND gate. The output terminal of the twelfth AND gate is connected to the EN terminal of the 2-bit counter. The CO terminal of the 2-bit counter is connected to the A input terminal of the fourth OR gate. The D_FF_RESET input terminal of the selection unit is connected to the B input terminal of the fourth OR gate. The output terminal of the fourth OR gate is connected to the CLK terminal of the ninth D flip-flop. The RESET input terminal of the selection unit is connected to the RESET terminal of the ninth D flip-flop and the input terminal of the ninth NOT gate, respectively. The output terminal of the ninth NOT gate is connected to the SET terminal of the ninth D flip-flop. The Q terminal of the ninth D flip-flop is connected to the 2-to-4 decoder. The input terminals of the 2-4 decoder and the output terminal NEXT_enable are respectively connected. The input terminals of the 1Y0, 1Y1, 1Y2, and 1Y3 of the 2-4 decoder are respectively connected to the input terminals of the fifth to eighth NOT gates. The output terminals of the fifth to eighth NOT gates are respectively connected to the B input terminals of the thirteenth to sixteenth AND gates. The input terminal OUT_enable of the selection unit is respectively connected to the A input terminals of the thirteenth to sixteenth AND gates. The output terminals of the thirteenth to sixteenth AND gates are respectively connected to the output terminals Output[3:0] of the selection unit. In existing technologies, selection units often employ simple combinational logic or single flip-flop control, resulting in inaccurate selection timing, susceptibility to noise interference in the output signal, and inability to coordinate with cascaded units. This leads to a high cell selection error rate, affecting the initialization reliability of the PUF. To address these issues, this invention employs a flip-flop-decoder collaborative precision selection unit technology. The selection unit is based on an 8-bit D flip-flop, a 2-to-4 decoder, and a 2-bit counter. The 8-bit signal is enabled by the IN_enable gate through the fourth to eleventh AND gates, triggering the first to eighth D flip-flops to form two sets of 4-bit ring shift registers. The outputs of these registers serve as the IA and IB input signals of the 2-to-4 decoder. The EN_enable signal and the Q input of the ninth D flip-flop are connected through the twelfth AND gate. The 2-bit counter is started. The carry signal CO of the counter and the D_FF_RESET signal are ORed through the fourth gate to trigger the ninth D flip-flop, generating the enable signal of the 2-to-4 decoder and the cascading control signal NEXT_enable. The 2-to-4 decoder converts the 4-bit input signal into 4-way strobe signals. After being inverted by the fifth to eighth NOT gates, the signals are ANDed with the OUT_enable signal through the thirteenth to sixteenth AND gates to output a 4-bit Output signal, realizing cell selection control. The RESET signal triggers the ninth D flip-flop through the ninth NOT gate to ensure that the initial state of the cells is consistent. Through the coordinated work of the flip-flop group, decoder, and counter, the selection timing is precisely controlled, the cell selection is accurate, the output signal is stabilized, and hierarchical cascading is supported.

[0014] Furthermore, the voltage at terminal VCC is 5V, the voltage at terminal VDD is 2V, the voltage at terminal VEE is -5V, and terminal GND serves as the power supply reference ground. Based on the forward / reverse threshold voltage characteristics of a threshold voltage type memristor, typically 1.5V to 2.5V forward and -3V to -6V reverse, VCC is configured to be 5V, VDD to be 2V, and VEE to be -5V. The absolute values ​​of VCC and VEE are both greater than the absolute value of the memristor's threshold voltage, ensuring stable switching between low and high impedance states. VDD provides the operating voltage for digital logic modules, such as Rule30 logic modules and flip-flops, ensuring stable digital signal transmission. GND serves as the reference ground, providing a potential reference for the entire circuit. This achieves the technical effect of solving the problem of unstable state switching caused by the mismatch between traditional power supply configurations and memristor characteristics, ensuring the reliability of memristor impedance state switching, improving the operational stability of digital modules, and ensuring consistent PUF response.

[0015] A method for using a PUF circuit based on a memristor cellular automaton, the method comprising the following steps:

[0016] Sp1: Reset phase; supplying terminal U RESET U D_FF_RESET Apply a high-level signal to terminal U MEM_assign U Reverse_Control U Rule30_enable U MEM_Init U IN_enable U OUT_enable U D_FF_CLK A low-level signal is applied to the Challenge[2N-1:0] terminal of the 2N-bit excitation signal input. The threshold voltage type memristors in the 2N cell modules are all reset to the high-impedance state. The Output[N-1:0] terminals of the first cell initialization module and the second cell initialization module both output a low level.

[0017] Sp2: Initialization phase;

[0018] Sp2-1: Supply terminal U RESET U D_FF_RESET Apply a low-level signal to terminal U OUT_enable Apply a high-level signal to terminal U D_FF_CLK A square wave signal V with a frequency of 1kHz, a duty cycle of 50%, and a duration of N cycles is applied. CLK V CLK The first half of the cycle is high level and the second half of the cycle is low level, which is given to terminal U. MEM_Init A sinusoidal signal V with an amplitude of 5V and a frequency of 1kHz, lasting for N cycles, is applied. INITApply a 2N-bit excitation signal to the 2N-bit excitation signal input terminals Challenge[2N-1:0], and in V CLK During the first cycle, give terminal U IN_enable Apply a high-level signal at V CLK After the first cycle ends, give terminal U IN_enable A low-level signal is continuously applied;

[0019] Sp2-2: In V CLK Within each cycle, the first cell initialization module initializes according to V CLK The number of cycles that have been sustained is selected from the 1st to the Nth cell module, and the second cell initialization module is based on the 2N-bit excitation signal and V. CLK The number of cycles that have been sustained is selected from the (N+1)th to 2Nth cell modules, choosing one cell module and then using V. INIT The signal sets the threshold voltage memristor with the higher reverse threshold voltage in the two selected cell modules to a high-resistance state, and the threshold voltage memristor with the lower reverse threshold voltage to a low-resistance state.

[0020] Sp2-3: V CLK After N cycles, a portion of the 2N threshold voltage type memristors in the 2N cell modules are set to a low resistance state, while the other threshold voltage type memristors remain in a high resistance state. When the resistance of the 2N threshold voltage type memristors in the 2N cell modules is in a high resistance state, the STATE terminal of the corresponding cell module outputs a high level. When the resistance of the 2N threshold voltage type memristors in the 2N cell modules is in a low resistance state, the STATE terminal of the corresponding cell module outputs a low level.

[0021] Sp2-4: In V CLK After the Nth cycle ends, input terminal U is given Reverse_Control U OUT_enable When high and low level signals are applied respectively, all 2N cell modules update the Q output signal of their SR latch according to the resistance state of their threshold voltage type memristor. When the resistance state of the threshold voltage type memristor is high, the Q output of the SR latch is high; otherwise, the Q output of the SR latch is low.

[0022] Sp3: Cell module evolution stage;

[0023] Sp3-1: Supply terminal U Reverse_Control Apply a low-level signal to terminal U Rule30_enable A square wave signal V with a frequency of 1kHz and a duty cycle of 50% is applied. Rule30_enable In V Rule30_enable In one cycle of the signal, the first half of the cycle is high level and the second half of the cycle is low level, simultaneously supplying terminal U. MEM_assignA square wave signal V with a frequency of 1kHz and a duty cycle of 50% is applied. MEM_assign In V MEM_assign In one cycle of the signal, the first half of the cycle is low level and the second half of the cycle is high level;

[0024] Sp3-2: In V Rule30_enable and V MEM_assign In the first half of a signal cycle, 2N Rule30 logic modules update the signals of their output terminals Reverse according to the signals of their input terminals Cell_A_State, Cell_B_State, and Cell_C_State. 2N cell modules update the Q output signal of their SR latches according to the signals of their input terminals Reverse. If the signal of the terminal Reverse is high, the Q state of the SR latch flips; otherwise, the Q state of the SR latch remains unchanged.

[0025] Sp3-3: In V Rule30_enable and V MEM_assign In the latter half of a signal cycle, if the Q output of the SR latch in the cell module is low, the threshold voltage type memristor in the cell module is updated to a high impedance state, and the STATE terminal of the cell module outputs a high level. When the STATE terminal outputs a low level, the threshold voltage type memristor in the cell module is updated to a low-impedance state, and the STATE terminal in the cell module outputs a low level.

[0026] Sp3-4: Continuous application of V Rule30_enable and V MEM_assign After K cycles of the signal, the preset K iterations of the evolution of the states of 2N cellular modules are completed;

[0027] Sp4: Response reading phase; stop applying V. Rule30_enable and V MEM_assign Then, the external circuit reads the signal output from the 2N-bit response signal output terminal Response[2N-1:0], and uses it as the 2N-bit response signal output by the PUF circuit;

[0028] Sp5: Repeating Sp1 to Sp4, when different 2N-bit excitation signals are input, the output 2N-bit response signal is unique and unpredictable due to the randomness of the threshold voltage of the threshold voltage type memristor.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] Firstly, this invention adopts a ring array memristor cellular automaton integrated architecture, which effectively solves the problems of high hardware overhead, poor scalability, and insufficient anti-attack capability of traditional PUF, and simplifies the circuit structure, reduces hardware resource consumption, and supports flexible expansion of response bit width.

[0031] Secondly, this invention adopts memristor-SR latch collaborative control cell module technology, which solves the problems of poor synchronization and response delay caused by the separation of state storage and control in traditional cell modules. It integrates cell state storage and next state control, improves state switching speed and synchronization accuracy, and ensures the stability of STATE terminal output.

[0032] Third, this invention adopts digital integrated Rule30 chaotic logic module technology, which solves the problem of high hardware overhead of traditional chaotic modules, simplifies the chaotic implementation architecture, improves the real-time performance of chaotic characteristics, enhances the nonlinear correlation of stimulus-response, and improves the technical effect of PUF's resistance to machine learning attacks.

[0033] Fourth, the present invention adopts a hierarchical cascaded cell selection and initialization module technology to achieve the technical effects of precise cell selection, controllable initialization timing, support for large-scale cell array expansion, and adaptation to different excitation signals.

[0034] Fifth, the present invention adopts the trigger-decoder collaborative precision selection unit technology. Through the coordinated work of the trigger group, decoder and counter, the precise control of the selection timing is achieved, resulting in precise cell selection, stable output signal and support for hierarchical cascading. Attached Figure Description

[0035] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the one-dimensional memristor cellular automaton (PUF) circuit in this invention;

[0037] Figure 2 This is a schematic diagram of the Rule30 logic module circuit in this invention;

[0038] Figure 3 This is a schematic diagram of the cell initialization module circuit in this invention;

[0039] Figure 4 This is a schematic diagram of the selection module circuit in this invention;

[0040] Figure 5 This is a schematic diagram of the cell module circuit in this invention. Detailed Implementation

[0041] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0042] The components of the embodiments of the invention described and shown in the accompanying drawings can typically be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention.

[0043] Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0045] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Specific Implementation Example 1:

[0047] The following is combined with Figures 1 to 5 As shown, this embodiment of the invention provides a PUF circuit based on a memristor cellular automaton. The circuit includes a first cell initialization module, a second cell initialization module, 2N cell node modules, and an input terminal U. RESET U MEM_assign U Reverse_Control U Rule30_enable U MEM_Init U IN_enable U OUT_enable UD_FF_CLK U D_FF_RESET The array consists of 2N input terminals (Challenge[2N-1:0]), 2N output terminals (Response[2N-1:0]), and power supply terminals (VCC, VDD, VEE, GND). These 2N cell node modules are connected end-to-end to form a ring array, where N is a positive integer multiple of 4. Each cell node module includes a Rule30 logic module and a cell module. The Rule30 logic module includes input terminals (Reverse_Control, Cell_A_State, Cell_B_State, Cell_C_State, Rule30_...). The cell module includes input terminals RESET, Reverse, MEM_assign, MEM_Select, MEM_L, and output terminals STATE and MEM_R. Both the first and second cell initialization modules include input terminals Bit[2N-1:0], IN_enable, OUT_enable, D_FF_CLK, D_FF_RESET, RESET, and output terminals Output[N-1:0]. The circuit structures of the first and second cell initialization modules are completely identical. RESET The terminal is connected to the RESET terminals of the 2N cell modules, the RESET terminals of the first cell initialization module and the second cell initialization module, respectively. MEM_assign The terminal is connected to the MEM_assign terminal of each of the 2N cell modules, U Reverse_Control The terminal is connected to the Reverse_Control terminal of each of the 2N Rule30 logic modules, U Rule30_enable The terminal is connected to the Rule30_enable terminal of each of the 2N Rule30 logic modules, U MEM_Init The terminal is connected to the MEM_L terminal of the 1st to Nth cell modules respectively, U IN_enable The terminal is connected to the IN_enable terminal of the first cell initialization module and the second cell initialization module respectively, U OUT_enable The terminal is connected to the OUT_enable terminal of the first cell initialization module and the second cell initialization module respectively, U D_FF_CLK The terminal is connected to the D_FF_CLK terminal of the first cell initialization module and the second cell initialization module respectively, U D_FF_RESETThe terminals are connected to the D_FF_RESET terminals of the first and second cell initialization modules, respectively. Terminals Bit(8i), Bit(8i+1), Bit(8i+4), and Bit(8i+6) of the first cell initialization module are connected to terminal VCC, and terminals Bit(8i+2), Bit(8i+3), Bit(8i+5), and Bit(8i+7) of the first cell initialization module are connected to terminal GND, where i is an integer from 0 to N / 4-1. The 2N-bit excitation signal input terminals Challenge[2N-1:0] are connected to the Bit[2N-1:0] terminals of the second cell initialization module. The terminals are connected accordingly. The STATE terminals of the 1st to 2Nth cell modules are connected to the Response[2N-1:0] terminals of the 2N-bit response signal output terminals, respectively. The Reverse terminals of the cell modules in the cell node modules are connected to the Reverse terminals of the Rule30 logic modules. The MEM_Select terminals of the 1st to 2Nth cell modules are connected to the Output[N-1:0] terminals of the first cell initialization module, respectively. The MEM_Select terminals of the N+1th to 2Nth cell modules are connected to the Output[N-1:0] terminals of the second cell initialization module, respectively. The MEM_R terminals of the first to Nth cell modules and the MEM_L terminals of the (N+1)th to 2Nth cell modules are all connected together. The MEM_R terminals of the (N+1)th to 2Nth cell modules are connected to the GND terminal. The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the y-th cell node module are connected to the STATE terminals of the (y-1)th, y-th, and (y+1)th cell node modules, respectively. y is an integer from 2 to 2N-1. The first cell node... The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the module are respectively connected to the STATE terminals of the cell modules in the 2Nth cell node module, the first cell node module, and the second cell node module. The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the 2Nth cell node module are respectively connected to the STATE terminals of the 2N-1th cell node module, the 2Nth cell node module, and the first cell node module.In existing technologies, traditional PUF circuits generally suffer from the problem of separating the entropy source extraction module and the chaotic confusion module, resulting in hardware redundancy, high resource overhead, and fixed-size cellular arrays that are difficult to expand by increasing the number of cells to increase the response bit width, leading to poor scalability. Furthermore, the weak nonlinear correlation between excitation and response makes them vulnerable to machine learning modeling attacks, severely impacting the security of PUFs. To address these issues, this invention adopts a ring array memristor cellular automaton integrated architecture. 2N cellular node modules are connected end-to-end to form a ring cellular space. Each cellular node module integrates a Rule30 logic module and a cellular module, achieving the integration of chaotic evolution and state storage. The first cell initialization module uses a fixed bit terminal... The sub-level combination selects the first to Nth cell modules in sequence. The second cell initialization module receives the 2N-bit excitation signal and selects the (N+1)th to 2Nth cell modules. The two modules work together to complete the initial resistance state configuration of the memristor. The Rule30 logic module obtains the state of the STATE terminal of the adjacent cell module and generates a Reverse signal by combining it with the control signal to drive the state evolution of the cell module. The STATE terminal is directly used as the response signal output without the need for an additional conversion module. The 2N-bit excitation signal is connected one-to-one with the Bit terminal of the second cell initialization module. The MEM_Select terminal of the cell module is connected one-to-one with the Output terminal of the initialization module to ensure the accuracy of signal transmission.

[0048] Specifically, the cell module includes a first single-pole single-throw (SPS) to a fourth SPS, a first single-pole double-throw (SPS) CNC switch, a second single-pole double-throw (SPS) CNC switch, a first resistor, a second resistor, a threshold voltage type memristor, a current mirror, a first NOT gate, an SR latch, input terminals RESET, Reverse, MEM_assign, MEM_Select, and MEM_L, output terminals MEM_R and STATE. The STATE terminal serves as the cell state output terminal. The cell module's input terminal RESET is connected to the "+" terminal of the third SPS, and the cell module's input terminal Reverse is connected to the SR latch. The input terminal MEM_assign is connected to the "+" terminal of the fourth single-pole single-throw CNC switch. The input terminal MEM_Select is connected to the "+" terminals of the first single-pole double-throw CNC switch and the second single-pole double-throw CNC switch, respectively. The input terminal MEM_L is connected to the S1 terminal of the first single-pole double-throw CNC switch. The output terminal MEM_R is connected to the S1 terminal of the second single-pole double-throw CNC switch. The output terminal STATE is connected to the output terminal of the first NOT gate and the R terminal of the SR latch, respectively. The "+" terminal of the first single-pole single-throw CNC switch is connected to the VCC terminal. The "-" terminal of the first single-pole single-throw CNC switch is connected to the SR latch. The terminals are connected as follows: the S1 terminal of the first single-pole single-throw (SPSS) CNC switch is connected to terminal VCC; the S2 terminal of the first SPSS CNC switch is connected to the S2 terminal of the second SPSS CNC switch and the S1 terminal of the fourth SPSS CNC switch, respectively; the "+" terminal of the second SPSS CNC switch is connected to terminal VCC; the "-" terminal of the second SPSS CNC switch is connected to the Q terminal of the SR latch; the S1 terminal of the second SPSS CNC switch is connected to terminal VEE; the "-" terminal of the fourth SPSS CNC switch is connected to terminal GND; the S2 terminal of the fourth SPSS CNC switch is connected to the S2 terminal of the first SPSS CNC switch; one end of the first resistor is connected to terminal VDD; the other end of the first resistor is connected to the S2 terminal of the first SPSS CNC switch; and the "-" terminal of the third SPSS CNC switch is connected to... The terminal GND is connected. The S1 terminal of the third single-pole single-throw CNC switch is connected to the terminal VEE. The S2 terminal of the third single-pole single-throw CNC switch is connected to the S2 terminal of the first single-pole double-throw CNC switch. The "-" terminals of the first and second single-pole double-throw CNC switches are connected to the terminal GND respectively. One end of the threshold voltage type memristor is connected to the S3 terminal of the first single-pole double-throw CNC switch. The other end of the threshold voltage type memristor is connected to the S3 terminal of the second single-pole double-throw CNC switch. The S2 terminal of the second single-pole double-throw CNC switch is connected to one end of the current mirror. The other end of the current mirror is connected to one end of the second resistor, the input terminal of the first NOT gate, and the S terminal of the SR latch respectively. The other end of the second resistor is connected to the terminal VCC. The output terminal of the first NOT gate is connected to the R terminal of the SR latch. In existing technologies, traditional cellular modules typically design state storage and next-state control as independent units, resulting in large signal delays and poor state synchronization when they work together. Furthermore, the ambiguous resistance-state switching and state output logic of the memristor affects the response speed and reliability of the PUF. To address these issues, this invention employs a memristor-SR latch collaborative control cellular module technology. A threshold voltage type memristor serves as the core state storage component, connected to the circuit via first and second single-pole double-throw digital switches. The MEM_Select signal controls the switch's on / off state, enabling the selection and connection of the memristor. The SR latch stores the cell's next-moment state, and the Reverse signal acts as the latch. The enable signal of the latch controls the Q-terminal state to flip. When Reverse is 1, it flips; when it is 0, it remains unchanged. The MEM_assign signal drives the fourth single-pole single-throw digital switch to synchronize the Q-terminal state of the SR latch to the memristor, completing the resistance state update. The first NOT gate converts the resistance state of the memristor into the STATE terminal output signal, where the high resistance state of the memristor corresponds to the STATE terminal output "0", and the low resistance state corresponds to the output "1". The RESET signal resets the memristor to the high resistance state through the third single-pole single-throw digital switch to ensure the consistency of the initial state. The current mirror and the second resistor form a signal detection circuit to accurately feedback the resistance state of the memristor and provide a trigger signal for the SR latch.

[0049] Specifically, the Rule30 logic module includes second to fourth NOT gates, first to third AND gates, first to third OR gates, input terminals Cell_A_State, Cell_B_State, Cell_C_State, Rule30_enable, Reverse_Control, and output terminal Reverse. The input terminal Cell_A_State is connected to the input of the second NOT gate and the A input of the second AND gate, respectively. The input terminal Cell_B_State is connected to the input of the third NOT gate and the A input of the first OR gate, respectively. The input terminal Cell_C_State is connected to the input of the fourth NOT gate and the C input of the first AND gate, respectively. The input terminal Rule30... The e30_enable input is connected to the B input of the third AND gate. The Reverse_Control input is connected to the B input of the third OR gate. The output of the second NOT gate is connected to the A input of the first AND gate. The output of the third NOT gate is connected to the B input of the first AND gate. The output of the fourth NOT gate is connected to the B input of the first OR gate. The output of the first AND gate is connected to the A input of the second OR gate. The output of the first OR gate is connected to the B input of the second AND gate. The output of the second AND gate is connected to the B input of the second OR gate. The output of the second OR gate is connected to the A input of the third AND gate. The output of the third AND gate is connected to the A input of the third OR gate. The output of the third OR gate is connected to the Reverse output terminal of the Rule30 logic module.In existing technologies, the implementation of chaotic confusion modules either relies on analog circuits, which are susceptible to temperature and voltage fluctuations and have unstable chaotic characteristics, or on complex digital circuits, such as floating-point arithmetic iterations, which have high hardware overhead and poor real-time performance, resulting in weak anti-interference capabilities and high hardware implementation difficulty for the PUF. To address these issues, this invention adopts a digitally integrated Rule30 chaotic logic module technology. This module integrates pure digital logic gates (NOT gates, AND gates, and OR gates) to implement the Rule30 evolution rules, eliminating the need for analog devices or complex arithmetic units. The Cell_A_State, Cell_B_State, and Cell_C_State terminals respectively receive the STATE signals from the left neighbor, current cell, and right neighbor cell modules. After being inverted by the second to fourth NOT gates, these signals are input to the first AND gate, the first OR gate, and the second AND gate, respectively, for logical operations. The le30_enable signal controls the conduction of the third AND gate, ensuring that chaotic evolution only occurs in the specified stage. The Reverse_Control signal acts as the control terminal of the third OR gate. When Reverse_Control is "1", the Reverse terminal directly outputs "1", forcing the cell state to flip. When Reverse_Control is "0", the signal is output according to Rule30. That is, when Cell_A_State, Cell_B_State, and Cell_C_State are "111", "110", "101", or "000", Reverse outputs "1", otherwise it outputs "0". This logic module is directly integrated into the cell node module and works in conjunction with the cell module. The generated Reverse signal precisely controls the state of the SR latch.

[0050] Specifically, the cell initialization module includes the first to the N / 4th selection units, 2N-bit input terminals Bit[2N-1:0], input terminals IN_enable, D_FF_CLK, OUT_enable, D_FF_RESET, RESET, and N-bit output terminals Output[N-1:0]. Each selection unit includes 8-bit input terminals Bit[7:0], input terminals IN_enable, D_FF_CLK, OUT_enable, EN_enable, D_FF_RESET, RESET, 4-bit output terminals Output[3:0] and NEXT_enable. The input terminals Bit[j×8-1:(j-1)×8] of the cell initialization module are connected to the input terminals Bit[7:0] of the j-th selection unit, where j is an integer from 1 to N / 4. The input terminal IN_enable of the cell initialization module is connected to the input terminals IN_enable of the N / 4 selection units. The input terminals of the cell initialization module... The input terminals D_FF_CLK of the sub-D_FF_CLK are connected to the input terminals D_FF_CLK of the N / 4 selection units respectively. The input terminal OUT_enable of the cell initialization module is connected to the input terminals OUT_enable of the N / 4 selection units respectively. The input terminal D_FF_RESET of the cell initialization module is connected to the input terminals D_FF_RESET of the N / 4 selection units respectively. The input terminal RESET of the cell initialization module is connected to the input terminals RESET of the N / 4 selection units respectively. The output terminal Output[j×4-1:(j-1)×4] of the cell initialization module is connected to the output terminal Output[3:0] of the j-th selection unit respectively, where j is an integer from 1 to N / 4. The EN_enable terminal of the first selection unit is connected to the terminal VCC. The EN_enable terminal of the k-th selection unit is connected to the NEXT_enable terminal of the (k-1)-th selection unit, where k is an integer from 2 to N / 4. The NEXT_enable terminal of the N / 4-th selection unit is left floating.In existing technologies, the cell selection initialization module of PUF mostly uses a single control logic, which cannot flexibly adjust the selection object according to the excitation signal. Moreover, when multiple units are cascaded, control signal conflicts are prone to occur, resulting in low selection accuracy, poor initialization efficiency, and difficulty in adapting to large-scale cell arrays. To address these issues, this invention adopts a hierarchical cascaded cell selection initialization module technology. The cell initialization module consists of N / 4 selection units cascaded hierarchically. Each selection unit processes 8 bits of signal and outputs 4 bits of output signal. Through multi-unit cascading, N bits of output signal are achieved. The first cell initialization module and the second cell initialization module are adapted to the selection requirements of 2N cell modules. The bit terminals of the first cell initialization module are connected to VCC or GND according to a fixed rule, Bit[8i], Bit[8i+1], Bit[8i+4] Bit[8i+6] is connected to VCC, and the rest are connected to GND. No external excitation is required. The first to N cell modules are automatically selected according to the D_FF_CLK timing sequence. The Bit terminals of the second cell initialization module are connected one-to-one with the 2N excitation signals. According to different combinations of excitation signals, the N+1 to 2N cell modules are selected. The selection unit is cascaded through the EN_enable and NEXT_enable terminals. The EN_enable of the first selection unit is connected to VCC and starts first. Subsequent selection units start by receiving the NEXT_enable signal of the previous unit in sequence, realizing hierarchical timing control and avoiding signal conflicts. The IN_enable and OUT_enable signals control the input enable and output enable of the selection unit, respectively. The D_FF_RESET signal realizes the trigger reset to ensure the reliability of initialization.

[0051] Specifically, the selection unit includes the fourth to sixteenth AND gates, the fifth to ninth NOT gates, the fourth OR gate, the first to ninth D flip-flops, a 2-to-4 decoder, a 2-bit counter, 8-bit input terminals Bit[7:0], input terminals IN_enable, D_FF_CLK, OUT_enable, EN_enable, D_FF_RESET, RESET, 4-bit output terminals Output[3:0], and output terminal NEXT_enable; the 8-bit input terminals Bit[7:0] of the selection unit are connected to the A input terminals of the fourth to eleventh AND gates respectively, the IN_enable input terminal of the selection unit is connected to the B input terminals of the fourth to eleventh AND gates respectively, and the output terminals of the fourth to eleventh AND gates are connected to the S input terminals of the first to eighth D flip-flops. The ET terminals are connected accordingly. The input terminals D_FF_CLK of the selection unit are connected to the CLK terminals of the first to eighth D flip-flops and the CLK terminal of the 2-bit counter, respectively. The Q terminal of the first D flip-flop is connected to the D terminal of the second D flip-flop. The Q terminal of the second D flip-flop is connected to the D terminal of the third D flip-flop. The Q terminal of the third D flip-flop is connected to the D terminal of the fourth D flip-flop. The Q terminal of the fourth D flip-flop is connected to the D terminal of the first D flip-flop and the IA terminal of the 2-to-4 decoder, respectively. The Q terminal of the fifth D flip-flop is connected to the D terminal of the sixth D flip-flop. The Q terminal of the sixth D flip-flop is connected to the D terminal of the seventh D flip-flop. The Q terminal of the seventh D flip-flop is connected to the D terminal of the eighth D flip-flop. The Q terminal of the eighth D flip-flop is connected to the D terminal of the fifth D flip-flop and the IB terminal of the 2-to-4 decoder, respectively. The ninth D flip-flop... The input terminal of the selection unit is connected to the A input terminal of the twelfth AND gate. The input terminal EN_enable of the selection unit is connected to the B input terminal of the twelfth AND gate. The output terminal of the twelfth AND gate is connected to the EN terminal of the 2-bit counter. The CO terminal of the 2-bit counter is connected to the A input terminal of the fourth OR gate. The input terminal D_FF_RESET of the selection unit is connected to the B input terminal of the fourth OR gate. The output terminal of the fourth OR gate is connected to the CLK terminal of the ninth D flip-flop. The input terminal RESET of the selection unit is connected to the RESET terminal of the ninth D flip-flop and the input terminal of the ninth NOT gate, respectively. The output terminal of the ninth NOT gate is connected to the SET terminal of the ninth D flip-flop. The Q terminal of the ninth D flip-flop is connected to the 2-to-4 decoder. The input terminals and output terminals NEXT_enable are connected respectively. The 1Y0, 1Y1, 1Y2, and 1Y3 terminals of the 2-4 decoder are connected to the input terminals of the fifth to eighth NOT gates respectively. The output terminals of the fifth to eighth NOT gates are connected to the B input terminals of the thirteenth to sixteenth AND gates respectively. The input terminal OUT_enable of the selection unit is connected to the A input terminals of the thirteenth to sixteenth AND gates respectively. The output terminals of the thirteenth to sixteenth AND gates are connected to the output terminals Output[3:0] of the selection unit respectively. In existing technologies, selection units often employ simple combinational logic or single flip-flop control, resulting in inaccurate selection timing, susceptibility to noise interference in the output signal, and inability to coordinate with cascaded units. This leads to a high cell selection error rate, affecting the initialization reliability of the PUF. To address these issues, this invention employs a flip-flop-decoder collaborative precise selection unit technology. The selection unit is based on an 8-bit D flip-flop, a 2-to-4 decoder, and a 2-bit counter. The 8-bit signal is passed through the fourth to eleventh AND gates, enabled by IN_enable, triggering the first to eighth D flip-flops to form two sets of 4-bit ring shift registers. The outputs of these registers serve as the IA and IB inputs of the 2-to-4 decoder. The EN_enable signal and the Q input of the ninth D flip-flop are connected to the twelfth AND gate to control the start of the 2-bit counter. The carry signal CO of the counter and the D_FF_RESET signal are connected to the fourth OR gate to trigger the ninth D flip-flop, generating the enable signal of the 2-to-4 decoder and the cascade control signal NEXT_enable. The 2-to-4 decoder converts the 4-bit input signal into 4-way strobe signals. After being inverted by the fifth to eighth NOT gates, the signals are connected to the OUT_enable signal and connected to the thirteenth to sixteenth AND gates to output a 4-bit Output signal, realizing cell selection control. The RESET signal is connected to the ninth NOT gate to trigger the ninth D flip-flop, ensuring that the initial state of the cells is consistent.

[0052] Specifically, the voltage at terminal VCC is 5V, the voltage at terminal VDD is 2V, the voltage at terminal VEE is -5V, and terminal GND is the power supply reference ground. Based on the forward / reverse threshold voltage characteristics of threshold voltage type memristors, typically 1.5V to 2.5V forward and -3V to -6V reverse, VCC is configured to 5V, VDD to 2V, and VEE to -5V. The absolute values ​​of VCC and VEE are both greater than the absolute value of the memristor's threshold voltage, ensuring stable switching between low and high impedance states. VDD provides the operating voltage for digital logic modules, such as Rule30 logic modules and flip-flops, ensuring stable transmission of digital signals. GND serves as the reference ground, providing a potential reference for the entire circuit. Specific Implementation Example 2:

[0054] A method for using a PUF circuit based on a memristor cellular automaton, the method comprising the following steps:

[0055] Sp1: Reset phase; supplying terminal U RESET U D_FF_RESET Apply a high-level signal to terminal U MEM_assign U Reverse_Control U Rule30_enable U MEM_Init U IN_enable U OUT_enable U D_FF_CLK Applying a low-level signal applies a low level to the 2N-bit excitation signal input terminal Challenge[2N-1:0]. The threshold voltage type memristors in the 2N cell modules are all reset to the high-impedance state, and the output terminals Output[N-1:0] of the first cell initialization module and the second cell initialization module both output a low level.

[0056] Sp2: Initialization phase;

[0057] Sp2-1: Supply terminal U RESET U D_FF_RESET Apply a low-level signal to terminal U OUT_enable Apply a high-level signal to terminal U D_FF_CLK A square wave signal V with a frequency of 1kHz, a duty cycle of 50%, and a duration of N cycles is applied. CLK V CLK The first half of the cycle is high level and the second half of the cycle is low level, which is given to terminal U. MEM_Init A sinusoidal signal V with an amplitude of 5V and a frequency of 1kHz, lasting for N cycles, is applied. INIT Apply a 2N-bit excitation signal to the 2N-bit excitation signal input terminals Challenge[2N-1:0], and in V CLK During the first cycle, give terminal U IN_enable Apply a high-level signal at V CLK After the first cycle ends, give terminal U IN_enable A low-level signal is continuously applied;

[0058] Sp2-2: In V CLK Within each cycle, the first cell initialization module initializes according to V CLK The number of cycles that have been sustained is selected from the 1st to the Nth cell module, and the second cell initialization module is based on the 2N-bit excitation signal and V. CLK The number of cycles that have been sustained is selected from the (N+1)th to 2Nth cell modules, choosing one cell module and then using V. INIT The signal sets the threshold voltage memristor with the higher reverse threshold voltage in the two selected cell modules to a high-resistance state, and the threshold voltage memristor with the lower reverse threshold voltage to a low-resistance state.

[0059] Sp2-3: VCLK After N cycles, a portion of the 2N threshold voltage type memristors in the 2N cell modules are set to a low resistance state, while the other threshold voltage type memristors remain in a high resistance state. When the resistance of the 2N threshold voltage type memristors in the 2N cell modules is in a high resistance state, the STATE terminal of the corresponding cell module outputs a high level. When the resistance of the 2N threshold voltage type memristors in the 2N cell modules is in a low resistance state, the STATE terminal of the corresponding cell module outputs a low level.

[0060] Sp2-4: In V CLK After the Nth cycle ends, input terminal U is given Reverse_Control U OUT_enable When high and low level signals are applied respectively, all 2N cell modules update the Q output signal of their SR latch according to the resistance state of their threshold voltage type memristor. When the resistance state of the threshold voltage type memristor is high, the Q output of the SR latch is high; otherwise, the Q output of the SR latch is low.

[0061] Sp3: Cell module evolution stage;

[0062] Sp3-1: Supply terminal U Reverse_Control Apply a low-level signal to terminal U Rule30_enable A square wave signal V with a frequency of 1kHz and a duty cycle of 50% is applied. Rule30_enable In V Rule30_enable In one cycle of the signal, the first half of the cycle is high level and the second half of the cycle is low level, simultaneously supplying terminal U. MEM_assign A square wave signal V with a frequency of 1kHz and a duty cycle of 50% is applied. MEM_assign In V MEM_assign In one cycle of the signal, the first half of the cycle is low level and the second half of the cycle is high level;

[0063] Sp3-2: In V Rule30_enable and V MEM_assign In the first half of a signal cycle, 2N Rule30 logic modules update the signals of their output terminals Reverse according to the signals of their input terminals Cell_A_State, Cell_B_State, and Cell_C_State. 2N cell modules update the Q output signal of their SR latches according to the signals of their input terminals Reverse. If the signal of the terminal Reverse is high, the Q state of the SR latch flips; otherwise, the Q state of the SR latch remains unchanged.

[0064] Sp3-3: In V Rule30_enable and V MEM_assignIn the latter half of a signal cycle, if the Q output of the SR latch in the cell module is low, the threshold voltage type memristor in the cell module is updated to a high impedance state, and the STATE terminal of the cell module outputs a high level. When the STATE terminal outputs a low level, the threshold voltage type memristor in the cell module is updated to a low-impedance state, and the STATE terminal in the cell module outputs a low level.

[0065] Sp3-4: Continuous application of V Rule30_enable and V MEM_assign After K cycles of the signal, the preset K iterations of the evolution of the states of 2N cellular modules are completed;

[0066] Sp4: Response reading phase; stop applying V. Rule30_enable and V MEM_assign Then, the external circuit reads the signal output from the 2N-bit response signal output terminal Response[2N-1:0] and uses it as the 2N-bit response signal output by the PUF circuit;

[0067] Sp5: Repeating Sp1 to Sp4, when different 2N-bit excitation signals are input, the output 2N-bit response signal is unique and unpredictable due to the randomness of the threshold voltage of the threshold voltage type memristor.

[0068] Working principle of the invention:

[0069] In this invention, 2N cell node modules are connected end-to-end to form a ring-shaped cell space. Each cell node module integrates a Rule30 logic module and a cell module, realizing the integration of chaotic evolution and state storage. The first cell initialization module selects the 1st to Nth cell modules in sequence by using a fixed combination of bit terminal levels. The second cell initialization module receives a 2N-bit excitation signal and selects the (N+1)th to 2Nth cell modules. The two modules work together to complete the initial resistance state configuration of the memristor. The Rule30 logic module obtains the STATE terminal state of adjacent cell modules, combines it with control signals to generate a Reverse signal, and drives the state evolution of the cell modules. The STATE terminal is directly output as a response signal, without the need for... An additional conversion module connects the 2N-bit excitation signal to the Bit terminals of the second cell initialization module one-to-one. The MEM_Select terminal of the cell module corresponds one-to-one with the Output terminal of the initialization module, ensuring accurate signal transmission. A threshold voltage type memristor serves as the core state storage component, connected to the circuit via the first and second single-pole double-throw digital switches. The MEM_Select signal controls the switch's on / off state, enabling the selection and connection of the memristor. The SR latch stores the cell's state at the next moment. The Reverse signal acts as the latch's enable signal, controlling the Q-terminal state to flip; a Reverse value of 1 flips the state, while a value of 0 remains unchanged. The MEM_assign signal drives the first... Four single-pole single-throw digital switches synchronize the Q-terminal state of the SR latch to the memristor, completing the resistance state update. The first NOT gate converts the memristor's resistance state into a STATE terminal output signal, where a high resistance state of the memristor corresponds to a STATE terminal output of "0", and a low resistance state corresponds to an output of "1". The RESET signal resets the memristor to a high resistance state through the third single-pole single-throw digital switch, ensuring initial state consistency. The current mirror and the second resistor constitute a signal detection circuit, accurately feeding back the memristor's resistance state and providing a trigger signal for the SR latch. The Rule30 evolution rule is implemented through the integration of pure digital logic gates, NOT gates, AND gates, and OR gates, without the need for analog devices or complex arithmetic units. Cell_A_State, Cell_ The B_State and Cell_C_State terminals receive the STATE signals from the left neighbor, current cell, and right neighbor cell modules, respectively. After being inverted by the second to fourth NOT gates, these signals are input to the first AND gate, the first OR gate, and the second AND gate, respectively, for logical operations. The Rule30_enable signal controls the third AND gate to conduct, ensuring that chaotic evolution only occurs in the specified stage. The Reverse_Control signal acts as the control terminal for the third OR gate. When Reverse_Control is "1", the Reverse terminal directly outputs "1", forcing the cell state to flip. When Reverse_Control is "0", the signal is output according to Rule30.That is, when Cell_A_State, Cell_B_State, and Cell_C_State are "111", "110", "101", or "000", the Reverse output is "1", otherwise it outputs "0". This logic module is directly integrated into the cell node module and works in conjunction with the cell module. The generated Reverse signal precisely controls the state of the SR latch. The cell initialization module consists of N / 4 cascaded selection units. Each selection unit processes 8 bits of signal and outputs 4 bits of output signal. Through the cascading of multiple units, N bits of output signal are achieved. The first cell initialization module and the second cell initialization module... The block adapts to the selection requirements of 2N cell modules. The Bit terminals of the first cell initialization module are connected to VCC or GND according to a fixed rule. Bit[8i], Bit[8i+1], Bit[8i+4], and Bit[8i+6] are connected to VCC, and the rest are connected to GND. No external excitation is required. The first to Nth cell modules are automatically selected according to the D_FF_CLK timing sequence. The Bit terminals of the second cell initialization module are connected one-to-one with the 2N excitation signals. According to different combinations of excitation signals, the N+1 to 2Nth cell modules are selected. The selection unit is cascaded through the EN_enable and NEXT_enable terminals. The EN_enable of the first selection unit... The selection unit starts with VCC as the primary input, and subsequent selection units start sequentially from the NEXT_enable signal of the previous unit, achieving hierarchical timing control and avoiding signal conflicts. The IN_enable and OUT_enable signals control the input and output enable of the selection unit, respectively. The D_FF_RESET signal resets the flip-flops, ensuring initialization reliability. The selection unit is based on an 8-bit D flip-flop, a 2-to-4 decoder, and a 2-bit counter. The 8-bit signal is passed through the fourth to eleventh AND gates, and enabled by IN_enable, triggering the first to eighth D flip-flops to form two sets of 4-bit ring shift registers. The output of these registers serves as the IA of the 2-to-4 decoder. The 1B input signal, the EN_enable signal, and the Q input of the ninth D flip-flop are connected via the twelfth AND gate to control the start of the 2-bit counter. The carry signal CO of the counter and the D_FF_RESET signal are connected via the fourth OR gate to trigger the ninth D flip-flop, generating the enable signal for the 2-to-4 decoder and the cascade control signal NEXT_enable. The 2-to-4 decoder converts the 4-bit input signal into 4-way strobe signals. After being inverted by the fifth to eighth NOT gates, these signals are connected with the OUT_enable signal via the thirteenth to sixteenth AND gates to output a 4-bit Output signal, realizing cell selection control. The RESET signal is connected via the ninth NOT gate to trigger the ninth D flip-flop, ensuring that the initial state of the cells is consistent.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PUF circuit based on memristor cellular automata, characterized in that: The circuit includes a first cell initialization module, a second cell initialization module, a 2N cell node module, and an input terminal U. RESET U MEM_assign U Reverse_Control U Rule30_enable U MEM_Init U IN_enable U OUT_enable U D_FF_CLK U D_FF_RESET The 2N-bit excitation signal input terminals Challenge[2N-1:0], 2N-bit response signal output terminals Response[2N-1:0], and power supply terminals VCC, VDD, VEE, and GND are connected end-to-end to form a ring array, where N is an integer multiple of 4. Each cell node module includes a Rule30 logic module and a cell module. The Rule30 logic module includes input terminals Reverse_Control, Cell_A_State, Cell_B_State, Cell_C_State, and Rule30_ The cell module includes input terminals RESET, Reverse, MEM_assign, MEM_Select, MEM_L, and output terminals STATE and MEM_R. Both the first and second cell initialization modules include input terminals Bit[2N-1:0], IN_enable, OUT_enable, D_FF_CLK, D_FF_RESET, RESET, and output terminals Output[N-1:0]. The circuit structures of the first and second cell initialization modules are completely identical. The U RESET The terminal is connected to the RESET terminals of the 2N cell modules, the RESET terminals of the first cell initialization module and the second cell initialization module, respectively, and the U MEM_assign The terminal is connected to the MEM_assign terminal of each of the 2N cell modules, and the U Reverse_Control The terminal is connected to the Reverse_Control terminal of each of the 2N Rule30 logic modules, and the U Rule30_enable The terminal is connected to the Rule30_enable terminal of each of the 2N Rule30 logic modules, and the U MEM_Init The terminal is connected to the MEM_L terminal of the first to Nth cell modules respectively, and the U IN_enable The terminal is connected to the IN_enable terminal of the first cell initialization module and the second cell initialization module respectively, and the U OUT_enable The terminal is connected to the OUT_enable terminal of the first cell initialization module and the second cell initialization module respectively, and the U D_FF_CLK The terminal is connected to the D_FF_CLK terminal of the first cell initialization module and the second cell initialization module respectively, and the U D_FF_RESET The terminals are connected to the D_FF_RESET terminals of the first and second cell initialization modules, respectively. The terminals Bit(8i), Bit(8i+1), Bit(8i+4), and Bit(8i+6) of the first cell initialization module are connected to the VCC terminal, and the terminals Bit(8i+2), Bit(8i+3), Bit(8i+5), and Bit(8i+7) of the first cell initialization module are connected to the GND terminal, respectively. Here, i is an integer from 0 to N / 4-1. The 2N-bit excitation signal input terminals Challenge[2N-1:0] are connected to the Bit[2N-1:0] terminals of the second cell initialization module, respectively. Corresponding connections are made: the STATE terminals of the 1st to 2Nth cell modules are respectively connected to the Response[2N-1:0] terminals of the 2Nth response signal output terminals; the Reverse terminals of the cell modules in the cell node modules are connected to the Reverse terminals of the Rule30 logic module; the MEM_Select terminals of the 1st to Nth cell modules are respectively connected to the Output[N-1:0] terminals of the first cell initialization module; and the MEM_Select terminals of the N+1th to 2Nth cell modules are respectively connected to the Output[N-1:0] terminals of the second cell initialization module. The MEM_R terminals of the first to the Nth cell module, and the MEM_L terminals of the (N+1)th to the 2Nth cell modules are all connected together. The MEM_R terminals of the (N+1)th to the 2Nth cell modules are respectively connected to the GND terminal. The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the yth cell node module are respectively connected to the STATE terminals of the (y-1)th, yth, and (y+1)th cell node modules, where y is an integer from 2 to 2N-1. The first cell node... The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the point module are respectively connected to the STATE terminals of the cell modules in the 2Nth, the first, and the second cell node modules. The Cell_A_State, Cell_B_State, and Cell_C_State terminals of the Rule30 logic module in the 2Nth cell node module are respectively connected to the STATE terminals of the 2N-1th, the 2Nth, and the first cell node modules.

2. The PUF circuit according to claim 1, characterized in that: The cell module includes a first single-pole single-throw (SPS) to a fourth SPS, a first single-pole double-throw (SPS) CNC switch, a second single-pole double-throw (SPS) CNC switch, a first resistor, a second resistor, a threshold voltage type memristor, a current mirror, a first NOT gate, an SR latch, input terminals RESET, Reverse, MEM_assign, MEM_Select, and MEM_L, output terminals MEM_R and STATE, wherein the STATE terminal serves as the cell state output terminal. The RESET input terminal of the cell module is connected to the "+" terminal of the third SPS, and the Reverse input terminal of the cell module is connected to the EN terminal of the SR latch. The input terminal MEM_assign is connected to the "+" terminal of the fourth single-pole single-throw CNC switch. The input terminal MEM_Select is connected to the "+" terminals of the first single-pole double-throw CNC switch and the second single-pole double-throw CNC switch, respectively. The input terminal MEM_L is connected to the S1 terminal of the first single-pole double-throw CNC switch. The output terminal MEM_R is connected to the S1 terminal of the second single-pole double-throw CNC switch. The output terminal STATE is connected to the output terminal of the first NOT gate and the R terminal of the SR latch, respectively. The "+" terminal of the first single-pole single-throw CNC switch is connected to the terminal VCC. The "-" terminal of the first single-pole single-throw CNC switch is connected to the SR latch. The first single-pole single-throw (SPS) CNC switch has its S1 terminal connected to terminal VCC. The S2 terminal of the first SPS CNC switch is connected to the S2 terminal of the second SPS CNC switch and the S1 terminal of the fourth SPS CNC switch, respectively. The "+" terminal of the second SPS CNC switch is connected to terminal VCC. The "-" terminal of the second SPS CNC switch is connected to the Q terminal of the SR latch. The S1 terminal of the second SPS CNC switch is connected to terminal VEE. The "-" terminal of the fourth SPS CNC switch is connected to terminal GND. The S2 terminal of the fourth SPS CNC switch is connected to the S2 terminal of the first SPS CNC switch. One end of the first resistor is connected to terminal VDD, and the other end of the first resistor is connected to the S2 terminal of the first SPS CNC switch. The "-" terminal of the third SPS CNC switch is connected to... The terminal GND is connected. The S1 terminal of the third single-pole single-throw CNC switch is connected to the terminal VEE. The S2 terminal of the third single-pole single-throw CNC switch is connected to the S2 terminal of the first single-pole double-throw CNC switch. The "-" terminals of the first single-pole double-throw CNC switch and the second single-pole double-throw CNC switch are respectively connected to the terminal GND. One end of the threshold voltage type memristor is connected to the S3 terminal of the first single-pole double-throw CNC switch. The other end of the threshold voltage type memristor is connected to the S3 terminal of the second single-pole double-throw CNC switch. The S2 terminal of the second single-pole double-throw CNC switch is connected to one end of the current mirror. The other end of the current mirror is connected to one end of the second resistor, the input terminal of the first NOT gate, and the S terminal of the SR latch respectively. The other end of the second resistor is connected to the terminal VCC. The output terminal of the first NOT gate is connected to the R terminal of the SR latch.

3. The PUF circuit according to claim 1, characterized in that: The Rule30 logic module includes a second NOT gate to a fourth NOT gate, a first AND gate to a third AND gate, a first OR gate to a third OR gate, input terminals Cell_A_State, Cell_B_State, Cell_C_State, Rule30_enable, Reverse_Control, and an output terminal Reverse. The input terminal Cell_A_State is connected to the input of the second NOT gate and the A input of the second AND gate, respectively. The input terminal Cell_B_State is connected to the input of the third NOT gate and the A input of the first OR gate, respectively. The input terminal Cell_C_State is connected to the input of the fourth NOT gate and the C input of the first AND gate, respectively. The input terminal Rule30_enable is connected to the... The third AND gate's B input is connected, the input terminal Reverse_Control is connected to the third OR gate's B input, the second NOT gate's output is connected to the first AND gate's A input, the third NOT gate's output is connected to the first AND gate's B input, the fourth NOT gate's output is connected to the first OR gate's B input, the first AND gate's output is connected to the second OR gate's A input, the first OR gate's output is connected to the second AND gate's B input, the second AND gate's output is connected to the second OR gate's B input, the second OR gate's output is connected to the third AND gate's A input, the third AND gate's output is connected to the third OR gate's A input, and the third OR gate's output is connected to the Rule30 logic module's Reverse output terminal.

4. The PUF circuit according to claim 1, characterized in that: The cell initialization module includes the first to the N / 4th selection units, 2N-bit input terminals Bit[2N-1:0], input terminals IN_enable, D_FF_CLK, OUT_enable, D_FF_RESET, RESET, and N-bit output terminals Output[N-1:0]. Each selection unit includes 8-bit input terminals Bit[7:0], input terminals IN_enable, D_FF_CLK, OUT_enable, EN_enable, D_FF_RESET, RESET, 4-bit output terminals Output[3:0] and NEXT_enable. The input terminals Bit[j×8-1:(j-1)×8] of the cell initialization module are respectively connected to the input terminals Bit[7:0] of the j-th selection unit, where j is an integer from 1 to N / 4. The input terminal IN_enable of the cell initialization module is respectively connected to the input terminals IN_enable of the N / 4 selection units. The input terminal D_FF_CLK of the cell initialization module... K is connected to the input terminals D_FF_CLK of N / 4 of the selection units respectively. The input terminal OUT_enable of the cell initialization module is connected to the input terminals OUT_enable of N / 4 of the selection units respectively. The input terminal D_FF_RESET of the cell initialization module is connected to the input terminals D_FF_RESET of N / 4 of the selection units respectively. The input terminal RESET of the cell initialization module is connected to the input terminals RESET of N / 4 of the selection units respectively. The output terminal Output[j×4-1:(j-1)×4] of the cell initialization module is connected to the output terminal Output[3:0] of the j-th selection unit respectively, where j is an integer from 1 to N / 4. The EN_enable terminal of the first selection unit is connected to the terminal VCC. The EN_enable terminal of the k-th selection unit is connected to the NEXT_enable terminal of the (k-1)-th selection unit, where k is an integer from 2 to N / 4. The NEXT_enable terminal of the N / 4-th selection unit is floating.

5. The PUF circuit according to claim 1, characterized in that: The selection unit includes four to sixteenth AND gates, five to ninth NOT gates, a fourth OR gate, first to ninth D flip-flops, a 2-to-4 decoder, a 2-bit counter, 8-bit input terminals Bit[7:0], input terminals IN_enable, D_FF_CLK, OUT_enable, EN_enable, D_FF_RESET, RESET, 4-bit output terminals Output[3:0], and output terminal NEXT_enable; the 8-bit input terminals Bit[7:0] of the selection unit are respectively connected to the A input terminals of the fourth to eleventh AND gates, the IN_enable input terminal of the selection unit is respectively connected to the B input terminals of the fourth to eleventh AND gates, and the output terminals of the fourth to eleventh AND gates are respectively connected to the SET terminals of the first to eighth D flip-flops. The input terminal D_FF_CLK is connected to the CLK terminals of the first to eighth D flip-flops and the CLK terminal of the 2-bit counter, respectively. The Q terminal of the first D flip-flop is connected to the D terminal of the second D flip-flop. The Q terminal of the second D flip-flop is connected to the D terminal of the third D flip-flop. The Q terminal of the third D flip-flop is connected to the D terminal of the fourth D flip-flop. The Q terminal of the fourth D flip-flop is connected to the D terminal of the first D flip-flop and the IA terminal of the 2-to-4 decoder, respectively. The Q terminal of the fifth D flip-flop is connected to the D terminal of the sixth D flip-flop. The Q terminal of the sixth D flip-flop is connected to the D terminal of the seventh D flip-flop. The Q terminal of the seventh D flip-flop is connected to the D terminal of the eighth D flip-flop. The Q terminal of the eighth D flip-flop is connected to the D terminal of the fifth D flip-flop and the IB terminal of the 2-to-4 decoder, respectively. The ninth D flip-flop... The input terminal of the selection unit is connected to the A input terminal of the twelfth AND gate. The input terminal EN_enable of the selection unit is connected to the B input terminal of the twelfth AND gate. The output terminal of the twelfth AND gate is connected to the EN terminal of the 2-bit counter. The CO terminal of the 2-bit counter is connected to the A input terminal of the fourth OR gate. The input terminal D_FF_RESET of the selection unit is connected to the B input terminal of the fourth OR gate. The output terminal of the fourth OR gate is connected to the CLK terminal of the ninth D flip-flop. The RESET input terminal of the selection unit is connected to the RESET terminal of the ninth D flip-flop and the input terminal of the ninth NOT gate, respectively. The output terminal of the ninth NOT gate is connected to the SET terminal of the ninth D flip-flop. The Q terminal of the ninth D flip-flop is connected to the 2-to-4 decoder. The input terminals of the 2-4 decoder and the output terminal NEXT_enable are respectively connected. The input terminals of the 1Y0, 1Y1, 1Y2, and 1Y3 of the 2-4 decoder are respectively connected to the input terminals of the fifth to eighth NOT gates. The output terminals of the fifth to eighth NOT gates are respectively connected to the B input terminals of the thirteenth to sixteenth AND gates. The input terminal OUT_enable of the selection unit is respectively connected to the A input terminals of the thirteenth to sixteenth AND gates. The output terminals of the thirteenth to sixteenth AND gates are respectively connected to the output terminals Output[3:0] of the selection unit.

6. The PUF circuit according to claim 1, characterized in that: The voltage of terminal VCC is 5V, the voltage of terminal VDD is 2V, the voltage of terminal VEE is -5V, and terminal GND is the reference ground of the power supply.

7. A method of using a PUF circuit based on a memristor cellular automaton, wherein the method is based on the PUF circuit of claim 1, characterized in that: Includes the following steps: Sp1: Reset phase; supplying terminal U RESET U D_FF_RESET Apply a high-level signal to terminal U MEM_assign U Reverse_Control U Rule30_enable U MEM_Init U IN_enable U OUT_enable U D_FF_CLK A low-level signal is applied to the Challenge[2N-1:0] terminal of the 2N-bit excitation signal input. The threshold voltage type memristors in the 2N cell modules are all reset to the high-impedance state. The Output[N-1:0] terminals of the first cell initialization module and the second cell initialization module both output a low level. Sp2: Initialization phase; Sp2-1: Supply terminal U RESET U D_FF_RESET Apply a low-level signal to terminal U OUT_enable Apply a high-level signal to terminal U D_FF_CLK A square wave signal V with a frequency of 1kHz, a duty cycle of 50%, and a duration of N cycles is applied. CLK V CLK The first half of the cycle is high level and the second half of the cycle is low level, which is given to terminal U. MEM_Init A sinusoidal signal V with an amplitude of 5V and a frequency of 1kHz, lasting for N cycles, is applied. INIT Apply a 2N-bit excitation signal to the 2N-bit excitation signal input terminals Challenge[2N-1:0], and in V CLK During the first cycle, give terminal U IN_enable Apply a high-level signal at V CLK After the first cycle ends, give terminal U IN_enable A low-level signal is continuously applied; Sp2-2: In V CLK Within each cycle, the first cell initialization module initializes according to V CLK The number of cycles that have been sustained is selected from the 1st to the Nth cell module, and the second cell initialization module is based on the 2N-bit excitation signal and V. CLK The number of cycles that have been sustained is selected from the (N+1)th to 2Nth cell modules, choosing one cell module and then using V. INIT The signal sets the threshold voltage memristor with the higher reverse threshold voltage in the two selected cell modules to a high-resistance state, and the threshold voltage memristor with the lower reverse threshold voltage to a low-resistance state. Sp2-3: V CLK After N cycles, a portion of the 2N threshold voltage type memristors in the 2N cell modules are set to a low resistance state, while the other threshold voltage type memristors remain in a high resistance state. When the resistance of the 2N threshold voltage type memristors in the 2N cell modules is in a high resistance state, the STATE terminal of the corresponding cell module outputs a high level. When the resistance of the 2N threshold voltage type memristors in the 2N cell modules is in a low resistance state, the STATE terminal of the corresponding cell module outputs a low level. Sp2-4: In V CLK After the Nth cycle ends, input terminal U is given Reverse_Control U OUT_enable High and low level signals are applied respectively. All 2N cell modules update the Q output signal of their SR latch according to the resistance state of their threshold voltage type memristor. When the resistance state of the threshold voltage type memristor is high, the Q output of the SR latch is high; otherwise, the Q output of the SR latch is low. Sp3: Cell module evolution stage; Sp3-1: For terminal U Reverse_Control Apply a low-level signal to terminal U Rule30_enable A square wave signal V with a frequency of 1kHz and a duty cycle of 50% is applied. Rule30_enable In V Rule30_enable In one cycle of the signal, the first half of the cycle is high level and the second half of the cycle is low level, simultaneously supplying terminal U. MEM_assign A square wave signal V with a frequency of 1kHz and a duty cycle of 50% is applied. MEM_assign In V MEM_assign In one cycle of the signal, the first half of the cycle is low level and the second half of the cycle is high level; Sp3-2: In V Rule30_enable and V MEM_assign In the first half of a signal cycle, 2N Rule30 logic modules update the signals of their output terminals Reverse according to the signals of their input terminals Cell_A_State, Cell_B_State, and Cell_C_State. 2N cell modules update the Q output signal of their SR latches according to the signals of their input terminals Reverse. If the signal of the terminal Reverse is high, the Q state of the SR latch flips; otherwise, the Q state of the SR latch remains unchanged. Sp3-3: In V Rule30_enable and V MEM_assign In the latter half of a signal cycle, if the Q output of the SR latch in the cell module is low, the threshold voltage type memristor in the cell module is updated to a high impedance state, and the STATE terminal of the cell module outputs a high level. When the STATE terminal outputs a low level, the threshold voltage type memristor in the cell module is updated to a low-impedance state, and the STATE terminal in the cell module outputs a low level. Sp3-4: Continuous application of V Rule30_enable and V MEM_assign After K cycles of the signal, the preset K iterations of the evolution of the states of 2N cellular modules are completed; Sp4: Response reading phase; stop applying V. Rule30_enable and V MEM_assign Then, the external circuit reads the signal output from the 2N-bit response signal output terminal Response[2N-1:0], and uses it as the 2N-bit response signal output by the PUF circuit; Sp5: Repeating Sp1 to Sp4, when different 2N-bit excitation signals are input, the output 2N-bit response signal is unique and unpredictable due to the randomness of the threshold voltage of the threshold voltage type memristor.

Images