Method and device for testing NANDFLASH chip

Abstract

The invention is suitable for the technical field of data identification, and provides a test method and device for an NANDFLASH chip, and the test method for the NANDFLASH chip comprises the following steps: carrying out acceleration test operation on a target storage block in an NAND type flash memory based on a preset test mode; counting a failure cycle number corresponding to a preset accumulated failure rate in the accelerated test operation; wherein the number of failure cycles comprises the occurrence of an uncorrectable ECC error, the bit error rate exceeding a first failure threshold value, the original bit error rate exceeding a second failure threshold value or the programming erasure time exceeding a time threshold value; calculating an electric field acceleration factor and a temperature acceleration factor; and according to the electric field acceleration factor, the temperature acceleration factor and the failure cycle number corresponding to the preset accumulated failure rate, calculating a life index. According to the scheme, the testing precision and reliability are improved, the testing time is greatly shortened, and the testing cost is reduced.

Description

Technical Field

[0001] This invention belongs to the technical field of data recognition, and in particular relates to a testing method and apparatus for NAND flash chips. Background Technology

[0002] NAND flash memory, a type of non-volatile memory, is widely used in various electronic devices such as smartphones, tablets, and solid-state drives. It boasts advantages such as high storage density, low cost, and low power consumption. However, the lifespan of NAND flash memory has always been a significant factor limiting its application and development.

[0003] The lifespan of a NAND flash chip is typically determined by the number of erase / write cycles it undergoes. During each erase / write operation, the floating gate charge in the memory cell gradually dissipates, causing changes in the cell's electrical characteristics. These changes increase the bit error rate (BER), ultimately leading to unrecoverable data errors and impacting the reliability of the stored data. Therefore, accurate testing and evaluation of the NAND flash chip's lifespan are crucial for improving its reliability and extending its service life.

[0004] Traditional NAND flash chip lifespan testing methods mainly include long-term testing under real-world usage conditions. Long-term testing under real-world usage conditions requires a considerable amount of time and is costly. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a testing method and apparatus for NAND FLASH chips to solve the technical problem that long-term testing in actual use environments requires a long time and is costly.

[0006] A first aspect of this invention provides a testing method for a NAND flash chip, the testing method comprising: Accelerated testing is performed on the target memory block in the NAND flash memory based on the preset test mode. The number of failure cycles corresponding to the preset cumulative failure rate during the accelerated testing operation is counted; wherein, the number of failure cycles includes the occurrence of uncorrectable ECC errors, bit error rate exceeding the first failure threshold, original bit error rate exceeding the second failure threshold, or programming erase time exceeding the time threshold; Calculate the electric field acceleration factor and the temperature acceleration factor; The lifetime index is calculated based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate; wherein, the lifetime index is a test result, and the lifetime index represents the number of cycles when the cumulative failure rate of the NAND FLASH chip reaches the preset cumulative failure rate under actual use environment.

[0007] Furthermore, the step of performing accelerated testing on the target memory block in the NAND flash memory based on a preset test mode includes: S1: At the accelerated test temperature, perform accelerated erasure operation on the target memory block in the NAND flash memory based on the preset test mode; S2: After performing the accelerated erase operation, perform a programming operation on the target storage block based on the accelerated test temperature; S3: After performing the programming operation, perform a read operation and error detection on the target storage block based on the accelerated test temperature; S4: Repeat steps S1 to S3 until a predetermined test termination condition is met; wherein, the test termination condition includes detecting that the number of uncorrectable memory cells exceeds a predetermined threshold.

[0008] Furthermore, the accelerated testing temperature includes 105 degrees Celsius.

[0009] Further, S1 includes: Apply a first negative voltage V_erase to all word lines of the target memory block in the NAND flash memory; During the application of the first negative voltage V_erase, a second negative voltage V_bl_neg is applied to all bit lines associated with the target memory block; During the application of the first negative voltage V_erase, the gate voltage V_dsl of the drain select transistor of the target memory block is set to a third voltage V_dsl_smfs, and the gate voltage V_ssl of the source select transistor of the target memory block is set to a fourth voltage V_ssl_smfs; wherein, the third voltage V_dsl_smfs and the fourth voltage V_ssl_smfs are used to put the drain select transistor and the source select transistor into a weak conduction state or a subthreshold conduction state; the weak conduction state or the subthreshold conduction state refers to a voltage negative offset between 50mV and 300mV.

[0010] Furthermore, the steps for calculating the electric field acceleration factor and the temperature acceleration factor include: Obtain the average effective electric field of the standard erase voltage and standard channel potential under actual operating conditions; To obtain the effective electric field for accelerating the erasure operation and the effective barrier parameters of the tunnel oxide layer material; Substituting the average effective electric field, the effective electric field of the accelerated erasure operation, and the effective barrier parameter of the tunnel oxide layer material into function one, we obtain the electric field acceleration factor; where function one is: electric field acceleration factor = exp[W * (1 / |E_normal| - 1 / |E_acc|)], E_normal represents the average effective electric field, E_acc represents the effective electric field of the accelerated erasure operation, and W represents the effective barrier parameter of the tunnel oxide layer material; The temperature acceleration factor was calculated using the Arrhenius model.

[0011] Further, the step of calculating the lifetime index based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate includes: Based on the Weibull distribution, characteristic lifetime and shape parameters are fitted; Multiply the electric field acceleration factor and the temperature acceleration factor together to obtain the total acceleration factor; Multiplying the total acceleration factor by the characteristic lifetime yields the accelerated characteristic lifetime; Obtain the current cumulative failure rate under the test termination condition; Substituting the shape parameters, the accelerated feature lifetime, and the current cumulative failure rate into a preset function yields a lifetime index; wherein, the lifetime index represents the number of cycles required to reach a cumulative failure rate of 1%, and the preset function is: lifetime index = η_normal * [-ln(1 - F_acc)] (1 / B) η_normal represents the accelerated feature lifetime, F_acc represents the current cumulative failure rate, and B represents the shape parameter.

[0012] Furthermore, the step of fitting the characteristic lifetime and shape parameters based on the Weibull distribution includes: Obtain the first cycle number corresponding to the first occurrence of an uncorrectable error in multiple NAND flash memories; Arrange the first loop counts corresponding to each of the multiple NAND flash memory devices from largest to smallest to obtain the order corresponding to each first loop count; Based on the order corresponding to each first loop count and the number of the plurality of NAND flash memories, calculate the median rank corresponding to each first loop count; where F = (i - 0.3) / (n + 0.4), F represents the median rank, i represents the order of the first loop count, and n represents the number of the plurality of NAND flash memories; Calculate the Weibull x-coordinate and Weibull y-coordinate based on the number of each first loop and the corresponding number of the first loop; where X = ln(number of first loops), Y = ln[ln(1 / 1-F)], X represents the Weibull x-coordinate, and Y represents the Weibull y-coordinate; By fitting the straight line Y = BX + C using the least squares method, the slope β and intercept C are obtained. The slope B is used as a shape parameter; Substituting the shape parameter B and the intercept C into function two, we obtain the characteristic lifetime; where function two is: characteristic lifetime = e -C / B .

[0013] A second aspect of this invention provides a testing apparatus for NAND flash chips, comprising: The test unit is used to perform accelerated testing operations on the target memory block in the NAND flash memory based on a preset test mode. The statistics unit is used to count the number of failure cycles corresponding to the preset cumulative failure rate in the accelerated testing operation; wherein, the number of failure cycles includes the occurrence of an uncorrectable ECC error, the bit error rate exceeding a first failure threshold, the original bit error rate exceeding a second failure threshold, or the programming erase time exceeding a time threshold; The first calculation unit is used to calculate the electric field acceleration factor and the temperature acceleration factor. The second calculation unit is used to calculate the lifetime index based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate; wherein, the lifetime index is a test result, and the lifetime index represents the number of cycles when the cumulative failure rate of the NAND FLASH chip reaches the preset cumulative failure rate under actual use environment.

[0014] A third aspect of the present invention provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the testing method for the NAND flash chip described in the first aspect.

[0015] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the testing method for the NAND flash chip described in the first aspect.

[0016] The beneficial effects of this invention compared to existing technologies are as follows: This invention employs a preset test mode to accelerate the testing of target memory blocks in NAND flash chips. The preset test mode simulates various operating conditions in real-world environments, ensuring more representative and accurate test results. During the accelerated testing process, the number of failure cycles corresponding to a preset cumulative failure rate is statistically analyzed, including various failure modes such as uncorrectable ECC errors, bit error rate exceeding a first failure threshold, original bit error rate exceeding a second failure threshold, or programming / erase time exceeding a time threshold. By comprehensively analyzing these failure modes, the reliability of the NAND flash chip can be more comprehensively evaluated. This invention fully considers the impact of electric field acceleration factors and temperature acceleration factors on the lifespan of NAND flash chips by calculating these two important acceleration factors. In the lifespan index calculation process, combining these acceleration factors allows for more accurate simulation of operating conditions in real-world environments, improving the accuracy of lifespan prediction. Based on the electric field acceleration factor, temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate, the calculated lifespan index accurately represents the number of cycles required for the NAND flash chip to reach the preset cumulative failure rate under real-world operating conditions. This metric not only helps predict the actual lifespan of a chip but also provides crucial data support for chip optimization and improvement. Traditional NAND flash chip lifespan testing methods are time-consuming, while this invention accelerates the testing process, enabling lifespan testing to be completed in a shorter time. This significantly improves testing efficiency and reduces testing costs, providing a more efficient solution for chip manufacturing and applications. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic flowchart of a testing method for a NAND flash chip provided by the present invention is shown; Figure 2 A schematic diagram of a testing apparatus for a NAND flash chip according to an embodiment of the present invention is shown. Figure 3 A schematic diagram of a terminal device provided in an embodiment of the present invention is shown. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0020] This invention provides a testing method and apparatus for NAND flash chips to solve the technical problem that long-term testing in actual use environments requires a long time and is costly.

[0021] First, this invention provides a testing method for NAND flash chips. Please refer to [link / reference]. Figure 1 , Figure 1 A schematic flowchart illustrating a testing method for a NAND flash chip provided by this invention is shown. Figure 1 As shown, the testing method for this NAND flash chip may include the following steps: Step 101: Perform accelerated testing on the target memory block in the NAND flash memory based on the preset test mode; The preset test mode is used to simulate harsh environments that far exceed normal working conditions, causing the chip to undergo a large amount of wear and tear in a short period of time, reaching or even exceeding the cumulative damage level that would take many years under normal use.

[0022] The preset test mode is crucial for acceleration. It specifies the acceleration stress conditions, including but not limited to: ① A higher wipe voltage (Verase) than normal operation is applied. The stronger electric field accelerates physical degradation mechanisms such as charge tunneling and interface trap formation.

[0023] ② Test at environments exceeding the chip's rated operating temperature (e.g., 85°C, 105°C, or even higher). High temperatures accelerate chemical reactions (such as oxide layer degradation) and carrier mobility, thus exacerbating aging.

[0024] ③ High frequency, specific data patterns (such as all 00 / all FF / checkerboard), specific block operation sequences, etc., are designed to maximize specific types of stress.

[0025] In this preset mode, the target block is repeatedly subjected to a complete Program-Erase cycle. Each P / E cycle represents one "consumption".

[0026] Specifically, step 101 includes S1 to S4: S1: At the accelerated test temperature, perform accelerated erasure operation on the target memory block in the NAND flash memory based on the preset test mode; This eraser combines high-voltage (electric field acceleration) and high-temperature (temperature acceleration) operations. High voltage directly accelerates charge migration, while high temperature increases carrier kinetic energy and chemical reaction rates (such as oxide layer degradation). This step simulates eraser operations in actual use, but accelerates eraser-related degradation mechanisms (mainly tunneling oxide layer damage) under more stringent conditions.

[0027] Accelerated testing temperatures include, but are not limited to, 105 degrees Celsius.

[0028] Specifically, step S1 includes S11 to S13: S11: Apply a first negative voltage V_erase to all word lines of the target memory block in the NAND flash memory; Applying a first negative voltage V_erase to all word lines is the core operation of NAND Flash block erasure. The essence of erasure is to remove electrons from the floating gate, thus lowering its threshold voltage (Vth).

[0029] The erase operation operates on the entire target block, requiring all word lines within the block to be selected simultaneously. The first negative voltage, V_erase, is the primary erase voltage applied to the word lines. Compared to traditional processes that may use zero or positive voltage for erasure, using a higher negative voltage (a more negative V_erase) is one of the core methods of electric field acceleration. The more negative V_erase, the greater the negative voltage difference (ΔV = V_well - V_erase) between the word line (WL) and the channel (which is typically biased to a higher positive voltage, such as V_well). This huge negative voltage difference generates an extremely strong electric field on the tunneling oxide layer. According to the Fowler-Nordheim (FN) tunneling principle, the strong electric field significantly accelerates the process of electrons tunneling from the floating gate through the tunneling oxide layer to the channel (P-well), thereby greatly accelerating the erase speed. The larger the |V_erase| value (i.e., the more negative it is), the stronger the electric field and the faster the erasure speed, but at the same time, it also puts greater stress on the oxide layer (accelerating aging).

[0030] S12: During the application of the first negative voltage V_erase, a second negative voltage V_bl_neg is applied to all bit lines associated with the target memory block; During the erase (during V_erase application), the bit line is also biased to a negative voltage (a second negative voltage V_bl_neg, V_bl_neg < 0V).

[0031] A negative voltage (V_bl_neg) is applied to the bit line and coupled to the channel potential of the NAND string through the drain select transistor (DSL) (whose gate voltage V_dsl is set in the next step). This helps to raise the potential of the entire channel, making it closer to or equal to the P-well bias (typically a higher positive voltage). Maintaining a high and uniform channel potential is crucial for achieving uniform erasure of all cells within the block, avoiding erase speed differences or incomplete erasures caused by channel potential inhomogeneity.

[0032] During erase operations (especially when using a high negative voltage V_erase), gate-induced drain leakage (GIDL) is prone to occur at the drain terminals of the drain select (DSL) and source select (SSL) transistors (connected to the BL and common source line CSL, respectively). GIDL generates unwanted electron-hole pairs. Applying a negative V_bl_neg can reduce the voltage difference at the drain terminal (BL side) of the DSL transistor, helping to suppress or reduce GIDL current generation, thereby improving the reliability and efficiency of the erase operation.

[0033] S13: During the application of the first negative voltage V_erase, the gate voltage V_dsl of the drain select transistor of the target memory block is set to a third voltage V_dsl_smfs, and the gate voltage V_ssl of the source select transistor of the target memory block is set to a fourth voltage V_ssl_smfs; wherein, the third voltage V_dsl_smfs and the fourth voltage V_ssl_smfs are used to put the drain select transistor and the source select transistor into a weak conduction state or a subthreshold conduction state; the weak conduction state or the subthreshold conduction state refers to a voltage negative offset between 50mV and 300mV.

[0034] The third voltage V_dsl_smfs and the fourth voltage V_ssl_smfs precisely control the state of the selection transistor, achieving the aforementioned channel potential coupling and isolation of non-target blocks. These two voltages control the conduction state of the DSL and SSL switches.

[0035] Weak inversion, or subthreshold region, refers to a state where the transistor is not fully turned on (strong inversion), but rather in a transitional region between on and off. In this state: The transistor has a certain conduction capability, allowing current (mainly leakage current) to flow, but its on-resistance is relatively large. It effectively couples the negative voltage V_bl_neg of the bit line (BL) (and the bias of the source line CSL, typically V_well or a similar high potential) to the NAND string channel, thereby achieving channel potential elevation and homogenization (as described in step S12). Simultaneously, the large on-resistance limits the current, preventing large punch-through currents from forming between non-target blocks or different strings, which is crucial for avoiding excessive power consumption and interference. Setting both the DSL and SSL transistors in this weak conduction state ensures that both ends of the channel can be effectively biased to the required potential (determined by V_bl_neg and the source line bias), guaranteeing the stability and consistency of the entire string channel potential.

[0036] The negative voltage offset refers to the negative difference between the gate voltage (Vg) of a selector transistor (DSL or SSL) and its threshold voltage (Vth). That is, the offset ΔV = Vg - Vth < 0. The larger |ΔV| is, the more the gate voltage Vg is lower than the Vth required to turn on the transistor.

[0037] The range of ΔV is limited to -300mV to -50mV (i.e., Vg is 50mV to 300mV lower than Vth).

[0038] Status Explanation: When ΔV≈0 (Vg≈Vth), the transistor is at the edge of the weak inversion / subthreshold region.

[0039] When ΔV = -50mV (Vg = Vth-50mV), the transistor is in the state of just entering the subthreshold region and has a small leakage current.

[0040] When ΔV = -300mV (Vg = Vth-300mV), the transistor is in a deeper subthreshold region, and the leakage current is smaller than when it is -50mV.

[0041] Within this range (-300mV to -50mV), the transistor has controllable, non-zero conduction capability (subthreshold current) sufficient to achieve channel potential coupling, but its on-resistance is large enough to effectively limit the current. This range represents the preferred value in engineering, balancing channel coupling effectiveness and leakage current suppression.

[0042] This quantization range ensures that the selector can operate stably in the required weak conduction state at different process angles and temperatures.

[0043] It is worth noting that high negative voltage erasure is the most direct and effective means of applying a stronger negative word line voltage to accelerate the erasure speed. It significantly enhances the electric field that tunnels through the oxide layer and is the main stress source that accelerates aging.

[0044] Negative bit offset is used to optimize erase uniformity and suppress GIDL, ensuring reliable and uniform erasure operations under high negative pressure V_erase. This is crucial for guaranteeing the representativeness and accuracy of accelerated test results.

[0045] The weak conduction setting of the selector is the key mechanism for achieving the negative line bias (V_bl_neg). By precisely controlling the gate voltages of the DSL and SSL transistors in the subthreshold region, V_bl_neg (negative) and the source line bias (positive) are effectively coupled to the channel, increasing and stabilizing the channel potential and ensuring erase uniformity. This limits the series current, reducing power consumption and interference risks. The quantized negative offset (50mV - 300mV) ensures the repeatability and robustness of this state under various conditions.

[0046] These three elements (high negative V_erase + negative V_bl_neg + weak conduction of the selector) together constitute the specific implementation of the "based on preset test mode" in the erase operation (S1). V_erase provides the main accelerating stress, while V_bl_neg and the selector state settings ensure the effectiveness, uniformity, and controllability of the erase operation under high stress, enabling the accelerated test to be carried out stably and reliably, thereby obtaining effective accelerated life data.

[0047] It is worth noting that due to minute differences in manufacturing processes (tunnel oxide thickness, doping concentration, structural geometry), differences in bit line / word line resistance, and crosstalk effects, the actual set value of the channel potential (V_ch) during erasure exhibits a small but significant distribution that impacts lifetime for different cells. This distribution results in: a few "lucky" cells experiencing stress slightly below the theoretical maximum; a more dispersed failure timeline for different cells; and the need for more cycles to expose the weakest cells.

[0048] To address the aforementioned issues, this embodiment employs logic for accelerated testing. The core idea of ​​this embodiment is to actively control and minimize the channel potential (V_ch) of all memory cells during the erase operation, eliminating or significantly reducing their distribution differences, and ensuring that each cell withstands the maximum electric field stress (V_g - V_ch) close to the physical limit when the erase high voltage (V_erase) is applied.

[0049] The tunneling current density J of FN is exponentially related to the electric field strength E: J ∝ E² * exp(-B / E). The electric field strength E ≈ (V_g - V_ch) / T_ox (V_g is the negative high voltage of the word line, and T_ox is the thickness of the tunnel oxide layer).

[0050] The key to maximizing tunneling current (i.e. maximizing degradation rate) lies in maximizing (V_g - V_ch). V_g is limited by the device breakdown voltage, and its improvement is limited.

[0051] Therefore, the key to acceleration lies in minimizing V_ch. In conventional operation, V_ch is typically set to 0V (or close to 0V) during erasure by grounding (or near grounding) the bit line / BL and the common source line / SL. However, due to the aforementioned process differences and circuit parasitic effects, the actual V_ch of all cells cannot be precisely clamped to an ideal, identical low potential (such as 0V), but rather exists within a small positive voltage distribution range (e.g., it may actually fluctuate between 0.1V and 0.5V).

[0052] The slight positive deviation of V_ch and its distribution cause the actual electric field E to be less than the theoretical maximum value, and the E values ​​of different elements differ, resulting in asynchronous stress and the weakest element not being subjected to the maximum pressure.

[0053] During the erase pulse (when a negative high voltage V_erase, such as -20V, is applied to the word line), the potential of all bit lines (including the bit lines of unselected cells) is actively controlled and set to a precisely controllable negative voltage (V_bl_neg), for example, -0.5V to -2.0V.

[0054] Precise control of the gate voltages (V_dsl, V_ssl) of the drain-select transistor (DSL) and source-select transistor (SSL). During the application of V_bl_neg, V_dsl and V_ssl are set to values ​​slightly higher than V_bl_neg but much lower than their normal operating turn-on voltage (e.g., V_dsl / V_ssl = -0.5V or 0V when V_bl_neg = -1V). This voltage setting is critical: it ensures the selectors are in a weakly on or critically on state. The purpose is to utilize the channel potential coupling effect in the NAND string. When a strong negative voltage V_erase is applied to the word line (WL), it pulls the channel potential down (making it more negative) through capacitive coupling.

[0055] At the same time, the negative bias voltage V_bl_neg applied to the BL and the weakly conducting DSL / SSL will help "clamp" the channel potential V_ch of the entire NAND string, making it closer to (or even slightly lower than) the target value of V_bl_neg.

[0056] By precisely designing V_bl_neg, V_dsl / V_ssl, and the erase pulse timing (rising / falling edge), the channel potential V_ch of all memory cells can be effectively set and stabilized at a uniform negative potential very close to V_bl_neg (e.g., V_ch≈V_bl_neg +ΔV, where ΔV is a small, controllable offset that may be 0V or a few millivolts).

[0057] Since V_ch of all cells is forced to be set to a uniform and more negative value (e.g., -1V), and V_erase is a uniform negative high voltage (e.g., -20V), the difference of (V_g - V_ch) of all cells is significantly increased (in this example, from the traditional (~20V) to (~19V)). More importantly, the distribution difference of this increased electric field value ((V_g - V_ch) / T_ox) in the array is greatly reduced (because the distribution of V_ch is forced to be uniform).

[0058] Throughout the accelerated life test, each erase operation was performed using the above-described embodiment, while programming and reading operations could be performed in a standard manner.

[0059] Unlike simply increasing V_erase or temperature, this embodiment starts by maximizing the core physical stress source (V_g - V_ch) of the erase operation and achieves this by actively controlling the channel potential. This is a systematic approach not seen in existing technologies (such as JEDEC standard methods or published literature).

[0060] Its core innovation lies in utilizing precise negative bias and the weak conduction state of the selected transistor to actively eliminate the natural random distribution of channel potential between cells during erasure, thereby enabling all cells to bear synchronous electric field stress close to the theoretical maximum value. This directly targets the weakest link (high V_ch cell) with "precision strike," eliminating the time required in traditional methods to wait for the weakest cell to be "randomly" selected.

[0061] Since the acceleration mechanism directly acts on the maximum FN tunneling electric field that the tunnel oxide layer is subjected to (which is the main source of durability failure), and avoids intriguing failure caused by excessive voltage, the failure mechanism induced in this embodiment (tunnel oxide layer trap accumulation, interface state generation) is highly consistent with the actual end-of-life mechanism, and the test results are more predictive and valuable for reference.

[0062] A small increase in the electric field E (due to the increase in (V_g - V_ch)) leads to an exponential increase in the FN current J (J ∝ exp(-B / E)), thus significantly accelerating the degradation rate of the tunnel oxide layer. Simultaneously, it eliminates the "long tail" of the stress distribution (high V_ch elements), making the failure distribution more concentrated and further shortening the time to expose the weakest element. The predicted acceleration factor is much higher than simply increasing V_erase or temperature.

[0063] Specifically, by applying the second negative voltage V_bl_neg and combining it with setting the third voltage V_dsl_smfs and the fourth voltage V_ssl_smfs to the weak conduction state or subthreshold conduction state, the channel potential (V_ch) of all memory cells in the target memory block is forced to be set to a uniform negative potential that is lower than the channel potential of the conventional erase operation during the accelerated erase operation. This increases and homogenizes the effective electric field stress ((V_g - V_ch) / T_ox) experienced by all memory cells during the erase operation, thereby achieving accelerated lifetime testing.

[0064] In the embodiments corresponding to S11 to S13, a precisely controlled negative bias of the bit lines and a weakly conducting gate voltage of the select transistor are applied during the erase operation. This forces the channel potential of all memory cells to reach a uniform and more negative value, thereby eliminating the natural distribution differences of electric field stress between cells. This ensures that each cell experiences a uniform electric field stress close to the theoretical maximum value during each erase operation. This method directly accelerates the intrinsic mechanism of tunnel oxide degradation and is expected to achieve an acceleration factor far exceeding existing methods, while maintaining high fidelity of failure modes. It provides a novel and effective solution for rapid reliability assessment and screening of NAND Flash. Its core innovation lies in the active and precise control of the channel potential to maximize and synchronize stress. Applying a precisely controlled negative bias of the bit lines and a weakly conducting gate voltage of the select transistor during the erase operation forces the channel potential of all memory cells to reach a uniform and more negative value, thereby eliminating the natural distribution differences of electric field stress between cells. This ensures that each cell experiences a uniform electric field stress close to the theoretical maximum value during each erase operation. This method directly accelerates the intrinsic mechanism of tunnel oxide layer degradation, and is expected to achieve an acceleration factor far exceeding that of existing methods, while maintaining high fidelity of failure modes. It provides a novel and effective solution for rapid reliability assessment and screening of NAND Flash. Its core innovation lies in the active and precise control of channel potential to maximize and synchronize stress.

[0065] S2: After performing the accelerated erase operation, perform a programming operation on the target storage block based on the accelerated test temperature; S3: After performing the programming operation, perform a read operation and error detection on the target storage block based on the accelerated test temperature; The lifespan of NAND Flash memory primarily depends on how many erase operations it can withstand. Each erase operation applies a strong electric field to the "small tunnels" (tunnel oxide layer) within the memory cells, "kicking" electrons out (Fowler-Nordheim tunneling). This strong electric field is like stretching a rubber band; excessive stretching causes the rubber band (oxide layer) to age, weaken, or even break (failure). Therefore, programming, reading, and error detection do not require additional accelerating voltages.

[0066] High temperatures exacerbate charge leakage and Vth instability, making cells that might be "qualified" at room temperature more prone to becoming "failed" at high temperatures. This helps to reach the preset failure criteria (cumulative failure rate) more quickly.

[0067] S4: Repeat steps S1 to S3 until a predetermined test termination condition is met; wherein, the test termination condition includes detecting that the number of uncorrectable memory cells exceeds a predetermined threshold.

[0068] Repeating steps S1 to S3 constitutes a cyclic process. Each complete S1->S2->S3 cycle represents one accelerated P / E cycle. The loop will not continue indefinitely; it will stop when a certain criterion is reached. Test termination conditions include, but are not limited to, detecting that the number of uncorrectable memory cells exceeds a predetermined threshold. In each or every S3 step (read and error detection) of a cycle, the number of memory cells that cannot be corrected by ECC in the target memory block is counted.

[0069] Set a predetermined threshold, which is an absolute number or a relative proportion (such as 1% of the total number of blocks). For example, if a block has 262,144 cells (256Kb x 8 bits / cell), the threshold can be set to 2621 (approximately 1%).

[0070] The test terminates when the number of non-correctable memory cells counted exceeds a predetermined threshold (for example, if the predetermined threshold is set to 1% of the total number of cells in the block, then the cumulative failure rate is 1%).

[0071] The failure cycle count is the number of P / E cycles (i.e., the number of times S1->S3 has been completed) that have been executed when the cumulative number of uncorrectable units first exceeds a predetermined threshold (i.e., the preset cumulative failure rate is reached).

[0072] In the embodiments corresponding to S1 to S4, the abstract accelerated testing operation is concretized into a clear and repeatable cyclic process: erase (high voltage + high temperature) -> program (high voltage + high temperature) -> read / detect (high temperature). This constitutes a complete P / E cycle under accelerated conditions.

[0073] Step 102: Count the number of failure cycles corresponding to the preset cumulative failure rate in the accelerated test operation; wherein, the number of failure cycles includes the occurrence of uncorrectable ECC errors, bit error rate exceeding the first failure threshold, original bit error rate exceeding the second failure threshold, or programming erase time exceeding the time threshold; The preset cumulative failure rate is a pre-defined failure criterion. It defines what percentage of memory cells or bits in a test block fail according to the defined criteria before the block is considered to have reached the end of its lifespan. For example, a cumulative failure rate of 1% or 0.1% is acceptable. This value is typically set based on product specifications and application requirements.

[0074] The failure cycle count records the total number of accelerated P / E cycles that the block underwent before reaching the preset cumulative failure rate. This value marks the "lifetime" under accelerated conditions.

[0075] The definition of failure includes, but is not limited to: ① "An uncorrectable ECC error has occurred": When the error correction code (ECC) engine is unable to correct errors in the read data, it indicates that the data has been corrupted to an unrecoverable degree. This is the most direct criterion for failure.

[0076] ② "Bit Error Rate (BER) exceeds the first failure threshold": BER is the proportion of erroneous bits to the total number of data bits. When the BER exceeds a pre-set safety threshold (the first failure threshold), the reliability is considered unacceptable, even if the ECC can still correct it.

[0077] ③ "Raw Bit Error Rate (RBER) exceeds the second failure threshold": RBER is the raw error rate before ECC error correction. It is an important indicator of early degradation and long-term reliability. When RBER exceeds its specific threshold (the second failure threshold), it indicates that the ECC error correction capability may soon be exhausted or its performance has significantly degraded.

[0078] ④ "Programming / Erase Time Exceeds Time Threshold": As the system ages, the time required for programming and erasing operations increases significantly. When the P / E time exceeds a set maximum value (time threshold), it means that the operational performance has degraded to an unacceptable level.

[0079] During accelerated testing, the aforementioned performance parameters of the target block are continuously monitored. When any failure criterion (or a combination thereof) reaches its preset threshold and accumulates to a preset "cumulative failure rate" (e.g., 1% of the cells in the entire block satisfy any failure condition), the number of P / E cycles completed at this point is recorded. This number is the quantized value of the "end of life" (N_acc) under accelerated conditions.

[0080] Step 103: Calculate the electric field acceleration factor and the temperature acceleration factor; The electric field acceleration factor quantifies the degree of lifetime acceleration caused by applying an electric field higher than the normal operating voltage. The temperature acceleration factor quantifies the degree of lifetime acceleration caused by testing at temperatures higher than the normal operating temperature. The acceleration effects of electric field and temperature are independent; therefore, the total acceleration factor AF_total is the product of the two. The total acceleration factor AF_total represents the effect of performing one P / E cycle under accelerated conditions, which is equivalent to performing AF_total P / E cycles under actual operating conditions.

[0081] Specifically, step 103 includes steps 1031 to 1034: Step 1031: Obtain the average effective electric field of the standard erase voltage and standard channel potential under actual operating conditions; The average effective electric field is used to determine the typical electric field strength that the memory cell tunnels through the oxide layer when the chip performs an erase operation under normal operating conditions. This is the basic reference value for subsequent calculations of the acceleration effect.

[0082] Under actual usage conditions, this refers to the normal operating voltage (Vpgm_use, Verase_use) and operating temperature (T_use).

[0083] The standard erase voltage is the rated voltage defined in the chip datasheet for use in erase operations during normal operation.

[0084] The standard channel voltage is the typical potential to which a NAND serial channel is biased during normal erase mode. Typically, to enable erasure, the P-well (or the entire substrate / well) is raised to a higher positive voltage (V_well_normal), and the channel potential is coupled to near V_well_normal through the state of the select transistor.

[0085] The average effective electric field (E_normal) is a calculated core physical quantity. It represents the average electric field strength applied to the tunnel oxide layer of the memory cell under normal operation and erase conditions. E_normal ≈ (V_well_normal - Verase_normal) / T_ox.

[0086] V_well_normal refers to the standard potential (high positive voltage) of the P-well / channel during erasure under actual usage conditions.

[0087] Verase_normal refers to the standard erase voltage applied to the word line (usually 0V or low voltage).

[0088] T_ox refers to the physical thickness of the tunneling oxide layer (a constant determined by the process).

[0089] The average electric field strength E_normal is obtained by dividing the voltage difference across the tunnel oxide layer (ΔV = V_well - Verase) by the oxide layer thickness (T_ox). This electric field drives FN tunneling erasure.

[0090] Step 1032: Obtain the effective electric field for accelerating the erasure operation and the effective barrier parameters of the tunnel oxide layer material; The effective electric field (E_acc) of the accelerated erase operation corresponds to the electric field strength in the accelerated erase mode.

[0091] Calculation formula: E_acc≈(V_well_acc - V_erase_acc) / T_ox; V_well_acc refers to the potential of the P-well / channel during accelerated aging (it may be the same as or different from the standard value, but it is usually set to a high positive voltage to achieve erasure). V_erase_acc refers to the first negative voltage (V_erase) applied to the word line during accelerated aging. The larger (more negative) |V_erase_acc| is, the larger the difference (V_well_acc - V_erase_acc) will be. T_ox refers to the thickness constant of the same tunneling oxide layer. The essence of acceleration lies in E_acc being significantly greater than E_normal (|E_acc| > |E_normal|), which is mainly achieved by applying a more negative V_erase_acc. A larger electric field E_acc is the core driving force for accelerated aging.

[0092] The effective barrier parameter (W) of the tunnel oxide layer material is an effective physical parameter describing the properties of the tunnel oxide layer (SiO2) material, and is closely related to the barrier height that electrons need to overcome during FN tunneling. Its unit is usually V or MV / cm (matched to the electric field unit).

[0093] In the simplified FN tunneling model, W can be understood as a combined parameter related to the effective barrier height (Φ_B) and effective electron mass (m_ox) of silicon oxide (W is usually proportional to (m_ox * Φ_B^{3 / 2})). It determines the sensitivity of the electric field to the tunneling probability (and thus the degradation rate).

[0094] This value is not a directly measured physical constant, but rather an empirical or "calibrated" value obtained by fitting accelerated life test data or device simulations. It characterizes the behavior of the oxide layer under specific failure mechanisms during a particular process. It serves as a crucial bridge for applying physical models to predict the reliability of actual products.

[0095] Step 1033: Substitute the average effective electric field, the effective electric field of the accelerated erasure operation, and the effective barrier parameter of the tunnel oxide layer material into function one to obtain the electric field acceleration factor; where, function one is: electric field acceleration factor = exp[W * (1 / |E_normal| - 1 / |E_acc|)], E_normal represents the average effective electric field, E_acc represents the effective electric field of the accelerated erasure operation, and W represents the effective barrier parameter of the tunnel oxide layer material; Using the three obtained parameters (E_normal, E_acc, W), the electric field acceleration factor (AF_E) is calculated through the physical model formula.

[0096] The core of the defined calculation formula for function one is: AF_E = exp[W * (1 / |E_normal| - 1 / |E_acc|)]; The principle of Function 1 is as follows: In FN tunneling, the tunneling current density J (proportional to the degradation / wear rate) is approximately related to the electric field E as follows: J∝exp(-constant / E). Therefore, the device lifetime under a constant electric field (or the number of P / E cycles N required to reach the same degree of degradation) can be considered to be inversely proportional to the tunneling current: N∝ 1 / J∝exp(constant / E).

[0097] Let N_normal be the number of cycles required to reach a specific degree of degradation under actual operating conditions (electric field E_normal).

[0098] Let N_acc_E be the number of cycles required to reach the same degree of degradation under accelerated conditions (electric field E_acc) (considering only the electric field acceleration part).

[0099] According to the model N_normal∝exp(constant / E_normal), similarly N_acc_E∝exp(constant / E_acc).

[0100] The electric field acceleration factor (AF_E) is defined as: AF_E = N_normal / N_acc_E (actual lifetime cycle count / accelerated lifetime cycle count).

[0101] Therefore, AF_E = [exp(constant / E_normal)] / [exp(constant / E_acc)] = exp[ (constant / E_normal) - (constant / E_acc) ].

[0102] This formula clearly quantifies the acceleration effect of electric field difference (E_acc > E_normal) on lifetime (AF_E > 1). The larger the W value, the more sensitive the oxide layer is to the electric field, and the more significant the acceleration effect (AF_E) brought about by the same increase in electric field. The larger E_acc is (the more negative the voltage, the larger |E_acc|), the smaller the (W / E_acc) term, resulting in a larger difference between (W / E_normal - W / E_acc), and ultimately a larger AF_E.

[0103] Step 1034: Calculate the temperature acceleration factor using the Arrhenius model.

[0104] The formula for calculating the temperature acceleration factor (AF_T) is: AF_T = exp[ (Ea / k) * (1 / T_use - 1 / T_acc) ] Ea represents the activation energy (unit: eV) of the failure mechanism. This is a key parameter characterizing the temperature sensitivity of the failure process. Different failure mechanisms (such as charge loss and interface state growth) may have different Ea values, requiring experimental fitting or empirical values.

[0105] k represents the Boltzmann constant. .

[0106] T_use represents the absolute temperature (in Kelvin) of the actual operating environment.

[0107] T_acc represents the absolute temperature (in K) of the accelerated testing environment. T_acc > T_use.

[0108] This model shows that at higher temperatures (T_acc), the failure process occurs at an exponentially faster rate. AF_T represents that one test at high temperature is equivalent to AF_T tests at room temperature. The larger the Ea value, the more significant the temperature acceleration effect.

[0109] In the embodiments corresponding to steps 1031 to 1034, the electric field acceleration factor is derived from the electric field under actual usage conditions and the electric field under accelerated testing conditions, as well as the effective barrier parameter of the tunnel oxide layer material. The temperature acceleration factor is calculated using the Arrhenius model, reflecting the effect of temperature changes on the aging rate. The calculation of these factors provides a scientific basis for further predicting the lifespan of NAND flash memory chips under actual usage conditions.

[0110] Step 104: Calculate the lifetime index based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate; wherein, the lifetime index is a test result, and the lifetime index represents the number of cycles when the cumulative failure rate of the NAND FLASH chip reaches the preset cumulative failure rate under actual use environment.

[0111] The accelerated test results are extrapolated to actual usage conditions to predict the true lifespan.

[0112] Specifically, step 104 includes steps 1041 to 1045: Step 1041: Fit the characteristic lifetime and shape parameters based on the Weibull distribution; The Weibull distribution is a lifetime distribution model, and its cumulative distribution function (CDF) is: F(t) = 1 - exp[-(t / η)^β] F(t) is the cumulative failure rate before time (or number of cycles) t.

[0113] η (Eta) is the characteristic lifetime. It is the lifetime (number of cycles) corresponding to a cumulative failure rate of 1 - 1 / e ≈ 63.2%. It is a scale parameter of the lifetime distribution, reflecting the "typical" lifetime level.

[0114] β (Beta) is the shape parameter. It determines the shape of the distribution. β < 1: Early failure period (failure rate decreases over time).

[0115] β = 1: random failure period (constant failure rate, exponential distribution).

[0116] β > 1: Wear failure period (failure rate increases over time). NAND Flash P / E wear is typically β > 1.

[0117] Based on the failure cycle count data obtained from accelerated testing (the number of failure P / E cycles of multiple samples when they reach a preset cumulative failure rate), statistical methods (such as maximum likelihood estimation (MLE) or least squares method) are used to determine the Weibull distribution parameters η_acc and β that best characterize these data.

[0118] The fitted η_acc is the Weibull characteristic lifetime under accelerated testing conditions. β describes the characteristics of the failure mode (such as the concentration of wear rate). It is generally assumed that accelerated testing does not change the value of β, and it reflects the nature of the failure mechanism.

[0119] Specifically, step 1041 includes steps A1 to A7: Step A1: Obtain the first cycle number corresponding to the first occurrence of an uncorrectable error in multiple NAND flash memories; Accelerated lifetime testing is performed on n identical NAND Flash chips (or target memory blocks) (the number n = "the number of multiple NAND flash memory chips").

[0120] Failure definition: When a test unit (chip or block) first encounters the test termination condition defined in S4 (i.e., "the number of uncorrectable memory units detected exceeds a predetermined threshold"), the unit is considered to have failed.

[0121] Record the number of P / E cycles that the failed element experienced at the time of failure. This number of cycles is called the failure lifetime or "first cycle number" (t_i) of the element.

[0122] These n failure lifetimes {t1, t2, ..., t} n This constitutes the completely failed sample data (all samples are failed) used for Weibull fitting.

[0123] Step A2: Arrange the first cycle counts of each of the multiple NAND flash memory devices from largest to smallest to obtain the order corresponding to each first cycle count; Sort these n "first cycle counts" (failure lifetimes t_i) in descending order. The sorting result is: t_{(1)} ≤ t_{(2)} ≤ ... ≤ t_{(n)}. Where t_{(i)} represents the lifetime of the i-th failure (i=1 is the earliest failure, i=n is the latest failure). i is the sequence number corresponding to the i-th failure data point after sorting.

[0124] Step A3: Calculate the median rank corresponding to each first loop count based on the order corresponding to each first loop count and the number of the plurality of NAND flash memories; where F = (i - 0.3) / (n + 0.4), F represents the median rank, i represents the order of the first loop count, and n represents the number of the plurality of NAND flash memories; Estimate the cumulative failure probability (F) for each failure lifetime data point. This is an estimate of the empirical distribution function (EDF).

[0125] The median rank is a commonly used formula for estimating the empirical cumulative distribution function (CDF). It provides the best median unbiased estimate of the cumulative failure probability corresponding to the i-th failure observation in an n-sample life test.

[0126] Formula: F_i = (i - 0.3) / (n + 0.4).

[0127] F_i represents the median rank (estimated cumulative failure probability) corresponding to the i-th failure point.

[0128] i represents the rank of the failure point, i = 1, 2, ..., n.

[0129] n represents the total number of samples (total number of test units).

[0130] The constants 0.3 and 0.4 are empirical constants designed to optimize the unbiasedness of the estimate, especially when the sample size n is small.

[0131] F_i represents our estimate that at time t_{(i)}, approximately F_i * 100% of similar products will fail. For example, with i=1, n=10, F1 = (1-0.3) / (10+0.4) ≈ 0.0673, meaning that we estimate approximately 6.73% of products will fail at the first failure.

[0132] Step A4: Calculate the Weibull x-coordinate and Weibull y-coordinate based on the number of each first loop and the corresponding number of first loops; where X = ln(number of first loops), Y = ln[ln(1 / 1-F)], X represents the Weibull x-coordinate, and Y represents the Weibull y-coordinate; The Weibull distribution and data are linearized to facilitate linear regression fitting.

[0133] The Weibull cumulative distribution function (CDF) is: F(t) = 1 - exp[-(t / η)^β]; Transformation: 1 - F(t) = exp[-(t / η)^β]; Taking the reciprocal: 1 / (1 - F(t)) = exp[(t / η)^β]; Take the natural logarithm twice: ln[ 1 / (1 - F(t)) ] = (t / η)^β; ln{ ln[ 1 / (1 - F(t)) ]} = β * ln(t) - β * ln(η); Linear equation: Let: Y = ln{ ln[ 1 / (1 - F(t)) ]} X = ln(t) B = β (slope) C = -β * ln(η) (intercept) The CDF of the Weibull distribution can then be expressed as a linear equation: Y = B * X + C Calculate coordinates: For each failed data point (t_{(i)}, F_i): The Weibull x-coordinate X_i = ln(t_{(i)}) is the natural logarithm of the failure lifetime.

[0134] The Weibull ordinate Y_i = ln{ ln[ 1 / (1 - F_i) ]} : the double natural logarithmic transformation value obtained by calculating the median rank F_i.

[0135] Step A5: Fit the line Y = BX + C using the least squares method to obtain the slope β and intercept C; Use linear regression to determine the parameters B and C of the straight line.

[0136] Core logic: There are now n data points: (X_i, Y_i) for i=1 to n.

[0137] Least Squares: Find a straight line Y = B * X + C such that the sum of the squares of the perpendicular distances (residuals) from all data points to this line is minimized.

[0138] The slope B and the intercept C of the fitted line.

[0139] Step A6: Use the slope B as a shape parameter; Based on the linear equation Y = β * X + C derived in step A4, the slope B is the shape parameter β.

[0140] Shape parameter β (Beta): As mentioned earlier, β determines the shape of the failure distribution. β < 1: Early failure period (decreased failure rate).

[0141] β ≈ 1: random failure period (constant failure rate, exponential distribution).

[0142] β > 1: Wear failure period (increased failure rate, typical characteristics of NAND P / E wear).

[0143] The larger the β value, the more concentrated the failure time (the smaller the variance), and the faster the wear.

[0144] Step A7: Substitute the shape parameter B and intercept C into function two to obtain the characteristic lifetime; where function two is: characteristic lifetime = e -C / B.

[0145] Calculate the characteristic lifetime η(Eta) of the Weibull distribution.

[0146] Core logic and derivation: Based on the linear equation relationship C = -β * ln(η) derived in step A4, solve the equation to find η: C = -β * ln(η); ln(η) = -C / β; η = exp(-C / B) (because B = β); As mentioned earlier, the characteristic lifetime η is the lifetime (P / E cycles) corresponding to a cumulative failure rate of 1 - 1 / e ≈ 63.2%. It is a scaling parameter of the lifetime distribution, reflecting the "typical" lifetime level.

[0147] The η (η_acc) calculated here is the characteristic lifetime under accelerated testing conditions. It will be multiplied by the total acceleration factor AF_total in a subsequent step to obtain the predicted actual characteristic lifetime η_normal = η_acc * AF_total.

[0148] In the embodiments corresponding to steps A1 to A7, the lifetime of NAND flash memory can be predicted more accurately by precisely fitting the distribution parameters. Characteristic lifetime and shape parameters provide a reliable basis for subsequent lifetime prediction. Statistical analysis and fitting methods can reduce the time and number of samples required for actual testing. A relatively accurate lifetime prediction can be obtained in the initial testing stage.

[0149] Step 1042: Multiply the electric field acceleration factor and the temperature acceleration factor to obtain the total acceleration factor; The accelerating effects of electric field stress (leading to FN tunneling degradation) and temperature stress (leading to thermal activation degradation) on device aging are separable and independent. Therefore, the total acceleration factor is the product of these two factors. AF_total represents the damage caused by one P / E cycle under accelerated conditions, equivalent to AF_total P / E cycles under actual operating conditions.

[0150] Step 1043: Multiply the total acceleration factor by the characteristic lifetime to obtain the accelerated characteristic lifetime; Accelerated feature lifetime = η_acc * AF_total; η_acc refers to the characteristic lifetime (number of cycles) obtained by fitting under accelerated testing conditions.

[0151] AF_total refers to the total acceleration factor.

[0152] η_acc is the number of P / E cycles required to achieve a cumulative failure rate of approximately 63.2% under accelerated conditions.

[0153] Because one P / E cycle under accelerated conditions is equivalent to the damage of AF_total cycles under actual conditions.

[0154] Therefore, the cumulative damage (63.2%) achieved under accelerated conditions after η_acc cycles is equivalent to the cumulative damage (63.2%) achieved under actual conditions after η_acc * AF_total cycles.

[0155] Therefore, η_normal = η_acc * AF_total is the predicted number of P / E cycles required to achieve a cumulative failure rate of approximately 63.2% under actual use conditions, which is the characteristic lifetime under actual use conditions.

[0156] Step 1044: Obtain the current cumulative failure rate under the test termination condition; The current cumulative failure rate F_acc refers to the actual cumulative failure rate of the target memory block when the test terminates due to reaching the aforementioned threshold, which is X%. For example, if the threshold is set to 1%, then F_acc = 0.01 (1%). If the threshold is set to 5%, then F_acc = 0.05 (5%). This value (F_acc) is the failure rate corresponding to the test stopping point.

[0157] Step 1045: Substitute the shape parameters, the accelerated feature lifetime, and the current cumulative failure rate into a preset function to obtain a lifetime index; wherein, the lifetime index represents the number of cycles required to reach a cumulative failure rate of 1%, and the preset function is: lifetime index = η_normal * [-ln(1 - F_acc)] (1 / B) η_normal represents the accelerated feature lifetime, F_acc represents the current cumulative failure rate, and B represents the shape parameter.

[0158] From the characteristic lifetime (η_normal) and the test termination failure rate (F_acc), accurately predict the number of cycles (lifetime metric) required to achieve a lower, engineering-critical target cumulative failure rate (F_acc=1%) under real-world usage conditions. Lifetime metric (N_use_target) = η_normal * [ -ln(1 - F_acc) ]^(1 / β).

[0159] η_normal is the characteristic lifetime (predicted value) under actual usage conditions calculated in the previous step.

[0160] F_acc refers to the target cumulative failure rate for the predicted lifetime. F_acc = 0.01 (i.e., 1%). ("The lifetime metric is used to represent the number of cycles required to reach a cumulative failure rate of 1%").

[0161] β is a Weibull shape parameter obtained from the accelerated test data (assuming it remains unchanged under actual use conditions).

[0162] Preset function derivation process: The Weibull cumulative failure probability function is: F(t) = 1 - exp[-(t / η)^β]. The goal is to find t (i.e., N_use_target, the lifetime index) when F(t) = F_target (here F_target = 1% = 0.01).

[0163] Transforming the formula for F(t): 1 - F(t) = exp[-(t / η)^β]; Taking the natural logarithm: ln(1 - F(t)) = -(t / η)^β; Multiply both sides by -1: -ln(1 - F(t)) = (t / η)^β; Raising both sides to the power of 1 / β: [ -ln(1 - F(t)) ]^(1 / β) = t / η; Solve for t: t = η * [ -ln(1 - F(t)) ]^(1 / β); Substitute the parameters under actual usage conditions: t -> N_use_target (target lifetime metric); η -> η_normal (characteristic lifetime under actual usage conditions); F(t) -> F_target = 0.01 (target cumulative failure rate 1%); Therefore, the preset function is obtained as N_use_target = η_normal * [ -ln(1 - 0.01) ]^(1 / β).

[0164] In the embodiments corresponding to steps 1041 to 1045, a simpler, more scientific, and more robust method for predicting lifespan is provided, which is especially suitable for predicting long lifespans with low failure rates (e.g., 1%), which is very important in engineering (e.g., setting SSD durability indicators).

[0165] In the embodiments corresponding to steps 101 to 104, the present invention employs a preset test mode to perform accelerated testing on the target memory block in the NAND FLASH chip. The preset test mode simulates various operating conditions in actual use environments, ensuring that the test results are more representative and accurate. During the accelerated testing process, the number of failure cycles corresponding to the preset cumulative failure rate is statistically analyzed, including various failure modes such as uncorrectable ECC errors, bit error rate exceeding the first failure threshold, original bit error rate exceeding the second failure threshold, or programming / erase time exceeding the time threshold. By comprehensively analyzing these failure modes, the reliability of the NAND FLASH chip can be more comprehensively evaluated. The present invention fully considers the impact of electric field acceleration factor and temperature acceleration factor on the lifespan of the NAND FLASH chip by calculating these two important acceleration factors. In the lifespan index calculation process, combining these acceleration factors allows for more accurate simulation of operating conditions in actual use environments, improving the accuracy of lifespan prediction. Based on the electric field acceleration factor, temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate, the calculated lifespan index accurately represents the number of cycles required for the NAND FLASH chip to reach the preset cumulative failure rate in actual use environments. This metric not only helps predict the actual lifespan of a chip but also provides crucial data support for chip optimization and improvement. Traditional NAND flash chip lifespan testing methods are time-consuming, while this invention accelerates the testing process, enabling lifespan testing to be completed in a shorter time. This significantly improves testing efficiency and reduces testing costs, providing a more efficient solution for chip manufacturing and applications.

[0166] like Figure 2 This invention provides a testing device for NAND flash chips. Please refer to [link / reference]. Figure 2 , Figure 2 A schematic diagram of a testing apparatus for a NAND flash chip provided by the present invention is shown, as follows. Figure 2 The test apparatus for a NAND flash chip shown includes: Test unit 21 is used to perform accelerated testing on the target memory block in NAND flash memory based on a preset test mode; The statistics unit 22 is used to count the number of failure cycles corresponding to the preset cumulative failure rate in the accelerated testing operation; wherein, the number of failure cycles includes the occurrence of an uncorrectable ECC error, the bit error rate exceeding the first failure threshold, the original bit error rate exceeding the second failure threshold, or the programming erase time exceeding the time threshold. The first calculation unit 23 is used to calculate the electric field acceleration factor and the temperature acceleration factor. The second calculation unit 24 is used to calculate the lifetime index based on the electric field acceleration factor, the temperature acceleration factor and the number of failure cycles corresponding to the preset cumulative failure rate; wherein, the lifetime index is a test result, and the lifetime index represents the number of cycles when the cumulative failure rate of the NAND FLASH chip reaches the preset cumulative failure rate under actual use environment.

[0167] This invention provides a testing device for NAND flash chips. The invention employs a preset test mode to accelerate the testing of target memory blocks within the NAND flash chip. The preset test mode simulates various operating conditions in real-world environments, ensuring more representative and accurate test results. During the accelerated testing process, the number of failure cycles corresponding to a preset cumulative failure rate is statistically analyzed, including various failure modes such as uncorrectable ECC errors, bit error rate exceeding a first failure threshold, original bit error rate exceeding a second failure threshold, or programming / erase time exceeding a time threshold. By comprehensively analyzing these failure modes, the reliability of the NAND flash chip can be more comprehensively evaluated. This invention fully considers the impact of electric field acceleration factors and temperature acceleration factors on the lifespan of the NAND flash chip by calculating these two important acceleration factors. In the lifespan index calculation process, combining these acceleration factors allows for more accurate simulation of operating conditions in real-world environments, improving the accuracy of lifespan prediction. Based on the electric field acceleration factor, temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate, the calculated lifespan index accurately represents the number of cycles required for the NAND flash chip to reach the preset cumulative failure rate under real-world operating conditions. This metric not only helps predict the actual lifespan of a chip but also provides crucial data support for chip optimization and improvement. Traditional NAND flash chip lifespan testing methods are time-consuming, while this invention accelerates the testing process, enabling lifespan testing to be completed in a shorter time. This significantly improves testing efficiency and reduces testing costs, providing a more efficient solution for chip manufacturing and applications.

[0168] Figure 3 This is a schematic diagram of a terminal device provided in an embodiment of the present invention. Figure 3 As shown, a terminal device 3 in this embodiment includes: a processor 30, a memory 31, and a computer program 32 stored in the memory 31 and executable on the processor 30, such as a test method program for a NAND flash chip. When the processor 30 executes the computer program 32, it implements the steps in the various NAND flash chip test method embodiments described above, for example... Figure 1 Steps 101 to 104 are shown. Alternatively, when the processor 30 executes the computer program 32, it implements the functions of each unit in the above-described device embodiments, for example... Figure 2 The function of the unit shown.

[0169] For example, the computer program 32 can be divided into one or more units, which are stored in the memory 31 and executed by the processor 30 to complete the present invention. The one or more units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program 32 in the terminal device 3. For example, the specific functions of each unit of the computer program 32 can be divided as follows: The test unit is used to perform accelerated testing operations on the target memory block in the NAND flash memory based on a preset test mode. The statistics unit is used to count the number of failure cycles corresponding to the preset cumulative failure rate in the accelerated testing operation; wherein, the number of failure cycles includes the occurrence of an uncorrectable ECC error, the bit error rate exceeding a first failure threshold, the original bit error rate exceeding a second failure threshold, or the programming erase time exceeding a time threshold; The first calculation unit is used to calculate the electric field acceleration factor and the temperature acceleration factor. The second calculation unit is used to calculate the lifetime index based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate; wherein, the lifetime index is a test result, and the lifetime index represents the number of cycles when the cumulative failure rate of the NAND FLASH chip reaches the preset cumulative failure rate under actual use environment.

[0170] The terminal device includes, but is not limited to, a processor 30 and a memory 31. Those skilled in the art will understand that... Figure 3 This is merely an example of a terminal device 3 and does not constitute a limitation on a terminal device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, the terminal device may also include input / output devices, network access devices, buses, etc.

[0171] The processor 30 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0172] The memory 31 can be an internal storage unit of the terminal device 3, such as a hard disk or memory of the terminal device 3. The memory 31 can also be an external storage device of the terminal device 3, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the terminal device 3. Furthermore, the memory 31 can include both internal and external storage units of the terminal device 3. The memory 31 is used to store the computer program and other programs and data required by the roaming control device. The memory 31 can also be used to temporarily store data that has been output or will be output.

[0173] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0174] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0175] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this invention. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0176] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0177] This invention provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the above-described method embodiments.

[0178] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0179] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0180] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0181] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0182] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units.

[0183] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0184] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0185] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0186] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0187] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0188] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A testing method for a NAND flash chip, characterized in that, The testing methods for the NAND flash chip include: Accelerated testing is performed on the target memory block in the NAND flash memory based on the preset test mode. The number of failure cycles corresponding to the preset cumulative failure rate during the accelerated testing operation is counted; wherein, the number of failure cycles includes the occurrence of uncorrectable ECC errors, bit error rate exceeding the first failure threshold, original bit error rate exceeding the second failure threshold, or programming erase time exceeding the time threshold; Calculate the electric field acceleration factor and the temperature acceleration factor; The lifetime index is calculated based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate; wherein, the lifetime index is a test result, and the lifetime index represents the number of cycles when the cumulative failure rate of the NAND FLASH chip reaches the preset cumulative failure rate under actual use environment.

2. The testing method for the NAND flash chip as described in claim 1, characterized in that, The steps for performing accelerated testing on the target memory block in NAND flash memory based on a preset test mode include: S1: At the accelerated test temperature, perform accelerated erasure operation on the target memory block in the NAND flash memory based on the preset test mode; S2: After performing the accelerated erase operation, perform a programming operation on the target storage block based on the accelerated test temperature; S3: After performing the programming operation, perform a read operation and error detection on the target storage block based on the accelerated test temperature; S4: Repeat steps S1 to S3 until a predetermined test termination condition is met; wherein, the test termination condition includes detecting that the number of uncorrectable memory cells exceeds a predetermined threshold.

3. The testing method for the NAND flash chip as described in claim 2, characterized in that, The accelerated testing temperature includes 105 degrees Celsius.

4. The testing method for the NAND flash chip as described in claim 2, characterized in that, S1 includes: Apply a first negative voltage V_erase to all word lines of the target memory block in the NAND flash memory; During the application of the first negative voltage V_erase, a second negative voltage V_bl_neg is applied to all bit lines associated with the target memory block; During the application of the first negative voltage V_erase, the gate voltage V_dsl of the drain select transistor of the target memory block is set to a third voltage V_dsl_smfs, and the gate voltage V_ssl of the source select transistor of the target memory block is set to a fourth voltage V_ssl_smfs; wherein, the third voltage V_dsl_smfs and the fourth voltage V_ssl_smfs are used to put the drain select transistor and the source select transistor into a weak conduction state or a subthreshold conduction state; the weak conduction state or the subthreshold conduction state refers to a voltage negative offset between 50mV and 300mV.

5. The testing method for the NAND flash chip as described in claim 1, characterized in that, The steps for calculating the electric field acceleration factor and the temperature acceleration factor include: Obtain the average effective electric field of the standard erase voltage and standard channel potential under actual operating conditions; To obtain the effective electric field for accelerating the erasure operation and the effective barrier parameters of the tunnel oxide layer material; Substituting the average effective electric field, the effective electric field of the accelerated erasure operation, and the effective barrier parameter of the tunnel oxide layer material into function one, we obtain the electric field acceleration factor; where function one is: electric field acceleration factor = exp[W * (1 / |E_normal| - 1 / |E_acc|)], E_normal represents the average effective electric field, E_acc represents the effective electric field of the accelerated erasure operation, and W represents the effective barrier parameter of the tunnel oxide layer material; The temperature acceleration factor was calculated using the Arrhenius model.

6. The testing method for the NAND flash chip as described in claim 1, characterized in that, The step of calculating the lifetime index based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate includes: Based on the Weibull distribution, characteristic lifetime and shape parameters are fitted; Multiply the electric field acceleration factor and the temperature acceleration factor together to obtain the total acceleration factor; Multiplying the total acceleration factor by the characteristic lifetime yields the accelerated characteristic lifetime; Obtain the current cumulative failure rate under the test termination condition; Substituting the shape parameters, the accelerated feature lifetime, and the current cumulative failure rate into a preset function yields a lifetime index; wherein, the lifetime index represents the number of cycles required to reach a cumulative failure rate of 1%, and the preset function is: lifetime index = η_normal * [-ln(1 - F_acc)] (1 / B) η_normal represents the accelerated feature lifetime, F_acc represents the current cumulative failure rate, and B represents the shape parameter.

7. The testing method for the NAND flash chip as described in claim 6, characterized in that, The steps for fitting the characteristic lifetime and shape parameters based on the Weibull distribution include: Obtain the first cycle number corresponding to the first occurrence of an uncorrectable error in multiple NAND flash memories; Arrange the first loop counts corresponding to each of the multiple NAND flash memory devices from largest to smallest to obtain the order corresponding to each first loop count; Based on the order corresponding to each first loop count and the number of the plurality of NAND flash memories, calculate the median rank corresponding to each first loop count; where F = (i - 0.3) / (n + 0.4), F represents the median rank, i represents the order of the first loop count, and n represents the number of the plurality of NAND flash memories; Calculate the Weibull x-coordinate and Weibull y-coordinate based on the number of each first loop and the corresponding number of the first loop; where X = ln(number of first loops), Y = ln[ln(1 / 1-F)], X represents the Weibull x-coordinate, and Y represents the Weibull y-coordinate; By fitting the straight line Y = BX + C using the least squares method, the slope β and intercept C are obtained. The slope B is used as a shape parameter; Substituting the shape parameter B and the intercept C into function two, we obtain the characteristic lifetime; where function two is: characteristic lifetime = e -C / B .

8. A testing device for NAND flash chips, characterized in that, The testing apparatus for the NAND flash chip includes: The test unit is used to perform accelerated testing operations on the target memory block in the NAND flash memory based on a preset test mode. The statistics unit is used to count the number of failure cycles corresponding to the preset cumulative failure rate in the accelerated testing operation; wherein, the number of failure cycles includes the occurrence of an uncorrectable ECC error, the bit error rate exceeding a first failure threshold, the original bit error rate exceeding a second failure threshold, or the programming erase time exceeding a time threshold; The first calculation unit is used to calculate the electric field acceleration factor and the temperature acceleration factor. The second calculation unit is used to calculate the lifetime index based on the electric field acceleration factor, the temperature acceleration factor, and the number of failure cycles corresponding to the preset cumulative failure rate; wherein, the lifetime index is a test result, and the lifetime index represents the number of cycles when the cumulative failure rate of the NAND FLASH chip reaches the preset cumulative failure rate under actual use environment.

9. A terminal device, characterized in that, The terminal device includes: a memory, a processor, and a test method program for a NAND flash chip stored in the memory and executable on the processor, wherein the test method program for the NAND flash chip is configured to implement the steps in the test method for the NAND flash chip as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps in the test method for the NAND flash chip as described in any one of claims 1 to 7.

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