Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes: a first semiconductor chip; a second semiconductor chip attached to an upper surface of the first semiconductor chip; a silicon heat sink thermally connected to at least one of the first semiconductor chip and the second semiconductor chip; and a molding member configured to surround the first semiconductor chip and the second semiconductor chip and expose an upper surface of the silicon heat sink.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on November 22, 2019, with application number 201911163580.5 and title "Semiconductor Packaging and Method for Manufacturing Semiconductor Packaging". Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application 10-2018-0146611, filed on November 23, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor package and a method for manufacturing the semiconductor package, and more specifically, to a semiconductor package having excellent heat dissipation characteristics and high reliability and which can be manufactured using a simple process, and a method for manufacturing the semiconductor package. Background Technology

[0004] Since logic chips typically generate a significant amount of heat during operation, their performance can be limited by temperature. Therefore, improvements related to heat dissipation in the semiconductor package that includes the logic chip are needed. Summary of the Invention

[0005] The present invention provides a semiconductor package that has excellent heat dissipation characteristics and high reliability, and can be manufactured using a simple process.

[0006] The present invention also provides a method for manufacturing semiconductor packages with excellent heat dissipation characteristics and high reliability using a simple process.

[0007] Furthermore, the present invention provides an electronic system including a semiconductor package.

[0008] According to one aspect of the present invention, a semiconductor package is provided. The semiconductor package includes: a first semiconductor chip; a second semiconductor chip attached to a upper surface of the first semiconductor chip; a silicon heat sink thermally connected to at least one of the first and second semiconductor chips; and a molding member configured to surround the first and second semiconductor chips and expose the upper surface of the silicon heat sink. The silicon heat sink is not electrically connected to either the first or second semiconductor chip included in the semiconductor package.

[0009] According to another aspect of the present invention, a semiconductor package is provided. The semiconductor package includes: a package substrate; a logic chip mounted on the package substrate; at least one memory chip attached to the logic chip; a molding member configured to encapsulate the logic chip and the memory chip; and a silicon heat sink attached to the upper surface of the logic chip, at least a portion of the silicon heat sink being exposed outside the package.

[0010] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided. The method includes: mounting a logic chip on a package substrate; attaching a memory chip to the logic chip on an exposed portion of the upper surface of the logic chip; attaching a silicon heat sink to the upper surface of the logic chip; and forming a molding member to encapsulate the logic chip and the memory chip, while exposing the upper surface of the silicon heat sink to the outside of the package.

[0011] According to another aspect of the present invention, an electronic system is provided. The electronic system includes one or more of the following: a controller; input / output (I / O) circuitry configured to input or output data; a memory configured to store data; an interface configured to send data to and receive data from an external device; and a bus configured to connect the controller, I / O circuitry, memory, and / or interface, such that the controller, I / O circuitry, memory, and / or interface communicate with each other. The controller and memory may be connected within a semiconductor package having a silicon heat sink. Attached Figure Description

[0012] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a plan view of a semiconductor package according to an embodiment;

[0014] Figure 2A It is the edge of semiconductor packaging Figure 1 A cross-sectional view taken from line IIA-IIA';

[0015] Figure 2B It is the edge of semiconductor packaging Figure 1 A cross-sectional view taken from line IIB-IIB';

[0016] Figure 3 yes Figure 2A The diagram shows an enlarged view of region III of the die-attached film (DAF);

[0017] Figure 4 This is a plan view of a semiconductor package according to an embodiment;

[0018] Figure 5A It is the edge of semiconductor packaging Figure 4A cross-sectional view of the line VA-VA';

[0019] Figure 5B It is the edge of semiconductor packaging Figure 4 A cross-sectional view of line VB-VB';

[0020] Figure 6 This is a plan view of a semiconductor package according to an embodiment;

[0021] Figure 7 It is the edge of semiconductor packaging Figure 6 A cross-sectional view taken from line VIIA-VIIA';

[0022] Figure 8 This is a plan view of a semiconductor package according to an embodiment;

[0023] Figure 9A It is the edge of semiconductor packaging Figure 8 A cross-sectional view taken from line IXA-IXA';

[0024] Figure 9B It is the edge of semiconductor packaging Figure 8 A cross-sectional view taken from line IXB-IXB';

[0025] Figure 10 This is a plan view of a semiconductor package according to an embodiment;

[0026] Figure 11A It is the edge of semiconductor packaging Figure 10 A cross-sectional view taken from line XIA-XIA';

[0027] Figure 11B It is the edge of semiconductor packaging Figure 10 A cross-sectional view taken from line XIB-XIB';

[0028] Figure 12 This is a plan view of a semiconductor package according to an embodiment;

[0029] Figure 13A It is the edge of semiconductor packaging Figure 4 A cross-sectional view taken from line XIIIA-XIIIA';

[0030] Figure 13B It is the edge of semiconductor packaging Figure 4 A cross-sectional view taken from line XIIIB-XIIIB';

[0031] Figures 14A to 14C This is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment;

[0032] Figure 15A and Figure 15BThis is a cross-sectional view illustrating a method for manufacturing a semiconductor package according to an embodiment; and

[0033] Figure 16 This is a block diagram of an electronic system according to an embodiment. Detailed Implementation

[0034] Figure 1 This is a plan view of the semiconductor package 100 according to an embodiment. Figure 2A It is the edge of semiconductor package 100 Figure 1 A cross-sectional view taken from line IIA-IIA'. Figure 2B It is the edge of semiconductor package 100 Figure 1 A cross-sectional view taken from line IIB-IIB'.

[0035] Reference Figure 1 , Figure 2A and Figure 2B Semiconductor package 100 includes a first semiconductor chip 110 mounted on a package substrate 101. One or more second semiconductor chips 120 are located on the first semiconductor chip 110. Furthermore, one or more silicon heat sinks 130 are thermally connected to at least one of the first semiconductor chip 110 and the second semiconductor chip 120. In this example, the silicon heat sink 130 includes a first silicon heat sink 131 and a second silicon heat sink 132. The first semiconductor chip 110, the second semiconductor chip 120, and the first and second silicon heat sinks 131 and 132 may be surrounded by a molding member 150. Portions of the first and second silicon heat sinks 131 and 132 may be exposed relative to the molding member 150.

[0036] The packaging substrate 101 may include, for example, a printed circuit board (PCB). In some embodiments, the packaging substrate 101 may include a multilayer PCB. The packaging substrate 101 may include a base layer, top pads and bottom pads formed on the upper and lower surfaces of the base layer, respectively, and a solder mask layer configured to expose the top pads and bottom pads.

[0037] In some embodiments, the base plate layer may include at least one material selected from phenolic resins, epoxy resins, and polyimides. For example, the base plate layer may include at least one material selected from flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy resin / polyphenylene ether, bismaleimide triazine (BT), thermosetting resins, cyanate esters, polyimides, and liquid crystal polymers.

[0038] Interconnect patterns and conductive vias can be disposed on the upper and lower surfaces of the base plate and / or within the base plate. Interconnect patterns can electrically connect top pads to bottom pads, and conductive vias can electrically connect the interconnect patterns. Interconnect patterns can include, for example, electrolytically deposited (ED) copper foil, rolled and annealed (RA) copper foil, stainless steel foil, aluminum foil, ultrathin copper foil, sputtered copper, and / or copper alloys. Conductive vias can be formed to penetrate at least a portion of the base plate. In some embodiments, conductive vias can include copper, nickel, stainless steel, or beryllium copper.

[0039] Terminal 101b may be disposed on the bottom pad to electrically connect the package substrate 101 to an external device. Terminal 101b may be, for example, a bump, solder ball, or conductive filler. For example, terminal 101b may include tin (Sn) as a main component and include materials selected from silver (Ag), copper (Cu), gold (Au), zinc (Zn), bismuth (Bi), indium (In), lead (Pb), chromium (Cr), platinum (Pt), tungsten (W), titanium (Ti), iridium (Ir), nickel (Ni), cobalt (Co), iron (Fe), phosphorus (P), and alloys thereof, but the inventive concept is not limited thereto.

[0040] The first semiconductor chip 110 may be a logic chip. For example, the first semiconductor chip 110 may be a baseband chip (e.g., a modem chip), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0041] The first semiconductor chip 110 can be mounted on the packaging substrate 101 in a flip-chip manner. In this case, the active surface of the first semiconductor chip 110 can face the packaging substrate 101, and the first semiconductor chip 110 can be electrically connected to the packaging substrate 101 through the chip interconnect member 110b.

[0042] The chip connection member 110b can be, for example, a bump, solder ball, or conductive filler. For example, the chip connection member 110b may include tin (Sn) as a main component and include materials selected from silver (Ag), copper (Cu), gold (Au), zinc (Zn), bismuth (Bi), indium (In), lead (Pb), chromium (Cr), platinum (Pt), tungsten (W), titanium (Ti), iridium (Ir), nickel (Ni), cobalt (Co), iron (Fe), phosphorus (P), and alloys thereof, but the inventive concept is not limited thereto.

[0043] In some embodiments, an underfill layer may also be disposed beneath the first semiconductor chip 110. The underfill layer can be formed by a capillary underfill method using epoxy resin. In another embodiment, a non-conductive film (NCF) can be used to form the underfill layer.

[0044] Each second semiconductor chip 120 may be a memory chip. For example, each second memory chip 120 may be a dynamic random access memory (DRAM) chip, a static RAM (SRAM) chip, a flash memory chip, an electrically erasable programmable ROM (EEPROM) chip, a phase-change RAM (PRAM) chip, a magnetic RAM (MRAM) chip, or a resistive RAM (RRAM) chip. Specifically, the second semiconductor chip 120 may include multiple memory chips, such as a first memory chip 120a and a second memory chip 120b. The first memory chip 120a and the second memory chip 120b may be arranged in a lateral direction (e.g., ...). Figure 1 and Figure 2B (As shown), however, those skilled in the art will understand that the first memory chip 120a and the second memory chip 120b can be stacked in a vertical direction. Furthermore, the first memory chip 120a and the second memory chip 120b can be arranged such that the active surfaces of the first memory chip 120a and the second memory chip 120b face upwards, i.e., facing the silicon heat sink 132 described below. In other words, the first memory chip 120a and the second memory chip 120b can be oriented such that the active surfaces of the first memory chip 120a and the second memory chip 120b face away from the first semiconductor chip 110.

[0045] In some embodiments, the ends of the first memory chip 120a and / or the second memory chip 120b may be suspended on the chip (or adapter board) to which they are mounted, forming suspension portions. Here, such suspension portions protrude beyond the side surface of the first semiconductor chip 110. Bonding pads 120p to be connected to the package substrate 101 may be provided in the suspension portions of the first memory chip 120a and / or the second memory chip 120b. Semiconductor devices in the first memory chip 120a and / or the second memory chip 120b may be electrically connected to the package substrate 101 via the bonding pads 120p. The bonding pads 120p may be electrically connected to the package substrate 101 via bonding wires 120w.

[0046] The bonding wire 120w may include, but is not limited to, gold (Au), copper (Cu), palladium (Pd), silver (Ag), platinum (Pt), aluminum (Al), beryllium (B), yttrium (Y), zirconium (Zr), calcium (Ca), nickel (Ni), iron (Fe), cobalt (Co), bismuth (Bi), phosphorus (P), ruthenium (Ru), rhodium (Rh) and alloys of at least two of these.

[0047] The first memory chip 120a and the second memory chip 120b can be electrically connected to the first semiconductor chip 110 via bonding wire 120w and packaging substrate 101, and send electrical signals to the first semiconductor chip 110 and receive electrical signals from the first semiconductor chip 110.

[0048] The first memory chip 120a and the second memory chip 120b can be attached to the first semiconductor chip 110 using a die attach film (DAF) 120f.

[0049] The first silicon heat sink 131 and the second silicon heat sink 132 may be thermally connected to at least one of the first semiconductor chip 110 and the second semiconductor chip 120. It should be understood that when two objects are referred to as being "thermally connected" to each other, heat can be transferred from one object to the other without the presence of a thermal insulator separating the two objects. For example, two objects may be referred to as being thermally connected when heat is transferred from one object to another without an intervening material (e.g., air) (with a thermal conductivity of 0.05 W / (mK) or less, 0.08 W / (mK) or less, or 0.1 W / (mK) or less) separating the two objects.

[0050] In some embodiments, the first silicon heat sink 131 may be connected to either the first semiconductor chip 110 or the second semiconductor chip 120 without a conductive interconnect (e.g., a metal interconnect). In some embodiments, the second silicon heat sink 132 may be connected to either the first semiconductor chip 110 or the second semiconductor chip 120 without a conductive interconnect (e.g., a metal interconnect). It should be understood that when the first silicon heat sink 131 and / or the second silicon heat sink 132 are connected to either the first semiconductor chip 110 or the second semiconductor chip 120 without a conductive interconnect, there is no conductive interconnect configured to connect the first silicon heat sink 131 and / or the second silicon heat sink 132 to the first semiconductor chip 110 or the second semiconductor chip 120.

[0051] The first silicon heat sink 131 and the second silicon heat sink 132 can be monocrystalline silicon or polycrystalline silicon (poly-Si). Although the first silicon heat sink 131 and the second silicon heat sink 132 can be cheaper than silver (Ag), they can have thermal conductivity similar to that of silver (Ag). Furthermore, as will be described in detail below, the first silicon heat sink 131 and the second silicon heat sink 132 can be easily attached to the first semiconductor chip 110 and the second semiconductor chip 120 via DAF.

[0052] In some embodiments, a first silicon heat sink 131 may be thermally connected to a first semiconductor chip 110, and a second silicon heat sink 132 may be thermally connected to a second semiconductor chip 120. The first silicon heat sink 131 may extend vertically from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100. The second silicon heat sink 132 may extend vertically from the upper surface of the second semiconductor chip 120 to the upper surface of the semiconductor package 100.

[0053] The upper surface of the first silicon heat sink 131 and the upper surface of the second silicon heat sink 132 may be substantially coplanar. Terms such as “identical,” “equal,” “planar,” or “coplanar” as used herein include approximate similarity, including variations that may occur due to manufacturing processes, for example. Unless the context or other statement otherwise indicates otherwise, the term “substantially” may be used herein to emphasize that meaning.

[0054] For example, such as Figure 2B As shown, the second silicon heat sink 132 can extend laterally across the upper surfaces of the first memory chip 120a and the second memory chip 120b. The second silicon heat sink 132 can extend laterally from the upper surface of the first memory chip 120a to the upper surface of the second memory chip 120b without encroaching on the area where the bonding pads 120p are formed. As described below, the space between the first memory chip 120a and the second memory chip 120b can be filled with a molding member 150, and the second silicon heat sink 132 can be supported by the molding member 150 between the first memory chip 120a and the second memory chip 120b.

[0055] The first silicon heat sink 131 and the second silicon heat sink 132 can be attached to the first semiconductor chip 110 and the second semiconductor chip 120 respectively via DAF 131f and DAF 132f.

[0056] Figure 3 yes Figure 2A An enlarged view of region III, which shows exemplary details of DAF 131f.

[0057] refer to Figure 3 The first silicon heat sink 131 can be attached to the first semiconductor chip 110 using DAF 131f. In some embodiments, DAF 131f may include a thermal DAF. The thermal DAF may include filler 131ff dispersed in a matrix.

[0058] The filler 131ff may include materials having a higher thermal conductivity than the matrix. For example, the filler may have a thermal conductivity of 30 W / (mK) or higher. For example, the filler 131ff may include, but is not limited to, carbon-based nanoparticles, inorganic powders, metal powders, or mixtures thereof. Because the filler 131ff (e.g., alumina (Al2O3) powder) with high thermal conductivity (i.e., high dielectric constant (k)) is dispersed in DAF 131f, DAF 131f can exhibit better heat transfer properties than typical DAFs.

[0059] DAF 131f can have a thickness of approximately 8 μm to approximately 30 μm. For example... Figure 3 As shown, a single-layer DAF 131f can contact the lower surface of the corresponding first silicon heat sink 131 and the upper surface of the first semiconductor chip 110 to attach them to each other. (The DAFs described elsewhere in this document can similarly contact the corresponding surfaces of various related structures to attach them.)

[0060] Return to reference Figure 1 , Figure 2A and Figure 2B The area of ​​the exposed surface (e.g., the upper surface) of the second silicon heat sink 132 can be larger than the area of ​​the exposed surface (e.g., the upper surface) of each first silicon heat sink 131. For clarity, this can be exaggerated. Figure 1 The shapes and dimensions of the various components shown are not limited to those of the first silicon heat sink 131 and the second silicon heat sink 132. Figure 1 The actual shape and size are shown. In some embodiments, the area of ​​the exposed surface of one or both of the first silicon heat sinks 131 may be larger than the area of ​​the exposed surface of the second silicon heat sink 132.

[0061] The molded component 150 may include, but is not particularly limited to, an epoxy molding compound (EMC). The molded component 150 may also include a filler, which may include a material having a higher thermal conductivity than EMC.

[0062] The molding member 150 may surround the side surfaces of the first semiconductor chip 110 and the second semiconductor chip 120. Furthermore, the molding member 150 may surround the side surfaces of the first silicon heat sink 131 and the second silicon heat sink 132. Simultaneously, the upper surfaces of the first silicon heat sink 131 and the second silicon heat sink 132 may be exposed relative to the molding member 150.

[0063] In some embodiments, the upper surfaces of the first silicon heat sink 131 and the second silicon heat sink 132, as well as the upper surface of the molding member 150, may be substantially coplanar with each other. The filler may include, but is not limited to, carbon-based nanoparticles, inorganic powders, metal powders, or mixtures thereof.

[0064] Figure 4 This is a plan view of the semiconductor package 100a according to an embodiment. Figure 5A It is the edge of semiconductor package 100a Figure 4 A cross-sectional view taken from line VA-VA'. Figure 5B It is the edge of semiconductor package 100a Figure 4 The cross-sectional view of line VB-VB'.

[0065] Figure 4 , Figure 5A and Figure 5B The illustrated embodiment may differ from the reference in the configuration of the second silicon heat sink 132a and the third silicon heat sink 133. Figure 1 , Figure 2A and Figure 2B The described embodiments differ. Therefore, repeated descriptions can be omitted below, and the main differences will be described.

[0066] Reference Figure 4 , Figure 5A and Figure 5B The second silicon heat sink 132a can be connected to the upper surfaces of the first memory chip 120a and the second memory chip 120b. The second silicon heat sink 132a can extend along the +Y and -Y directions, and extend above the upper surface of the first semiconductor chip 110 in a lateral direction. The second silicon heat sink 132a can be formed on the upper surface of the second memory chip 120.

[0067] Since the area of ​​the second silicon heat sink 132a is larger than the area of ​​each second semiconductor chip 120, the heat generated by the second semiconductor chip 120 can be dissipated relatively smoothly.

[0068] In some embodiments, a third silicon heat sink 133 may be disposed below an extension of the second silicon heat sink 132a, the extension of which may extend beyond the upper surface of the second memory chip 120. The third silicon heat sink 133 may extend vertically from the upper surface of the first semiconductor chip 110 to the lower surface of the second silicon heat sink 132a in the Z direction, and the two are thermally connected.

[0069] When the first semiconductor chip 110 is a logic chip, it can generate a large amount of heat in a short time. In this case, the heat can be smoothly dissipated to the outside through the third silicon heat sink 133 and the second silicon heat sink 132a. When the third silicon heat sink 133 is not used, the heat generated by the first semiconductor chip 110 can be dissipated through the second semiconductor chip 120 and the second silicon heat sink 132a. In this case, the heat dissipation efficiency may be reduced, and the second semiconductor chip 120 may be damaged due to heat.

[0070] The material and method of attaching the third silicon heat sink 133 can be referenced. Figure 1 The first silicon heat sink 131 and the second silicon heat sink 132 are made of the same material and are described in the same way, and their repeated descriptions may be omitted.

[0071] Figure 6 This is a plan view of the semiconductor package 100b according to an embodiment. Figure 7 It is the edge of semiconductor package 100b Figure 6 A cross-sectional view taken from line VIIA-VIIA'.

[0072] Figure 6 and Figure 7 The embodiments and references shown Figure 4 , Figure 5A and Figure 5B The difference in the described embodiment lies in the modification of the configuration of the second silicon heat sink 132b and the use of a metal heat sink 139. Therefore, repeated descriptions can be omitted below, and the main focus will be on the differences.

[0073] Reference Figure 6 and Figure 7 The second silicon heat sink 132b can be attached to the second semiconductor chip 120 via a DAF 132bf. The second silicon heat sink 132b can extend in a lateral direction on the second semiconductor chip 120 and extend in a lateral direction above the upper surface of the first semiconductor chip 110. However, the second silicon heat sink 132b may not extend beyond the upper surface of the second semiconductor chip 120 in the opposite lateral direction.

[0074] The semiconductor package 100b may include a metal heat sink 139 connected to the upper surface of the first semiconductor chip 110. The metal heat sink 139 may extend vertically from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100b.

[0075] The metal heat sink 139 can be formed of a metal with high thermal conductivity. For example, the metal heat sink 139 can be silver (Ag), aluminum (Al), copper (Cu), titanium (Ti), platinum (Pt), iron (Fe), cobalt (Co), nickel (Ni), zinc (Zn) or alloys thereof.

[0076] The metal heat sink 139 can be attached to the upper surface of the first semiconductor chip 110 using, for example, a thermal interface material (TIM). The TIM can be a solid or paste-like material capable of thermally bonding two objects together. For example, the TIM can be a thermal grease, thermal adhesive, or thermal pad, but the invention is not limited thereto.

[0077] In some embodiments, the lower horizontal width of the metal heat sink 139 may be greater than its upper horizontal width. That is, the vertical cross-section of the metal heat sink 139 may have a trapezoidal shape.

[0078] The first semiconductor chip 110 may include various semiconductor devices and may generate relatively high heat in areas densely packed with semiconductor devices configured to provide specific functions. For example, the first semiconductor chip 110 may include a system-on-a-chip (SoC) comprising a processor core and several physically separate functional modules. It may be necessary to rapidly dissipate heat generated in areas densely packed with semiconductor devices configured to generate particularly high heat during operation (e.g., in the case that the first semiconductor chip 110 is an SoC, one or more functional modules of the SoC may be particularly prone to generating high heat). Therefore, a metal heat sink 139 with high thermal conductivity may be used in areas where rapid heat dissipation of the first semiconductor chip 110 is particularly needed (e.g., in areas of the first semiconductor chip 110 having one or more functional modules of the SoC). In contrast, in other areas of the first semiconductor chip 110 (e.g., areas that generate heat during operation but where the temperature rises at a relatively low rate), heat can be dissipated by the second semiconductor chip 120 and a second silicon heat sink 132b attached to the upper part of the second semiconductor chip 120.

[0079] Figure 8 This is a plan view of the semiconductor package 100c according to an embodiment. Figure 9A It is the edge of semiconductor package 100c Figure 8 The cross-sectional view taken from line IXA-IXA'. Figure 9B It is the edge of semiconductor package 100c Figure 8 The cross-sectional view taken from line IXB-IXB'.

[0080] Figure 8 , Figure 9A and Figure 9B The illustrated embodiments and references Figure 1 , Figure 2A and Figure 2B The difference in the described embodiment lies in the omission of the second silicon heat sink and the modification of the configuration of the first silicon heat sink 131c. Therefore, repeated descriptions can be omitted below, and the main focus will be on describing the differences.

[0081] refer to Figure 8 , Figure 9A and Figure 9BThe silicon heat sink attached to the second semiconductor chip 120 can be omitted. The first silicon heat sink 131c attached to the first semiconductor chip 110 does not need to be in direct contact with the second semiconductor chip 120, but rather contacts the upper surface of the first semiconductor chip 110 over the largest possible area. The first silicon heat sink 131c may include a DAF 131cf to attach the first silicon heat sink 131c to the upper surface of the first semiconductor chip 110.

[0082] like Figure 8 As shown, the second semiconductor chip 120 may include a first memory chip 120a and a second memory chip 120b, which may be arranged laterally on the first semiconductor chip 110 and spaced apart from each other by a predetermined distance. Consequently, a path with a width corresponding to the predetermined distance can be formed between the first memory chip 120a and the second memory chip 120b. This path can connect two relatively exposed upper surfaces of the first semiconductor chip 110.

[0083] The first silicon heat sink 131c can cover each of the two relatively exposed upper surfaces of the first semiconductor chip 110 over the largest possible area. Furthermore, the first silicon heat sink 131c can cover the surface of the path to connect portions of the first silicon heat sink 131c to the two relatively exposed upper surfaces of the first semiconductor chip 110. As a result, the first silicon heat sink 131c can have a planar shape similar to an I-shape.

[0084] As the first silicon heat sink 131c traverses the path, its side surfaces can extend to face at least three side surfaces of each of the first memory chip 120a and the second memory chip 120b. That is, in Figure 8 In this configuration, one side surface of the first silicon heat sink 131c can extend to face three side surfaces of the first memory chip 120a. Furthermore, another side surface of the first silicon heat sink 131c can extend to face three side surfaces of the second memory chip 120b.

[0085] The heat generated by the second semiconductor chip 120 (i.e., the first memory chip 120a and the second memory chip 120b) can be dissipated to the outside through the molding member 150. Simultaneously, the heat generated by the first semiconductor chip 110 can be dissipated to the outside through the first silicon heat sink 131c. To maximize the contact area between the first semiconductor chip 110 and the first heat sink 131c, Figure 8The first semiconductor chip 110 and the second semiconductor chip 120 shown can be arranged such that the first silicon heat sink 131c can have a planar shape similar to an I-shape. The maximized contact area allows the heat generated by the first semiconductor chip 110 to be effectively dissipated.

[0086] Furthermore, the heat generated by the portion of the first semiconductor chip 110 covered by the second semiconductor chip 120 can be dissipated to the outside through the second semiconductor chip 120 and the molding member 150. It is understood that the portion of the molding member 150 between the second semiconductor chip 120 and the first silicon heat sink 131c can be made thinner, for example, thinner than the thickness of the molding member 150 disposed above the second semiconductor chip 120.

[0087] When the first semiconductor chip 110 is a logic chip, a large amount of heat can be generated at a relatively uniform rate over a short period of time across the entire area of ​​the first semiconductor chip 110. In this case, the heat generated by the first semiconductor chip 110 can be smoothly dissipated to the outside through the first silicon heat sink 131c.

[0088] Figure 10 This is a plan view of the semiconductor package 100d according to an embodiment. Figure 11A It is the edge of semiconductor package 100d Figure 10 A cross-sectional view taken from the line XIA-XIA'. Figure 11B It is the edge of semiconductor package 100d Figure 10 The cross-sectional view taken from line XIB-XIB'.

[0089] Figure 10 , Figure 11A and Figure 11B The embodiment shown may differ from the reference in terms of the arrangement of the second semiconductor chip 120 and the configuration of the first silicon heat sink 131d. Figure 8 , Figure 9A and Figure 9B The described embodiments differ. Therefore, repeated descriptions can be omitted below, and the main differences will be described.

[0090] Reference Figure 10 , Figure 11A and Figure 11B The second semiconductor chip 120 may include a first memory chip 120a and a second memory chip 120b that can be stacked in a vertical direction. Specifically, the first memory chip 120a and the second memory chip 120b may be stacked in a slightly offset manner to expose the bonding pads 120ap of the first memory chip 120a to assist the line bonding process.

[0091] Specifically, the first memory chip 120a can be attached to the first semiconductor chip 110 using DAF 120af. Furthermore, the second memory chip 120b can be attached to the first memory chip 120a using DAF 120bf.

[0092] The bonding pad 120bp of the second memory chip 120b can be electrically connected to the first memory chip 120a via bonding wire 120bw. Furthermore, the bonding pad 120ap of the first memory chip 120a can be electrically connected to the package substrate 101 via bonding wire 120aw.

[0093] Since the first memory chip 120a and the second memory chip 120b are stacked in a slightly offset manner, a space can be formed below one side portion of the second memory chip 120b, in which the first memory chip 120a is recessed.

[0094] The first silicon heat sink 131d can be attached to the upper surface of the first semiconductor chip 110. The first silicon heat sink 131d can be attached to the upper surface of the first semiconductor chip 110 via a die attachment pad 131df. As described above, the die attachment pad 131df can include a thermal DAF containing filler.

[0095] The first silicon heat sink 131d may partially surround the periphery of the second semiconductor chip 120. In some embodiments, the first silicon heat sink 131d may surround three side surfaces of the first memory chip 120a and the second memory chip 120b. Moreover, the first silicon heat sink 131d may extend vertically from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100d.

[0096] A portion of the first silicon heat sink 131d may extend toward the first memory chip 120a below the suspended portion of the second memory chip 120b. Therefore, the first silicon heat sink 131d can form an L-shaped structure (see...). Figure 11B The portion of the first silicon heat sink 131d extending toward the first memory chip 120a can be inserted into the space where the first memory chip 120a is retracted. As a result, the upper surface of the portion of the first silicon heat sink 131d extending toward the first memory chip 120a can face the lower surface of the second memory chip 120b.

[0097] A support structure 140s configured to support the suspended portion may be disposed below the first memory chip 120a. The support structure 140s may be silicon (e.g., crystalline silicon), EMC, and / or any other material having electrical insulating properties.

[0098] Figure 12 This is a plan view of the semiconductor package 100e according to an embodiment. Figure 13A It is the edge of semiconductor package 100e Figure 4 A cross-sectional view taken from line XIIIA-XIIIA'. Figure 13B It is the edge of semiconductor package 100e Figure 4 A cross-sectional view taken from line XIIIB-XIIIB'.

[0099] Figure 12 , Figure 13A and Figure 13B The embodiment shown can be configured similarly to the reference in terms of the first silicon heat sink 131e. Figure 8 , Figure 9A and Figure 9B The described embodiments differ. Therefore, repeated descriptions can be omitted below, and the main differences will be described.

[0100] Reference Figure 12 , Figure 13A and Figure 13B The first silicon heat sink 131e can be attached to the upper surface of the first semiconductor chip 110 through the die attach pad 131ef.

[0101] The first silicon heat sink 131e can extend from the upper surface of the first semiconductor chip 110 to the upper surface of the semiconductor package 100e. The surface area of ​​the upper surface of the first silicon heat sink 131e can be larger than the surface area of ​​the lower surface of the first silicon heat sink 131e. The vertical extension of the first silicon heat sink 131e can extend vertically from the lower surface of the first silicon heat sink 131e, and the horizontal extension of the first silicon heat sink 131e can extend laterally from the upper surface of the semiconductor package 100e. In some embodiments, the horizontal extension can extend laterally across the first memory chip 120a and the second memory chip 120b.

[0102] Because the first silicon heat sink 131e has a large upper surface, it can have an increased heat dissipation effect. In other words, since heat can be smoothly dissipated from the upper surface of the first silicon heat sink 131e, the temperature of the lower surface of the first silicon heat sink 131e can be kept relatively low, allowing the first semiconductor chip to be effectively cooled 110.

[0103] Although the first silicon heat sink 131e is in Figure 13A The diagram shows an integrated type (e.g., continuous and monolithic), but two or more silicon heat sinks can be combined with each other via DAF to form a first silicon heat sink 131e.

[0104] In the following, a method for manufacturing a semiconductor package 100 according to an embodiment will be described.

[0105] Figures 14A to 14CThis is a cross-sectional view illustrating a method for manufacturing a semiconductor package 100 according to an embodiment.

[0106] Reference Figure 14A The first semiconductor chip 110 can be mounted on the packaging substrate 101. (See reference...) Figure 1 , Figure 2A and Figure 2B The first semiconductor chip 110 can be mounted on the packaging substrate 101 in a flip-chip manner, and its repeated detailed description will be omitted.

[0107] One or more second semiconductor chips can be attached to the first semiconductor chip 110. Although in Figure 14A The illustration shows an example of a second memory chip 120b as a second semiconductor chip, but the inventive concept is not limited thereto. The second memory chip 120b can be attached to the upper surface of the first semiconductor chip 110 using a DAF 120bf.

[0108] Reference Figure 14B Silicon heat sinks 131m and 132m can be attached to the first semiconductor chip 110 and the second memory chip 120b. Silicon heat sinks 131m and 132m can be attached to the first semiconductor chip 110 and the second memory chip 120b using DAFs 131f and 132f (e.g., thermal DAF).

[0109] Reference Figure 14C The first semiconductor chip 110, the second memory chip 120b, and the silicon heat sinks 131m and 132m can be molded by molding member 150 to surround the side and top surfaces of the first semiconductor chip 110, the second memory chip 120b, and the silicon heat sinks 131m and 132m.

[0110] For example, the molding method using the molding component 150 can be performed by injecting EMC resin into a mold and curing the EMC resin, but the inventive concept is not limited thereto.

[0111] Subsequently, the upper part of the molded component 150 can be removed, for example, along line P, to expose the upper surfaces of the silicon heat sinks 131m and 132m. Thus, according to reference... Figure 1 , Figure 2A and Figure 2B The semiconductor package 100 of the described embodiment. The upper part of the molded component 150 can be removed using, for example, grinding and mechanical polishing processes (e.g., by planarization, such as by chemical mechanical polishing (CMP)).

[0112] Figure 15A and Figure 15B This is a cross-sectional view illustrating a method for manufacturing a semiconductor package 100 according to an embodiment.

[0113] Reference Figure 15A The first semiconductor chip 110 and one or more second semiconductor chips (e.g., second memory chip 120b) can be attached to the packaging substrate 101, and silicon heat sinks 131 and 132 can be attached to the first semiconductor chip 110 and the second semiconductor chip. Because... Figure 15A process and reference Figure 14A and Figure 14B The processes described are the same, so their detailed descriptions will be omitted.

[0114] Reference Figure 15B The upper surfaces of silicon heat sinks 131 and 132 can contact the protective film 210 included in molds 201 and 202, and then molding resin (e.g., EMC) can be injected into molds 201 and 202 and cured. The molding resin can cure to form a molded component. The fully cured workpiece can be removed from molds 201 and 202, and the protective film 210 can be removed. Thus, according to reference... Figure 1 , Figure 2A and Figure 2B Semiconductor package 100 of the described embodiment.

[0115] According to reference Figures 4 to 13B The semiconductor packages described in the embodiments can be manufactured using the same methods, and those skilled in the art can refer to [reference needed]. Figures 14A to 15B These embodiments can be implemented as easily as described. Semiconductor packages with excellent heat dissipation characteristics and high reliability can be fabricated using simple processes.

[0116] Figure 16 This is a block diagram of an electronic system 2000 according to an embodiment.

[0117] The electronic system 2000 may include a controller 2010, input / output (I / O) circuitry 2020, a memory 2030, and an interface 2040, which can be connected to each other via a bus 2050.

[0118] The controller 2010 may include at least one of a microprocessor, a digital signal processor, or a similar processor. The I / O device 2020 may include at least one of a keypad, a keyboard, or a display device. The memory 2030 may be used to store commands executed by the controller 2010. For example, the memory 2030 may be used to store user data.

[0119] Electronic system 2000 may constitute a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. Interface 2040 may include a wireless interface, enabling electronic system 2000 to transmit and receive data via a wireless communication network. Interface 2040 may include an antenna and / or a wireless transceiver. In some embodiments, electronic system 2000 may be used for communication interface protocols of third-generation communication systems, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Cellular (NADC), Extended Time Division Multiple Access (E-TDMA), and / or Wideband Code Division Multiple Access (WCDMA). Electronic system 2000 (e.g., at least one of controller 2010 and memory 2030) may include at least one or more of semiconductor packages according to any of the above embodiments and semiconductor packages modified and altered within the scope of the inventive concept.

[0120] Electronic Systems 2000 can be applied to portable telephones, desktop computers, laptop computers, tablet PCs, game consoles, navigation devices, digital cameras, personal digital assistants (PDAs), cordless phones, digital music players, or any electronic product capable of sending and / or receiving information in a wireless environment.

[0121] The configurations and effects of the inventive concept will be described in more detail below with reference to specific experimental and comparative examples. However, these examples are intended only to facilitate understanding and not to limit the scope of the inventive concept.

[0122] The temperature change experiment was conducted on a semiconductor package, in which the modem chip and DRAM chip were mounted, such as... Figure 1 On the packaging substrate shown.

[0123] The following semiconductor packages were manufactured: a semiconductor package lacking a silicon heat sink (Comparative Example 1), including those using, for example... Figure 1 The semiconductor package shown (Experimental Example 1) includes a typical DAF with a silicon heat sink, including the use of, Figure 1 The semiconductor package shown (Experimental Example 2) includes a silicon heat sink for the thermal DAF, including the use of, Figure 1 The thermal DAF shown includes a silicon heat sink and a semiconductor package (Experimental Example 3) using EMC containing filler as a molding component, and includes the use of, for example Figure 8 The semiconductor package shown is a typical DAF including a silicon heat sink (Experimental Example 4). The specific configurations for each example are shown in Table 1.

[0124] Temperature changes were measured while approximately 1.55 W of power was supplied to each semiconductor package at an air temperature of 25°C, and the results are listed in Table 1. [Table 1]

[0125] Thermal resistance, obtained experimentally, refers to the temperature change per unit power supplied to each semiconductor package and is expressed in °C / W. As heat dissipation becomes smoother, the temperature can rise at a lower rate, and the thermal resistance can be lower.

[0126] As shown in Table 1, it can be inferred that the fillers contained in silicon heat sinks, thermal DAFs, and EMCs all contribute to heat dissipation.

[0127] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Packaging substrate; A first semiconductor chip, wherein the active surface of the first semiconductor chip faces the packaging substrate, and the first semiconductor chip is electrically connected to the packaging substrate via a chip interconnect component; The second semiconductor chip is attached to the upper surface of the first semiconductor chip; A first silicon heat sink is thermally connected to the upper surface of the second semiconductor chip and is configured to extend laterally above the upper surface of the first semiconductor chip. A second silicon heat sink is thermally connected to the upper surface of the first semiconductor chip and extends vertically from the upper surface of the first semiconductor chip to the lower surface of the first silicon heat sink; and Molded components are configured to surround the first semiconductor chip and the second semiconductor chip. The first silicon heat sink has an exposed upper surface relative to the molded member, and The first silicon heat sink and the second silicon heat sink are not connected to either the first semiconductor chip and the second semiconductor chip included in the semiconductor package via conductive interconnection.

2. The semiconductor package according to claim 1, wherein, At least one of the first silicon heat sink and the second silicon heat sink is monocrystalline silicon or polycrystalline silicon.

3. The semiconductor package according to claim 1, wherein, The first silicon heat sink is attached to the upper surface of the second semiconductor chip via a die-attach film (DAF).

4. The semiconductor package according to claim 3, wherein, The DAF includes: thermal DAF, which includes a thermally conductive filler.

5. The semiconductor package according to claim 1, wherein, The first silicon heat sink is attached to the second silicon heat sink via a die-attachment film.

6. The semiconductor package according to claim 1, wherein, The second silicon heat sink is attached to the upper surface of the first semiconductor chip via a die-attachment film.

7. The semiconductor package according to claim 1, wherein, The second semiconductor chip is attached to the upper surface of the first semiconductor chip via a die-attachment film.

8. The semiconductor package according to claim 1, wherein, The first semiconductor chip is mounted on the packaging substrate in a flip-chip manner.

9. The semiconductor package according to claim 1, wherein, The second semiconductor chip is mounted on the first semiconductor chip such that the active surface of the second semiconductor chip faces the first semiconductor chip.

10. The semiconductor package according to claim 1, wherein, The second semiconductor chip includes at least one memory chip, the at least one memory chip including at least one bonding pad formed on the upper surface of the at least one memory chip, and wherein the at least one bonding pad is electrically connected to the package substrate via the at least one bonding line.

11. The semiconductor package of claim 10, wherein, The at least one memory chip includes a first memory chip and a second memory chip arranged to be spaced apart from each other in the lateral direction.

12. The semiconductor package of claim 11, wherein, The first silicon heat sink vertically overlaps with a portion of the first memory chip and the second memory chip, without covering the at least one bonding pad.

13. The semiconductor package according to claim 1, wherein, The first silicon heat sink vertically overlaps the second silicon heat sink completely.

14. The semiconductor package according to claim 1, wherein, The second silicon heat sink includes at least two portions arranged to be spaced apart from each other in the lateral direction.

15. The semiconductor package of claim 14, wherein, The at least two portions of the second silicon heat sink are supported by the molded component.

16. The semiconductor package according to claim 1, wherein, The second silicon heat sink is coplanar with the upper surface of the second semiconductor chip.

17. The semiconductor package according to claim 1, wherein, The surface area of ​​the lower surface of the first silicon heat sink is greater than the surface area of ​​the upper surface of the second silicon heat sink.

18. The semiconductor package according to claim 1, wherein, The first semiconductor chip is a logic chip.

19. The semiconductor package according to claim 1, wherein, The molded component includes an alumina filler.

20. An electronic system comprising: Controller; The memory is configured to store data; The interface circuit is configured to send data to and receive data from external devices. as well as A bus is configured to connect the controller, the memory, and the interface circuitry, enabling the controller, the memory, and the interface circuitry to communicate with each other. Wherein, at least one of the controller and the memory comprises the semiconductor package as described in claim 1.

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