Power semiconductor device with bidirectional conduction capability
By setting a bidirectional SGT structure and a conductivity-type well region in the power semiconductor device, bidirectional conduction capability is achieved, solving the problems of large circuit area and high cost in the prior art, reducing conduction loss and parasitic capacitance, and improving breakdown voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-24
- Publication Date
- 2026-04-03
AI Technical Summary
In the existing technology, using two power semiconductor devices as switches results in a large circuit area and high cost, making it difficult to meet the needs of practical applications.
Design a power semiconductor device with bidirectional conduction capability by setting a bidirectional SGT structure in the cell trench and separating the epitaxial layer of the first conductivity type into two regions by a well region of the second conductivity type, thereby achieving bidirectional conduction. The shielding gate acts as a field plate to improve the breakdown voltage and reduce the conduction loss.
It enables bidirectional conduction of power semiconductor devices, reduces conduction losses and parasitic capacitance, improves breakdown voltage, and reduces switching losses.
Smart Images
Figure CN121793401A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a power semiconductor device, and more particularly to a power semiconductor device with bidirectional conduction capability. Background Technology
[0002] Currently, in fields such as power supplies, two power semiconductor devices are generally used as switches. The two power semiconductor devices work together to achieve charging and discharging control. Among them, the power semiconductor devices are generally MOSFET devices.
[0003] Understandably, using two power semiconductor devices for functional control results in a larger circuit area and higher cost, making it difficult to meet practical application requirements. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a power semiconductor device with bidirectional conduction capability, which can have bidirectional conduction and reduce conduction loss.
[0005] According to the technical solution provided by the present invention, a power semiconductor device with bidirectional conduction capability is provided, the power semiconductor device comprising: Semiconductor substrate; An active region is distributed in the central region of the semiconductor substrate. The active region includes a plurality of SGT cells arranged in parallel, each SGT cell including a cell trench. A bidirectional SGT structure is provided in the cell trench. The bidirectional SGT structure is adapted to be electrically connected to the front first electrode metal on the front side of the semiconductor substrate and the back electrode metal on the back side of the semiconductor substrate, so that each SGT cell has bidirectional conduction capability. When the SGT cell is turned on, the voltage applied to the front first electrode and the back electrode metal is configured to configure the channel direction of the SGT cell.
[0006] On the cross-section of each SGT cell, the bidirectional SGT structure includes a control gate located within the cell trench and shielding gates located on both sides of the control gate, wherein, The shielding grid located above the control grid is electrically connected to the back electrode metal, and the shielding grid located below the control grid is electrically connected to the front first electrode metal, and the control grid and each shielding grid form an SGT structure.
[0007] Within the cell trench, the control gate is insulated from the sidewall of the cell trench by the control gate oxide layer; The control gate and the shielding gate located above the control gate are insulated and isolated by an upper shielding gate oxide layer, and the shielding gate located above the control gate is insulated and isolated from the sidewall of the cell trench by the upper shielding gate oxide layer. The control gate and the shielding gate located below the control gate are insulated and isolated by a lower shielding gate oxide layer, and the shielding gate located below the control gate is insulated and isolated from the sidewalls and bottom walls of the cell trench by the lower shielding gate oxide layer.
[0008] The semiconductor substrate includes a first conductivity type epitaxial layer and a first conductivity type substrate adjacent to the first conductivity type epitaxial layer, wherein... A second conductivity type well region is provided in the first conductivity type epitaxial layer. The second conductivity type well region traverses the active region and is in contact with the outer wall of the cell trench. The second type of conductivity well region is located above the bottom of the cell trench, and the second type of conductivity well region corresponds directly to the control gate in the cell trench.
[0009] In the cross-section of the SGT cell, the upper surface of the control gate is located above the upper surface of the second conductivity type well region, and the lower surface of the control gate is located below the lower surface of the second conductivity type well region.
[0010] A front-side first-conductivity bipolar region is formed within the first-conductivity epitaxial layer, and a back-side electrode metal is formed on the first-conductivity substrate. The first conductivity type bipolar region on the front side is isolated from the second conductivity type well region through the first conductivity type epitaxial layer; The front first conductivity type bipolar region is in ohmic contact with the front first electrode metal, and the back electrode metal is in ohmic contact with the first conductivity type substrate.
[0011] The bottom of the cell trench passes through the first conductivity type epitaxial layer and extends into the first conductivity type substrate.
[0012] On the cross-section of the SGT cell, the front first conductivity type bipolar region is in contact with the outer wall of the cell trench, and the front first conductivity type bipolar region is located above the bottom of the upper shielding grid.
[0013] On the cross-section of the SGT cell, the shielding gates on both sides of the control gate are symmetrically distributed.
[0014] Both the control gate and the shielding gate are made of conductive polycrystalline silicon. The control gate makes ohmic metal contact with the front second electrode; The shielding grid above the control grid makes ohmic contact with the metal of the back electrode, and the shielding grid below the control grid makes ohmic contact with the metal of the first electrode on the front.
[0015] The advantages of this invention are as follows: A bidirectional SGT structure is formed within the cell trench, and the first conductivity type epitaxial layer is separated into two regions by a second conductivity type well region. PN junctions are formed between the second conductivity type well region and the first conductivity type epitaxial layers on both sides. When the second conductivity type well region is not inverted, the current is blocked by the diode regardless of the current direction, allowing bidirectional switching between the drain and source electrodes of the power semiconductor device of this invention. Furthermore, based on the bidirectional conduction characteristic, parasitic capacitance can be reduced, thereby reducing switching losses.
[0016] When an SGT structure is formed between the control gate and the lower shielding gate, the lower shielding gate can act as a field plate, increasing the breakdown voltage of the power semiconductor device. When the gate of the power semiconductor device is turned on, the back electrode metal connected to the upper shielding gate forms the drain electrode and is at a high potential. Electrons in the epitaxial layer of the first conductivity type above the second conductivity type well region will accumulate towards the edge of the cell trench, increasing the electron concentration in the upper epitaxial layer of the first conductivity type near the cell trench, reducing the resistance of the upper epitaxial layer of the first conductivity type, thereby reducing conduction losses. Similarly, when the control gate and the upper shielding gate form an SGT structure, the upper shielding gate acts as a field plate, increasing the breakdown voltage of the power semiconductor device. When the gate of the power semiconductor device is turned on, the metal of the first electrode on the front side connected to the lower shielding gate forms the drain electrode and is at a high potential. Electrons in the first conductivity type epitaxial layer below the second conductivity type well region will gather towards the edge of the cell trench, increasing the electron concentration in the lower first conductivity type epitaxial layer near the cell trench, reducing the resistance of the lower first conductivity type epitaxial layer, thereby reducing conduction losses. Attached Figure Description
[0017] Figure 1 This is a cross-sectional view of an embodiment of the SGT cell of the present invention.
[0018] Explanation of reference numerals in the attached figures: 1-N+ substrate, 2-N-type epitaxial layer, 3-P-type well region, 4-cell trench, 5-back electrode metal, 6-lower shielding gate, 7-lower shielding gate oxide layer, 8-control gate oxide layer, 9-control gate, 10-upper shielding gate oxide layer, 11-bipolar region contact hole, 12-upper shielding gate, 13-front N-type bipolar region, and 14-surface dielectric layer. Detailed Implementation
[0019] The present invention will be further described below with reference to specific accompanying drawings and embodiments.
[0020] To achieve bidirectional conduction, the present invention provides a power semiconductor device with bidirectional conduction capability. Specifically, the power semiconductor device includes: Semiconductor substrate; An active region is distributed in the central region of the semiconductor substrate. The active region includes a plurality of SGT cells arranged in parallel. Each SGT cell includes a cell trench 4. A bidirectional SGT structure is provided in the cell trench 4. The bidirectional SGT structure is adapted to be electrically connected to the first front electrode metal on the front side of the semiconductor substrate and the back electrode metal on the back side of the semiconductor substrate, so that each SGT cell has bidirectional conduction capability. When the SGT cell is turned on, the voltage applied to the front first electrode and the back electrode metal is configured to configure the channel direction of the SGT cell.
[0021] Consistent with existing power semiconductor devices, the power semiconductor device of the present invention also includes a semiconductor substrate and an active region distributed in the central region of the semiconductor substrate. The material of the semiconductor substrate can be selected as needed, such as silicon. The active region serves as the functional region of the power semiconductor device. The active region generally includes several cells. In the present invention, the cells in the active region adopt an SGT structure to form SGT cells. Therefore, each SGT cell should include a cell trench 4.
[0022] In order to achieve bidirectional conduction, the present invention provides a bidirectional SGT structure in each cell trench 4. The bidirectional SGT structure should be electrically connected to the front first electrode metal located above the front side of the semiconductor substrate and the back electrode metal located on the back side of the semiconductor substrate. That is, bidirectional conduction can be achieved through the electrical connection between the bidirectional SGT structure and the front first electrode metal and the back electrode metal.
[0023] In specific implementation, the front first electrode of the power semiconductor device can be formed through the front first electrode metal, and the back electrode of the power semiconductor device can be formed through the back electrode metal. The types of the front first electrode and the back electrode are related to the type of power semiconductor device. It should be noted that the power semiconductor device of the present invention mainly forms a MOSFET-type device. In this case, when bidirectional conduction can be achieved, the front first electrode can form the source electrode or drain electrode of the MOSFET device, and at the same time, the back electrode can form the drain electrode or source electrode of the MOSFET device. That is, both the front first electrode and the back electrode can form the source electrode and drain electrode of the MOSFET-type device. The specific type of electrode formed should be related to the direction of conduction.
[0024] It should be understood that the conduction direction of the power semiconductor device is related to the voltage applied to the front first electrode and the back electrode. That is, by configuring the magnitude of the voltage applied to the front first electrode and the back electrode, the conduction direction of the SGT cell can be configured, and the conduction direction of the entire power semiconductor device can be configured according to the conduction direction of the SGT cell. In one embodiment of the present invention, when the front first electrode needs to be configured as the source electrode, it can be grounded or connected to a low voltage. In this case, the conduction direction of the SGT cell can be the reverse direction from the back electrode to the front first electrode, and the back electrode serves as the drain electrode of the power semiconductor device. Similarly, when the back electrode needs to be configured as the source electrode, it can be grounded or connected to a low voltage. In this case, the conduction direction of the SGT cell can be the direction from the front first electrode to the back electrode, and the front first electrode serves as the drain electrode of the power semiconductor device.
[0025] In one embodiment of the present invention, on the cross-section of each SGT cell, the bidirectional SGT structure includes a control gate 9 located within the cell trench 4 and shielding gates located on both sides of the control gate 9, wherein, The shielding grid located above the control grid 9 is electrically connected to the back electrode metal, and the shielding grid located below the control grid 9 is electrically connected to the front first electrode metal, and the control grid and each shielding grid form an SGT structure.
[0026] Figure 1 The figure shows a cross-sectional view of an embodiment of the SGT cell. As can be seen from the figure, a control gate 9 is provided in the cell trench 4, and a shielding gate is provided on both sides of the control gate 9. In the figure, the shielding gate located above the control gate 9 forms the upper shielding gate 12, and the shielding gate located below the control gate 9 forms the lower shielding gate 6. In specific implementation, the upper shielding gate 12 should be electrically connected to the back electrode metal, and the lower shielding gate 6 should be electrically connected to the front first electrode metal, so that an SGT structure can be formed between the control gate 9 and each shielding gate.
[0027] In specific implementation, on the cross-section of the SGT cell, the shielding gates on both sides of the control gate 9 are symmetrically distributed, and the upper shielding gate 12 and the lower shielding gate 6 can be symmetrically distributed. Generally, the SGT cell is elongated, that is, the cell groove 4 in the active region is elongated. At this time, on the top view plane of the active region, the upper shielding gate 12 and the lower shielding gate 6 are also elongated in their main body, and their shapes are consistent with the elongated shape of the SGT cell. Therefore, they are symmetrically distributed, specifically meaning that the main body of the upper shielding gate 12 and the corresponding main body of the lower shielding gate 6 are symmetrically distributed.
[0028] In one embodiment of the present invention, both the control gate 9 and the shielding gate are made of conductive polysilicon, wherein, Control gate 9 makes ohmic contact with the front second electrode metal; The shielding grid above the control grid 9 makes ohmic contact with the metal of the back electrode, and the shielding grid below the control grid 9 makes ohmic contact with the metal of the first electrode on the front.
[0029] Similar to existing technologies, the control gate 9 and the shielding gate are generally made of conductive polysilicon, and can be fabricated within the cell trench 4 using a filling process. Furthermore, the control gate 9 should make ohmic contact with the front-side second electrode metal above the front side of the semiconductor substrate to form the front-side second electrode. It is understood that the front-side second electrode should be the gate electrode of a MOSFET-type device. In addition, Figure 1 The front second electrode metal, the front first electrode metal, and the back electrode metal are not shown in the figure. The distribution of the front second electrode metal and the front first electrode metal on the front side of the semiconductor substrate, and the distribution of the back electrode metal on the back side of the semiconductor substrate, can be consistent with the prior art and will not be described in detail here.
[0030] In one embodiment of the present invention, within the cell trench 4, the control gate 9 is insulated and isolated from the sidewall of the cell trench 4 by the control gate oxide layer 8. The control gate 9 and the shielding gate located above the control gate 9 are insulated and isolated by the upper shielding gate oxide layer 10, and the shielding gate located above the control gate 9 is insulated and isolated from the sidewall of the cell trench 4 by the upper shielding gate oxide layer 10. The control gate 9 and the shielding gate located below the control gate 9 are insulated and isolated by the lower shielding gate oxide layer 7, and the shielding gate located below the control gate 9 is insulated and isolated from the sidewall and bottom wall of the cell trench 4 by the lower shielding gate oxide layer 7.
[0031] Figure 1 In the middle region of the cell trench 4, the control gate 9 is located and is insulated from the sidewall of the cell trench 4 by the control gate oxide layer 8. The upper shielding gate 12 is located above the control gate 9 and corresponds to the opening of the cell trench 4, while the lower shielding gate 6 is located below the control gate 9 and corresponds to the bottom of the cell trench 4. Figure 1 In this configuration, the lower shielding gate oxide layer 7 provides insulation between the lower shielding gate 6 and the control gate 9. The lower shielding gate oxide layer 7 can also enclose the lower shielding gate 6 to provide insulation between the lower shielding gate 6 and the inner wall of the cell trench 4. Simultaneously, the upper shielding gate oxide layer 10 provides insulation between the upper shielding gate 12 and the control gate 9. The upper shielding gate oxide layer 10 can also enclose the upper shielding gate 12 to provide insulation between the upper shielding gate 12 and the inner wall of the cell trench 4.
[0032] In practice, both the lower shielding gate oxide layer 7 and the upper shielding gate oxide layer 10 are silicon dioxide layers, and the corresponding thicknesses of the lower shielding gate oxide layer 7 and the upper shielding gate oxide layer 10 are greater than the thickness of the control gate oxide layer 8.
[0033] It should be understood that the conductivity type of the semiconductor substrate can be N-type or P-type. The following explanation uses an N-type semiconductor substrate as an example. In this case, the semiconductor substrate includes an N-type epitaxial layer 2 and an N+ substrate 1 adjacent to the N-type epitaxial layer 2. A P-type well region 3 is provided in the N-type epitaxial layer 2. The P-type well region 3 traverses the active region and is in contact with the outer wall of the cell trench 4. The P-type well region 3 is located above the bottom of the cell trench 4, and the P-type well region 3 corresponds directly to the control gate 9 in the cell trench 4.
[0034] Similar to existing semiconductor substrates, the doping concentration of the N+ substrate 1 is greater than that of the N-type epitaxial layer 2. In a specific implementation, the surface where the N-type epitaxial layer 2 is located can form the front side of the semiconductor substrate, and the corresponding surface of the N+ substrate 1 can serve as the back side of the semiconductor substrate, with the front and back sides of the semiconductor substrate directly corresponding to each other.
[0035] Figure 1 The diagram shows a P-type well region 3 disposed within the N-type epitaxial layer 2. Generally, the P-type well region 3 traverses the active region, that is, P-type well regions 3 are distributed throughout the active region. The P-type well region 3 should correspond to the control gate 9 and contact the outer wall of the cell trench 4. Figure 1 In this configuration, the P-type well region 3 should be located above the bottom of the cell trench 4, above the lower shielding grid 6, and below the upper shielding grid 12.
[0036] Figure 1 In the SGT cell, the upper surface of the control gate 9 is located above the upper surface of the P-type well region 3, and the lower surface of the control gate 9 is located below the lower surface of the P-type well region 3; that is, the cross-sectional thickness of the control gate 9 should be greater than the corresponding thickness of the P-type well region 3. Furthermore, Figure 1 In this process, the bottom of the cell trench 4 passes through the N-type epitaxial layer 2 and extends into the N+ substrate 1, so as to maintain the charge balance at the bottom of the cell trench 4, so that both the upper shielding gate 12 and the lower shielding gate 6 can achieve the same withstand voltage effect.
[0037] In one embodiment of the present invention, a front-side N-type bipolar region 13 is formed within the N-type epitaxial layer 2, and a back-side electrode metal 5 is formed on the N+ substrate 1, wherein... The front-side N-type bipolar region 13 is isolated from the P-well region 3 through the N-type epitaxial layer 2; The N+ substrate 1 is isolated from the P-well region 3 by the N-type epitaxial layer 2; The front N-type bipolar region 13 is in ohmic contact with the front first electrode metal, and the back electrode metal 5 is in ohmic contact with the N+ substrate 1.
[0038] In order to form a conductive channel, Figure 1In the N-type epitaxial layer 2, a front-side N-type bipolar region 13 is provided. The front-side N-type bipolar region 13 should be in ohmic contact with the front-side first electrode metal. At this time, when the front-side first electrode metal can form a source electrode, the front-side N-type bipolar region 13 can serve as an N-type source region. Figure 1 In this process, a back electrode metal 5 is placed on the N+ substrate 1. At this time, the N+ substrate 1 can serve as a bipolar region on the back side. The back electrode metal 5 is in ohmic contact with the N+ substrate 1. When the back electrode metal 5 forms a source electrode, the N+ substrate 1 can also serve as an N-type source region.
[0039] Furthermore, on the cross-section of the SGT cell, the front N-type bipolar region 13 contacts the outer wall of the cell trench 4, and the front N-type bipolar region 13 is located above the bottom of the upper shielding grid, that is, the front N-type bipolar region 13 should be located above the bottom of the upper shielding grid 12. Figure 1 In this process, a surface dielectric layer 14 is also provided on the N-type epitaxial layer 2. The surface dielectric layer 14 enables insulation isolation between the upper shielding gate 12 and the front first electrode metal and the front second electrode metal. In order to achieve ohmic contact between the front first electrode metal and the front N-type bipolar region 13, a bipolar region contact hole 11 is provided above the surface of the N-type epitaxial layer 2. After the front first electrode metal is fabricated, the front first electrode metal can make ohmic contact with the front N-type bipolar region 13 through the bipolar region contact hole 11.
[0040] As explained above, the P-type well region 3 can separate the N-type epitaxial layer 2 into two regions, meaning that PN junctions are formed between the P-type well region 3 and the N-type epitaxial layers 2 on both sides. When the P-type well region 3 is not inverted, the current will be blocked by the diode regardless of the current direction, allowing bidirectional switching between the drain and source electrodes of the power semiconductor device of this invention. Furthermore, based on the bidirectional conduction characteristic, parasitic capacitance can be reduced, thereby reducing switching losses.
[0041] When an SGT structure is formed between the control gate 9 and the lower shielding gate 6, the lower shielding gate 6 can act as a field plate, increasing the breakdown voltage of the power semiconductor device. When the gate of the power semiconductor device is turned on, the back electrode metal 5 connected to the upper shielding gate 12 forms a drain electrode and is at a high potential. Electrons in the N-type epitaxial layer 2 above the P-type well region 3 will accumulate towards the edge of the cell trench 4, increasing the electron concentration in the upper N-type epitaxial layer 2 near the cell trench 4, reducing the resistance of the upper N-type epitaxial layer 2, thereby reducing conduction losses. Similarly, when the control gate 9 and the upper shielding gate 12 form an SGT structure, the upper shielding gate 12 acts as a field plate, increasing the breakdown voltage of the power semiconductor device. When the gate of the power semiconductor device is turned on, the metal of the first electrode on the front side connected to the lower shielding gate 6 forms the drain electrode and is at a high potential. Electrons in the N-type epitaxial layer 2 below the P-type well region 3 will accumulate towards the edge of the cell trench 4, increasing the electron concentration in the lower N-type epitaxial layer 2 near the cell trench 4, reducing the resistance of the lower N-type epitaxial layer 2, thereby reducing conduction losses.
Claims
1. A power semiconductor device with bidirectional conduction capability, characterized in that, The power semiconductor device includes: Semiconductor substrate; An active region is distributed in the central region of the semiconductor substrate. The active region includes a plurality of SGT cells arranged in parallel, each SGT cell including a cell trench. A bidirectional SGT structure is provided in the cell trench. The bidirectional SGT structure is adapted to be electrically connected to the front first electrode metal on the front side of the semiconductor substrate and the back electrode metal on the back side of the semiconductor substrate, so that each SGT cell has bidirectional conduction capability. When the SGT cell is turned on, the voltage applied to the front first electrode and the back electrode metal is configured to configure the channel direction of the SGT cell.
2. The power semiconductor device with bidirectional conduction capability according to claim 1, characterized in that: On the cross-section of each SGT cell, the bidirectional SGT structure includes a control gate located within the cell trench and shielding gates located on both sides of the control gate, wherein, The shielding grid located above the control grid is electrically connected to the back electrode metal, and the shielding grid located below the control grid is electrically connected to the front first electrode metal, and the control grid and each shielding grid form an SGT structure.
3. The power semiconductor device with bidirectional conduction capability according to claim 2, characterized in that: Within the cell trench, the control gate is insulated from the sidewall of the cell trench by the control gate oxide layer; The control gate and the shielding gate located above the control gate are insulated and isolated by an upper shielding gate oxide layer, and the shielding gate located above the control gate is insulated and isolated from the sidewall of the cell trench by the upper shielding gate oxide layer. The control gate and the shielding gate located below the control gate are insulated and isolated by a lower shielding gate oxide layer, and the shielding gate located below the control gate is insulated and isolated from the sidewalls and bottom walls of the cell trench by the lower shielding gate oxide layer.
4. The power semiconductor device with bidirectional conduction capability according to claim 2 or 3, characterized in that: The semiconductor substrate includes a first conductivity type epitaxial layer and a first conductivity type substrate adjacent to the first conductivity type epitaxial layer, wherein... A second conductivity type well region is provided in the first conductivity type epitaxial layer. The second conductivity type well region traverses the active region and is in contact with the outer wall of the cell trench. The second type of conductivity well region is located above the bottom of the cell trench, and the second type of conductivity well region corresponds directly to the control gate in the cell trench.
5. The power semiconductor device with bidirectional conduction capability according to claim 4, characterized in that: in In the cross-section of the SGT cell, the upper surface of the control gate is located above the upper surface of the second conductivity type well region, and the lower surface of the control gate is located below the lower surface of the second conductivity type well region.
6. The power semiconductor device with bidirectional conduction capability according to claim 4, characterized in that: in A front-side first-conductivity bipolar region is formed within the first-conductivity epitaxial layer, and a back-side electrode metal is formed on the first-conductivity substrate. The first conductivity type bipolar region on the front side is isolated from the second conductivity type well region through the first conductivity type epitaxial layer; The front first conductivity type bipolar region is in ohmic contact with the front first electrode metal, and the back electrode metal is in ohmic contact with the first conductivity type substrate.
7. The power semiconductor device with bidirectional conduction capability according to claim 4, characterized in that: The bottom of the cell trench passes through the first conductivity type epitaxial layer and extends into the first conductivity type substrate.
8. The power semiconductor device with bidirectional conduction capability according to claim 6, characterized in that: in On the cross-section of the SGT cell, the first conductive type bipolar region on the front side contacts the outer wall of the cell trench, and the first conductive type bipolar region on the front side is located above the bottom of the upper shielding grid.
9. The power semiconductor device with bidirectional conduction capability according to any one of claims 1 to 3, characterized in that: On the cross-section of the SGT cell, the shielding gates on both sides of the control gate are symmetrically distributed.
10. The power semiconductor device with bidirectional conduction capability according to claim 9, characterized in that: Both the control gate and the shielding gate are made of conductive polycrystalline silicon. The control gate makes ohmic metal contact with the front second electrode; The shielding grid above the control grid makes ohmic contact with the metal of the back electrode, and the shielding grid below the control grid makes ohmic contact with the metal of the first electrode on the front.