Power semiconductor device with integrated field plate structure and method of manufacturing the same

Abstract

The application relates to a power semiconductor device with an integrated field plate structure and a manufacturing method thereof. In order to solve the problems of complex manufacturing process and high cost caused by multilayer independent field plates, the application adopts an integrated single field plate, cooperates with a first ladder-shaped groove and a second ladder-shaped groove, is favorable for reducing the electric field peak between the gate and the drain and between the gate and the source, makes the electric field distribution more even, improves the breakdown voltage and reliability of the device. In addition, the application provides a device manufacturing method with the integrated field plate structure, only needs to perform once photoetching and field plate deposition steps, can form the integrated field plate with three layers of different heights, is favorable for reducing process steps and lowering production cost.

Description

Technical Field

[0001] This invention relates to power semiconductor devices, particularly power semiconductor devices with an integrated field plate structure and methods for manufacturing the same. Background Technology

[0002] In recent years, group III nitride materials, such as gallium nitride, have been increasingly used in high-frequency applications such as power, radio frequency, and microwave, compared to silicon and silicon carbide materials, due to their higher electron mobility, saturated electron velocity, and breakdown electric field.

[0003] An existing high-voltage, high-electron-mobility transistor structure, such as Figure 1 As shown, the high-voltage device has a multilayer independent field plate 102 located next to the gate metal 101. The multilayer independent field plate 102 may be connected to the gate or the source, and the farther away from the gate, the higher the distance from the upper surface of the barrier layer. Its main function is to reduce the electric field spike between the gate metal 101 and the drain metal 103, so that the electric field distribution is more uniform and the breakdown voltage and reliability of the device are improved.

[0004] The number of independent field plates (102 layers) is inversely proportional to the maximum electric field between the gate and drain. The more independent field plates (102 layers), the lower the maximum electric field between the gate and drain, and the higher the breakdown voltage and reliability of the device. Typically, a high-voltage device (>400V) requires two or more independent field plate (102 layers) structures to achieve sufficient breakdown voltage. However, each independent field plate requires separate deposition, photolithography, and etching processes. The more field plate layers, the more complex the process and the higher the cost. Summary of the Invention

[0005] To address the aforementioned problems, the present invention provides the following technical solution:

[0006] A power semiconductor device with an integrated field plate structure includes a substrate layer at the bottom, a buffer layer above the substrate layer, a channel layer above the buffer layer, a barrier layer above the channel layer, a first source metal layer, a gate structure, a first drain metal layer, and a first dielectric layer above the barrier layer, and a third dielectric layer above the first dielectric layer. A source contact trench is provided above the first source metal layer, and a drain contact trench is provided above the first drain metal layer. One or more first trenches and second trenches are formed in the third dielectric layer above the first dielectric layer and between the gate structure and the first drain metal layer. The first trenches are closer to the gate structure than the second trenches. A second dielectric layer is provided at the bottom of the second trench. The height H3 of the upper surface of the third dielectric layer is higher than the height H2 of the upper surface of the second dielectric layer, which is higher than the height H1 of the upper surface of the first dielectric layer.

[0007] A third trench is formed above the source contact trench and part of the first dielectric layer, and the source contact trench and the third trench are combined to form a first stepped trench.

[0008] A fourth trench is formed above the drain contact trench and part of the first dielectric layer, and the drain contact trench and the fourth trench are combined to form a second stepped trench.

[0009] Above the third dielectric layer, there is also a spaced integral field plate and a second drain metal layer. The integral field plate fills downward into the first stepped trench, the first trench and the second trench. The second drain metal layer fills downward into the second stepped trench.

[0010] The opening width W2 of the second groove is narrower than the opening width W1 of the first groove.

[0011] Furthermore, the first groove extends along a first direction, and one or more second grooves are arranged at intervals along the first direction and extend in a second direction.

[0012] Furthermore, the first groove and the second groove are connected in the second direction.

[0013] Furthermore, two or more sets of second grooves are arranged at intervals along the first direction and extend in the second direction, with each set of second grooves having the same arrangement.

[0014] Furthermore, two or more sets of second grooves are arranged at intervals along the first direction and extend in the second direction. The second set of second grooves that are farther away from the first groove are staggered with the first set of second grooves in the second direction. The interval D7 between the second grooves in the second set of second grooves in the first direction is greater than the interval D6 between the second grooves in the first set of second grooves in the first direction.

[0015] Furthermore, the opening width W2 of the second groove is wider on the left and narrower on the right along the second direction.

[0016] Furthermore, one or more second grooves are arranged at intervals along the first direction and extend obliquely.

[0017] Furthermore, the integrated field plate is connected to the gate structure.

[0018] Furthermore, one or more second grooves are arranged at intervals along the first direction and extend in the first direction.

[0019] Furthermore, one or more second grooves extend along the first direction and are arranged in parallel intervals in the second direction.

[0020] Furthermore, a third metal layer is provided in the first dielectric layer to the right of the gate structure, and the third metal layer is located in the horizontal direction between the gate structure and the first trench.

[0021] The present invention also provides a method for manufacturing a power semiconductor device with an integrated field plate structure, the method comprising the following steps:

[0022] The first step is to form a buffer layer, a channel layer and a barrier layer sequentially from bottom to top on the substrate layer. A patterned first source metal layer, a first drain metal layer and a gate structure are formed above the barrier layer. Then, a first dielectric layer and a third dielectric layer are formed sequentially above the device.

[0023] The second step is to perform photolithography on the surface of the third dielectric layer to form a patterned photoresist, and then etch the third dielectric layer to form the first trench, the second trench, the third trench and the fourth trench, and expose the first dielectric layer located below it, and remove the photoresist.

[0024] The third step involves depositing a second medium layer, which only covers the sidewalls and bottom of the first, third, and fourth trenches and does not completely fill them, while the second medium layer completely fills the second trench.

[0025] The fourth step is to perform wet etching on the second dielectric layer, leaving only the second dielectric layer located at the bottom of the second trench;

[0026] The fifth step involves photolithography to form patterned photoresist on the surface of the first dielectric layer in the third and fourth trenches, dry etching of the first dielectric layer at these two locations to form drain contact trenches and source contact trenches, exposing the first source metal layer and the first drain metal layer located below them, and then removing the photoresist.

[0027] The sixth step is to form an integrated field plate and a second drain metal layer on top of the device.

[0028] This invention employs a single integrated field plate, combined with first and second stepped trenches, which helps reduce electric field spikes between the gate and drain, and between the gate and source, resulting in a more uniform electric field distribution and improved device breakdown voltage and reliability. Furthermore, this invention provides a device manufacturing method with an integrated field plate structure, requiring only one photolithography and field plate deposition step to form a single integrated field plate with three layers of different heights, thus reducing process steps and production costs. Attached Figure Description

[0029] Figure 1 This is a cross-sectional schematic diagram of an existing high-voltage, high-electron-mobility transistor structure.

[0030] Figure 2 This is a cross-sectional schematic diagram of the device structure along the first direction according to the first embodiment of the present invention, and corresponding to... Figure 3 The midtangent is AA'.

[0031] Figure 3 This is a top view of the distribution of the first trench 220 and the second trench 221 in the first embodiment of the present invention.

[0032] Figure 4 This is a top view of the distribution of the first trench 220 and the second trench 221 in the third embodiment of the present invention.

[0033] Figure 5 This is a top view of the distribution of the first trench 220 and the second trench 221 in the fourth embodiment of the present invention.

[0034] Figure 6 This is a top view of the distribution of the first trench 220 and the second trench 221 in the fifth embodiment of the present invention.

[0035] Figure 7 This is a top view of the distribution of the first trench 220 and the second trench 221 in the sixth embodiment of the present invention.

[0036] Figure 8 This is a top view of the distribution of the first trench 220 and the second trench 221 in the seventh embodiment of the present invention.

[0037] Figure 9 This is a top view of the distribution of the first trench 220 and the second trench 221 in the eighth embodiment of the present invention.

[0038] Figure 10 This is a top view of the distribution of the first trench 220 and the second trench 221 in the ninth embodiment of the present invention.

[0039] Figure 11 This is a cross-sectional schematic diagram of the device structure according to the tenth embodiment of the present invention.

[0040] Figure 12 This is a top view of the distribution of the first trench 220 and the second trench 221 according to one embodiment of the present invention.

[0041] Figures 13-17 This is a key step in the manufacturing process of one embodiment of the present invention. Detailed Implementation

[0042] To facilitate understanding of the present invention, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that the positional terms used in this specification, such as "upper," "lower," "left," "right," "front," "back," "vertical," "horizontal," "vertical," and similar expressions, are for illustrative purposes only and correspond to the relative positions shown in the reference drawings. A fixed orientation is not limited in specific implementations. The devices in the drawings are not necessarily drawn to scale. The straight lines representing the boundaries of doped regions and trenches in the drawings, as well as the sharp angles formed by these boundaries, are generally not straight lines or precise angles in practical applications.

[0043] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0044] The term "Group III nitrides" as used in this text refers to compound semiconductors containing nitrogen (N) and at least one Group III element (aluminum Al, gallium Ga, indium In, boron B), including but not limited to their various alloys, such as aluminum boron nitride, (Al... x B (1-x) N), aluminum gallium nitride (Al) x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) N), gallium arsenide phosphide (GaAs) a P b N (1-a-b) ) and aluminum indium gallium arsenide phosphide alloy (Al x In y Ga (1-x-y) As a P b N (1-a-b) ), etc., among which aluminum gallium nitride (AlGaN) alloy has the chemical formula Al x Ga (1-x) N, 0 <x<1。

[0045] The terms "opening width" and "opening length" used in this article are used to name dimensions based on the relative side lengths of a rectangle. "Opening width" and "opening length" correspond to the shorter and longer sides of the rectangle, respectively. When both sides are of equal length, "opening width" and "opening length" are considered equal. The above terms only reflect the relative size of the side lengths and are unrelated to the rectangle's orientation, location, position, or combination of other components, nor do they constitute a limitation on its size or direction.

[0046] Referring to the accompanying drawings, the first direction referred to below is the Y direction in the drawings; the second direction, the horizontal direction, is the X direction in the drawings; and the third direction, the vertical direction, and the thickness direction are the Z direction in the drawings.

[0047] For high electron mobility transistors, this invention is applicable to both depletion-type and enhancement-type device structures. Example 1

[0048] Figure 2This is a cross-sectional schematic diagram of the device structure along the first direction according to the first embodiment of the present invention, and corresponding to... Figure 3 The tangent AA', the structure includes:

[0049] The substrate layer 200 is located at the bottom;

[0050] Buffer layer 201 located above substrate layer 200;

[0051] Channel layer 202 located above buffer layer 201;

[0052] Barrier layer 203 located above channel layer 202;

[0053] Gate structure 204 located above barrier layer 203;

[0054] The first source metal layer 206 and the first drain metal layer 207 are located above the barrier layer 203;

[0055] The first dielectric layer 210 is located above the barrier layer 203;

[0056] A third dielectric layer 212 located above the first dielectric layer 210;

[0057] The first trench 220, the second trench 221, the third trench 222, and the fourth trench 223 are located above the first dielectric layer 210; the bottom of the first trench 220, the second trench 221, the third trench 222, and the fourth trench 223 is the upper surface of the first dielectric layer 210; the source contact trench 217 is located below the third trench 222; the opening width of the source contact trench 217 is smaller than that of the third trench 222, and the third trench 222 and the source contact trench 217 combine to form a first stepped trench;

[0058] Below the fourth trench 223 is the drain contact trench 216; the opening width of the drain contact trench 216 is smaller than that of the fourth trench 223, and the fourth trench 223 and the drain contact trench 216 are combined to form a second stepped trench; there is a second dielectric layer 211 at the bottom of the second trench 221; an integral field plate 232 and a second drain metal layer 242 are located above the third dielectric layer 212.

[0059] Figure 3 This is a schematic diagram showing the top distribution of the first groove 220 and the second groove 221 in the first embodiment of the present invention.

[0060] like Figure 3As shown, L1 and W1 correspond to the opening length and opening width of the first groove 220, respectively; L2 and W2 correspond to the opening length and opening width of the second groove 221, respectively; D1 is the width of the first groove 220 at the tangent AA' section; D3 is the width of the second groove 221 at the tangent AA' section; D2 is the distance between the first groove 220 and the second groove 221 at the tangent AA' section; wherein, the opening width W2 of the second groove 221 is narrower than the opening width W1 of the first groove 220. In a specific embodiment, the size ratio of W1:W2 is 8:1.

[0061] The first groove 220 extends along a first direction, and one or more second grooves 221 are arranged at intervals along the first direction and extend in a second direction.

[0062] The opening length L2 of the second groove 221 is in the second direction, and the opening width W2 (short side) of the second groove 221 is in the first direction.

[0063] The first trench 220 and the second trench 221 are separated by a third dielectric layer 212.

[0064] Adjacent second trenches 221 are separated by a third dielectric layer 212.

[0065] In the horizontal direction, the first trench 220 and the second trench 221 are located between the gate structure 204 and the first drain metal layer 207; the first trench 220 is closer to the gate structure 204 than the second trench 221.

[0066] The substrate 200 is usually made of silicon, but it may also be made of materials such as gallium nitride, silicon carbide, or sapphire.

[0067] The buffer layer 201 is composed of group III nitride materials and may include multiple material layer combinations such as aluminum gallium nitride, aluminum nitride, gallium nitride, and aluminum boron nitride. This material layer combination may contain impurities such as carbon, iron, and magnesium.

[0068] The channel layer 202 may be an undoped, doped, or unintentionally doped group III nitride material layer.

[0069] The barrier layer 203 is composed of group III nitride materials, which may be a combination of multiple material layers such as aluminum gallium nitride, aluminum nitride, aluminum indium nitride, and boron nitride, typically aluminum gallium nitride. This combination of material layers may contain impurities such as carbon, iron, and magnesium. The barrier layer 203 may be an undoped, doped, or unintentionally doped group III nitride material layer.

[0070] In an enhancement device, the gate structure 204 may consist of a p-type gallium nitride layer and a gate metal layer. The p-type gallium nitride layer is located above the gate metal layer.

[0071] In a depletion-type device, the gate structure 204 may consist of a gate dielectric layer and a gate metal layer. The gate dielectric layer is located above the gate metal layer.

[0072] Optionally, the first dielectric layer 210 and the third dielectric layer 212 may be composed of the same material. The first dielectric layer 210 and the third dielectric layer 212 are typically composed of oxides or nitrides, such as, but not limited to, aluminum oxide, silicon oxide, gallium oxide, aluminum nitride, silicon nitride, etc. When the first dielectric layer 210 and the third dielectric layer 212 are composed of the same material, they can be considered as a single passivation layer and formed by the same step.

[0073] Optionally, the first dielectric layer 210 and the third dielectric layer 212 may be composed of different materials. The first dielectric layer 210 is typically composed of silicon nitride or silicon oxynitride, and its main function is to prevent degradation of dynamic on-resistance. The third dielectric layer 212 is typically composed of silicon dioxide, and its main function is to provide good insulation.

[0074] Optionally, the thickness of the first dielectric layer 210 is thinner than the thickness of the third dielectric layer 212. In some embodiments, the thickness of the third dielectric layer 212 is more than 10 times the thickness of the first dielectric layer 210.

[0075] Optionally, the thickness of the first dielectric layer 210 is thinner than the thickness of the gate structure 204.

[0076] In the above structure, the second dielectric layer 211 only fills part of the second trench 221.

[0077] In the above structure, the height (H3) of the upper surface of the third dielectric layer 212 is higher than the height (H2) of the upper surface of the second dielectric layer 211, and H2 is higher than the height (H1) of the upper surface of the first dielectric layer 210 (H3>H2>H1).

[0078] In the above structure, in the horizontal direction, D4 is the extension distance of the integral field plate 232 at the tangent AA' section, starting from the right side wall of the second trench 221 towards the drain electrode.

[0079] In the above structure, in the horizontal direction, D5 is the distance between the integrated field plate 232 and the second drain metal layer 242 at the tangent AA' section. D5 needs to be set according to the device breakdown voltage, as well as the corresponding creepage distance and safety clearance. Generally, the higher the breakdown voltage, the longer D5 is.

[0080] In the above structure, the integrated field plate 232 and the second drain metal layer 242 are typically composed of the same metallic material. This metallic material may include, but is not limited to, metals such as titanium, nickel, tungsten, aluminum, and gold, and their metal compounds.

[0081] In the above structure, the surface of the channel layer 202 has a horizontal two-dimensional electron gas (2DEG) and forms a current channel between the source and drain when the device is turned on.

[0082] Typically, the first trench 220 and the second trench 221 have the same depth. In some embodiments, the first trench 220 may be deeper than the second trench 221.

[0083] In one embodiment of a 650V enhancement-mode high electron mobility transistor, the horizontal distance between the gate structure 204 and the first drain metal layer 207 is approximately 30-50 μm, wherein H1 is approximately 0.1-0.5 μm, H2 is approximately 0.2-1 μm, H3 is approximately 0.3-5 μm, D1 is approximately 0.3-10 μm, D2 is approximately 0-5 μm, D3 is approximately 0.3-10 μm, and D5 is approximately 3-30 μm.

[0084] Compared with existing multi-field plate technology, the present invention adopts an integrated single-field plate, combined with a first stepped trench and a second stepped trench, which helps to reduce electric field spikes between the gate and drain, and between the gate and source, making the electric field distribution more uniform and improving the breakdown voltage and reliability of the device. Example 2

[0085] In some embodiments, the integrated field plate 232 may be connected to the gate structure 204. Example 3

[0086] In some embodiments, based on Embodiment 1, the first trench 220 and one or more second trenches 221 are connected in a second direction, such as... Figure 4 As shown. Example 4

[0087] In some embodiments, based on Embodiment 1, the opening length L2 of the second groove 221 is in the first direction, the opening width W2 of the second groove 221 is in the second direction, and the second grooves 221 are spaced apart along the first direction and extend in the first direction, such as... Figure 5 As shown. Example 5

[0088] In some embodiments, based on Embodiment 4, the second grooves 221 are changed from being spaced apart along the first direction to extending along the first direction, such as... Figure 6 As shown, this can improve the consistency and smoothness of the electric field distribution between channels. Example 6

[0089] In some embodiments, based on Embodiment 1, the opening length L2 direction of the second groove 221 is arbitrary. In one specific embodiment, the opening length L2 direction of the second groove 221 is at a 45-degree angle to the opening length L1 direction of the first groove, such as... Figure 7 As shown. Example 7

[0090] In some embodiments, based on Embodiment 1, the second grooves 221 may be arranged at intervals along a second direction. In one specific embodiment, the second grooves 221 are divided into two groups: a first group of second grooves 221a and a second group of second grooves 221b. Figure 8 As shown, the first group of second grooves 221a is located horizontally between the first groove 220 and the second group of second grooves 221b. In the first direction, the spacing distance (D6) between the first group of second grooves 221a is the same as the spacing distance (D7) between the second group of second grooves 221b, as shown. Figure 8 As shown.

[0091] Dividing the second trench 221 into a first group of second trenches 221a and a second group of second trenches 221b helps to prevent voids from appearing during the filling of the second trench, which would affect the device yield and reliability. Example 8

[0092] In some embodiments, based on Example 7, D6 is shorter than D7, such as... Figure 9 As shown, the first group of second trenches 221a and the second group of second trenches 221b are staggered in the horizontal direction. This makes the electric field distribution more uniform, improving the breakdown voltage and reliability of the device. Example 9

[0093] In some embodiments, based on Embodiment 1, the opening width W2 of the second groove 221 is wider on the left and narrower on the right along the second direction, for example, a triangle or a trapezoid. Figure 10 As shown.

[0094] The opening shape of the second trench 221 described above can make the electric field distribution more uniform, further improving the breakdown voltage and reliability of the device. Example 10

[0095] In some embodiments, a third metal layer 234 is provided to the right of the gate structure 204, such as Figure 11 As shown.

[0096] The third metal layer 234 is located within the first dielectric layer 210 and is situated horizontally between the gate structure 204 and the first trench 220.

[0097] The third metal layer 234 may be connected to the gate structure 204 or the first source metal layer 206.

[0098] The height (H0) of the upper surface of the third metal layer 234 is lower than the height of the bottom of the first trench 220.

[0099] The third metal layer 234 acts as a field plate, which can move the electric field peak further away from the gate structure 204, prevent high-energy electrons from accumulating at defects near the gate structure 204, prevent gate-related electrical failures of the device, and improve reliability.

[0100] Those skilled in the art should understand that the structural features mentioned in the various embodiments of the present invention above can be combined with each other to form more device structures according to the embodiments of the present invention. For example, combining embodiments 4 and 6 with each other can form a mesh structure, such as... Figure 12 As shown. Furthermore, different embodiments can be used simultaneously in different regions of the same chip.

[0101] Based on the structural features of the above embodiments of the present invention, and combined with existing high electron mobility transistor manufacturing processes, various methods for forming embodiments can be obtained. Figures 13-17 The key steps of the manufacturing process of one embodiment of the present invention are shown.

[0102] First, a buffer layer 201, a channel layer 202, and a barrier layer 203 are sequentially formed from bottom to top on the substrate layer 200. A patterned first source metal layer 206, a first drain metal layer 207, and a gate structure 204 are formed above the barrier layer 203. Then, a first dielectric layer 210 and a third dielectric layer 212 are sequentially formed above the device. Figure 13 As shown.

[0103] Typically, the first source metal layer 206 and the first drain metal layer 207 need to form ohmic contacts with the semiconductor located beneath them.

[0104] In some embodiments, the first dielectric layer 210 and the third dielectric layer 212 may be formed by chemical vapor deposition or other suitable deposition methods.

[0105] In some embodiments, the first dielectric layer 210 and the third dielectric layer 212 may be planarized after formation to reduce surface roughness and improve interface quality.

[0106] The second step involves photolithography on the surface of the third dielectric layer 212 to form a patterned photoresist. Then, the third dielectric layer 212 is etched to form the first trench 220, the second trench 221, the third trench 222, and the fourth trench 223, exposing the underlying first dielectric layer 210. The photoresist is then removed. Figure 14 As shown.

[0107] In some embodiments, the first dielectric layer 210 can serve as an etching stop layer for the first trench 220 and the second trench 221, so that the depths of the first trench 220 and the second trench 221 are kept consistent.

[0108] In some embodiments, the first dielectric layer 210 and the third dielectric layer 212 are composed of the same material and can form trenches in the same step using anisotropic dry etching, and the depth of the etched trenches can be controlled by adjusting the etching time.

[0109] In some embodiments, a combination of anisotropic dry etching and isotropic wet etching processes can also be used for etching.

[0110] The third step involves deposition to form a second dielectric layer 211. The second dielectric layer 211 only covers the sidewalls and bottom of the first trench 220, the third trench 222, and the fourth trench 223, not completely filling the trenches; however, the second dielectric layer 211 completely fills the second trench 221, as shown below. Figure 15 As shown.

[0111] In some embodiments, the material of the second dielectric layer 211 may be borosilicate glass (BPSG), which is reflowed after deposition. Using borosilicate glass can improve the filling capacity and prevent voids from forming in the trench.

[0112] The fourth step involves wet etching the second dielectric layer 211, leaving only a portion of the second dielectric layer 211 located at the bottom of the second trench 221, such as... Figure 16 As shown.

[0113] In some embodiments, a combination of anisotropic dry etching and isotropic wet etching processes can be used simultaneously to ensure that H2 > H1.

[0114] Fifth step: Photolithography is performed on the surface of the first dielectric layer 210 in the third trench 222 and the fourth trench 223 to form patterned photoresist. Dry etching is then performed on the first dielectric layer 210 at these two locations to form drain contact trench 216 and source contact trench 217, exposing the first source metal layer 206 and the first drain metal layer 207 located beneath them. The photoresist is then removed. Figure 17 As shown.

[0115] Step 6: Form an integrated field plate 232 and a second drain metal layer 242 on top of the device, such as... Figure 2 As shown.

[0116] The integrated field plate 232 and the second drain metal layer 242 are typically composed of the same metal material. This metal material may be formed by processes such as vapor deposition and sputtering, and patterned through process steps such as photolithography, dry etching, and wet etching.

[0117] In some embodiments, a method for manufacturing the integral field plate 232 and the second drain metal layer 242 is as follows: first, a metal with good trench filling ability, such as tungsten or titanium, is deposited to fill all trenches, and then a thicker layer of aluminum metal is formed by deposition. This can better prevent voids from occurring during the trench filling process.

[0118] The above-described device manufacturing method for the integrated field plate structure of the present invention only requires one photolithography and field plate deposition step. By utilizing the difference in opening width between the first trench 220 and the second trench 221, the second dielectric layer 211 is formed only in the second trench 221, thereby forming an integrated field plate with three different heights. This helps to reduce process steps and lower production costs.

[0119] Those skilled in the art will understand that the above manufacturing steps only list the key steps and do not show the complete process for forming the device. Specific, detailed manufacturing steps can be derived from common manufacturing processes and general knowledge, and can be appropriately added to, subtracted from, or modified.

Claims

1. A power semiconductor device of an integrated field plate structure, the power semiconductor device comprising a substrate layer (200) at the bottom, a buffer layer (201) above the substrate layer (200), a channel layer (202) above the buffer layer (201), a barrier layer (203) above the channel layer (202), a first source metal layer (206), a gate structure (204), a first drain metal layer (207) and a first dielectric layer (210) above the barrier layer (203), a third dielectric layer (212) above the first dielectric layer (210), a source contact trench (217) above the first source metal layer (206), and a drain contact trench (216) above the first drain metal layer (207), characterized in that, The third dielectric layer (212) is provided above the first dielectric layer (210) between the gate structure (204) and the first drain metal layer (207), and one or more first grooves (220) and second grooves (221) are formed in the third dielectric layer (212), wherein the first grooves (220) are closer to the gate structure (204) than the second grooves (221), and the second grooves (221) are provided with the second dielectric layer (211) at the bottom; the height H3 of the upper surface of the third dielectric layer (212) is higher than the height H2 of the upper surface of the second dielectric layer (211), and the height H2 of the upper surface of the second dielectric layer (211) is higher than the height H1 of the upper surface of the first dielectric layer (210); The source contact groove (217) and part of the first dielectric layer (210) are provided with the third groove (222) above them, and the source contact groove (217) and the third groove (222) combine to form the first stepped groove; The drain contact groove (216) and part of the first dielectric layer (210) are provided with the fourth groove (223) above them, and the drain contact groove (216) and the fourth groove (223) combine to form the second stepped groove; The integral field plate (232) and the second drain metal layer (242) are further provided above the third dielectric layer (212) and are separated from each other, the integral field plate (232) is filled downward into the first stepped groove, the first groove (220) and the second groove (221), and the second drain metal layer (242) is filled downward into the second stepped groove; The opening width W2 of the second groove (221) is narrower than the opening width W1 of the first groove (220), and the opening width W2 of the second groove (221) is in the first direction, and the first groove (220) extends along the first direction.

2. The power semiconductor device of one-piece field plate structure of claim 1, wherein, The first groove (220) extends along the first direction, and one or more second grooves (221) are arranged in the first direction and extend in the second direction.

3. The power semiconductor device of one-piece field plate structure of claim 2, wherein, The first groove (220) and the second groove (221) are connected in the second direction.

4. The power semiconductor device of one piece field plate structure of claim 2, wherein, Two or more groups of second grooves (221) are arranged in the first direction and extend in the second direction, and each group of second grooves (221) is arranged in the same way.

5. The power semiconductor device of one-piece field plate structure of claim 2, wherein, Two or more groups of second grooves (221) are arranged in the first direction and extend in the second direction, and the second group of second grooves (221) farther from the first groove (220) is arranged in the second direction in a staggered manner with the first group of second grooves (221), wherein the interval D7 between the second grooves (221) in the first direction in the second group of second grooves (221) is greater than the interval D6 between the second grooves (221) in the first direction in the first group of second grooves (221).

6. The power semiconductor device of one piece field plate structure of claim 2, wherein, The opening width W2 of the second groove (221) is in the shape of "left large and right small" along the second direction.

7. The power semiconductor device of one piece field plate structure of claim 1, wherein, One or more second grooves (221) are arranged in the first direction and extend in a diagonal direction.

8. The power semiconductor device of one piece field plate structure of claim 1, wherein, The integral field plate (232) is connected to the gate structure (204).

9. The power semiconductor device of one piece field plate structure of claim 1, wherein, One or more second grooves (221) are arranged in the first direction and extend in the first direction.

10. The power semiconductor device of one piece field plate structure of claim 1, wherein, The second grooves (221) extend in the first direction and are arranged in parallel in the second direction.

11. The power semiconductor device of one-piece field plate structure of claim 1, wherein, The third metal layer (234) is arranged in the first dielectric layer (210) on the right of the gate structure (204) and is located between the gate structure (204) and the first groove (220) in the horizontal direction.

12. The method of manufacturing a power semiconductor device with an integral field plate structure according to any one of claims 1 to 11, characterized in that The manufacturing method comprises the following steps: In the first step, a buffer layer (201), a channel layer (202) and a barrier layer (203) are sequentially formed on the substrate layer (200) from bottom to top, a patterned first source metal layer (206), a first drain metal layer (207) and a gate structure (204) are formed above the barrier layer (203), and then a first dielectric layer (210) and a third dielectric layer (212) are sequentially formed above the device; In the second step, photoresist is formed by photoetching on the surface of the third dielectric layer (212), the third dielectric layer (212) is etched to form a first groove (220), a second groove (221), a third groove (222) and a fourth groove (223), and the first dielectric layer (210) below is exposed, and the photoresist is removed; In the third step, a second dielectric layer (211) is formed by deposition, the second dielectric layer (211) only covers the sidewalls and bottom of the first groove (220), the third groove (222) and the fourth groove (223) and does not completely fill the grooves, and the second dielectric layer (211) completely fills the second groove (221); In the fourth step, the second dielectric layer (211) is wet-etched, and only the second dielectric layer (211) at the bottom of the second groove (221) remains; In the fifth step, photoresist is formed by photoetching on the surface of the first dielectric layer (210) in the third groove (222) and the fourth groove (223), the first dielectric layer (210) in the two places is dry-etched to form a drain contact groove (216) and a source contact groove (217), and the first source metal layer (206) and the first drain metal layer (207) below are exposed, and the photoresist is removed; In the sixth step, an integrated field plate (232) and a second drain metal layer (242) are formed above the device.

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