Semiconductor device, method for manufacturing semiconductor device, and communication device

Abstract

There is provided a semiconductor device including: a ternary compound semiconductor layer or a quaternary compound semiconductor layer; a first insulating layer laminated on the compound semiconductor layer and having a first opening exposing a first region on an upper surface of the compound semiconductor layer; a second insulating layer that is laminated on the first insulating layer and within the first opening and has a second opening that has an opening narrower than the first opening and exposes a second region that is a part of a first region of the compound semiconductor layer that is exposed by the first opening; and a gate electrode laminated on the upper surface of the second insulating layer and within the second opening, and in direct contact with a second region on the upper surface of the compound semiconductor layer.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, methods for manufacturing semiconductor devices, and communication devices. Background Technology

[0002] High electron mobility transistors (HEMTs), which are heterogeneous field-effect transistors (FETs) made of materials such as gallium nitride (GaN) as wide-bandgap semiconductors, are expected to be used in power devices or radio frequency (RF) devices, such as switches in 5G high-speed communication systems, due to their low resistance and ability to operate at high speed and high voltage.

[0003] Reference List

[0004] Patent documents

[0005] PTL 1: JP 2021-125575 A

[0006] PTL 2: JP 2020-13883 A Summary of the Invention

[0007] Technical issues

[0008] However, in HEMT devices of related technologies, it is difficult to suppress the degradation of on-state characteristics while reducing the off-state current determined by gate leakage. In addition, even if it is possible to suppress the degradation of on-state characteristics while reducing the off-state current, it is difficult to avoid greatly complicating the manufacturing process and even causing damage to the semiconductor surface.

[0009] Therefore, this disclosure proposes a semiconductor device that can be manufactured by a simple and non-destructive method and can suppress the degradation of on-state characteristics while reducing off-state current, a method for manufacturing the semiconductor device, and a communication device equipped with a reaction device.

[0010] Solution to the problem

[0011] According to this disclosure, a semiconductor device is provided, comprising: a compound semiconductor layer, which is a ternary compound semiconductor layer or a quaternary compound semiconductor layer; a first insulating layer, which is stacked on the compound semiconductor layer and includes a first opening that exposes a first region on the upper surface of the compound semiconductor layer; a second insulating layer, which is stacked on the first insulating layer and within the first opening and includes a second opening, the second opening having a narrower opening than the first opening and exposing a second region of the compound semiconductor layer that is part of the first region exposed by the first opening; and a gate electrode, which is stacked on the upper surface of the second insulating layer and within the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer.

[0012] Additionally, according to this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: stacking a first insulating layer on a compound semiconductor layer, which is a ternary compound semiconductor layer or a quaternary compound semiconductor layer, the first insulating layer including a first opening that exposes a first region on the upper surface of the compound semiconductor layer; performing a reduction process on the first region; stacking a second insulating layer on the first insulating layer and within the first opening, the second insulating layer including a second opening having a narrower opening than the first opening and exposing a second region of the compound semiconductor layer that is part of the first region exposed by the first opening; and forming a gate electrode on the upper surface of the second insulating layer and within the second opening that is in direct contact with the second region on the upper surface of the compound semiconductor layer.

[0013] Additionally, according to this disclosure, a communication device including a semiconductor device is provided. The semiconductor device includes: a compound semiconductor layer, which is a ternary compound semiconductor layer or a quaternary compound semiconductor layer; a first insulating layer stacked on the compound semiconductor layer and including a first opening that exposes a first region on the upper surface of the compound semiconductor layer; a second insulating layer stacked on the first insulating layer and within the first opening and including a second opening, the second opening having a narrower opening than the first opening and exposing a second region of the compound semiconductor layer that is part of the first region exposed by the first opening; and a gate electrode stacked on the upper surface of the second insulating layer and within the second opening, the gate electrode being in direct contact with the second region on the upper surface of the compound semiconductor layer. Attached Figure Description

[0014] Figure 1 This is a schematic diagram illustrating a HEMT device with a MIS gate structure.

[0015] Figure 2 This is a schematic diagram illustrating a HEMT device with a Schottky gate structure.

[0016] Figure 3 This is an explanatory diagram (part 1) used to describe the details of the research conducted by the inventors.

[0017] Figure 4 This is an explanatory diagram (part 2) used to describe the details of the research conducted by the inventors.

[0018] Figure 5 This is an explanatory diagram (part 3) used to describe the details of the research conducted by the inventors.

[0019] Figure 6This is an explanatory diagram (part 4) used to describe the details of the research conducted by the inventors.

[0020] Figure 7 This is an explanatory diagram (part 5) used to describe the details of the research conducted by the inventors.

[0021] Figure 8 This is an explanatory diagram (part 6) used to describe the details of the research conducted by the inventors.

[0022] Figure 9 This is an explanatory diagram (part 7) used to describe the details of the research conducted by the inventors.

[0023] Figure 10 This is an explanatory diagram (part 8) used to describe the details of the research conducted by the inventors.

[0024] Figure 11 This is an explanatory diagram (part 9) used to describe the details of the research conducted by the inventors.

[0025] Figure 12 This is an explanatory diagram (part 10) used to describe the details of the research conducted by the inventors.

[0026] Figure 13A This is a cross-sectional view of the structure of a HEMT device according to a first embodiment of the present disclosure.

[0027] Figure 13B yes Figure 13A The diagram shows an enlarged cross-sectional view of region B.

[0028] Figure 14A This is a cross-sectional view (part 1) used to describe a method for manufacturing a HEMT device according to a first embodiment of the present disclosure.

[0029] Figure 14B This is a cross-sectional view (part 2) used to describe a method for manufacturing a HEMT device according to a first embodiment of the present disclosure.

[0030] Figure 14C This is a cross-sectional view (part 3) used to describe a method for manufacturing a HEMT device according to a first embodiment of the present disclosure.

[0031] Figure 14D This is a cross-sectional view (part 4) used to describe a method for manufacturing a HEMT device according to a first embodiment of the present disclosure.

[0032] Figure 14E This is a cross-sectional view (part 5) used to describe a method for manufacturing a HEMT device according to a first embodiment of the present disclosure.

[0033] Figure 14FThis is a cross-sectional view (part 6) used to describe a method for manufacturing a HEMT device according to a first embodiment of the present disclosure.

[0034] Figure 14G This is a cross-sectional view (part 7) used to describe a method for manufacturing a HEMT device according to a first embodiment of the present disclosure.

[0035] Figure 15A This is a cross-sectional view of the structure of a HEMT device according to a second embodiment of the present disclosure.

[0036] Figure 15B yes Figure 15A The diagram shows an enlarged cross-sectional view of region C.

[0037] Figure 16A This is a cross-sectional view (part 1) used to describe a method for manufacturing a HEMT device according to a second embodiment of the present disclosure.

[0038] Figure 16B This is a cross-sectional view (part 2) used to describe a method for manufacturing a HEMT device according to a second embodiment of the present disclosure.

[0039] Figure 16C This is a cross-sectional view (part 3) used to describe a method for manufacturing a HEMT device according to a second embodiment of the present disclosure.

[0040] Figure 17A This is a cross-sectional view of the structure of a HEMT device according to a third embodiment of the present disclosure.

[0041] Figure 17B yes Figure 17A The diagram shows an enlarged cross-sectional view of region D.

[0042] Figure 18A This is a cross-sectional view (part 1) used to describe a method for manufacturing a HEMT device according to a third embodiment of the present disclosure.

[0043] Figure 18B This is a cross-sectional view (part 2) used to describe a method for manufacturing a HEMT device according to a third embodiment of the present disclosure.

[0044] Figure 19 These are explanatory diagrams illustrating application examples of HEMT devices according to various embodiments of the present disclosure. Detailed Implementation

[0045] In the following, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in this specification and the drawings, components having substantially the same functional configuration are represented by the same reference numerals, and redundant descriptions will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations can be distinguished from each other by adding different letters after the same reference numerals. However, when it is not necessary to specifically distinguish multiple components having substantially the same or similar functional configurations, only the same reference numerals are assigned.

[0046] Furthermore, the accompanying drawings referenced in the following description are intended to explain embodiments of this disclosure and facilitate understanding thereon, and for ease of understanding, the shapes, dimensions, scales, etc., illustrated in the drawings may differ from actual shapes, dimensions, scales, etc. Moreover, the design of the apparatus illustrated in the drawings can be appropriately modified in light of the following description and known technologies.

[0047] Note that the descriptions will be presented in the following order.

[0048] 1. Background

[0049] 2. Study of the embodiments of this disclosure

[0050] 3. First Embodiment

[0051] 3.1 Detailed Configuration

[0052] 3.2 Manufacturing Method

[0053] 4. Second Embodiment

[0054] 4.1 Detailed Configuration

[0055] 4.2 Manufacturing Method

[0056] 5. Third Embodiment

[0057] 5.1 Detailed Configuration

[0058] 5.2 Manufacturing Method

[0059] 6. Summary

[0060] 7. Application Examples

[0061] 8. Supplement

[0062] 1. Background

[0063] First, refer to Figure 1 and Figure 2 The background that led the inventors to create the embodiments of this disclosure is described. Figure 1 This is a schematic diagram illustrating a HEMT device 10b with a MIS gate structure. Figure 2This is a schematic diagram illustrating a HEMT device 10a with a Schottky gate structure.

[0064] GaN, as a wide-bandgap semiconductor material, possesses characteristics such as high dielectric breakdown voltage, high-temperature operation, and high saturation drift velocity. Furthermore, the two-dimensional electron gas (2DEG) layer formed in GaN-based heterojunctions exhibits high mobility and high sheet electron density. Due to these properties, GaN HEMTs, as a type of GaN-based heteroFET, exhibit low resistance and are capable of high-speed and high-voltage operation, making them promising applications in power devices and RF devices such as switches in 5G high-speed communication systems. GaN HEMTs are particularly promising for use in power amplifiers (hereinafter referred to as PAs) in millimeter-wave bands where spatial attenuation is significant, where characteristics such as power density, power-added efficiency, and output (Pout) are crucial.

[0065] Here, the 2DEG layer will be described. The 2DEG layer is a layer in which electrons are distributed in a two-dimensional manner. Specifically, a sheet-like electron distribution is obtained at the heterojunction interface through polarization generated in the crystal, which is one of the characteristics of group III nitrides. The sheet-like layer obtained through this electron distribution is called the 2DEG layer, and the 2DEG layer is used as the channel of HEMT devices.

[0066] First, refer to Figure 1 The configuration of HEMT device 10b with a general metal-insulator-semiconductor (MIS) gate structure is described. For example... Figure 1 As illustrated in the upper part, the HEMT device 10b with a MIS structure includes a GaN buffer layer 110 on a substrate 100 and a GaN channel layer 112 on the GaN buffer layer 110 forming a 2DEG layer 114. Furthermore, in the MIS structure, a layer composed of AlGaN, AlInN, etc., is formed as a barrier layer 120 on the GaN channel layer 112 to form a heterojunction. Additionally, in the MIS structure, to control the current flowing between the source 160a and the drain 160b, a gate insulating film 140 and a gate electrode 152 are formed on the barrier layer 120, interposed between the source 160a and the drain 160b.

[0067] In the HEMT device 10b having the above-described MIS gate structure, when stress such as voltage or temperature is applied, electrons are trapped at the interface between the gate insulating film 140 and the semiconductor layer (specifically, the barrier layer 120), or electrons are emitted from the traps. Therefore, as Figure 1As shown in the lower part, the actual measured value of the threshold voltage Vth of the HEMT device 10b may fluctuate towards the positive or negative side compared to the theoretical value. Therefore, when fluctuations in the threshold voltage Vth occur during operation, device control becomes difficult. Consequently, there are concerns regarding the reliability of the HEMT device 10b with its MIS gate structure during long-term use.

[0068] Due to this concern, it is considered that HEMT devices 10a with Schottky gate structures rather than MIS gate structures are preferably used in RF devices in 5G high-speed communication systems. Specifically, such as Figure 2 As illustrated in the upper part, the HEMT device 10a with a Schottky gate structure also includes a GaN buffer layer 110 on a substrate 100 and a GaN channel layer 112 on the GaN buffer layer 110 forming a 2DEG layer 114. Furthermore, in the Schottky gate structure, a barrier layer 120 is formed on the GaN channel layer 112 to form a heterojunction. Additionally, in the Schottky gate structure, a gate electrode 152 is formed on the barrier layer 120. In this way, since there is no gate insulating film 140 in the Schottky gate structure, the number of trap sources is less than that in the MIS gate structure; therefore, the threshold voltage Vth is less likely to fluctuate.

[0069] However, as Figure 2 As shown in the lower part, because there is no gate insulating film 140, the HEMT device 10a with a Schottky gate structure has a higher turn-off current determined by gate leakage than the HEMT device with a MIS gate structure. Moreover, because the electric field strength is high at the gate end of the gate electrode 152, leakage current may be generated significantly.

[0070] The off-state current, determined by gate leakage, is the current flowing between the gate electrode 152 and the 2DEG layer 114, and to improve this, it is effective to alleviate the electric field concentration at the gate end of the gate electrode 152. Therefore, it is conceivable to alleviate the electric field by utilizing the field plate effect (FP effect) by adjusting the shape of the gate electrode 152, but there are limitations to the improvement that can be achieved by adjusting the shape.

[0071] Additionally, as a method for improving gate leakage, a depletion layer 170 (see [reference]) is generated in the region directly below the gate electrode 152 on the drain 160b side of the semiconductor layer (specifically, the barrier layer 120) when a voltage is applied. Figure 9It is easier to extend (easily expand). Therefore, it is conceivable to reduce the electron concentration Ns in the channel by changing the composition of the barrier layer 120 (e.g., increasing the In concentration in the barrier layer 120 composed of AlInN) or by thinning the barrier layer 120. However, in this method, the electron concentration Ns decreases uniformly throughout the entire region of the HEMT device 10a. Therefore, in particular, the resistance on the source 160a side is increased, and thus, degradation of on-state characteristics such as an increase in the on-resistance (Ron) or a decrease in the on-state current (Id) of the HEMT device 10a may occur. Accordingly, a decrease in the power density of the HEMT device 10a occurs.

[0072] Alternatively, it is conceivable to solve the above problems by partially changing the composition of the barrier layer 120 or by thinning the barrier layer 120, but this approach would greatly complicate the manufacturing process and further make the semiconductor surface more likely to be damaged.

[0073] Therefore, in view of such circumstances, the inventors have repeatedly sought to obtain a structure that can be manufactured by a simple and non-destructive method and can suppress the degradation of on-state characteristics while reducing the off-state current determined by gate leakage. Then, in the course of this exploration, the inventors created embodiments of the present disclosure that can be manufactured by a simple and non-destructive method and can suppress the degradation of on-state characteristics while reducing the off-state current.

[0074] 2. Study of the embodiments of this disclosure

[0075] First, refer to Figures 3 to 12 Details of the research conducted by the inventors in order to create embodiments of this disclosure are described. Figures 3 to 12 These are explanatory diagrams used to describe the details of the research conducted by the inventors.

[0076] The inventors have investigated methods to make the depletion layer more likely to extend (expand) using Technical Computer-Aided Design Simulation (TCAD Sim) in order to obtain a structure that can be fabricated in a simple and non-destructive manner and can suppress the degradation of the on-state characteristics while reducing the off-state current determined by gate leakage. Specifically, the inventors have investigated methods to make the state of the fixed charge on the surface of the barrier layer 120 (semiconductor layer) negative, thereby making the depletion layer 170 (see Figure 9A more likely approach was investigated to reduce the electron concentration Ns in the channel. In this investigation, the inventors focused on the surface of the barrier layer 120 (semiconductor layer) surrounding the gate electrode 152. It was then discovered that on the surface of the barrier layer 120 surrounding the gate electrode 152, as the positive fixed charge decreases or as the negative fixed charge increases, the depletion layer 170 extends further toward the drain 160b side, thereby mitigating the electric field at the gate end of the gate electrode 152 and reducing the off-state current determined by gate leakage.

[0077] Specifically, such as Figure 3 As illustrated, the inventors performed TCAD Sim under the following conditions: a fixed charge density of 5.0 e12 / cm² was set in region A of the barrier layer 120 located around the gate electrode 152 and sandwiched between the gate electrode 152 and the drain electrode 154 (and the source electrode). 2 (Positive fixed charge), none, and -5.0e12 / cm 2 (Negative fixed charge). Under each condition, the Vg (gate voltage) - Id (drain current) characteristics were calculated (with Vd (drain voltage) = 5V applied). The results showed that in region A, the turn-off current determined by gate leakage decreased as the amount of positive fixed charge decreased or as the amount of negative fixed charge increased.

[0078] In addition, the inventors have used TCAD Sim to investigate how the off-state current, determined by gate leakage, changes when the surface of the barrier layer 120 (semiconductor layer) surrounding the gate electrode 152 is divided into multiple regions and the fixed surface charge density is varied in each region.

[0079] Specifically, such as Figure 4 As illustrated, the surface of the barrier layer 120 of the HEMT device 10a with a Schottky gate structure is divided into three regions: the region between the gate electrode 152 and the source 160a (GS) (region a), the region directly below the gate electrode 152 (region b), and the region between the gate electrode 152 and the drain 160b (GD) (region b). Furthermore, the fixed charge density of the corresponding regions is set to 5.0 e12 / cm². 2 (Positive fixed charge), none, and -5.0e12 / cm 2 (Negative fixed charge). Then, under each condition, the Vg-Id characteristics were calculated (with Vd = 5V applied).

[0080] first, Figure 5The results are shown when the fixed charge density is varied across all regions a, b, and c. In this case, the smaller the amount of positive fixed charge or the larger the amount of negative fixed charge in regions a, b, and c, the smaller the off-state current determined by gate leakage. Additionally, as the positive fixed charge decreases or the negative fixed charge increases in regions a, b, and c, the on-state current (Id) in the on-state also decreases (the scale used on the vertical axis is a linear scale). Therefore, there is a concern that the power density in the HEMT device 10a may decrease.

[0081] Next, Figure 6 The results obtained by varying the fixed charge density in regions a and c (i.e., the regions outside the gate electrode 152) are shown. In this case, both the off-state current and the on-state current are related to... Figure 5 The effect of changing the fixed charge density is the same in all regions a, b, and c. This result indicates that the effect of changing the fixed charge density on the off-state current and on-state current is mainly due to the change in the fixed charge density in the region outside the gate electrode 152.

[0082] Next, Figure 7 The results are shown when the fixed charge density is varied in region a (i.e., the region between G and S (GS)). In this case, the off-state current does not change (no sensitivity). Furthermore, in region a, the on-state current (Id) decreases as the positive fixed charge decreases or the negative fixed charge increases (the scale used on the vertical axis is linear). This is because when the fixed charge density in region a changes, the extension of the depletion layer 170 towards the drain 160b side does not change, and only the source resistance increases. This state is the least desirable state for device characteristics.

[0083] Next, Figure 8 The results obtained by varying the fixed charge density in region c (i.e., the region between G and D (GD)) are shown. In region c, the off-state current, determined by gate leakage, decreases as the positive fixed charge decreases or as the negative fixed charge increases. Furthermore, the on-state current (Id) does not change significantly even when the fixed charge density in region c is varied. This result indicates that when the fixed charge density is varied in the negative direction in region c, the depletion layer 170 extends towards the drain 160b side and the source resistance increases only slightly. This state represents the most preferred state for device characteristics.

[0084] As a result of the inventor's own research, it was found that if the fixed charge density can be changed in the negative direction in region c (i.e., the region between G and D (GD)), the degradation of the on-state characteristics can be suppressed while reducing the off-state current determined by gate leakage.

[0085] Therefore, the inventors investigated which range of the region between G and D (GD) should be changed in the negative direction to reduce the off-state current determined by gate leakage.

[0086] In this case, such as Figure 9 As illustrated, to define the range of the region where the fixed charge density between G and D (GD) changes in the negative direction, the distance from the end face of the drain 160b side of a portion of the gate electrode 152 that is in direct contact with the surface of the barrier layer 120 to the end of the drain 160b side of the region where the fixed charge density changes in the negative direction is defined as Ld. Then, Figure 10 This illustrates when the fixed charge density of the surface region is set to -5.0e12 / cm². 2 The calculated results of the Vg-Id characteristics (with Vd = 5V applied) obtained by changing the distance Ld when (with a negative fixed charge). Additionally, in Figure 11 In the figure, the curve of the off-state current relative to the distance Ld when Vg = -5V is plotted.

[0087] As from Figure 11 It can be seen that when the distance Ld is equal to or greater than 5 nm, the off-state current decreases rapidly. Furthermore, as the distance Ld increases, the effect of reducing the off-state current gradually saturates and becomes difficult to achieve near 100 nm. That is, in order to reduce the off-state current determined by gate leakage, it is considered effective to set the range of the region where the fixed charge density changes in the negative direction to a position 5 nm to 100 nm away from the end face of the drain 160b side of the portion of the gate electrode 152 that directly contacts the surface of the barrier layer 120.

[0088] In addition, the inventors investigated the extent to which the expansion of the region where the fixed charge density between G and S (GS) changes in the negative direction should be suppressed, thereby suppressing the deterioration of the on-state characteristics.

[0089] Here, as Figure 9 As illustrated, to define the range of the region where the fixed charge density changes in the negative direction between G and S (GS), the distance from the end face of the source 160a side of a portion of the gate electrode 152 that is directly in contact with the surface of the barrier layer 120 to the end of the source 160a side of the region where the fixed charge density changes in the negative direction is defined as Ls. Then, when the fixed charge density of the surface region is set to -5.0e12 / cm²... 2 The Vg-Id characteristics were calculated when the distance Ls was changed (with a negative fixed charge) (applied Vd = 5V), and... Figure 12 The figure shows a plot of the drain current value relative to the distance Ls when Vg = 0V.

[0090] As from Figure 12 As can be seen, the on-state current (Id) decreases accordingly with the increase of distance Ls. That is, in order to suppress the decrease of the on-state current, it is effective to consider that the region where the fixed charge density between G and S (GS) changes in the negative direction should not extend as far as possible toward the source 160a side.

[0091] Therefore, based on the research results to date, the inventors have created the structure of the HEMT device 10 as described below. Specifically, in the HEMT device 10 created by the inventors according to the embodiments of this disclosure (see...), Figure 13A In this embodiment, when the gate electrode 152 is formed, the gate opening relative to the surface of the barrier layer 120 is wider on the drain 160b side than on the source 160a side. Then, by performing a reduction process on the surface of the barrier layer 120 exposed by the opening, the fixed charge density of the surface changes in the negative direction. Furthermore, in embodiments of this disclosure, after the reduction process, the gate electrode 152 is formed at a position closer to the source 160a side than the center of the gate opening. By employing this configuration, the surface of a specific semiconductor layer (specifically, the barrier layer 120) located between the gate electrode 152 and the drain 160b can be selectively charged with a negative charge. As a result, according to embodiments of this disclosure, the reduction in the on-state current and the off-state current determined by gate leakage can be suppressed.

[0092] In the following description, details of the structure of the HEMT device 10 according to various embodiments of the present disclosure created by the inventors will be described in turn, each embodiment enabling the surface of a particular semiconductor layer (specifically, barrier layer 120) to selectively carry a negative charge.

[0093] 3. First Embodiment

[0094] 3.1 Detailed Configuration

[0095] First, refer to Figure 13A and Figure 13B The detailed structure of the HEMT device 10 according to the first embodiment of the present disclosure is described. Figure 13A This is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Figure 13B yes Figure 13A An enlarged cross-sectional view of region B is shown in the figure. Note that in all figures referenced in the following description, the restored surface 122 is indicated by a thick line.

[0096] like Figure 13AAs illustrated, the HEMT device 10 according to this embodiment includes a buffer layer 110 on a substrate 100 and a channel layer 112 on the buffer layer 110 forming a 2DEG layer 114. In this embodiment, a barrier layer 120 is formed on the channel layer 112 to form a heterojunction. Furthermore, in this embodiment, a source electrode 160a and a drain electrode 160b are formed sandwiching the barrier layer 120. Additionally, the thickness of the barrier layer 120 located below the insulating layer 132 (described later) is the same as the thickness of the barrier layer 120 located below the gate electrode 152 (described later). That is, the barrier layer 120 is a continuous layer with a uniform thickness. Note that in the following description, the stacked layer from the substrate 100 to the barrier layer 120 is also referred to as a compound semiconductor layer.

[0097] In this embodiment, an insulating layer (first insulating layer) 132 having an opening (first opening) 132a is stacked on the barrier layer 120. The opening 132a exposes a reduced surface (first region) 122, which is part of the upper surface of the barrier layer 120. Additionally, an insulating layer (second insulating layer) 130 is stacked on the insulating layer 132 and within the opening 132a. The insulating layer 130 has an opening (second opening) 130a that exposes a portion (second region) of the reduced surface 122 exposed by the opening 132a above the upper surface of the barrier layer 120 and has an opening narrower than the opening 132a.

[0098] Specifically, the center of opening 130a is located closer to the source electrode 160a than the center of opening 132a. Furthermore, the inner surface of opening 132a on the source electrode 160a side is located on the source electrode 160a side relative to the inner surface of opening 130a on the source electrode 160a side. Additionally, the inner surface of opening 132a on the drain electrode 160b side is located on the drain electrode 160b side relative to the inner surface of opening 130a on the drain electrode 160b side.

[0099] In addition, in this embodiment, a gate electrode 152 is formed on the insulating layer 130 located between the source electrode 160a and the drain electrode 160b and inside the opening 130a, which is in direct contact with the upper surface (second region) of the barrier layer 120 exposed through the opening 130a.

[0100] In this embodiment, by having this structure, a region on the surface of a specific semiconductor layer located between the gate electrode 152 and the drain electrode 160b is subjected to a reduction process and selectively carries a negative charge.

[0101] In this embodiment, as Figure 13BAs illustrated, the reduced surface 122 is region d (first region), which is part of the upper surface of the barrier layer 120 sandwiched between the source 160a and the drain 160b. Specifically, the reduced surface 122 includes region c (third region) located on the drain 160b side, relative to region b (second region) which is in direct contact with the gate electrode 152 and the barrier layer 120. Additionally, the reduced surface 122 also includes region b, which is in direct contact with the gate electrode 152 and the barrier layer 120. Furthermore, the reduced surface 122 includes region a (fourth region) located on the source 160a side, relative to region b. In this embodiment, region c is wider than region a.

[0102] Furthermore, in this embodiment, the distance Ld between the end of the drain 160b side of region c and the end face of the drain 160b side of the gate electrode 152 that directly contacts region b is preferably from 5 nm to 100 nm. Additionally, in this embodiment, the distance Ls between the end of the source 160a side of region a and the end face of the source 160a side of the gate electrode 152 that directly contacts region b is preferably as short as possible.

[0103] In this embodiment, since the reduced-treated surface 122 (region d) in direct contact with the gate electrode 152 and the insulating layer 130 has undergone reduction treatment, the reduced-treated surface 122 has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120 other than region d (specifically, the upper surface of the barrier layer 120 in direct contact with the insulating layer 132). In this embodiment, by adopting this configuration, the channel electron concentration Ns of the reduced-treated surface 122 can be reduced compared to the upper surface of the barrier layer 120 other than region d (specifically, the upper surface of the barrier layer 120 in direct contact with the insulating layer 132). For example, the reduced-treated surface 122 may have a smaller amount of oxygen or a larger amount of hydrogen than the upper surface of the barrier layer 120 other than region d. Note that the oxygen and hydrogen amounts can be analyzed using, for example, secondary ion mass spectrometry (SIMS).

[0104] Furthermore, in this embodiment, the gate electrode 152 is in direct contact with the barrier layer 120. Additionally, in this embodiment, the following structure is adopted: the gate electrode 152 is... Figure 13B A portion of region c, as illustrated, protrudes above the insulating layer 130. Then, in this embodiment, the film thickness t1 of the insulating layer 130 is reduced (e.g., from 5 nm to 50 nm) to narrow the distance between the gate electrode 152 and the barrier layer 120 (the reduced surface 122) in region c. In this embodiment, by employing this configuration, a field plate effect due to the shape of the gate electrode 152 is exhibited, thus mitigating the electric field at the gate end of the gate electrode 152.

[0105] In addition, the details of each layer will be described in turn.

[0106] The substrate 100 is made of a semiconductor material and can be formed of a ternary or quaternary compound semiconductor material such as a III-V compound semiconductor material, and more specifically, of a semi-insulating single-crystal GaN substrate, for example. Note that the substrate 100 can be a substrate having a lattice constant different from that of the channel layer 112, controlled by the buffer layer 110 described later. Specifically, substrates such as silicon carbide (SiC), sapphire, or silicon (Si) substrates can be used as the substrate 100. In particular, when using a Si substrate, an advantage is gained in terms of the ability to use inexpensive materials with large diameters.

[0107] The buffer layer 110 is made of, for example, a compound semiconductor epitaxially grown on the substrate 100. When the lattice constant of the substrate 100 differs from that of the channel layer 112, the buffer layer 110 controls the lattice constant, thereby improving the crystal state of the channel layer 112 and controlling the warpage of the entire compound semiconductor layer. For example, when the substrate 100 is made of single-crystal silicon and the channel layer 112 is made of GaN, the buffer layer 110 can be made of aluminum nitride (AlN), AlGaN, GaN, etc. Furthermore, the buffer layer 110 does not necessarily need to be a single layer and can be a stack of different layers. Additionally, when the buffer layer 110 is made of a ternary or quaternary compound semiconductor, the composition of the buffer layer 110 can gradually change along the film thickness.

[0108] The channel layer 112 is the region in which charge carriers accumulate through polarization with the barrier layer 120 described later. The channel layer 112 is made of a compound semiconductor in which charge carriers readily accumulate through polarization. As an example of the channel layer 112, an epitaxial growth layer of GaN can be used. The channel layer 112 can be an undoped GaN (u-GaN) layer without added impurities. Accordingly, impurity scattering of charge carriers in the channel layer 112 is suppressed, and high-mobility carrier movement can be achieved. Furthermore, in this embodiment, the film thickness of the channel layer 112 is preferably, for example, from 50 nm to 300 nm.

[0109] The barrier layer 120 is formed using a compound semiconductor in which a two-dimensional electron gas is generated in the channel layer 112 (heterojunction interface) through polarization with the channel layer 112, and charge carriers are accumulated. The barrier layer 120 is composed of, for example, a group III nitride containing at least one of indium (In), gallium (Ga), and aluminum (Al), and specifically, Al can be used. 1-x-y Ga x In yAn epitaxial growth layer of N (0≤x < 1, 0≤y < 1). Additionally, the barrier layer 120 can be unimpregnated u-Al. 1-x- y Ga x In y N. Accordingly, impurity scattering of carriers in the channel layer 112 is suppressed, and carrier movement with high mobility can be achieved. Furthermore, the barrier layer 120 does not necessarily need to be a single layer, and can be a stack of different layers, for example, an Al layer with different compositions. 1-x-y Ga x In y N-layer. Alternatively, the barrier layer 120 may have a composition that gradually changes along the film thickness. Additionally, in this embodiment, the film thickness of the barrier layer 120 is preferably, for example, from 3 nm to 20 nm. Furthermore, a cap layer (not shown) may be provided on the upper surface of the barrier layer 120 to protect it from oxidation or thermal processes. For example, the cap layer may be made of GaN or silicon nitride (Si). x N y It consists of layers with a film thickness ranging from 0.2 nm to 5 nm.

[0110] Additionally, in this embodiment, a back barrier layer (not shown) may be provided between the channel layer 112 and the buffer layer 110. The back barrier layer is made of a semiconductor having a bandgap wider than that of the channel layer 112. As an example of a back barrier layer, Al can be used. 1-x-y Ga x In y N (0≤x < 1, 0≤y < 1) or u-Al 1-x-y Ga x In y The epitaxial growth layer of N. Furthermore, the back barrier layer does not necessarily need to be a single layer, and can be a stack of different layers, for example, Al as a stack of layers with different compositions. 1-x- y Ga x In y N layers. Alternatively, the back barrier layer can have a composition that gradually changes along the film thickness.

[0111] Furthermore, both insulating layers 132 and 130 are stacked on the source electrode 160a and the drain electrode 160b. Although not shown, source electrodes 150 and drain electrodes 154 electrically connected to the source electrode 160a and drain electrode 160b can be provided on the source electrode 160a and drain electrode 160b. Additionally, insulating layer 132 is preferably made of a material that is insulating relative to barrier layer 120, has the property of forming a good interface with barrier layer 120 without degrading device characteristics, and can be etched by wet etching. Specifically, insulating layer 132 is made of an oxide, and is made of, for example, aluminum oxide (Al2O3), hafnium oxide (HfO2), silicon oxide (SiO2), or a stacked layer thereof. Furthermore, as the insulating layer 130, a material that is insulating relative to the insulating layer 132 is preferably used. Because the insulating layer 130 is in direct contact with the barrier layer 120 in the opening 132a, this material has the characteristic of forming a good interface with the barrier layer 120 without degrading device characteristics. Moreover, a material that can be etched by dry etching is preferably used as the insulating layer 130. Specifically, the insulating layer 132 is composed of a nitride, such as Si3N4.

[0112] Additionally, the gate electrode 152 may have a stacked structure in which nickel (Ni) and gold (Au) are layered. Furthermore, to reduce gate impedance, the gate electrode 152 is generally formed in a T-shaped gate shape. In addition, to suppress metal diffusion, a barrier metal (not shown) such as titanium (Ti) may be formed to cover the surface of the gate electrode 152.

[0113] As described above, in this embodiment, by employing the above structure, a region on the surface of a specific semiconductor layer located between the gate electrode 152 and the drain 160b can be selectively subjected to reduction treatment and can be made negatively charged. Specifically, in this embodiment, by selectively making the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b negatively charged, the electron concentration in the channel on the drain 160b side is reduced, and the extension of the depletion layer 170 toward the drain 160b side is promoted. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 can be alleviated, and the turn-off current determined by gate leakage can be reduced. In addition, according to this embodiment, the region to be negatively charged on the source 160a side is narrower than the region to be negatively charged on the drain 160b side, thus suppressing the deterioration of the turn-on characteristics.

[0114] Note that in this embodiment, the structure of the HEMT device 10 is not limited to... Figure 13A and Figure 13B The structure shown in the figure can be modified into various structures.

[0115] 3.2 Manufacturing Method

[0116] Next, we will refer to Figures 14A to 14G A method for manufacturing the HEMT device 10 according to this embodiment is described. Figures 14A to 14G This is a cross-sectional view used to illustrate a method for manufacturing a HEMT device according to this embodiment. Specifically, Figures 14A to 14G Each of these is located at the corresponding manufacturing step. Figure 13A The corresponding cross-sectional view.

[0117] First, a GaN buffer layer 110 is stacked on a GaN substrate 100, and a GaN channel layer 112 and a barrier layer 120 are sequentially stacked on the GaN buffer layer 110. Then, a high-concentration N-type (N+) region is formed in the area to be formed as the source 160a and drain 160b. Specifically, the source 160a and drain 160b are formed, for example, by forming ohmic electrodes (not shown) on both sides of the area where the gate electrode 152 is to be formed, and by performing an annealing process on the ohmic electrodes. On the substrate side, the high-concentration N-type region is formed, for example, by selectively performing ion implantation. In this way, the contact resistance can be reduced (both the source 160a and drain 160b are electrically connected to the aforementioned 2DEG layer 114). Alternatively, the source 160a and drain 160b can be formed by selective crystal regrowth on the substrate instead of ion implantation. In this case, the layer to be regrown can be, for example, n (N-type) In. 1-x Ga x N-layer. Furthermore, in this embodiment, the high-concentration N-type regions serving as source 160a and drain 160b do not necessarily need to be a single layer, and can be a stack of different layers, for example, In... 1-x Ga x The N-layer (0 ≤ x < 1) can be a stack of layers with different compositions. Alternatively, the high-concentration N-type region can have a composition that gradually changes along the film thickness. Furthermore, Si, germanium (Ge), etc., can be used as the N-type dopant (impurity), and the impurity concentration is preferably, for example, 1 × 10⁻⁶. 18 cm -3 That's all. Furthermore, the aforementioned ohmic electrode preferably covers a high-concentration N-type region and is connected to the high-concentration N-type region with low resistance. As such an ohmic electrode, a structure in which titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au) are sequentially stacked from the substrate side can be used, for example.

[0118] Additionally, a device isolation portion (not shown) is formed on the substrate side to separate the region of the HEMT device 10. The device isolation portion can be formed by creating an inactive region that has high resistance due to ion implantation, for example, with boron (B). In this way, a [missing information - likely a specific structure or feature] can be obtained. Figure 14AThe form is illustrated in the figure. Furthermore, although the source 160a and drain 160b are formed first in the above description, the method is not limited to this, and the source 160a and drain 160b can be formed after the gate electrode 152, which will be described later, is formed.

[0119] Subsequently, as Figure 14B As illustrated, an insulating layer (first insulating layer) 132 is formed on the barrier layer 120 (semiconductor layer). Preferably, the insulating layer 132 is made of a material that is insulating to the barrier layer 120, has the property of forming a good interface with the barrier layer 120 without degrading device characteristics, and can be etched by wet etching. Therefore, as the insulating layer 132, aluminum oxide (Al2O3) or hafnium oxide (HfO2) with a film thickness from approximately 1 nm to 50 nm, formed by atomic layer deposition (ALD), is used, for example. Alternatively, the insulating layer 132 can be, for example, SiO2 formed by chemical vapor deposition (CVD).

[0120] Subsequently, as Figure 14C As illustrated, the insulating layer 132 is isotropically wet-etched until a portion of the surface of the barrier layer 120 is exposed, thereby forming an opening (first opening) 132a. For example, buffered hydrofluoric acid (BHF) or a diluted aqueous solution of tetramethylammonium hydroxide (TMAH) can be used for wet etching. By performing this wet etching, damage to the surface of the barrier layer 120, etc., can be reduced. At this time, the opening 132a is formed such that its opening towards the drain 160b side is wider than the actual gate length. Specifically, when measuring the length using a portion of the drain 160b side of the gate end to be formed as the starting point for measurement, the opening 132a is formed such that its opening ranges from 5 nm to 200 nm.

[0121] Subsequently, as Figure 14D As illustrated, the surface (first region) of the barrier layer 120 exposed from the opening 132a undergoes a reduction treatment to form a reduced surface 122. By performing this treatment, the amount of positive fixed charge can be reduced and the amount of negative fixed charge can be increased on the surface of the barrier layer 120 exposed from the opening 132a. For example, the reduction treatment can be a treatment using a gas or processing liquid containing fluorine (F), chlorine (Cl), hydrogen (H), etc., and the reduced surface 122 can be formed by performing, for example, a hydrogen plasma treatment for about 0.3 minutes to 3 minutes.

[0122] In this way, in this embodiment, the region on the surface of a specific semiconductor layer (specifically, barrier layer 120) located between the gate electrode 152 and the drain electrode 160b is not subjected to ion implantation or the like, but is selectively subjected to reduction treatment, thus suppressing internal damage to the barrier layer 120 and the like.

[0123] Subsequently, as Figure 14E As illustrated, an insulating layer (second insulating layer) 130 is formed on the insulating layer 132 and within the opening 132a. Furthermore, the insulating layer 130 is preferably made of a material that is insulating relative to the insulating layer 132 and, because the insulating layer 130 is in direct contact with the barrier layer 120 in the opening 132a, has the characteristic of forming a good interface with the barrier layer 120 without degrading device characteristics. Moreover, a material that can be etched by dry etching is preferably used as the insulating layer 130. Therefore, as the insulating layer 130, p (P-type) SiN with a film thickness from approximately 5 nm to 200 nm can be used, for example, formed by plasma CVD. Specifically, silane gas (SiH4) and ammonia gas (NH3) react with each other using plasma energy to produce a silicon nitride film and hydrogen, and the silicon nitride film is deposited on the substrate, thereby forming the insulating layer 130.

[0124] Subsequently, as Figure 14F As illustrated, the insulating layer 130 is subjected to dry etching using a fluorocarbon (CF) gas, forming an opening (second opening) 130a with a narrower opening than the opening 132a. The opening width of the opening 130a corresponds to the gate length and is preferably, for example, from 0.1 μm to 1.0 μm. As a result, the insulating layer 130 protrudes to directly contact the barrier layer 120 (reduced surface 122) in the opening 132a of the insulating layer 132, and the protrusion is greater on the drain 160b side than on the source 160a side.

[0125] Subsequently, as Figure 14G As illustrated, a gate electrode 152 is formed on the insulating layer 130 and within the opening 130a. The gate electrode 152 can be formed, for example, by depositing Ni and Au from the substrate side using a mask. As described above, to reduce gate impedance, the gate electrode 152 is generally formed in a T-shaped gate configuration. Furthermore, to suppress the diffusion of the upper metal Au, a barrier metal such as Ti (not shown) can be formed between the upper metal Au and the lower metal Ni.

[0126] In this way, the HEMT device 10 according to this embodiment can be manufactured. As described above, in this embodiment, the HEMT device 10 according to this embodiment can be manufactured by a simple and non-destructive method without significantly changing the manufacturing process used in related technologies. That is, according to this embodiment, a HEMT device 10 that can be manufactured by a simple and non-destructive method and can suppress the degradation of on-state characteristics while reducing off-state current can be obtained.

[0127] 4. Second Embodiment

[0128] 4.1 Detailed Configuration

[0129] First, refer to Figure 15A and Figure 15B The detailed structure of the HEMT device 10 according to the second embodiment of the present disclosure is described. Figure 15A This is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Figure 15B yes Figure 15A The figure shows an enlarged cross-sectional view of region C. Compared to the first embodiment, this embodiment differs in that the film thickness t1 of the insulating layer 130 is increased.

[0130] Furthermore, in this embodiment, similar to the first embodiment, the HEMT device 10 according to this embodiment includes a buffer layer 110, a channel layer 112, and a barrier layer 120 on the substrate 100, such as... Figure 15A As illustrated in the figure. In addition, in this embodiment, the source 160a and drain 160b are also formed with a barrier layer 120 sandwiched between them.

[0131] In this embodiment, an insulating layer 132 having an opening 132a exposing a reduced surface 122, which is part of the upper surface of the barrier layer 120, is stacked on the barrier layer 120. Additionally, in this embodiment, an insulating layer 130 is also stacked on the insulating layer 132 and within the opening 132a. The insulating layer 130 has an opening 130a that exposes a portion of the reduced surface 122 exposed by the opening 132a on the upper surface of the barrier layer 120, and has an opening narrower than the opening 132a. Furthermore, in this embodiment, the center of the opening 130a is located closer to the source electrode 160a than the center of the opening 132a. Additionally, in this embodiment, the inner surface of the opening 132a on the source electrode 160a side is also located on the source electrode 160a side relative to the inner surface of the opening 130a on the source electrode 160a side. Furthermore, in this embodiment, the inner surface of the drain electrode 160b side of the opening 132a is also located on the drain electrode 160b side relative to the inner surface of the drain electrode 160b side of the opening 130a.

[0132] In addition, in this embodiment, a gate electrode 152 is also formed on the insulating layer 130 located between the source electrode 160a and the drain electrode 160b and in the opening 130a, which is in direct contact with the upper surface of the barrier layer 120 exposed by the opening 130a.

[0133] In this embodiment, as Figure 15BAs illustrated, the reduced surface 122 is also region d, which is part of the upper surface of the barrier layer 120 sandwiched between the source 160a and the drain 160b. Specifically, the reduced surface 122 includes region b, which is in direct contact with the gate electrode 152 and the barrier layer 120; region c, which is located on the drain 160b side relative to region b; and region a, which is located on the source 160a side relative to region b. Furthermore, in this embodiment, region c is also wider than region a. Specifically, in this embodiment, the distance Ld between the end of region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with region b is preferably from 5 nm to 100 nm. Additionally, in this embodiment, the distance Ls between the end of region a on the source 160a side and the end face of the gate electrode 152 on the source 160a side that is in direct contact with region b is preferably as short as possible.

[0134] In this embodiment, since the reduced-treated surface 122, which is in direct contact with the gate electrode 152 and the insulating layer 130, has undergone reduction treatment, the reduced-treated surface 122 also has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120 other than region d (specifically, the upper surface of the barrier layer 120 in direct contact with the insulating layer 132). In this embodiment, by adopting this configuration, the channel electron concentration Ns of the reduced-treated surface 122 can also be reduced compared to the upper surface of the barrier layer 120 in direct contact with the insulating layer 132.

[0135] In addition, in this embodiment, the following structure is also adopted: wherein the gate electrode 152 is in Figure 15B A portion of region c, as illustrated, protrudes above the insulating layer 130. In this embodiment, the film thickness t1 of the insulating layer 130 is made thicker than in the first embodiment described above (e.g., from 50 nm to 200 nm). By employing this configuration, the distance between the gate electrode 152 and the barrier layer 120 (the reduced surface 122) is widened, thus reducing the capacitance Cgd between the gate electrode 152 and the drain 160b. As a result, according to this embodiment, the gain characteristics of the HEMT device 10 are improved. In this way, in each embodiment of this disclosure, the film thickness t1 of the insulating layer 130 is preferably adjusted to correspond to the desired characteristics.

[0136] As described above, in this embodiment, by employing the above structure, the surface region of a specific semiconductor layer located between the gate electrode 152 and the drain 160b can also be selectively reduced and made negatively charged. Specifically, in this embodiment, by selectively making the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b negatively charged, the electron concentration in the channel on the drain 160b side is reduced, and the extension of the depletion layer 170 toward the drain 160b side is promoted. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 can be alleviated, and the off-state current determined by gate leakage can be reduced. In addition, according to this embodiment, the region to be negatively charged on the source 160a side is narrower than the region to be negatively charged on the drain 160b side, thus suppressing the deterioration of the turn-on characteristics.

[0137] Note that in this embodiment, the structure of the HEMT device 10 is not limited to... Figure 15A and Figure 15B The structure shown in the figure can be modified into various structures.

[0138] 4.2 Manufacturing Method

[0139] Next, we will refer to Figures 16A to 16C A method for manufacturing the HEMT device 10 according to this embodiment is described. Figures 16A to 16C This is a cross-sectional view used to describe a method for manufacturing a HEMT device according to this embodiment. Specifically, Figures 16A to 16C Each of these is located at the corresponding manufacturing step. Figure 15A The corresponding cross-sectional view.

[0140] First, with reference Figures 14A to 14E The manufacturing method of the HEMT device 10 according to the first embodiment is similar, stacking layers up to the insulating layer 130, and achieving a result as described above. Figure 16A The form shown in the figure. Note that this embodiment differs from the first embodiment in that the insulating layer 130 is thicker.

[0141] Subsequently, as in the first embodiment, dry etching is performed on the insulating layer 130 to form an opening 130a having a narrower opening than the opening 132a, such as Figure 16B As shown in the diagram.

[0142] Subsequently, as in the first embodiment, a gate electrode 152 is formed on the insulating layer 130 and within the opening 130a, as follows. Figure 16C As shown in the diagram.

[0143] In this way, the HEMT device 10 according to this embodiment can be manufactured. As described above, in this embodiment, the HEMT device 10 according to this embodiment can be manufactured by a simple and non-destructive method without significantly changing the manufacturing process used in related technologies. That is, according to this embodiment, a HEMT device 10 that can be manufactured by a simple and non-destructive method and can suppress the degradation of on-state characteristics while reducing off-state current can be obtained.

[0144] 5. Third Embodiment

[0145] 5.1 Detailed Configuration

[0146] First, refer to Figure 17A and Figure 17B The detailed structure of the HEMT device 10 according to the third embodiment of the present disclosure is described. Figure 17A This is a cross-sectional view of the structure of the HEMT device 10 according to this embodiment, and Figure 17B yes Figure 17A The figure shows an enlarged cross-sectional view of region D. The difference between this embodiment and the first and second embodiments is that the reduced surface 122 is disposed only on the drain 160b side of the gate electrode 152 and not on the source 160a side of the gate electrode 152.

[0147] In this embodiment, similar to the first embodiment, the HEMT device 10 according to this embodiment also includes a buffer layer 110, a channel layer 112, and a barrier layer 120 on the substrate 100, such as... Figure 17A As illustrated in the figure. In addition, in this embodiment, the source 160a and drain 160b are also formed with a barrier layer 120 sandwiched between them.

[0148] In this embodiment, an insulating layer 132 having an opening 132a that exposes a reduced-processed surface 122, which is part of the upper surface of the barrier layer 120, is stacked on the barrier layer 120. An insulating layer 130 is stacked on the insulating layer 132 and within the opening 132a. The insulating layer 130 has an opening 130a that exposes the upper surface of the barrier layer 120 exposed by the opening 132a, and has an opening narrower than the opening 132a. In this embodiment, unlike the previous embodiment, the opening 130a does not expose the reduced-processed surface 122. Furthermore, in this embodiment, the center of the opening 130a is located closer to the source electrode 160a than the center of the opening 132a. Also, unlike the previous embodiment, in this embodiment, the inner surface of the opening 132a on the source electrode 160a side is flush with the inner surface of the opening 130a on the source electrode 160a side. However, in this embodiment, the inner surface of the source electrode 160a side of the opening 132a is not limited to being flush with the inner surface of the source electrode 160a side of the opening 130a, and the inner wall of the source electrode 160a side of the opening 132a may be located closer to the source electrode 160a side compared to the inner surface of the source electrode 160a side of the opening 130a. Furthermore, in this embodiment, the inner surface of the drain electrode 160b side of the opening 132a is also located on the drain electrode 160b side relative to the inner surface of the drain electrode 160b side of the opening 130a.

[0149] In addition, in this embodiment, the gate electrode 152, which is in direct contact with the upper surface of the barrier layer 120 exposed by the opening 130a, is also formed on the insulating layer 130 located between the source 160a and the drain 160b and within the opening 130a. Unlike the embodiments described above, in this embodiment, the gate electrode 152 is not in direct contact with the reduced surface 122.

[0150] Specifically, in this embodiment, unlike the embodiments described above, such as... Figure 17B As illustrated, the reduced surface 122 includes only region c located on the drain 160b side relative to region b, which is in direct contact with the gate electrode 152 and the barrier layer 120. Furthermore, in this embodiment, the distance Ld between the end of region c on the drain 160b side and the end face of the gate electrode 152 on the drain 160b side that is in direct contact with region b is preferably from 5 nm to 100 nm.

[0151] In this embodiment, since the reduced-treated surface 122, which is in direct contact with the insulating layer 130, has undergone reduction treatment, the reduced-treated surface 122 also has a smaller amount of positive fixed charge or a larger amount of negative fixed charge than the upper surface of the barrier layer 120, which is in direct contact with the gate electrode 152 and the insulating layer 132. In this embodiment, by adopting this configuration, the channel electron concentration Ns of the reduced-treated surface 122 can also be reduced compared to the upper surface of the barrier layer 120, which is in direct contact with the gate electrode 152 and the insulating layer 132.

[0152] Furthermore, in this embodiment, the following structure is also adopted: wherein the gate electrode 152 is in Figure 17B A portion of region c, as illustrated, protrudes above the insulating layer 130. In this embodiment, as the thickness t1 of the insulating layer 130 increases, the distance between the gate electrode 152 and the barrier layer 120 (the reduced surface 122) increases, thus reducing the capacitance Cgd between the gate electrode 152 and the drain 160b. As a result, the gain characteristics of the HEMT device 10 can be improved. Furthermore, in this embodiment, as the thickness t1 of the insulating layer 130 decreases, the distance between the gate electrode 152 and the barrier layer 120 (the reduced surface 122) in region c decreases, thus exhibiting the field plate effect caused by the shape of the gate electrode 152 and mitigating the electric field at the gate end of the gate electrode 152. In this way, in this embodiment, the thickness t1 of the insulating layer 130 is preferably adjusted to correspond to the desired characteristics.

[0153] As described above, in this embodiment, by employing the above structure, the surface region of a specific semiconductor layer located between the gate electrode 152 and the drain 160b can also be selectively subjected to reduction treatment and can be made negatively charged. Specifically, in this embodiment, by selectively making the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b negatively charged, the electron concentration in the channel on the drain 160b side is reduced, and the extension of the depletion layer 170 toward the drain 160b side is promoted. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 can be alleviated, and the off-state current determined by gate leakage can be reduced. In addition, in this embodiment, since the reduced surface 122 is not provided on the source 160a side of the gate electrode 152, the resistance on the source 160a side does not increase, and thus the degradation of the turn-on characteristics can be further suppressed. In addition, in this embodiment, since the upper surface (region b) of the barrier layer 120 directly below the gate electrode 152 is not subjected to reduction treatment, the characteristic fluctuations of the HEMT device 10 can be suppressed.

[0154] Note that in this embodiment, the structure of the HEMT device 10 is not limited to... Figure 17A and Figure 17B The structure shown in the figure can be modified into various structures.

[0155] 5.2 Manufacturing Method

[0156] Next, we will refer to Figure 18A and Figure 18B A method for manufacturing the HEMT device 10 according to this embodiment is described. Figure 18A and Figure 18B This is a cross-sectional view used to describe a method for manufacturing a HEMT device according to this embodiment. Specifically, Figure 18A and Figure 18B Each of these is located at the corresponding manufacturing step. Figure 18A The corresponding cross-sectional view.

[0157] First, with reference Figures 14A to 14E The manufacturing method of the HEMT device 10 according to the first embodiment and the reference are described. Figure 16A The HEMT device 10 according to the second embodiment is manufactured in the same manner, with each layer stacked up to the insulating layer 130. Furthermore, in this embodiment, as... Figure 16A As illustrated, dry etching is performed on the insulating layer 130, and an opening 130a with a narrower opening than the opening 132a is formed on the source 160a side. At this time, the end of the reduced surface 122 on the source 160a side is preferably in the same position as the inner surface of the opening 130a on the drain 160b side. However, this embodiment is not limited to this form, and a portion of the reduced surface 122 may exist within the opening of the opening 130a. Furthermore, in this embodiment, the inner surface of the opening 132a on the source 160a side is preferably flush with the inner surface of the opening 130a on the source 160a side.

[0158] Subsequently, as in the first embodiment, a gate electrode 152 is formed on the insulating layer 130 and within the opening 130a, as follows. Figure 18B As shown in the diagram.

[0159] In this way, the HEMT device 10 according to this embodiment can be manufactured. As described above, in this embodiment, the HEMT device 10 can be manufactured by a simple and non-destructive method without significantly changing the manufacturing process used in related technologies. That is, according to this embodiment, a HEMT device 10 that can be manufactured by a simple and non-destructive method and that can suppress the degradation of on-state characteristics while reducing off-state current can be obtained.

[0160] 6. Summary

[0161] As described above, in each embodiment of this disclosure, a region on the surface of a specific semiconductor layer located between the gate electrode 152 and the drain 160b can be selectively subjected to a reduction process and can be made negatively charged. Specifically, in this embodiment, by selectively making the surface of the barrier layer 120 located between the gate electrode 152 and the drain 160b negatively charged, the electron concentration in the channel on the drain 160b side is reduced, and the extension of the depletion layer 170 toward the drain 160b side is promoted. As a result, according to this embodiment, the electric field at the gate end of the gate electrode 152 can be alleviated, and the off-state current determined by gate leakage can be reduced. In addition, according to each embodiment of this disclosure, the region to be negatively charged on the source 160a side is narrower than the region to be negatively charged on the drain 160b side, or no region to be negatively charged is provided on the source 160a side, thus suppressing the degradation of the turn-on characteristics.

[0162] Furthermore, in each embodiment of this disclosure, the surface region of a specific semiconductor layer (specifically, barrier layer 120) located between the gate electrode 152 and the drain electrode 160b is selectively subjected to reduction treatment instead of ion implantation, thereby suppressing internal damage to the barrier layer 120. Additionally, according to each embodiment of this disclosure, the HEMT device 10 can be manufactured using a simple method without significantly altering the manufacturing process used in related technologies. That is, according to each embodiment of this disclosure, a HEMT device 10 can be provided that can be manufactured using a non-destructive method and can suppress degradation of on-state characteristics while reducing off-state current.

[0163] It should be noted that although the HEMT device 10 according to each embodiment of the present disclosure is based on GaN compound semiconductor, the present disclosure is not limited thereto, and the HEMT device 10 may be a compound semiconductor such as GaAs, or may be a semiconductor using a Si substrate, etc.

[0164] Furthermore, the materials, film thicknesses, film formation methods, and film formation conditions of each layer in the above embodiments are not limited to those described above, and can be appropriately changed. That is, in this embodiment, the HEMT device 10 can be manufactured using methods, apparatus, and conditions for manufacturing general semiconductor devices.

[0165] It should be noted that examples of the methods mentioned above include physical vapor deposition (PVD), CVD, and ALD. Examples of PVD include vacuum evaporation, electron beam (EB) evaporation, various sputtering methods (magnetron sputtering, RF-DC coupled bias sputtering, electron cyclotron resonance (ECR) sputtering, directed target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD include plasma CVD, thermal CVD, metal-organic (MO) CVD, and photoCVD. Other examples of methods include various coating methods such as electroplating, electroless plating, spin coating, dip coating, casting, microcontact printing, and drip coating; various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing; and embossing, spraying, air knife coating, doctor blade coating, bar coating, knife coating, extrusion coating, reverse roller coating, transfer roller coating, gravure coating, coincidence coating, cast coating, spray coating, slotted hole coating, and calendering coating. Additionally, examples of patterning methods include chemical etching such as shadow masks, laser transfer, and photolithography, as well as physical etching using ultraviolet light, lasers, etc. Furthermore, examples of planarization techniques include chemical mechanical polishing (CMP), laser planarization, and reflow.

[0166] 7. Application Examples

[0167] The technology disclosed herein (the technology) can be applied to various products. For example, the technology disclosed herein can be applied to communication devices. Therefore, reference will be made to... Figure 19 The wireless communication device (communication device) 500 is described as an application example of the technology according to this disclosure. Figure 19 This is an explanatory diagram illustrating application examples of the HEMT device 10 according to various embodiments of the present disclosure.

[0168] Figure 19 The wireless communication device 500 illustrated herein is a mobile phone system with multiple functions such as voice communication, data communication, and local area network (LAN) connection. For example, the wireless communication device 500 includes an antenna (ANT) 510, an antenna switching circuit 520, a radio frequency integrated circuit (RFIC) 530, a baseband unit 540, a high-power amplifier (HPA) 550, and an output unit 560 including a voice output unit (MIC), a data output unit (DT), and an interface (IF) unit. The interface (IF) unit can be connected to a device that performs wireless communication such as wireless LAN or Bluetooth (trademark name). Furthermore, the radio frequency integrated circuit RFIC 530 and the baseband unit 540 are connected to each other via an internal bus.

[0169] During transmission, the transmit signal output from the baseband unit 540 is output to the antenna 510 via the radio frequency integrated circuit RFIC 530, the high-power amplifier 550, and the antenna switch circuit 520. Conversely, during reception, the receive signal received by the antenna 510 is input to the baseband unit 540 via the antenna switch circuit 520 and the radio frequency integrated circuit RFIC 530. The baseband unit 540 processes the input signals and outputs the processed signals from the output unit 560 to external devices, etc.

[0170] For example, the technology according to this disclosure can be applied to antenna switching circuit 520, radio frequency integrated circuit 530, high-power amplifier 550, etc. In particular, the effects of the technology according to this disclosure are manifested in wireless communication devices with communication frequencies equal to or higher than the ultra-high frequency (UHF) band. That is, by using HEMT devices 10 with excellent high-frequency and high-efficiency characteristics according to various embodiments of this disclosure as antenna switching circuit 520, radio frequency integrated circuit 530, high-power amplifier 550, etc., faster, more efficient, and lower power consumption communication processing can be achieved in wireless communication device 500. In particular, when wireless communication device 500 is applied to portable communication terminals, processing speed and efficiency are improved and power consumption is reduced, thus extending battery life and improving portability.

[0171] The configuration example of the wireless communication device 500 has been described above. Each of the above components can be composed of general-purpose components or can be composed of hardware dedicated to the function of each component. This configuration can be appropriately changed according to the level of technology at the time of implementation.

[0172] 8. Supplement

[0173] While preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the scope of the present disclosure is not limited to such examples. It is clear that those skilled in the art can conceive of various changes or modifications within the scope of the technical concept described in the claims, and it should be understood that these also naturally fall within the scope of the present disclosure.

[0174] Furthermore, the effects described in this specification are merely illustrative or exemplary and not restrictive. That is, the technology according to this disclosure can exhibit other effects that are clear to those skilled in the art from the description in this specification, in conjunction with or in lieu of the effects described above.

[0175] Note that this technology can also be configured as follows. (1)

[0177] A semiconductor device includes: a compound semiconductor layer, the compound semiconductor layer being a ternary compound semiconductor layer or a quaternary compound semiconductor layer; a first insulating layer, the first insulating layer being stacked on the compound semiconductor layer and including a first opening, the first opening exposing a first region of an upper surface of the compound semiconductor layer; a second insulating layer, the second insulating layer being stacked on the first insulating layer and within the first opening and including a second opening, the second opening having a narrower opening than the first opening and exposing a second region of the compound semiconductor layer that is part of the first region exposed by the first opening; and a gate electrode, the gate electrode being stacked on the upper surface of the second insulating layer and within the second opening, the gate electrode being in direct contact with the second region of the upper surface of the compound semiconductor layer. (2)

[0179] In the semiconductor device according to (1) above, the first region includes a third region, which is the upper surface of the compound semiconductor layer and is located on the drain side relative to the second region, and the third region is a surface that has undergone reduction treatment. (3)

[0181] In the semiconductor device according to (2) above, the reduced surface has more negative fixed charge than other regions on the upper surface of the compound semiconductor layer. (4)

[0183] In the semiconductor device according to (2) above, the reduced surface has less positive fixed charge than other regions on the upper surface of the compound semiconductor layer. (5)

[0185] In the semiconductor device according to (2) above, the reduced surface has less oxygen than other regions on the upper surface of the compound semiconductor layer. (6)

[0187] In a semiconductor device according to any one of (2) to (5) above, the reduced surface extends to a portion of the upper surface of the compound semiconductor layer located below the gate electrode. (7)

[0189] In the semiconductor device according to (6) above, the reduced surface extends in the second region and extends to the upper surface of the compound semiconductor layer located on the source side relative to the second region, and the third region is wider than the fourth region. (8)

[0191] In the semiconductor device according to any one of (2) to (7) above, the distance between the end face of the drain side of a portion of the gate electrode that is in direct contact with the second region and the end face of the drain side of the third region is 5 nm or more. (9)

[0193] In the semiconductor device according to (8) above, the distance between the end face of the drain side of a portion of the gate electrode that is in direct contact with the second region and the end face of the drain side of the third region is 100 nm or less. (10)

[0195] In a semiconductor device according to any one of (2) to (6) above, the center of the second opening is located closer to the source side than the center of the first opening. (11)

[0197] In the semiconductor device according to (10) above, the inner surface of the source side of the first opening and the inner surface of the source side of the second opening are flush with each other. (12)

[0199] In the semiconductor device according to (10) above, the inner surface of the source side of the first opening is located on the source side relative to the inner surface of the source side of the second opening. (13)

[0201] In the semiconductor device according to (12) above, the inner surface of the drain side of the first opening is located on the drain side relative to the inner surface of the drain side of the second opening. (14)

[0203] In the semiconductor device according to any one of (1) to (13) above, the compound semiconductor layer includes a group III nitride containing at least one of gallium, indium and aluminum. (15)

[0205] In a semiconductor device according to any one of (1) to (14) above, the first insulating layer is made of oxide. (16)

[0207] In the semiconductor device according to (15) above, the first insulating layer is composed of aluminum oxide, hafnium oxide, silicon oxide, or a stacked layer of aluminum oxide, hafnium oxide and silicon oxide. (17)

[0209] In the semiconductor device according to any one of (1) to (16) above, the second insulating layer is made of nitride. (18)

[0211] In the semiconductor device according to (17) above, the second insulating layer is made of silicon nitride. (19)

[0213] In a method for manufacturing a semiconductor device, the method includes: stacking a first insulating layer on a compound semiconductor layer, which is a ternary compound semiconductor layer or a quaternary compound semiconductor layer, the first insulating layer including a first opening that exposes a first region on the upper surface of the compound semiconductor layer; performing a reduction process on the first region; stacking a second insulating layer on the first insulating layer and within the first opening, the second insulating layer including a second opening having a narrower opening than the first opening and exposing a second region of the compound semiconductor layer that is part of the first region exposed by the first opening; and forming a gate electrode on the upper surface of the second insulating layer and within the second opening that is in direct contact with the second region on the upper surface of the compound semiconductor layer. (20)

[0215] In a communication device including a semiconductor device, the semiconductor device includes: a compound semiconductor layer, said compound semiconductor layer being a ternary compound semiconductor layer or a quaternary compound semiconductor layer; a first insulating layer, the first insulating layer being stacked on the compound semiconductor layer and including a first opening, the first opening exposing a first region of the upper surface of the compound semiconductor layer; a second insulating layer, the second insulating layer being stacked on the first insulating layer and within the first opening and including a second opening, the second opening having an opening narrower than the first opening and exposing a second region of the compound semiconductor layer that is part of the first region exposed by the first opening; and a gate electrode, said gate electrode being stacked on the upper surface of the second insulating layer and within the second opening, the gate electrode being in direct contact with the second region of the upper surface of the compound semiconductor layer.

[0216] List of reference numerals

[0217] 10, 10a, 10b HEMT devices

[0218] 100 substrates

[0219] 110 buffer layer

[0220] 112 channel layer

[0221] 1142DEG layer

[0222] 120 barrier layers

[0223] 122 Surface after reduction treatment

[0224] 130, 132 insulation layers

[0225] 130a, 132a openings

[0226] 140 gate insulating film

[0227] 150 source electrode

[0228] 152 gate electrode

[0229] 154 drain electrode

[0230] 160a source electrode

[0231] 160b drain

[0232] 170 depletion layers

[0233] 500 wireless communication devices

[0234] 510 antenna

[0235] 520 antenna switching circuit

[0236] 530 Radio Frequency Integrated Circuit (RFIC)

[0237] 540 baseband unit

[0238] 550 high-power amplifier

[0239] 560 output unit

Claims

1. A semiconductor device, comprising: A compound semiconductor layer, wherein the compound semiconductor layer is a ternary compound semiconductor layer or a quaternary compound semiconductor layer; A first insulating layer is stacked on the compound semiconductor layer and includes a first opening that exposes a first region of the upper surface of the compound semiconductor layer. A second insulating layer is stacked on the first insulating layer and within the first opening and includes a second opening, the second opening having a narrower opening than the first opening and exposing a second region that is part of the first region of the compound semiconductor layer exposed by the first opening; as well as A gate electrode is stacked on the upper surface of the second insulating layer and inside the second opening, and the gate electrode is in direct contact with a second region on the upper surface of the compound semiconductor layer.

2. The semiconductor device according to claim 1, wherein The first region includes a third region, which is the upper surface of the compound semiconductor layer and is located on the drain side relative to the second region. The third region is a surface that has undergone reduction treatment.

3. The semiconductor device according to claim 2, wherein The reduced surface has a greater amount of negative fixed charge than other areas on the upper surface of the compound semiconductor layer.

4. The semiconductor device according to claim 2, wherein The reduced surface has less positive fixed charge than other areas on the upper surface of the compound semiconductor layer.

5. The semiconductor device according to claim 2, wherein The reduced surface has less oxygen than other areas on the upper surface of the compound semiconductor layer.

6. The semiconductor device according to claim 2, wherein The reduced surface extends to a portion of the upper surface of the compound semiconductor layer located below the gate electrode.

7. The semiconductor device according to claim 6, wherein The reduced surface extends in the second region and into a fourth region on the upper surface of the compound semiconductor layer located on the source side relative to the second region, and The third region is wider than the fourth region.

8. The semiconductor device according to claim 2, wherein The distance between the end face of the drain side of a portion of the gate electrode that is in direct contact with the second region and the end face of the drain side of the third region is 5 nm or more.

9. The semiconductor device according to claim 8, wherein The distance between the end face of the drain side of a portion of the gate electrode that is in direct contact with the second region and the end face of the drain side of the third region is less than 100 nm.

10. The semiconductor device according to claim 2, wherein The center of the second opening is located closer to the source side compared to the center of the first opening.

11. The semiconductor device of claim 10, wherein The inner surface of the source side of the first opening is flush with the inner surface of the source side of the second opening.

12. The semiconductor device of claim 10, wherein The inner surface of the source side of the first opening is located on the source side relative to the inner surface of the source side of the second opening.

13. The semiconductor device of claim 12, wherein The inner surface of the drain side of the first opening is located on the drain side relative to the inner surface of the drain side of the second opening.

14. The semiconductor device of claim 1, wherein The compound semiconductor layer includes a group III nitride containing at least one of gallium, indium, and aluminum.

15. The semiconductor device according to claim 1, wherein The first insulating layer is composed of oxides.

16. The semiconductor device of claim 15, wherein The first insulating layer is composed of aluminum oxide, hafnium oxide, silicon oxide, or a stacked layer of aluminum oxide, hafnium oxide, and silicon oxide.

17. The semiconductor device of claim 1, wherein The second insulating layer is composed of nitride.

18. The semiconductor device of claim 17, wherein The second insulating layer is made of silicon nitride.

19. A method for manufacturing a semiconductor device, the method comprising: A first insulating layer is stacked on a compound semiconductor layer that is a ternary compound semiconductor layer or a quaternary compound semiconductor layer. The first insulating layer includes a first opening that exposes a first region on the upper surface of the compound semiconductor layer. Perform restoration processing on the first region; A second insulating layer is stacked on the first insulating layer and inside the first opening, the second insulating layer including a second opening having a narrower opening than the first opening and exposing a second region that is part of the first region of the compound semiconductor layer exposed by the first opening; as well as A gate electrode is formed on the upper surface of the second insulating layer and within the second opening, which is in direct contact with a second region of the upper surface of the compound semiconductor layer.

20. A communication device, comprising Semiconductor device, the semiconductor device comprising The compound semiconductor layer is a ternary compound semiconductor layer or a quaternary compound semiconductor layer. A first insulating layer is stacked on the compound semiconductor layer and includes a first opening that exposes a first region on the upper surface of the compound semiconductor layer. A second insulating layer, stacked on the first insulating layer and within the first opening, includes a second opening having a narrower opening than the first opening and exposing a second region that is part of the first region of the compound semiconductor layer exposed by the first opening. A gate electrode is stacked on the upper surface of the second insulating layer and inside the second opening, and the gate electrode is in direct contact with a second region on the upper surface of the compound semiconductor layer.

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