Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a semiconductor device in which warpage after bonding of a power module substrate and a cooling fin is reduced. The semiconductor device includes a cooling fin, a first circuit pattern, an insulating substrate, a second circuit pattern, a third circuit pattern, and a plurality of intermediate materials. The first circuit pattern is mounted on the cooling fin. The insulating substrate is disposed over the first circuit pattern. The second circuit pattern is disposed over the insulating substrate. The third circuit pattern is disposed over the second circuit pattern. A plurality of intermediate materials are disposed between the cooling fin and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern, respectively. The thickness of the first circuit pattern is thinner than the thickness of at least one of the second circuit pattern and the third circuit pattern.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] A power module substrate incorporating a power semiconductor element is mounted on cooling fins for cooling the power semiconductor element. Patent Document 1 discloses a power module substrate with a heat sink.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-98423 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] The power module substrate, which houses power semiconductor components, has a multi-layered structure consisting of an insulating substrate and circuit patterns. Therefore, warping can sometimes occur when the power module substrate is joined to the cooling fins.

[0008] In order to solve the above problems, the purpose of this disclosure is to provide a semiconductor device that reduces warping of the power module substrate and cooling fins after bonding.

[0009] Technical means for solving technical problems

[0010] The semiconductor device of this invention includes a cooling fin, a first circuit pattern, an insulating substrate, a second circuit pattern, a third circuit pattern, and a plurality of intermediate materials. The first circuit pattern is mounted on the cooling fin. The insulating substrate is disposed above the first circuit pattern. The second circuit pattern is disposed above the insulating substrate. The third circuit pattern is disposed above the second circuit pattern. The plurality of intermediate materials are respectively disposed between the cooling fin and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern. The thickness of the first circuit pattern is thinner than the thickness of at least one of the second and third circuit patterns.

[0011] Invention Effects

[0012] According to this disclosure, a semiconductor device is provided that can reduce warping after the power module substrate and cooling fins are joined.

[0013] The purpose, features, aspects, and advantages of this disclosure will become more apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0014] Figure 1This is a cross-sectional view showing the structure of the semiconductor device in Embodiment 1.

[0015] Figure 2 It is a cross-sectional view showing the structure of the components contained in a semiconductor device.

[0016] Figure 3 This is a flowchart illustrating the manufacturing method of the semiconductor device in Embodiment 1.

[0017] Figure 4 This is a cross-sectional view showing the structure of the semiconductor device in Modification 1 of Embodiment 1.

[0018] Figure 5 It is a cross-sectional view showing the structure of the components contained in a semiconductor device.

[0019] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device in Modification 2 of Embodiment 1.

[0020] Figure 7 It is a cross-sectional view showing the structure of the components contained in a semiconductor device.

[0021] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device in Embodiment 2.

[0022] Figure 9 It is a cross-sectional view showing the structure of the components contained in a semiconductor device.

[0023] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device in Embodiment 3.

[0024] Figure 11 It is a cross-sectional view showing the structure of the components contained in a semiconductor device. Detailed Implementation

[0025] <Implementation Method 1>

[0026] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device 101 in Embodiment 1. Figure 2 This is a cross-sectional view showing the structure of the components included in the semiconductor device 101. The semiconductor device 101 includes cooling fins 10, a first circuit pattern 20, an insulating substrate 30, a second circuit pattern 40, a third circuit pattern 50, a plurality of intermediate materials 60, and semiconductor elements (not shown). Hereinafter, the structure including the first circuit pattern 20, the insulating substrate 30, the second circuit pattern 40, the third circuit pattern 50, and the plurality of intermediate materials 60 will be referred to as a power module substrate.

[0027] The cooling fin 10 includes a plate portion 10A and a fin portion 10B. The fin portion 10B is disposed on the lower surface of the plate portion 10A. The plate portion 10A has a mounting surface on its upper surface. The cooling fin 10 has the function of transferring heat generated by electronic components such as semiconductor elements to the outside. The cooling fin 10 is formed of metals such as copper and aluminum. The cooling fin 10 is also called a heat sink or radiator.

[0028] The first circuit pattern 20 is mounted on the mounting surface of the cooling fins 10 via an intermediate material 60. The first circuit pattern 20 is formed, for example, from an Al-Mg-Si alloy. The first circuit pattern 20 is formed, for example, according to A6063 as specified in JIS standard (Japanese Industrial Standards).

[0029] An insulating substrate 30 is disposed above the first circuit pattern 20 via an intermediate material 60. The insulating substrate 30 is formed of, for example, ceramic. The ceramic is, for example, SiN.

[0030] The second circuit pattern 40 is disposed above the insulating substrate 30 via an intermediate material 60. The second circuit pattern 40 is formed, for example, by Al. The purity of the Al is, for example, above 99.99% (4N).

[0031] The third circuit pattern 50 is disposed above the second circuit pattern 40 via an intermediate material 60. The third circuit pattern 50 is formed, for example, from an Al-Mg-Si alloy. The third circuit pattern 50 is formed, for example, from A6063 as specified in the JIS standard.

[0032] As described above, intermediate materials 60 are respectively disposed between the cooling fins 10 and the first circuit pattern 20, between the first circuit pattern 20 and the insulating substrate 30, between the insulating substrate 30 and the second circuit pattern 40, and between the second circuit pattern 40 and the third circuit pattern 50. The thickness of each intermediate material 60 is preferably thinner than the thickness of any one of the first circuit pattern 20, the second circuit pattern 40, and the third circuit pattern 50. The intermediate material 60 is, for example, conductive. The intermediate material 60 is, for example, a cladding material integrally formed with solder rolled onto a core material, i.e., a brazing sheet.

[0033] Semiconductor elements are mounted on the third circuit pattern 50, for example, via a bonding material (not shown). Semiconductor elements are also referred to as semiconductor chips. Semiconductor elements are formed, for example, from semiconductors such as Si. Semiconductor elements are preferably formed from so-called wide-bandgap semiconductors such as SiC, GaN, Ga2O3, and diamond. Semiconductor elements are power semiconductor elements, control ICs (Integrated Circuits) for controlling the power semiconductor element, etc. Semiconductor elements include, for example, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), Schottky barrier diodes, etc. Alternatively, a semiconductor element may include an RC-IGBT (Reverse-Conducting IGBT) in which an IGBT and a return diode are formed within a single semiconductor substrate.

[0034] The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50. The first circuit pattern 20 preferably has a thickness such that the difference between the volume of the component above the insulating substrate 30 and the volume of the component below the insulating substrate 30 converges to within 15%. Here, the component below the insulating substrate 30 includes only the plate portion 10A of the cooling fin 10 that plays a dominant role in the rigidity of the cooling fin 10. The plate portion 10A that plays a dominant role in the rigidity of the cooling fin 10 corresponds to... Figure 2 The area A is indicated by a diagonal line. In other words, the components below the insulating substrate 30 do not include the frame portion disposed on the outer periphery of the fin portion 10B and the plate portion 10A of the cooling fin 10.

[0035] In such a semiconductor device 101, the rigidity of the components below the insulating substrate 30 is reduced. Therefore, warpage after the power module substrate is joined to the cooling fins 10 is reduced. For example, warpage on the lower convex side of the cooling fins 10 is reduced.

[0036] Figure 3 This is a flowchart illustrating a method for manufacturing the semiconductor device 101 in Embodiment 1.

[0037] In step S1, cooling fins 10 are prepared.

[0038] In step S2, a first circuit pattern 20, an insulating substrate 30, a second circuit pattern 40, a third circuit pattern 50, and a plurality of intermediate materials 60 are stacked on the cooling fin 10. At this time, the intermediate materials 60 are respectively disposed between the cooling fin 10 and the first circuit pattern 20, between the first circuit pattern 20 and the insulating substrate 30, between the insulating substrate 30 and the second circuit pattern 40, and between the second circuit pattern 40 and the third circuit pattern 50. The thickness of the first circuit pattern 20 is thinner than at least one of the second circuit pattern 40 and the third circuit pattern 50.

[0039] In step S3, the cooling fins 10, the first circuit pattern 20, the insulating substrate 30, the second circuit pattern 40, and the third circuit pattern 50 are bonded together using multiple intermediate materials 60.

[0040] Semiconductor elements are mounted on the third circuit pattern 50, for example, after step S3. This completes the semiconductor device 101 of Embodiment 1.

[0041] In this manufacturing method, after the components are stacked on the cooling fins 10, they are bonded together with each other using an intermediate material 60. Good bonding can be achieved even when the thickness of the circuit pattern on the upper side of the insulating substrate 30 is different from that on the lower side.

[0042] In summary, the semiconductor device 101 in Embodiment 1 includes a cooling fin 10, a first circuit pattern 20, an insulating substrate 30, a second circuit pattern 40, a third circuit pattern 50, and a plurality of intermediate materials 60. The first circuit pattern 20 is mounted on the cooling fin 10. The insulating substrate 30 is disposed above the first circuit pattern 20. The second circuit pattern 40 is disposed above the insulating substrate 30. The third circuit pattern 50 is disposed above the second circuit pattern 40. The plurality of intermediate materials 60 are respectively disposed between the cooling fin 10 and the first circuit pattern 20, between the first circuit pattern 20 and the insulating substrate 30, between the insulating substrate 30 and the second circuit pattern 40, and between the second circuit pattern 40 and the third circuit pattern 50. The thickness of the first circuit pattern 20 is thinner than at least one of the second circuit pattern 40 and the third circuit pattern 50.

[0043] In such a semiconductor device 101, warpage is reduced after the power module substrate is joined to the cooling fins 10.

[0044] (Modification 1 of Implementation Method 1)

[0045] Figure 4 This is a cross-sectional view showing the structure of the semiconductor device 101A in a variation of Embodiment 1. Figure 5 This is a cross-sectional view showing the structure of the components included in the semiconductor device 101A.

[0046] In Modification 1, the second circuit pattern 40 is thicker than the third circuit pattern 50. The first circuit pattern 20 is thinner than at least one of the second circuit pattern 40 and the third circuit pattern 50. Even with this structure, the same effect as in Embodiment 1 can be achieved.

[0047] (Modification 2 of Implementation Method 1)

[0048] Figure 6 This is a cross-sectional view showing the structure of the semiconductor device 101B in a modified example 2 of embodiment 1. Figure 7 This is a cross-sectional view showing the structure of the components included in the semiconductor device 101B.

[0049] In Modification 2, the third circuit pattern 50 is thicker than the second circuit pattern 40. The first circuit pattern 20 is thinner than at least one of the second circuit pattern 40 and the third circuit pattern 50. Even with this structure, the same effect as in Embodiment 1 can be achieved.

[0050] <Implementation Method 2>

[0051] In Embodiment 2, the same reference numerals are assigned to the same structural elements as in Embodiment 1, and their detailed descriptions are omitted.

[0052] Figure 8 This is a cross-sectional view showing the structure of the semiconductor device 102 in Embodiment 2. Figure 9 This is a cross-sectional view showing the structure of the components included in the semiconductor device 102.

[0053] The semiconductor device 102 includes a first cladding material 71 and a second cladding material 72. A plurality of intermediate materials 60 include a first intermediate material 61, a second intermediate material 62, a third intermediate material 63, and a fourth intermediate material 64.

[0054] The first cladding material 71 includes a first circuit pattern 20, a first intermediate material 61, and a second intermediate material 62. The first circuit pattern 20 is the base material. The first intermediate material 61 is bonded as solder to the lower surface of the first circuit pattern 20. The second intermediate material 62 is bonded as solder to the upper surface of the first circuit pattern 20. The first cladding material 71 is a double-sided solder cladding circuit pattern with solder bonded to both sides of the first circuit pattern 20.

[0055] The second cladding material 72 includes a second circuit pattern 40, a third intermediate material 63, and a fourth intermediate material 64. The second circuit pattern 40 is a base material. The third intermediate material 63 is bonded as solder to the lower surface of the second circuit pattern 40. The fourth intermediate material 64 is bonded as solder to the upper surface of the second circuit pattern 40. The second cladding material 72 is a double-sided solder cladding circuit pattern with solder bonded to both sides of the second circuit pattern 40. In the manufacturing method, in... Figure 3 In step S2, for Figure 9 The components are stacked and then joined together in step S3.

[0056] Even with this structure, the same effects as in Embodiment 1 can be achieved. Furthermore, the number of components constituting the semiconductor device 102 is reduced, and the thermal resistance is lowered.

[0057] <Implementation Method 3>

[0058] In Embodiment 3, the same reference numerals are assigned to the same structural elements as in Embodiment 1 or 2, and their detailed descriptions are omitted.

[0059] Figure 10 This is a cross-sectional view showing the structure of the semiconductor device 103 in Embodiment 3. Figure 11 This is a cross-sectional view showing the structure of the components included in the semiconductor device 103.

[0060] The second circuit pattern 40 and the third circuit pattern 50 are cladding materials directly bonded to each other. The second circuit pattern 40 is formed, for example, of Al. The purity of the Al is, for example, above 99.99% (4N). The third circuit pattern 50 is formed, for example, of Cu. The thickness of the first circuit pattern 20 is thinner than the thickness of at least one of the second circuit pattern 40 and the third circuit pattern 50. In the manufacturing method, in Figure 3 In step S2, for Figure 11 The components are stacked and then joined together in step S3.

[0061] Even with this structure, the same effects as in Embodiment 1 can be achieved. Furthermore, the number of components constituting the semiconductor device 103 is reduced, and the thermal resistance is lowered.

[0062] While this disclosure has been described in detail, the foregoing description is exemplary in all respects and not restrictive. Examples are to be understood as numerous variations not shown can be contemplated.

[0063] In this disclosure, various embodiments can be freely combined, or appropriately modified or omitted.

[0064] Label Explanation

[0065] 10 Cooling fins, 10A Plate section, 10B Fin section, 20 First circuit pattern, 30 Insulating substrate, 40 Second circuit pattern, 50 Third circuit pattern, 60 Intermediate material, 61 First intermediate material, 62 Second intermediate material, 63 Third intermediate material, 64 Fourth intermediate material, 71 First cladding material, 72 Second cladding material, 101 Semiconductor device, 101A Semiconductor device, 101B Semiconductor device, 102 Semiconductor device, 103 Semiconductor device, Region A.

Claims

1. A semiconductor device, characterized in that, include: Cooling fins; A first circuit pattern mounted on the cooling fins; An insulating substrate disposed above the first circuit pattern; A second circuit pattern disposed above the insulating substrate; A third circuit pattern positioned above the second circuit pattern; as well as Multiple intermediate materials are respectively disposed between the cooling fins and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern. The thickness of the first circuit pattern is thinner than the thickness of at least one of the second and third circuit patterns.

2. The semiconductor device as claimed in claim 1, characterized in that, The second circuit pattern is thicker than the third circuit pattern.

3. The semiconductor device as claimed in claim 1, characterized in that, The third circuit pattern is thicker than the second circuit pattern.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, Also includes: First cladding material; as well as Second cladding material, The plurality of intermediate materials include: As a first intermediate material for solder bonding to the lower surface of the first circuit pattern; As a second intermediate material for solder bonding to the upper surface of the first circuit pattern; As a third intermediate material bonded to the lower surface of the second circuit pattern by solder; and As a fourth intermediate material bonded to the upper surface of the second circuit pattern by solder; The first cladding material includes the first circuit pattern, the first intermediate material, and the second intermediate material. The second cladding material includes the second circuit pattern, the third intermediate material, and the fourth intermediate material.

5. A semiconductor device, characterized in that, include: Cooling fins; A first circuit pattern mounted on the cooling fins; An insulating substrate disposed above the first circuit pattern; A second circuit pattern disposed above the insulating substrate; A third circuit pattern positioned above the second circuit pattern; as well as Multiple intermediate materials are respectively disposed between the cooling fins and the first circuit pattern, between the first circuit pattern and the insulating substrate, and between the insulating substrate and the second circuit pattern. The thickness of the first circuit pattern is thinner than the thickness of at least one of the second and third circuit patterns. The second circuit pattern and the third circuit pattern are cladding materials that are directly bonded to each other.

6. A method for manufacturing a semiconductor device, characterized in that, include: The process of preparing cooling fins; The process of stacking a first circuit pattern, an insulating substrate, a second circuit pattern, a third circuit pattern, and multiple intermediate materials on the cooling fins; as well as The process of joining the cooling fins, the first circuit pattern, the insulating substrate, the second circuit pattern, and the third circuit pattern together using the multiple intermediate materials. The plurality of intermediate materials are respectively disposed between the cooling fins and the first circuit pattern, between the first circuit pattern and the insulating substrate, between the insulating substrate and the second circuit pattern, and between the second circuit pattern and the third circuit pattern. The thickness of the first circuit pattern is thinner than the thickness of at least one of the second and third circuit patterns.

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