DDR (Double Data Rate) controller Write leveling optimization method

Abstract

The invention belongs to the field of design of high-reliability embedded systems, and provides a DDR (Double Data Rate) controller Write leveling optimization method, which comprises the following steps of: initializing a sliding window filtering mechanism, configuring window capacity, judging a threshold value and dynamically adjusting a strategy; performing initial low-level search to obtain an initial calibration point when a stable low-level condition is met for the first time; performing high-level capture to obtain candidate alignment points when a stable high-level condition is met for the first time; and performing redundancy check on the candidate alignment points, and after the check is passed, adding a fixed phase protection margin and then outputting for parameter solidification. The method is implemented in a pure software mode, hardware modification is not needed, the method is particularly suitable for airborne and other severe environments, and the Write Leveling calibration success rate can be increased to 99.9% or above from 95% of a traditional method.

Description

Technical Field

[0001] This invention belongs to the field of high-reliability embedded system design technology, and relates to a DDR controller write leveling optimization method based on sliding window filtering. Background Technology

[0002] In airborne embedded computer systems, DDR (Double Data Rate) memory plays a crucial role in data storage and high-speed data exchange, and its stable operation has a decisive impact on the overall system performance and reliability. The Write Leveling operation of the DDR controller is essential for ensuring accurate data transmission between the DDR chips and the controller. The purpose of Write Leveling is to adjust the delay of the DQS (Data Strobe) signal so that the rising edge of the DQS signal is aligned with the rising edge of the clock signal CLK. This ensures that the DDR chip can accurately sample the clock signal level on the rising edge of the DQS signal and return the correct level to the DDR controller via the DQ signal.

[0003] The write leveling operation of the DDR controller requires the DQ signal (feedback signal) read back from the DDR chip to determine the phase relationship between the clock signal (CLK) and the strobe signal (DQS signal). However, in harsh airborne environments (such as temperature fluctuations from -55°C to 125°C, and 30G mechanical shock), power supply noise will be generated, causing the CLK signal to experience high-frequency jitter (Jitter > 100ps) due to changes in transmission path impedance. This can lead to the following two risks: 1. Instantaneous sampling misjudgment: Under the influence of high jitter, when the DDR chip samples the CLK level at the rising edge of the DQS signal, it may make incorrect judgments (for example, misjudging the actual low level CLK as a high level), resulting in distorted feedback information.

[0004] 2. Phase Shift Accumulation: Traditional Write Leveling often uses a successive approximation algorithm based on single sampling results. This algorithm is extremely sensitive to the aforementioned instantaneous misjudgments. A single erroneous feedback may cause repeated oscillations and incorrect adjustments of the DQS signal delay parameter, which not only significantly prolongs the calibration time, but may also cause the initialization process to time out or even the DDR bus to completely lock and fail, endangering system startup.

[0005] To address the timing tolerance issues caused by environmental interference, existing technologies primarily seek optimization at the hardware level. For example, published patent CN220820669U proposes using a third-order RC filter network to filter the analog power supply to suppress noise. However, such hardware solutions have inherent limitations and cannot meet the demands of modern high-performance, highly integrated airborne systems: (1) Hardware redundancy: It is necessary to add energy storage capacitors, third-order filter networks and decoupling capacitors, occupying PCB area ≥15mm², which does not meet the high-density integration requirements of airborne equipment. (2) Insufficient dynamic performance: The RC filter circuit has a fixed cutoff frequency (typical value 1MHz), which cannot be adapted to high clock rate (1.6GHz) scenarios such as DDR4-3200, and is ineffective against ns-level clock jitter; (3) Poor environmental adaptability: The influence of airborne temperature drift on RC component parameters (such as capacitance drift ±20%) is not considered, and the filtering characteristics deteriorate under extreme temperatures.

[0006] In summary, existing solutions focus on hardware filtering or signal integrity optimization. However, airborne scenarios require: zero hardware modifications to avoid redesigning the PCB layout; fully digital processing to adapt to parameter drift over a wide temperature range; and real-time error correction capabilities to suppress noise within μs. Therefore, there is an urgent need for an optimization method that can suppress clock jitter interference on the Write Leveling process in harsh environments in real time through digital and adaptive methods without changing the existing hardware design. Summary of the Invention

[0007] To address the issue of DQS signal and CLK phase calibration failure caused by clock jitter in airborne embedded computers under harsh operating conditions such as strong vibration, wide temperature variation, and electromagnetic interference, and to improve the initialization stability of the DDR bus, this invention discloses a DDR controller write leveling optimization method, which includes the following steps: S1. Initialize the sliding window filtering mechanism: Configure the window capacity, decision threshold, and dynamic adjustment mechanism of the window capacity, and enable the sliding window filtering function; S2. Perform initial low-level search: Start by adjusting the DQS signal delay parameter incrementally from the minimum DQS signal delay parameter, and use a sliding window to judge the DQ level status fed back by the continuously sampled DDR chip. Record the DQS signal delay parameter when the stable low-level condition is first met as the initial calibration point. S3. Perform high-level capture: Starting from the initial calibration point, gradually increase the DQS signal delay parameter. Through sliding window decision, record the DQS signal delay parameter when the stable high-level condition is met for the first time as a candidate alignment point. S4. Redundancy check on candidate alignment points: Delay the candidate alignment points forward and backward respectively, and check whether the high level difference between the forward and backward offset points meets the preset conditions. If it meets the conditions, output the candidate alignment point. If it does not meet the conditions, fine-tune the candidate alignment point until it meets the preset conditions and then output it.

[0008] Further, in step S1, enabling the sliding window filtering function includes: S11. Configure the DDR controller to enter Write Leveling mode, and disable the single sampling function at the same time; S12, Force enable sliding window filtering flag.

[0009] Further, in step S2, the delay parameters of the DQS signal when the stable low-level condition is first met are obtained, including: S21. Set the DQS signal delay parameter to the minimum value and send the test mode signal; S22. After each adjustment of the DQS signal delay parameter, continuously sample the DQ level state according to the window size and store it in the sliding window. S23. Make a decision based on the decision threshold. When the proportion of low level in the sliding window is greater than or equal to the decision threshold, it is determined to be a stable low level state, and the current DQS signal delay parameter is recorded as the initial calibration point.

[0010] Further, in step S3, the delay parameters of the DQS signal when the stable high-level condition is first met are obtained, including: S31. Starting from the initial calibration point, increment the DQS signal delay parameter by 1 delay unit. S32. After each increment of the DQS signal delay parameter, continuously sample the DQ level state according to the window size. If the proportion of high level in the sliding window is greater than or equal to the decision threshold, mark the current DQS signal delay parameter as a candidate alignment point. S33. After marking the candidate alignment point, continue to add multiple delay units and verify whether the percentage of high level within the sliding window is greater than or equal to the decision threshold after each delay.

[0011] Further, in step S4, verifying whether the high-level difference between the preceding and following offset points meets preset conditions includes: S41. Offset the candidate alignment point forward and backward by multiple delay units respectively to obtain the forward offset point and the backward offset point, and perform sliding window sampling on the forward offset point and the backward offset point respectively; S42. If the proportion of high-level signal at the forward offset point is less than the first threshold and the proportion of high-level signal at the backward offset point is greater than the second threshold, then the candidate alignment point is determined to be valid. S43. If the verification fails, the delay step size is halved, and the high-level capture and redundancy verification are performed again within the DQS signal delay parameter range of ±1 delay unit of the candidate alignment point.

[0012] Furthermore, the sliding window adopts a FIFO queue structure, so that each time new sampled data enters the queue, it overwrites the oldest historical data and dynamically updates the content of the sliding window.

[0013] In an improved embodiment of the above-described DDR controller write leveling optimization method, the method further includes: S5. Parameter solidification: Add phase protection margin to the candidate alignment points that pass the verification of the output, and write the final DQS delay parameters into the controller register. The phase protection margin is a fixed percentage of the clock cycle.

[0014] In another improved embodiment of the above-described DDR controller write leveling optimization method, the method further includes: S6. Perform exception handling: If the verification is not completed within the preset maximum delay range or the verification fails continuously, the exception handling mechanism is activated to perform at least one of the following operations: increase the window capacity, raise the decision threshold, or switch the search mode, and then return to the corresponding verification step.

[0015] Furthermore, in step S6, the exception handling mechanism includes: S61. If no valid alignment point is found within the preset maximum delay range, activate the reverse decreasing search mode. S62. If the decision is not completed multiple times in a row, the dynamic adjustment mechanism of the window capacity is activated to expand the window capacity, or an error code is reported and a switch to the backup clock source is triggered. S63. After marking the candidate alignment point, continue to add multiple delay units and verify whether the high level ratio within the sliding window is greater than or equal to the decision threshold after each delay. If not, start the dynamic adjustment mechanism of window capacity N to expand the window capacity or increase the decision threshold.

[0016] Furthermore, in step S62, the expansion adjustment of the window capacity is dynamically related to the DDR operating frequency and the intensity of electromagnetic interference.

[0017] The method of this invention, compared to the traditional Write Leveling method which directly determines the adjustment direction of the DQS signal delay parameter by sampling the level state of the DQ signal in a single instance, suffers from drawbacks under extreme conditions such as high-frequency clock jitter and electromagnetic interference. Single sampling is prone to misjudgment due to transient interference, leading to errors in delay parameter calibration. This invention introduces a sliding window filtering mechanism, using multiple samplings and state decisions within a dynamic window to suppress the influence of random interference on level determination, thereby improving the robustness of the calibration parameters.

[0018] The technical solution of the present invention has at least the following technical effects: 1. Multi-sampling decision instead of single sampling: Through the statistical decision mechanism within the sliding window, misjudgments caused by transient interference are effectively suppressed, increasing the calibration success rate from 95% of the traditional method to over 99.9%.

[0019] 2. Dynamic window size adjustment: The window size is adaptively optimized according to the intensity of environmental interference, balancing calibration speed and reliability.

[0020] 3. Parameter neighborhood redundancy verification: Add a local verification step before final parameter confirmation to avoid systematic deviations caused by residual noise within the window.

[0021] 4. No external sensor dependency: Anti-interference is achieved entirely based on the internal signal processing of the DDR controller, which meets the requirements of airborne equipment for hardware simplification. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of the DDR controller write leveling optimization method of the present invention; Figure 2 This is a transformation diagram for a sliding window; Figure 3 This outlines the process for solidifying and optimizing the determined DQS delay parameters, as well as the process for handling anomalies during optimization. Detailed Implementation

[0024] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0025] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features of the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] This invention discloses a DDR controller write leveling optimization method, such as... Figure 1 and Figure 2 As shown, the method includes the following steps: S1. Initialize the sliding window filtering mechanism: Configure the window capacity, decision threshold, and dynamic adjustment mechanism of the window capacity, and enable the sliding window filtering function; S2. Perform initial low-level search: Start by adjusting the DQS signal delay parameter incrementally from the minimum DQS signal delay parameter, and use a sliding window to judge the DQ level status fed back by the continuously sampled DDR chip. Record the DQS signal delay parameter when the stable low-level condition is first met as the initial calibration point. S3. Perform high-level capture: Starting from the initial calibration point, gradually increase the DQS signal delay parameter. Through sliding window decision, record the DQS signal delay parameter when the stable high-level condition is met for the first time as a candidate alignment point. S4. Redundancy check on candidate alignment points: Delay the candidate alignment points forward and backward respectively, and check whether the high level difference between the forward and backward offset points meets the preset conditions. If it meets the conditions, output the candidate alignment point. If it does not meet the conditions, fine-tune the candidate alignment point until it meets the preset conditions and then output it.

[0027] In one embodiment of step S1, enabling the sliding window filtering function includes: S11. Configure the DDR controller to enter Write Leveling mode, and disable the single sampling function at the same time; S12, Force enable sliding window filtering flag.

[0028] In practice, the initial window capacity N = 10, the decision threshold M = 70%, the maximum window capacity N_max = 30, and the protection margin Δ = 5% * clock cycle can be set.

[0029] In one embodiment of step S2, the DQS signal delay parameters when the stable low-level condition is first met are obtained, including: S21. Set the DQS signal delay parameter to the minimum value and send the test mode signal; S22. After each adjustment of the DQS signal delay parameter, continuously sample the DQ level state according to the window size and store it in the sliding window. S23. Make a decision based on the decision threshold M. When the proportion of low level in the sliding window is greater than or equal to the decision threshold M, it is determined to be a stable low level state, and the current DQS signal delay parameter is recorded as the initial calibration point.

[0030] In practice, firstly, the DQS delay parameter is set to its minimum value (e.g., DQS_delay=0), and a test mode signal is sent to the DDR chip. Then, the controller continuously reads the clock sampling results 10 times through the DQ signal and stores them in the sliding window. Secondly, the number of low levels in the sliding window is calculated. If the number of low levels is ≥7, it is determined that the delay needs to be increased. If the number of low levels is ≤3, it is determined that the initial low level point has been found. Otherwise, the window is cleared and resampling is performed. Finally, if the decision is not completed for 3 consecutive times, the sliding window is expanded by increasing N from 10 to 15, and sampling is repeated until the initial point is locked.

[0031] In one embodiment of step S3, the DQS signal delay parameters when the stable high-level condition is first met are obtained, including: S31. Starting from the initial calibration point, increment the DQS signal delay parameter by 1 delay unit. S32. After each increment of the DQS signal delay parameter, continuously sample the DQ level state according to the window size. If the proportion of high level in the sliding window is greater than or equal to the decision threshold M, then mark the current DQS signal delay parameter as a candidate alignment point P1. S33. After marking the candidate alignment point P1, continue to add multiple delay units and verify whether the percentage of high level within the sliding window is greater than or equal to the decision threshold M after each delay.

[0032] In practice, starting from the initial low-level point obtained in step S2, DQS_delay is incremented by a step size of 1, and the following operations are performed at each step: 1) Send a test signal, sample the DQ level 10 times and fill the sliding window; 2) If the number of high-level events within the window is ≥7, record the current DQS_delay as the candidate alignment point P1; 3) If the sliding window does not meet the decision condition, keep the delay value unchanged and trigger a second sampling (N=15).

[0033] Secondly, when candidate alignment point P1 is captured for the first time, a delay of 2 steps is added to verify whether the window state maintains a stable high level. If so, candidate alignment point P1 is output.

[0034] In one embodiment, in steps S2 and S3 above, the stable low-level condition and the stable high-level condition are that the proportion of high-level / low-level within the sliding window exceeds the decision threshold M, wherein the value range of the decision threshold M can be set to 60%~80%.

[0035] In one embodiment of step S4, verifying whether the high-level difference between the preceding and following offset points meets a preset condition includes: S41. Offset the candidate alignment point P1 forward and backward by multiple delay units respectively to obtain the forward offset point and the backward offset point, and perform sliding window sampling on the forward offset point and the backward offset point respectively. S42. If the high-level percentage of the forward offset point (P1-2) is less than the first threshold (e.g., 30%), and the high-level percentage of the backward offset point (P1+2) is greater than the second threshold (e.g., 90%), then the candidate alignment point P1 is determined to be valid. S43. If the verification fails, the delay step size is halved, and the high-level capture and redundancy verification are performed again within the DQS signal delay parameter range of ±1 delay unit of the candidate alignment point P1.

[0036] In practice, the candidate alignment point P1 is offset forward and backward by ±2 delay units respectively, resulting in forward offset point (P1-2) and backward offset point (P1+2). Window sampling is then performed on each of these points. If the high-level percentage of the sliding window at the forward offset point (P1-2) is less than the first threshold (e.g., set to 30%), and the high-level percentage at the backward offset point (P1+2) is greater than the second threshold (e.g., set to 90%), then the candidate alignment point P1 is considered valid. Otherwise, the delay step is halved, and fine-tuning is performed near the candidate alignment point P1 until the verification conditions are met.

[0037] Furthermore, the sliding window adopts a FIFO queue structure, so that each time new sampled data enters the queue, it overwrites the oldest historical data and dynamically updates the content of the sliding window.

[0038] In an improved embodiment of the above-described DDR controller write leveling optimization method, such as Figure 3 As shown, the method further includes: S5. Parameter solidification: Add phase protection margin to the candidate alignment points that pass the verification of the output, and write the final DQS delay parameters into the controller register. The phase protection margin is a fixed percentage of the clock cycle, i.e., Δ=5%*clock cycle.

[0039] In another improved embodiment of the above-described DDR controller write leveling optimization method, such as Figure 3 As shown, the method further includes: S6. Perform exception handling: If the verification is not completed within the preset maximum delay range or the verification fails continuously, the exception handling mechanism is activated to perform at least one of the following operations: increase the window capacity, raise the decision threshold, or switch the search mode, and then return to the corresponding verification step.

[0040] Furthermore, in step S6, the exception handling mechanism includes: S61. If no valid alignment point is found within the preset maximum delay range, activate the reverse decreasing search mode to avoid the process being stuck due to misjudgment of the initial point. S62. If the decision is not completed multiple times (e.g., 3 times) in a row, the dynamic adjustment mechanism of the window capacity N is activated to expand the window capacity N, or an error code is reported and a switch to the backup clock source is triggered. S63. After marking the candidate alignment point P1, continue to add multiple delay units and verify whether the proportion of high level in the sliding window is greater than or equal to the decision threshold M after each delay. If not, start the dynamic adjustment mechanism of window capacity N to expand the window capacity or increase the decision threshold M.

[0041] For example, the window size can be increased to N_max=30, and the decision threshold can be adjusted to M=80%.

[0042] Furthermore, in step S62, the expansion adjustment of the window capacity is dynamically related to the DDR operating frequency and the intensity of electromagnetic interference.

[0043] The present invention verifies the above method using actual test data from a certain type of airborne computer. The results show that the method of the present invention successfully reduces the write leveling calibration failure rate from 3.5% of the traditional method to 0.03%, and the average calibration time only increases by 15% (from 2.1ms to 2.4ms), which fully meets the airborne real-time requirements.

[0044] The embodiments of the present invention achieve the following technical effects: 1. Multi-sampling decision instead of single sampling: Through the statistical decision mechanism within the sliding window, misjudgments caused by transient interference are effectively suppressed, increasing the calibration success rate from 95% of the traditional method to over 99.9%.

[0045] 2. Dynamic window size adjustment: The window size is adaptively optimized according to the intensity of environmental interference, balancing calibration speed and reliability.

[0046] 3. Parameter neighborhood redundancy verification: Add a local verification step before final parameter confirmation to avoid systematic deviations caused by residual noise within the window.

[0047] 4. No external sensor dependency: Anti-interference is achieved entirely based on the internal signal processing of the DDR controller, which meets the requirements of airborne equipment for hardware simplification.

[0048] In this embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements any of the above-described DDR controller write leveling optimization methods.

[0049] Specifically, the computer device can be a computer terminal, a server, or a similar computing device.

[0050] In this embodiment, a computer-readable storage medium is provided, which stores a computer program that executes any of the above-described DDR controller write leveling optimization methods.

[0051] Specifically, computer-readable storage media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media does not include transient media, such as modulated data signals and carrier waves.

[0052] Obviously, those skilled in the art should understand that the modules or steps of the above-described embodiments of the present invention can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of the present invention are not limited to any particular hardware and software combination.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for optimizing write leveling in a DDR controller based on sliding window filtering, characterized in that, The method includes: Initialize the sliding window filtering mechanism: Configure the window size, decision threshold, and dynamic adjustment mechanism of the window size, and enable the sliding window filtering function; Perform initial low-level search: Start by incrementally adjusting the DQS signal delay parameter from the minimum DQS signal delay parameter, and use a sliding window to determine the DQ level status fed back from the continuously sampled DDR chips. Record the DQS signal delay parameter when the stable low-level condition is first met as the initial calibration point. High-level capture: Starting from the initial calibration point, the DQS signal delay parameter is gradually increased. Through sliding window decision, the DQS signal delay parameter when the stable high-level condition is met for the first time is recorded as a candidate alignment point. Redundancy check of candidate alignment points: The candidate alignment points are delayed forward and backward respectively, and the difference in high level between the forward and backward offset points is checked to see if it meets the preset conditions. If it meets the conditions, the candidate alignment point is output. If it does not meet the conditions, the candidate alignment point is fine-tuned until it meets the preset conditions and then output.

2. The DDR controller write leveling optimization method according to claim 1, characterized in that, Enable sliding window filtering, including: Configure the DDR controller to enter Write Leveling mode, and disable single sampling function; Force the sliding window filtering enable flag to be enabled.

3. The DDR controller write leveling optimization method according to claim 1, characterized in that, The DQS signal delay parameters when the stable low-level condition is first met are obtained, including: Set the DQS signal delay parameter to the minimum value and send the test mode signal; Each time the DQS signal delay parameter is adjusted, the DQ level state is continuously sampled and stored in the sliding window according to the window size. The decision is made based on the decision threshold. When the proportion of low level within the sliding window is greater than or equal to the decision threshold, it is determined to be a stable low level state, and the current DQS signal delay parameter is recorded as the initial calibration point.

4. The DDR controller write leveling optimization method according to claim 1, characterized in that, The DQS signal delay parameters when the stable high-level condition is first met are obtained, including: Starting from the initial calibration point, the DQS signal delay parameter is increased in increments of 1 delay unit. After each increment of the DQS signal delay parameter, the DQ level is continuously sampled according to the window size. If the proportion of high level in the sliding window is greater than or equal to the decision threshold, the current DQS signal delay parameter is marked as a candidate alignment point. After marking the candidate alignment point, continue to add multiple delay units and verify whether the percentage of high level within the sliding window is greater than or equal to the decision threshold after each delay.

5. The DDR controller write leveling optimization method according to claim 1, characterized in that, Verify whether the high-level difference between the offset points before and after meets the preset conditions, including: The candidate alignment point is offset forward and backward by multiple delay units to obtain forward offset point and backward offset point, and sliding window sampling is performed on the forward offset point and the backward offset point respectively; If the proportion of high-level values ​​at the forward offset point is less than the first threshold, and the proportion of high-level values ​​at the backward offset point is greater than the second threshold, then the candidate alignment point is determined to be valid. If the verification fails, the delay step size is halved, and high-level capture and redundancy verification are performed again within the DQS signal delay parameter range of ±1 delay unit of the candidate alignment point.

6. The DDR controller write leveling optimization method according to claim 1, characterized in that, The sliding window adopts a FIFO queue structure. Each time new sampled data enters the queue, it overwrites the oldest historical data, and the content of the sliding window is dynamically updated.

7. The DDR controller write leveling optimization method according to any one of claims 1 to 6, characterized in that, The method further includes: Parameter solidification: Add phase protection margin to the candidate alignment points that pass the verification of the output, and write the final DQS delay parameters into the controller register. The phase protection margin is a fixed percentage of the clock cycle.

8. The DDR controller write leveling optimization method according to any one of claims 1 to 6, characterized in that, The method further includes: Exception handling: If the verification is not completed within the preset maximum delay range or the verification fails continuously, the exception handling mechanism is activated to perform at least one of the following operations: increase the window capacity, raise the decision threshold, or switch the search mode, and then return to the corresponding verification step.

9. The DDR controller write leveling optimization method according to claim 8, characterized in that, The exception handling mechanism includes: If no valid alignment point is found within the preset maximum delay range, the reverse decreasing search mode is activated; If the judgment is not completed multiple times in a row, the dynamic adjustment mechanism of the window capacity will be activated to expand the window capacity, or an error code will be reported and a switch to the backup clock source will be triggered. After marking the candidate alignment point, continue to add multiple delay units and verify whether the percentage of high level within the sliding window is greater than or equal to the decision threshold after each delay. If not, start the dynamic adjustment mechanism of window capacity to expand the window capacity or increase the decision threshold.

10. The DDR controller write leveling optimization method according to claim 9, characterized in that, The adjustment of the window capacity is dynamically related to the DDR operating frequency and the intensity of electromagnetic interference.

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