Image sending and displaying method and electronic equipment

Abstract

The invention discloses an image transmitting and displaying method and electronic equipment, and relates to the technical field of terminals. The method comprises the following steps: at a first moment, the electronic equipment generates a first hardware TE signal, and the SoC sends first image data to a display screen in response to the first hardware TE signal; at a second time, the electronic device generates a second hardware TE signal. At a third time, the electronic device generates a first software TE signal, and the SoC sends second image data to the display screen in response to the first software TE signal. At a fourth time, the electronic device generates a third hardware TE signal. Thus, picture sending can be triggered when the hardware TE signals are generated, picture sending can also be triggered when the software TE signals are generated between the two hardware TE signals, and display lagging is reduced by increasing the picture sending opportunity.

Description

Technical Field

[0001] This application relates to the field of terminal technology, and in particular to an image display method and electronic device. Background Technology

[0002] Electronic devices can use a central processing unit (CPU) and a graphics processing unit (GPU) to complete drawing, rendering, and compositing, processing the image data of a frame. Then, the display driver can send the image data to the display screen when a tear effect (TE) signal is detected, such as when the rising edge of the TE signal is detected.

[0003] However, if the CPU and GPU do not complete image processing and obtain image data in time before the TE signal arrives, the display driver will not send new image data to the display screen. Subsequently, the display driver will only send the image data processed by the CPU and GPU to the display screen when the next TE signal arrives. In this case, the display screen will continuously display the same frame of image, resulting in display junk. Furthermore, if the CPU and GPU fail to process multiple frames of image data in time, multi-frame display junk will occur. Summary of the Invention

[0004] This application provides an image display method and electronic device, which can increase the timing of triggering display, improve the timeliness of display, thereby reducing display lag and improving display performance.

[0005] Firstly, this application provides an image display method. This method can be executed by an electronic device, or by a component of the electronic device, such as a processor, chip, or chip system. It can also be implemented by a logic module or software (such as a display driver) capable of implementing all or part of the electronic device; this application does not specifically limit this. The following description primarily uses an electronic device as an example, which includes a System-on-Chips (SoC) and a display screen. The electronic device generates a hardware TE signal with a first cycle (e.g., the cycle corresponding to 60Hz, 90Hz, 120Hz, etc.). Generating a hardware TE signal can be understood as generating the rising edge signal of the hardware TE signal. It should be noted that in the following embodiments, the hardware TE signal can be referred to as a TE signal.

[0006] Specifically, the method includes: at a first moment, the electronic device generates a first hardware TE signal, and in response to the first hardware TE signal, the SoC sends first image data to the display screen. At a second moment, the electronic device generates a second hardware TE signal, wherein the second moment is after the first moment, and the second hardware TE signal is the next hardware TE signal after the first hardware TE signal, and the time interval between the first moment and the second moment is a first period. It should be noted that in the embodiments below, the software TE signal may be referred to as the target signal. At a third moment, the electronic device generates a first software TE signal, and in response to the first software TE signal, the SoC sends second image data to the display screen, wherein the third moment is after the second moment, and the second image data is the next frame of image data after the first image data. At a fourth moment, the electronic device generates a third hardware TE signal, wherein the third moment is after the second moment, and the third hardware TE signal is the next hardware TE signal after the second hardware TE signal.

[0007] For example, in the following text Figure 13 and Figure 16 In the above, the first time point is time t1, the first image data is Figure A, the second time point is time t3, the third time point is time t5, the first software TE signal is the target signal Z1, the second image data is Figure B, and the fourth time point is time t6. (This is consistent with the above.) Figure 13 and Figure 16 The difference is that in the following text Figure 14 and Figure 15 In the middle, the third time point is time t4.

[0008] The hardware TE signal can be generated by the display screen, such as the DDIC within the display. The software TE signal can be generated by the SoC. For example, the SoC can generate the TE signal based on the timing of a timer. When the timing is reached, a software TE signal is generated. Accordingly, the software TE signal can be a timer signal, also known as a clock signal. Of course, the software TE signal can also be other forms of signal, and this application does not specifically limit it. It should be noted that the aforementioned first software TE signal and hardware TE signal usually do not overlap.

[0009] In summary, electronic devices can trigger image transmission based on either hardware or software TE signals, thereby increasing the opportunities for image transmission. This allows the electronic device to promptly trigger image transmission based on the first software TE signal when processing the second image data experiences a processing bottleneck, which helps reduce display stuttering and improve display performance.

[0010] In one possible design of the first aspect, the method further includes: after the first moment, the electronic device displays the first image data on the display screen.

[0011] For example, the first image data is displayed starting from the fifth moment, which can be the moment after the high level of the first hardware TE signal ends. For example, as described below... Figures 13-16 In the above, the fifth time point is time t2.

[0012] In other words, once an electronic device triggers a graphic based on a hardware TE signal, it can then begin displaying image data on the screen.

[0013] In one possible design of the first aspect, the method further includes: after the fourth moment, the electronic device displays second image data on the display screen.

[0014] For example, the display of the second image data begins at a sixth moment, which can be the moment after the high level of the third hardware TE signal ends. For instance, as described below... Figure 13 and Figure 16 In the text, the sixth time point is time t7, which will be discussed below. Figure 14 and Figure 15 In the middle, the sixth time point is time t5.

[0015] In other words, electronic devices trigger image transmission based on software TE signals, and can start displaying image data on the screen after the software TE signal and the nearest hardware TE signal.

[0016] In one possible design approach in the first aspect, at the second and fourth time points, as follows: Figures 13-16 At times t3 and t6, the SoC does not send image data to the display.

[0017] If the second image data is delayed in processing and has not been processed by the second time step, then the image cannot be sent when the second hardware TE signal is generated at the second time step.

[0018] If the second image data has already been sent in advance at the third time before the fourth time, then when the third hardware TE signal is generated at the fourth time, there is no need to send the image.

[0019] In one possible design of the first aspect, after the electronic device generates the third hardware TE signal, the method further includes: at a seventh moment, the electronic device generates a second software TE signal, and in response to the second software TE signal, the SoC sends third image data to the display screen. The third image data is the image data of the next frame after the second image data.

[0020] For example, in the following text Figures 13-16 In the diagram, the seventh time is time t8, the second software TE signal is the target signal Z2, and the third image data is Figure C.

[0021] Thus, even if there is a processing bottleneck in the processing of the third image data, and the condition of sending the image at a specific time is met, Figures 13-16 Figure C illustrates this situation, where the electronic device can still trigger image transmission based on the software TE signal, thus achieving timely image transmission. Alternatively, even if there is no processing lag in the processing of the third image data, the electronic device can still trigger image transmission based on the software TE signal when the previous frame of image data (the second image data) is sent, thus ensuring the time interval between the two image transmissions. See the case of S817 below for details.

[0022] In one possible design of the first aspect, after the SoC sends third image data to the display screen in response to the second software TE signal, the method further includes: at an eighth moment, the electronic device generates a fourth hardware TE signal; wherein the fourth hardware TE signal is the next hardware TE signal after the third hardware TE signal.

[0023] For example, in the following text Figures 13-16 In the middle, the eighth time is time t9.

[0024] In one possible design of the first aspect, the method further includes: after the eighth moment, the electronic device displays third image data on the display screen. For example, the third image data is displayed starting from the ninth moment, which can be the moment after the high level of the fourth hardware TE signal ends. For example, as described below... Figures 13-16 In the middle, the ninth time is time t10.

[0025] In one possible design approach of the first aspect, the SoC does not send image data to the display at the eighth time step. Since the third image data has already been sent in advance at the seventh time step, prior to the eighth time step, there is no need to perform image sending when the fourth hardware TE signal is generated at the eighth time step.

[0026] In one possible design of the first aspect, after the electronic device generates the third hardware TE signal at the fourth moment, the above method further includes: at the tenth moment, the electronic device generates a fifth hardware TE signal, and in response to the fifth hardware TE signal, the SoC sends fourth image data to the display screen.

[0027] For example, in the following text Figure 13 and Figure 15 In this context, the tenth time is time t11. It should be noted that... Figure 13 and Figure 15 In this context, the second image data is shown in Figure B, and the fourth image data is shown in Figure D. In practice, the fourth image data can also be the image data of the next frame after the second image data, and this application does not make any specific limitation on this.

[0028] In other words, after the processing of the first image data is delayed, the subsequent fourth image data (which can be the next frame of the first image data or the image data at least one frame later) may continue to experience processing delays. However, unlike the third image data, the fourth image data may experience processing delays but does not meet the conditions for sending the image at a specific time. In this case, the electronic device will trigger the image sending based on the hardware TE signal, thereby ensuring that the fourth image data can be sent to the display screen for display.

[0029] In one possible design of the first aspect, the method further includes: after the tenth moment, the electronic device displays fourth image data on the display screen. For example, the display of the fourth image data begins from the eleventh moment, which can be the moment after the high level of the fifth hardware TE signal ends. For example, as described below... Figure 13 and Figure 15 In the diagram, the eleventh time is time t12.

[0030] In one possible design of the first aspect, after the SoC sends the fourth image data to the display screen in response to the fifth hardware TE signal, the method further includes: at a twelfth moment, the electronic device generates a sixth hardware TE signal, and in response to the sixth hardware TE signal, the SoC sends the fifth image data to the display screen. Wherein, the fifth image data is the image data of the next frame after the fourth image data, and the sixth hardware TE signal is the hardware TE signal following the fifth hardware TE signal.

[0031] For example, in the following text Figure 13 In the image, the twelfth moment is time t13, and the fifth image data is Figure E.

[0032] Thus, if the fourth image data of the previous frame is sent based on the hardware TE signal, and there is no processing delay in the fifth image data, the electronic device can continue to send the image based on the hardware TE signal, thereby ensuring the time interval between the two image transmissions. For details, please refer to the case of S816 below.

[0033] In one possible design approach of the first aspect, the above method further includes: after the twelfth time, as follows: Figure 13 At time t14, the electronic device displays the fifth image data on the screen.

[0034] In one possible design approach of the first aspect, before the electronic device generates the first software TE signal, the method further includes: after obtaining the second image data, the SoC detects whether the conditions for triggering image transmission based on the software TE signal are met. It should be understood that the SoC can obtain the second image data after image drawing, rendering, compositing, and other processing. Meeting the conditions for triggering image transmission via the software TE signal indicates that the image can be transmitted in advance before the next hardware TE signal arrives.

[0035] Accordingly, in response to the first software TE signal, the SoC sends second image data to the display screen, including: when the conditions for triggering image sending based on the software TE signal are met, the SoC sends the second image data to the display screen in response to the first software TE signal. In this way, the electronic device can achieve targeted advance image sending.

[0036] In one possible design approach of the first aspect, the conditions for triggering the pattern based on the software TE signal include any of the following:

[0037] If the time interval between the last time image data was sent to the display and the thirteenth time when the SoC prepares to send the second image data to the display exceeds the preset frame length, a processing lag occurs. Furthermore, the period between the thirteenth time and the time when the next TE signal is generated includes the time when the software TE signal is generated, meaning there is an opportunity to send the image before the next hardware TE signal arrives. In other words, the electronic device can send the image ahead of time even when processing lag exists, thus maximizing the early image sending and reducing display lag caused by processing lag.

[0038] The time interval between the last time image data was sent to the display and the thirteenth moment when the SoC was preparing to send the second image data to the display did not exceed the preset frame length, meaning there was no processing lag. Furthermore, the previous image data was sent to the display based on a software TE signal. In other words, even without processing lag, the electronic device maintains the triggering method of the previous image transmission. For example, if the previous image transmission was based on a hardware TE signal, then the current transmission will also be based on a hardware TE signal. This allows control over the time interval between image transmissions between consecutive frames.

[0039] Secondly, this application also provides an electronic device including a display screen, a memory, and one or more processors. The display screen, memory, and processors are coupled. The memory stores computer program code, including computer instructions, which, when executed by the processor, cause the electronic device to perform the methods described in the first aspect and any of its possible designs.

[0040] Thirdly, this application provides a chip system applied to an electronic device including a display screen and a memory; the chip system includes one or more interface circuits and one or more processors; the interface circuits and processors are interconnected via lines; the interface circuits are used to receive signals from the memory of the electronic device and send signals to the processor, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device performs the method as described in the first aspect and any of its possible design embodiments.

[0041] Fourthly, this application provides a computer storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform a method as described in the first aspect and any possible design thereof.

[0042] Fifthly, this application provides a computer program product that, when run on a computer, causes the computer to perform the method as described in the first aspect and any of its possible design methods.

[0043] Understandably, the beneficial effects that the electronic device of the second aspect, the chip system of the third aspect, the computer storage medium of the fourth aspect, and the computer program product of the fifth aspect can achieve can be referred to the beneficial effects of the first aspect and any of its possible design embodiments, which will not be repeated here. Attached Figure Description

[0044] Figure 1 One of the schematic diagrams illustrating the principle of image display provided in the embodiments of this application;

[0045] Figure 2 A second schematic diagram illustrating the principle of image display provided in this application embodiment;

[0046] Figure 3 The third schematic diagram illustrating the principle of image display provided in the embodiments of this application;

[0047] Figure 4 This is a schematic diagram illustrating display lag provided in an embodiment of this application;

[0048] Figure 5 A hardware structure diagram of the electronic device provided in the embodiments of this application;

[0049] Figure 6 A schematic diagram of the TE signal for various screens provided in the embodiments of this application;

[0050] Figure 7 Hardware and software architecture diagrams of electronic devices provided in embodiments of this application;

[0051] Figure 8 A timing interaction diagram of the image display method provided in the embodiments of this application;

[0052] Figure 9 A schematic diagram of the initialization timer provided in an embodiment of this application;

[0053] Figure 10 This is a schematic diagram illustrating the determination of processing lag in an embodiment of this application;

[0054] Figure 11 This is a schematic diagram illustrating the timing of triggering the image in the event of processing lag, as provided in an embodiment of this application.

[0055] Figure 12 A schematic diagram illustrating the timing of triggering an image when there is no processing lag, as provided in the embodiments of this application;

[0056] Figure 13 A schematic diagram illustrating the sending and refreshing of images in Example 1, provided as an embodiment of this application;

[0057] Figure 14 This is a schematic diagram of the image submission and refresh display provided in Example 2 of the embodiments of this application;

[0058] Figure 15 This is a schematic diagram of the image submission and refresh display provided in Example 3 of the embodiments of this application;

[0059] Figure 16 This is a schematic diagram of the image submission and refresh display provided in Example 4, which is an embodiment of this application.

[0060] Figure 17 A schematic diagram of another image display scheme provided in an embodiment of this application;

[0061] Figure 18 This is a schematic diagram of the chip system provided in an embodiment of this application. Detailed Implementation

[0062] The technical solutions of the embodiments of this application are described below with reference to the accompanying drawings. In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to limit the application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0063] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0064] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0065] Before introducing the embodiments of this application, the following will first combine... Figures 1-3 A brief introduction to the principle of image display.

[0066] See Figure 1 Electronic devices include system-on-chips (SoCs) and displays (also known as screens).

[0067] The SoC integrates key chips such as an application processor (AP) and a baseband processor (BP, also known as a modem). Furthermore, the AP may include processing units such as a CPU and a GPU. The display screen further includes a display control module, an image storage unit, and a display panel.

[0068] For example, the display control module may be a display driver integrated circuit (DDIC). It should be noted that the display control module may also be referred to as a controller, driver circuit, etc., and this application embodiment does not specifically limit it in this way.

[0069] For example, the image storage unit can be random access memory (RAM), such as graphics RAM (GRAM).

[0070] The following explanation will use DDIC as an example, where the display control module is a display controller and GRAM is the image storage unit.

[0071] During image processing, electronic devices can execute image processing steps such as drawing, rendering, and compositing using the CPU and GPU within the SoC. The display driver in the SoC's software architecture sends (writes) the processed image data to the GRAM in the display screen. Finally, the DDIC refreshes the image data in the GRAM onto the display panel, thus enabling image display.

[0072] DDIC can control the writing and reading of image data in GRAM through the Tear Effect (TE) signal.

[0073] See Figure 2 The TE signal can be a periodic pulse signal. When the DDIC completes refreshing one frame of image on the display panel, it can generate a TE signal, triggering the display driver to write the image data of the new frame into the GRAM. For example, the DDIC, when refreshing a frame of image on the display panel... Figure 3 After the image data of the last line M in the GRAM is refreshed (read) to the display panel, the DDIC can generate a TE signal. The display driver detects the rising edge of the TE signal, such as... Figure 2 After TE (up) arrives, it can be Figure 2 During the time period indicated by the "Send Image (short for sending image data from the display driver to the GRAM)" flag X, the image data of a new frame is written into the GRAM.

[0074] Subsequently, after the falling edge of the TE signal arrives, DDIC can refresh the image data of the new frame in the GRAM onto the display panel, allowing the display panel to show the new frame of image. See also... Figure 2 and Figure 3 DDIC from Figure 3 After the last row M in the GRAM returns to the first row N in the GRAM, the falling edge of the TE signal arrives, and the DDIC begins reading the image data of the new frame from the GRAM and refreshing it onto the display panel, as shown in... Figure 2 During the time period marked Y after the arrival of TE (bottom), the image data of the new frame in GRAM is refreshed to the display panel.

[0075] The display panel can be refreshed via a source signal. See also... Figure 2 After the falling edge of the TE signal arrives, the DDIC reads image data from the GRAM. At this time, the source signal generated by the display panel is high. This high level illuminates the corresponding pixels on the display panel based on the image data read by the DDIC, thereby refreshing the image on the display panel. It should be noted that in actual implementation, the DDIC can also read image data from the GRAM before the falling edge of the TE signal arrives, and complete the reading of the entire image data when the falling edge of the TE signal arrives. In this way, the display panel can quickly refresh and display the new image after the falling edge of the TE signal arrives.

[0076] After the refresh is complete, the display panel can pull the source signal low to reduce power consumption when the image is not being refreshed. It should be noted that during the period when the source signal is low, the image will not be refreshed; this state can be called the hold state.

[0077] As can be seen, the TE signal allows control over the process. After a frame refresh is completed, the display driver writes image data to the GRAM based on the rising edge of the TE signal, and the DDIC reads image data from the GRAM based on the falling edge of the TE signal. Furthermore, by controlling the rate at which the display driver writes to the GRAM and the rate at which the DDIC reads from the GRAM, the progress of the DDIC reading from the GRAM is always behind the progress of the display driver writing to the GRAM, thus preventing screen tearing.

[0078] Furthermore, electronic devices can control the image processing rhythm of the SoC (such as CPU, GPU, etc.) through the Vsync signal. It should be noted that the Vsync signal in this article refers to the software Vsync signal simulated by the SoC (such as the surfaceflinger (SF) in the SoC's software architecture) based on the rising edge of the TE signal. The SoC can simulate a Vsync signal that coincides with the rising edge of the TE signal, so that with each arrival of the rising edge of the TE signal, the Vsync signal changes, such as a level transition (including a transition from low to high or from high to low), thereby triggering the start of processing a new frame of image when the TE signal arrives. That is, the Vsync signal can be a clock signal, such as a transition every 8.3ms.

[0079] Therefore, it should be noted that an image goes through three stages from the start of processing to its display on the screen. In the first stage, drawing and rendering begin when the Vsync signal corresponding to the rising edge of a TE signal is triggered. In the second stage, when the Vsync signal corresponding to the rising edge of another TE signal is triggered, compositing and preparation for display begin. Then, in the third stage, when another TE signal is triggered, display is executed, and the processed image is displayed on the screen.

[0080] Furthermore, the processing and display of multiple frames can be as follows: After the rising edge of a TE signal arrives, on the one hand, the drawing and rendering of the (k+1)th frame can begin under the trigger of the corresponding Vsync signal. On the other hand, the synthesis and preparation for display of the kth frame can begin under the trigger of the corresponding Vsync signal. Finally, under the trigger of the rising edge of the TE signal, the display of the (k-1)th frame can begin, and the (k-1)th frame can be displayed on the screen.

[0081] Specifically, the DDIC can generate a TE signal. Triggered by the rising edge of this TE signal, the display driver can write the currently processed image data into the GRAM, such as the image data of the (k-1)th frame mentioned above, to achieve image display. The image compositer can obtain the timestamp corresponding to the rising edge of the TE signal and calculate the time of the rising edge of the next TE signal accordingly. The CPU, GPU, etc., can estimate the timing of starting a new frame image based on this calculated time, such as the timing of drawing and rendering the (k+1)th frame mentioned above, and start drawing and rendering the new frame image after the timing arrives, so that the drawing and rendering of the new frame image can be completed before the arrival of the next TE signal. Furthermore, the CPU, GPU, etc., can also estimate the timing of starting the current frame image based on this calculated time, such as the timing of compositing the kth frame mentioned above, and start compositing the current frame image after the timing arrives, so that the compositing of the current frame image can be completed and the image data of the current frame image can be obtained before the arrival of the next TE signal, and then sent to the display driver. After the arrival of the next TE signal, the display driver can then execute the display.

[0082] In reality, due to factors such as load, image processing modules such as the CPU and GPU may not be able to complete image processing within the estimated time. This may result in the inability to provide new image data to the display driver in a timely manner, which is called processing lag. Furthermore, if the display driver does not receive new image data, it cannot write the new image data into the GRAM, and the display panel can only display the old image data, which results in display lag.

[0083] The following is combined with Figure 4Taking the (k-1)th frame as the 0th frame, the kth frame as the 1st frame, and the (k+1)th frame as the 2nd frame as an example, the specific process of handling stuttering and display stuttering is described:

[0084] After TE2 arrives, the display driver can send the 0th frame image to the screen when triggered by the rising edge of TE2, so that the display screen can display the 0th frame image between TE2 and TE3.

[0085] After TE2 arrives, the image synthesizer can obtain the timestamp corresponding to the rising edge of TE2 and calculate the time of the rising edge of the next TE signal, TE3. The CPU, GPU, etc., can estimate in advance the timing of starting the synthesis of the first frame image (before the rising edge of TE3) based on this time, and start the synthesis of the first frame image after the timing arrives. Furthermore, the synthesis of the first frame image is completed before TE3 arrives.

[0086] Furthermore, the CPU and GPU can predict the timing of starting the drawing and rendering of the second frame based on the rising edge of TE3 (located before the rising edge of TE3), and begin drawing and rendering the second frame after the timing arrives, thus completing the drawing and rendering of the second frame before TE3 arrives. In reality, however, before TE3 arrives, the GPU is still rendering the second frame and has not completed the drawing and rendering of the second frame as expected, resulting in processing lag.

[0087] Next, after TE3 arrives, the display driver can execute the sending of the first frame image under the trigger of the rising edge of TE3, so that the display screen can display the first frame image between TE3 and TE4.

[0088] After TE3 arrives, the image synthesizer can obtain the timestamp corresponding to the rising edge of TE3 and calculate the time of the rising edge of the next TE signal TE4. The CPU, GPU, etc. can estimate the timing of starting the drawing and rendering of the third frame image in advance based on the time of the rising edge of TE4 (located before the rising edge of TE4), and start the drawing and rendering of the third frame image after the timing arrives.

[0089] In addition, since the rendering of the second frame has not been completed after TE3 arrives, the compositing of the second frame will not be triggered after TE3 arrives.

[0090] Then, after TE4 arrives, because the synthesis of the second frame image has not yet been completed (in fact, it has not yet started), the display driver, triggered by the rising edge of TE3, is also unable to send the second frame image for display. Consequently, the display screen will continue to display the first frame image, meaning the first frame image will be displayed continuously for at least two frames. In other words, the processing delay of the second frame image causes the display delay of the first frame image.

[0091] It should be noted that, Figure 4 Taking the display of frame 0 after TE2 as an example, in practice, when the rising edge of TE2 arrives, the display driver can first start writing the image data of frame 0 to the GRAM in the display screen. Then, after the falling edge of TE2 arrives, the DDIC in the display screen can refresh the image data of frame 0 in the GRAM to the display panel. Only then does the display of frame 0 begin. That is, the actual time when the display of frame 0 begins is slightly later than the arrival of the rising edge of TE2. The sending and display of other frames is similar, and will not be elaborated here.

[0092] The above regarding Figure 4 The description mainly shows the process of processing stuttering (such as the second frame image) and display stuttering (such as the first frame image). In reality, when the CPU and GPU experience processing stuttering during the processing of multiple consecutive frames, corresponding continuous display stuttering may occur, making the stuttering problem more prominent.

[0093] To address the aforementioned issues, this application provides an image delivery method that can trigger image delivery by the display driver both when a TE signal arrives and between two TE signals. Thus, after image processing is completed, especially after a processing lag has occurred and image processing is finished, the display driver does not necessarily have to wait for the next TE signal to deliver the image; instead, it can deliver the image before the next TE signal arrives, thereby enabling timely image delivery, reducing display lag, and improving display performance.

[0094] In particular, when there are consecutive frames of processing stuttering, the implementation of this application can greatly reduce display stuttering, and the effect is more obvious.

[0095] For example, the electronic devices in this application embodiment may be mobile phones, tablets, desktop computers, laptop computers, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), artificial intelligence (AI) devices, wearable devices, in-vehicle devices, smart home devices, and / or smart city devices, etc., that have image processing and display requirements. This application embodiment does not impose any special limitations on the specific form of the electronic device.

[0096] See Figure 5 This is a hardware structure diagram of an electronic device. For example... Figure 5As shown, taking a mobile phone as an example, the electronic device may include a processor 210, an external memory interface 220, an internal memory (RAM) 221, a universal serial bus (USB) interface 230, a charging management module 240, a power management module 241, a battery 242, an antenna 1, an antenna 2, a mobile communication module 250, a wireless communication module 260, an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, a sensor module 280, buttons 290, a motor 291, an indicator 292, a camera 293, a display screen 294, and a subscriber identification module (SIM) card interface 295, etc.

[0097] It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on the mobile phone. In other embodiments, the mobile phone may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0098] The processor 210 may include one or more processing units, such as an application processor (AP), a modem, a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), and / or a neural network processing unit (NPU).

[0099] Different processing units can be independent devices or integrated into one or more processors. For example, an AP can integrate a CPU, GPU, etc.

[0100] In some embodiments, the processor 210 can execute an image display method by running instructions stored in the internal memory 221.

[0101] In addition, one or more processing units in the aforementioned processor 210, as well as other components of the mobile phone (such as memory, input / output interfaces, etc.), can be integrated into the SoC.

[0102] The charging management module 240 receives charging input from the charger. The power management module 241 connects the battery 242, the charging management module 240, and the processor 210. The power management module 241 receives input from the battery 242 and / or the charging management module 240, providing power to the processor 210, internal memory 221, display screen 294, camera 293, and wireless communication module 260, etc. The power management module 241 can also monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance).

[0103] The wireless communication function of a mobile phone can be implemented through antenna 1, antenna 2, mobile communication module 250, wireless communication module 260, modem processor, and baseband processor.

[0104] Mobile phones can achieve display functions through GPU, display screen 294, and application processor. The GPU is a microprocessor for image processing, connecting the display screen 294 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering.

[0105] Mobile phones can achieve camera functions through cameras 293, ISP, video codecs, GPU, display panels 294, application processors (AP), neural network processors (NPU), etc.

[0106] Mobile phones can perform audio functions, such as music playback and recording, through an audio module 270, a speaker 270A, a receiver 270B, a microphone 270C, a headphone jack 270D, and an application processor.

[0107] Display screen 294 is used to display images, videos, etc. Display screen 294 includes a display panel. The display panel may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, a mobile phone may include one or more displays screens 294.

[0108] The display screen 294 also includes driving circuitry and a storage unit (such as GRAM, which will be used as an example below). The GRAM can be used to store image data of the image to be displayed.

[0109] For details on the functions and working principles of the display panel, DDIC, and GRAM, please refer to the previous text. Figure 1 and Figure 2 The details and related information will not be elaborated here.

[0110] The display panel can be a low-temperature polycrystalline oxide (LTPO) display panel, a low-temperature polycrystalline silicon (LTPS) display panel, etc.

[0111] Furthermore, based on the different numbers of transistors in the pixel circuits of the LTPO display panel, the display screen 294 can be divided into 7T-LTPO screens and 8T-LTPO screens. 7T means that the pixel circuit includes 7 transistors, and 8T means that the pixel circuit includes 8 transistors.

[0112] See Figure 6 In (a) of the LTPS / 7T-LTPO screen, the DDIC can generate a TE signal of up to 120Hz, so the refresh rate can reach 120Hz, and the image on the display panel can be refreshed once every 8.3ms.

[0113] Of course, the DDIC of the LTPS / 7T-LTPO screen can also generate TE signals below 120Hz (such as 90Hz, 60Hz, etc.).

[0114] For example, the 90Hz TE signal generated by the DDIC in the LTPS / 7T-LTPO screen, such as Figure 6 As shown in (b), the refresh rate can reach 90Hz, and the image on the display panel can be refreshed once every 11.1ms.

[0115] For example, the 60Hz TE signal generated by the DDIC in an LTPS screen... Figure 6 As shown in (c), the refresh rate can reach 60Hz, and the image on the display panel can be refreshed once every 16.6ms.

[0116] Therefore, it should be noted that the duration of the low-level TE signal is the same in the 120Hz TE signal generated by the DDIC in the LTPS / 7T-LTPO screen, the 90Hz TE signal generated by the DDIC in the LTPS / 7T-LTPO screen, and the 60Hz TE signal generated by the DDIC in the LTPS screen. Correspondingly, the lower the frequency and the longer the period, the longer the duration of the high-level signal. Figure 6 In (c), the duration of the high level of the TE signal is > Figure 6 In (b) of the text, the duration of the high level of the TE signal is > Figure 6 The duration of the high level of the TE signal in (a) is shown.

[0117] However, as mentioned above Figure 6 The difference between the 60Hz TE signal generated by the DDIC in the LTPS screen shown in (c) is: Figure 6 As shown in (d), the 60Hz TE signal generated by the DDIC in the 7T-LTPO screen is equivalent to generating one TE signal every other TE signal from the 120Hz TE signal. Therefore, the duration of the low level of the 60Hz TE signal generated by the DDIC in the 7T-LTPO screen is approximately twice the duration of the low level of the 120Hz TE signal generated by the DDIC in the LTPS / 7T-LTPO screen.

[0118] See Figure 6 In section (e), the DDIC in an 8T-LTPO screen can generate a TE signal of up to 360Hz, thus achieving a refresh rate of 360Hz, which means the image on the display panel can be refreshed approximately once every 2.7ms. Of course, the DDIC in an 8T-LTPO screen can also generate TE signals lower than 360Hz (such as 120Hz or 60Hz), and correspondingly, the refresh rate can be lower than 360Hz.

[0119] It should be noted that in an 8T-LTPO screen, compared to a 360Hz TE signal: a 120Hz TE signal is equivalent to generating one TE signal every two TE signals of the 360Hz TE signal. A 60Hz TE signal is equivalent to generating one TE signal every five TE signals of the 360Hz TE signal.

[0120] The image display method provided in this application embodiment can be applied to the above. Figure 6 The various TE signal scenarios shown are illustrated.

[0121] The software system of the aforementioned electronic device (such as the software system on the AP side) can adopt a layered architecture, event-driven architecture, microkernel architecture, microservice architecture, or cloud architecture. This application embodiment uses a layered architecture based on Android. TMTaking a system as an example, this section illustrates the software structure of an electronic device. A layered architecture divides the software system of an electronic device into several layers, each with a clear role and function, and the layers communicate with each other through software interfaces.

[0122] See Figure 7 Taking mobile phones as an example, the software and hardware architecture of electronic devices can include the application layer, application framework layer, hardware abstraction layer (HAL), kernel layer, and hardware layer, etc.

[0123] The application layer can accommodate various applications such as email, video player, memo, alarm clock, settings, and games. When these applications are running in the foreground, the screen can refresh to display multiple frames of images. For example, a game application can display multiple frames of game footage through screen refresh.

[0124] The application framework layer provides the application layer with an application programming interface (API) and a programming framework. The application framework layer may include a surface-flinger (SF). It should be noted that the term "surface-flinger" can also be translated as "surface thrower," "surface drawing module," or "image compositing service," etc., and this application does not specifically limit the terminology used.

[0125] Image compositers can be used for refresh rate control, image compositing control, and more.

[0126] In one specific implementation, as explained above, the image synthesizer can simulate the corresponding Vsync signal based on the TE signal. This Vsync signal can trigger the CPU, GPU, etc. to perform image processing, thereby controlling the frequency of the obtained image data and achieving refresh rate control.

[0127] In one specific implementation, the image compositor, after receiving multiple layers with drawn content, can allocate compositing tasks to either the Hardware Composer (HWC) in the Hardware Abstraction Layer or the GPU. For example, if the compositing task includes tasks such as rounded corner cropping, it can be assigned to the GPU for image compositing; if the compositing task only includes simple layer overlay tasks, it can be assigned to the HWC for image compositing. This allows for control over image compositing.

[0128] The Hardware Abstraction Layer (HWC) runs in user space, encapsulates kernel-level drivers, and provides calling interfaces to higher layers. The HWC can include image compositing and processing, as well as providing the composited image data to the display driver.

[0129] It should be noted that the image data obtained by the GPU in performing image synthesis can also be sent to the display driver via HWC.

[0130] The kernel layer includes drivers that control the hardware, such as the display driver. The display driver can be used to send the synthesized image data to the display screen for display, such as writing image data to RAM and then refreshing it to the display screen in response to the arrival of the TE signal.

[0131] The kernel layer may also include a Display Serial Interface (DSI). DSI can be used for data transmission between the display driver and the display screen, such as transmitting image data.

[0132] The hardware layer may include hardware such as CPU, GPU, and display screen (further including display panel, DDIC, GRAM, etc.).

[0133] Furthermore, image data can be transmitted between the kernel layer and the hardware layer through the Mobile Industry Processor Interface (MIPI).

[0134] At this point, it needs to be clarified that the above... Figure 5 and Figure 7 In the descriptions of electronic devices, the division of hardware and software modules is exemplary and not a limitation in practice. For example, the core display driver function in this article may also be implemented by other modules or merged into other modules.

[0135] The image display method provided in this application can be executed in an electronic device having the above-described hardware structure and software architecture. The image display method of this application embodiment will be further described in detail below with reference to the above-described hardware structure and software architecture.

[0136] Furthermore, in an embodiment where the electronic device decides the image delivery method based on whether there is a processing lag, see... Figure 8 The image display method includes the following steps:

[0137] S801. After power-on, the display driver detects the first identifier, which indicates that the target image transmission scheme is enabled. The target image transmission scheme refers to a scheme in which the display driver can be triggered to transmit images at specific times between two TE signals. In other words, the electronic device can not only transmit images when a TE signal is detected, but also at specific times between two TE signals. It should be noted that the target image transmission scheme can also be called a software high-frequency TE scheme, a software and hardware TE combined scheme, etc., and this application does not specifically limit it to these terms.

[0138] In one specific implementation, a target image delivery scheme is applied to a specific display screen, and a first identifier can be pre-configured in a mobile phone with that specific display screen.

[0139] It should be noted that in an 8T-LTPO screen, during the time the Source signal remains in a hold state (i.e., low level) after image loading, the DDIC can trigger the display driver to send the image in advance based on the 360Hz TE signal and respond to image loading at any time, displaying the new image on the display panel, thereby reducing display stuttering. However, since LTPS / 7T-LTPO screens cannot generate a 360Hz TE signal, nor can they respond to image loading at any time during the time the Source signal remains in a hold state, they cannot reduce display stuttering using the same method as the 8T-LTPO screen. Therefore, the specific display screen mentioned above can be an LTPS / 7T-LTPO screen; that is, a targeted image loading scheme can be applied to LTPS / 7T-LTPO screens to achieve the goal of reducing display stuttering.

[0140] In another specific implementation, a target image delivery scheme is applied to certain models, in which a first identifier can be pre-configured. It should be noted that, even among electronic devices with LTPS / 7T-LTPO screens, some models may be compatible with the target image delivery scheme, while others may not.

[0141] Upon power-on, during initialization, the electronic device can query the first identifier. If the first identifier is found, it indicates that the electronic device has enabled the target image delivery scheme. If the first identifier is not found, it indicates that the electronic device has not enabled the target image delivery scheme.

[0142] Of course, the embodiments of this application are not limited to determining whether to enable the target image sending scheme by querying the first identifier.

[0143] For example, electronic devices can also determine whether to enable the target image delivery scheme by matching a model whitelist. The model whitelist records mobile phone models that have enabled the target image delivery scheme, such as some of the models mentioned above and / or mobile phone models with specific displays. If the current model is in the model whitelist, it indicates that the mobile phone has enabled the target image delivery scheme. If the current model is not in the model whitelist, it indicates that the mobile phone has not enabled the target image delivery scheme.

[0144] Therefore, it should be noted that in actual implementation, the target image transmission scheme can be applied to all mobile phones, or the target image transmission scheme code can be configured only in mobile phones that are compatible with the target image transmission scheme, such as some of the models mentioned above or mobile phones with specific displays. In these embodiments, the electronic device does not need to determine whether the current electronic device has enabled the software high-frequency TE scheme. For example, the above-mentioned S801 can also be omitted.

[0145] When the target image transmission scheme is enabled, the display driver can execute S802-S804 to time the timer, thereby determining a specific moment between two TE signals and executing image transmission. Alternatively, if the target image transmission scheme is not enabled, the electronic device can use a conventional scheme, triggering image transmission upon each TE signal arrival.

[0146] S802 and DDIC generate the TE signal.

[0147] For example, DDIC can periodically generate TE signals. The frequency of the TE signal can be 60Hz, 90Hz, 120Hz, etc., and the corresponding periods are approximately 16.6ms, 11.1ms, and 8.3ms, respectively.

[0148] It should be noted that DDIC can continuously generate TE signals, and its execution timing is not based on... Figure 8 The illustrations shown are for illustrative purposes only. Furthermore, the accompanying figures in this article primarily illustrate at a fixed frequency; in practice, the frequency of the TE signal can vary, such as from 120Hz to 90Hz.

[0149] S803, the display driver detected the arrival of the rising edge of the TE signal.

[0150] Each time the DDIC generates a TE signal, the display driver can detect the arrival of the rising edge of the TE signal. It should be understood that the arrival of the rising edge of the TE signal indicates the arrival of a new TE signal.

[0151] In conventional schemes, when the rising edge of the TE signal arrives, if processed image data is already available, the display driver is triggered to send the image. If no processed image data is available, the display driver will only be triggered to send the image when the next rising edge of the TE signal is detected. However, in this embodiment, the display driver does not trigger image sending upon detecting the rising edge of the TE signal. Instead, after each receipt of image data, the triggering method for image sending is determined based on whether there is a processing bottleneck, and then the image sending is triggered. The triggering methods include sending the image when the rising edge of the TE signal arrives and sending the image at a specific moment between two TE signals. For details, please refer to the descriptions in S812-S817 below, which will not be elaborated further here.

[0152] S804: The display driver initializes the timer for the target image sending scheme, causing the timer to restart.

[0153] The timer can be used to indicate a specific moment. For example, if the timer's timing interval is 2.7ms, then when the timer reaches 2.7ms, it indicates that a specific moment has arrived and a trigger signal can be generated.

[0154] In one specific implementation, a target signal, which is a clock signal, can be generated when the timer's set time expires. This target signal is used to trigger image transmission. When the electronic device detects this target signal, it can then execute image transmission, thereby achieving image transmission at a specific time.

[0155] It should be noted that the target signal can be generated by the display driver or by other modules in the SoC. This application does not make specific limitations on this. In the following text, the target signal generated by the display driver will be used as an example.

[0156] In practical implementation, those skilled in the art can set the timing interval according to actual needs. There can be multiple specific moments between two TE signals, and correspondingly, multiple timing intervals can be set. The interval between timing intervals can be fixed or variable. This article primarily focuses on the case where the interval between timing intervals is fixed. For example, the frequency of the timing interval can be 240Hz, 360Hz, 480Hz, etc. For instance, a timing interval of 360Hz means that the timing interval arrives approximately every 2.7ms. It should be noted that, typically, the frequency of the timing interval is higher than the frequency of the TE signal. This ensures that the timing interval arrives at least once between the arrival times of two TE signals, i.e., at a specific moment, thus enabling timely image transmission.

[0157] It should be noted that multiple specific moments can be set by the timing periods of multiple timers, or multiple specific moments can be set by multiple timing periods of the same timer; this application does not impose specific limitations on this. This document primarily uses the example of multiple timing periods of a single timer for illustration.

[0158] Taking a timer frequency of 360Hz as an example, this indicates that multiple specific moments, including when the timer reaches approximately 2.7ms, 5.5ms, and 8.3ms, are represented.

[0159] It's important to note that the TE signal is generated by the DDIC based on the display's clock, while the timer indicating a specific moment is generated based on the SoC's clock. It should be understood that the display's clock and the SoC's clock differ in frequency, error, and other aspects. Therefore, after each detection of the rising edge of the TE signal, the electronic device can initialize / calibrate the timer, such as resetting it so that it starts counting based on the time of the current detected rising edge of the TE signal. This avoids misalignment between the target signal and the TE signal due to clock differences, further preventing screen flickering.

[0160] Taking a TE signal with a frequency of 120Hz as an example, see... Figure 9 The display driver can initialize the timer when it detects the rising edge of the TE signal approximately every 8.3ms, allowing the timer to start counting from 0. Thus, the timer's timing interval refers to the time interval since the current (most recent) rising edge of the TE signal.

[0161] See also Figure 9 Taking a timer frequency of 360Hz as an example, specific moments include time t1, which is 2.7ms away from the rising edge of the most recently detected TE signal; time t2, which is 5.5ms away from the rising edge of the most recently detected TE signal; and time t0, which is 8.3ms away from the rising edge of the most recently detected TE signal, i.e., the rising edge of the next TE signal.

[0162] It should be noted that after initializing the timer, the timer will continue counting down, and will trigger the generation of the target signal when the set interval is reached. In cases with multiple set intervals, the target signal will be generated at each set interval. For example, the target signal may be generated approximately every 2.7ms.

[0163] In other embodiments, the electronic device may disregard clock differences, thus omitting the aforementioned S804. In this embodiment, the display driver can start a timer when it detects the rising edge of the first TE signal, and the timer can continue counting indefinitely instead of restarting after each rising edge of the TE signal is detected. For example, if the timer counts to 8.3ms before the rising edge of the TE signal arrives, it can continue counting from 8.3ms after the rising edge of the TE signal arrives.

[0164] If the target image sending scheme is determined to be enabled, the processing of one frame of image will still be completed through the following steps S806-S811.

[0165] S806, the Image Synthesizer (SF) sends the Vsync signal to the application.

[0166] For example, the image compositor can simulate a Vsync signal based on the TE signal, and after each Vsync signal arrives, it distributes the Vsync signal to the application that needs to refresh the image, thereby triggering the application to start processing a new frame of image. The application that needs to refresh the image is typically a foreground application.

[0167] For example, if a game application is running in the foreground, the image compositor can send Vsync signals to the game application.

[0168] It should be noted that there can be one or more applications running in the foreground, and the image compositor can distribute Vsync signals to each application.

[0169] S807: In response to the Vsync signal, the application performs drawing processing and then performs rendering processing after drawing is completed, resulting in a layer with content.

[0170] For example, an application can call upon the CPU, GPU, etc. to complete drawing and rendering processes.

[0171] S808: The application sends the layer with the content drawn to it to the image compositor.

[0172] S809, The image synthesizer performs image synthesis to obtain image data.

[0173] For example, an image compositor can assign the compositing task to a GPU or a hardware compositor (HWC) to complete the image compositing process.

[0174] It should be noted that in the above S807-S809, due to factors such as load, the CPU and GPU may not be able to start image processing of a new frame in time, and may not be able to complete image processing in a timely manner.

[0175] S810, the image synthesizer sends image data to the display driver.

[0176] S811, the display driver receives image data.

[0177] After that, the display driver can perform image sending processing.

[0178] Therefore, it should be noted that the execution timing of S802-S804 and S806-S811 is not based on... Figure 8 The above is for illustrative purposes only. In practice, the display driver can execute S802-S804 as soon as it detects the rising edge of the TE signal; after the image synthesizer simulates and distributes the Vsync signal, it can execute S806-S811. There is no absolute order between the two. Typically, the rising edge of the TE signal coincides with the simulated Vsync signal; that is, the moment the display driver detects the rising edge of the TE signal usually coincides with the moment the image synthesizer distributes the Vsync signal.

[0179] After receiving image data, the display driver can determine the triggering method for sending the image through the following S812-S817.

[0180] S812. The display driver checks for processing lag. If yes, proceed to S813; otherwise, proceed to S816.

[0181] Among them, processing stuttering refers to the situation where the time interval between sending two adjacent frames exceeds the preset frame length, which is the frame length corresponding to the applied frame rate. When the refresh rate of the display is consistent with the applied frame rate, such as when the refresh rate is equal to the frame length corresponding to the applied frame rate, which is also equal to the period of the TE signal, the following explanation mainly uses the example of the preset frame length being equal to the period of the TE signal.

[0182] In one specific implementation, the image sending time interval includes the interval between the start time of the previous image sending by the display driver and the time after the display driver receives the image data this time.

[0183] Specifically, if the interval between the start time of the previous image transmission by the display driver and the time after the display driver receives the image data this time exceeds the preset frame length, it indicates that the interval between the two image transmissions is too long, resulting in processing lag. If the interval between the start time of the previous image transmission by the display driver and the time after the display driver receives the image data this time does not exceed the preset frame length, it indicates that the interval between the two image transmissions is appropriate, and there is no processing lag.

[0184] It should be noted that if the current processing obtains image data of the first frame, the start time of the previous image transmission can be understood as the time of the rising edge of the first TE signal. Of course, in some other embodiments, if it is the first frame image, the display driver can also directly trigger the image transmission when the rising edge of the TE signal arrives, that is, S812 and its subsequent steps can be omitted.

[0185] Furthermore, after receiving image data, the display driver can also perform pre-send preparations, such as initializing the hardware image sending registers and initializing the image sending timing. After completing these pre-send preparations, the display driver can execute the image sending. These pre-send preparations will increase the image sending time interval. Therefore, the image sending time interval can specifically include the interval between the start time of the display driver's previous image sending and the time the display driver needs to prepare for the current image sending.

[0186] See Figure 10 In (a), the driver starts sending the image of Figure A at time t3 and completes the preparation work before sending the image of Figure B at time t4. The interval between time t3 and time t4 exceeds the period of the TE signal (abbreviated as TE period in the figure, the same below), so there is a processing lag in the processing of Figure B.

[0187] See Figure 10 In (b), the driver starts sending Figure A at time t5 and completes the preparation work before sending Figure B at time t6. The interval between time t5 and time t6 does not exceed the period of the TE signal, so there is no processing lag in the processing of Figure B.

[0188] It should be noted that the above Figure 10 (a) and Figure 10 (b) in the example assumes that the start time of the previous image transmission (as shown in Figure A) coincides with the rising edge of the TE signal. In practice, the start time of the previous image transmission may not coincide with the rising edge of the TE signal, such as... Figure 10 (c) and Figure 10 As shown in (d) in the figure.

[0189] The above Figure 10 (a) Figure 10 (b) Figure 10 (c) Figure 10 (d) in the examples all assume that the time when the display driver prepares to send the drawing (e.g., completing the preparatory work before sending Figure B) does not coincide with the rising edge of the TE signal. In reality, the time when the display driver prepares to send the drawing may also coincide exactly with the rising edge of the TE signal, such as... Figure 10 (e) and Figure 10 As shown in (f), times t7 and t8 coincide exactly with the rising edge of the TE signal.

[0190] Of course, in actual implementation, the method of detecting processing lag described above is not the only option. For example, the display driver can also detect processing lag based on the interval between the time of the previous received image data and the time of the current received image data. If the interval between the time of the previous received image data and the time of the current received image data exceeds a preset frame length, it indicates that processing lag exists; if the interval between the time of the previous received image data and the time of the current received image data does not exceed the preset frame length, it indicates that processing lag does not exist.

[0191] If there is processing lag, the display driver can use the following S813-S815 trigger diagrams.

[0192] S813. The display driver checks whether the conditions for triggering the image at a specific time are met. If yes, proceed to S814; otherwise, proceed to S815.

[0193] Specifically, the display driver can detect whether the conditions for triggering image transmission at a specific time are met by detecting whether the time from the current moment (e.g., the moment when preparations for image transmission are completed and the image transmission is ready) to the arrival of the rising edge of the TE signal includes a specific moment that does not coincide with the rising edge of the TE signal. It should be noted that the coincidence of the rising edge of the TE signal with the specific moment is only theoretical. Taking the specific moment indicated by a timer as an example, if the frequency of the TE signal is 120Hz and the frequency of the timer's timing interval is 360Hz, then theoretically, the last timing interval within one TE cycle is 8.3ms (e.g., ...). Figure 9 As shown in the time t0, it coincides with the rising edge of the TE signal. As explained above, the clock of the display and the clock of the SoC differ in frequency, error, etc. Therefore, the last timing time of 8.3ms in a TE cycle may deviate from the rising edge of the TE signal.

[0194] If the current time up to the rising edge of the TE signal includes a specific time that does not coincide with the rising edge of the TE signal, it indicates that the pattern can be triggered more timely by the included specific time before the rising edge of the TE signal arrives, thus satisfying the condition of triggering the pattern at the specific time.

[0195] Taking the TE signal frequency of 120Hz and the timing frequency of 360Hz as an example, see [link to example]. Figure 11In (a), the current time is after time t9 and before time t1. The time from the current time to the arrival of the rising edge of the TE signal (denoted as time t10 in the figure) includes three specific times: time t1, time t2, and time t10. Among them, time t1 and time t2 do not coincide with the rising edge of the TE signal, indicating that the image can be triggered in time t1 or time t2 before the arrival of the rising edge of the TE signal, thus satisfying the condition of triggering the image at a specific time.

[0196] See also Figure 11 In (a), if the current time is after time t1 and before time t2, then the time from the current time to time t10 includes two specific times, time t2 and time t10. Here, time t2 does not coincide with the rising edge of the TE signal, indicating that the pattern can be triggered at time t2 before the rising edge of the TE signal arrives, thus satisfying the condition of triggering the pattern at a specific time.

[0197] If the time from the current moment to the arrival of the rising edge of the TE signal does not include a specific moment that does not coincide with the rising edge of the TE signal, it indicates that the map cannot be triggered in time at a specific moment before the arrival of the rising edge of the TE signal, and the condition for triggering the map at a specific moment is not met.

[0198] See also Figure 11 In (a), if the current time is after time t2 and before time t10, then the time from the current time to time t10 includes only one specific time, time t10. Since time t10 coincides with the rising edge of the TE signal, it is impossible to trigger the image more timely at the specific time before the arrival of the TE signal, and the condition of triggering the image at the specific time is not met.

[0199] Furthermore, if the conditions for triggering image transmission at a specific time are met, the display driver can execute S814, thereby enabling more timely image transmission at that specific time. If the conditions for triggering image transmission at a specific time are not met, the display driver can execute S815, thereby enabling image transmission to be performed when the rising edge of the TE signal arrives, avoiding unnecessary power consumption such as detecting target signals.

[0200] S814. When the timer's timing period is detected to have expired, the display driver writes image data into the GRAM.

[0201] In this context, "arriving at a set time" is equivalent to arriving at a specific time.

[0202] See Figure 11 In (b), the current time is t11, which is after time t9 and before time t1. Then the next timing time corresponds to time t1. The display driver can detect the target signal Z1 at time t1, thereby triggering the sending of the image in Figure B.

[0203] See Figure 11 In (c), the current time is t12, which is after time t1 and before time t2. Then the next timing time corresponds to time t2. The display driver can detect the target signal Z2 at time t2, thereby triggering the sending of the image in Figure B.

[0204] It should be noted that if the current time happens to fall within a specific timeframe, the image submission can be performed directly at that specific time. For example, if the current time is... Figure 11 In (a) of the diagram, at time t1, the display driver can detect the target signal at time t1 and trigger the sending of image B. For example, if the current time is... Figure 11 At time t2 in (a), the display driver can detect the target signal at time t2 and trigger the sending of the image in Figure B.

[0205] S815: When the rising edge of the TE signal is detected, the display driver writes image data into the GRAM.

[0206] For example, the display driver can perform image sending, i.e., writing image data into the GRAM, when the rising edge of the next TE signal arrives.

[0207] See Figure 11 In (d), the current time is t13, which is after time t2 and before time t10. The display driver can wait until time t10 to detect the rising edge of the next TE signal, thereby triggering the sending of the image in Figure B.

[0208] It should be noted that if the current time happens to coincide with the arrival of the rising edge of the TE signal, the image transmission can be performed directly at that moment. For example, if the current time is... Figure 11 At time t10 in (a), the display driver can detect the rising edge of the TE signal at time t10, thereby triggering the sending of the image in Figure B.

[0209] Using the S813-S815 described above, in the event of processing lag: On the one hand, if the condition for image delivery at a specific time is met, the display driver can perform image delivery at that specific time, rather than necessarily only when the rising edge of the TE signal is detected, thereby improving the timeliness of image delivery. On the other hand, if the condition for image delivery at a specific time is not met, the display driver will still trigger image delivery when the rising edge of the TE signal is detected, thus ensuring the arrival of the TE signal and facilitating timer initialization.

[0210] Of course, in some other embodiments that do not initialize the timer, in the case of processing lag, the display driver can also directly execute the image sending when the timer timing period (which can be the timing period that coincides with the rising edge of the TE signal) is detected, that is, the above S813-S815 can be omitted.

[0211] If there is no processing lag, the display driver can use the triggering method of the previous image submission (submitting the image when the rising edge of the TE signal arrives or at a specific time). See S816-S817 below for details.

[0212] S816. If the image was triggered when the rising edge of the TE signal arrived last time, the display driver writes image data into the GRAM when the rising edge of the TE signal is detected.

[0213] See Figure 12 In (a), the previous sending of the image in Figure A was performed on the rising edge of the TE signal. The display driver can wait until time t14 to detect the rising edge of the next TE signal, thereby triggering the sending of the image in Figure B.

[0214] It should be noted that if the current time happens to coincide with the arrival of the rising edge of the TE signal, the image transmission can be performed directly at that moment. For example, if the current time is... Figure 12 At time t14 in (a), the display driver can detect the sending of execution diagram B at time t14.

[0215] In addition, the previous triggering of image sending upon the rising edge of the TE signal includes the following two cases: First, there is a processing lag in the processing of the previous frame image (as shown in Figure A), and image sending is triggered by the aforementioned S815 upon the rising edge of the TE signal. Second, there is no processing lag in the processing of the previous frame image (as shown in Figure A), and image sending is triggered by the S816 upon the rising edge of the TE signal.

[0216] S817. If the image was triggered after the timer expired in the previous time, the display driver writes image data to the GRAM after detecting that the timer expired.

[0217] See Figure 12 In (b), the previous timer sent the image of Figure A at a specific time t15 corresponding to the timer's timing period. The display driver can detect the target signal Z3 when the next timer timing period arrives at a specific time t16, thereby triggering the sending of the image of Figure B.

[0218] It should be noted that if the current time is exactly the time when the timer's set timer expires, the image submission can be performed directly at that time. For example, if the current time is... Figure 12 At time t16 in (b), the display driver can detect the target signal at time t16 and trigger the sending of the image in Figure B.

[0219] Similarly, the previous triggering of image sending when the timer expires also includes the following two situations: First, there is a processing lag in the processing of the previous frame image (as shown in Figure A), and the image is triggered by S814 when the timer expires. Second, there is no processing lag in the processing of the previous frame image (as shown in Figure A), and the image is triggered by S817 when the timer expires.

[0220] Using the S816-S817 described above, in the absence of processing lag, the display driver can continue to use the triggering method of the previous image submission, and it is not necessarily required to perform image submission only upon detecting the rising edge of the TE signal, thereby improving the timeliness of image submission. For example, in Figure 12 In (b) of the diagram, after the display driver completes the preparation work before sending the image, it can trigger the image sending at time t16 without waiting for the rising edge of the next TE signal.

[0221] In addition, if there is no processing lag, the display driver continues to use the triggering method of the previous image submission. This can control the time interval of image submission to be consistent with the agreement of the upper layer (such as the image synthesizer SF), and will not submit images when the time interval is less than the agreed time interval, thus avoiding more serious processing lag caused by inconsistency.

[0222] After the aforementioned steps are completed and the display driver sends the image, the image on the display panel can be refreshed and displayed after the falling edge of the TE signal ends, as shown in S818-S819 below:

[0223] S818. After the falling edge of the TE signal ends, the DDIC refreshes the image data in the GRAM to the display panel.

[0224] S819, The display panel displays a new frame of image.

[0225] The following section uses LTPS / 7T-LTPO screens as an example, and combines several specific examples to illustrate the use of... Figure 8 The implementation examples are used to illustrate the effect of reducing display stuttering.

[0226] Example 1

[0227] See Figure 13 The TE signal has a frequency of 120Hz, so its period is approximately 8.3ms. The timer's timing frequency is 360Hz, meaning the timing intervals are 2.7ms, 5.5ms, and 8.3ms after the rising edge of the TE signal. These correspond to the three target signals (including those detected and those not detected) following the rising edge of each TE signal in the diagram. That is, the timing interval can be reached three times within one TE cycle. Furthermore, there are continuous processing stutters from Figures B to D, each lasting 2.7ms.

[0228] It should be noted that, for ease of viewing, the target signal corresponding to 8.3ms does not completely coincide with the rising edge of the TE signal. In practice, they can coincide, as will be discussed below. Figures 14-16 The same principle applies to other signals. It's understandable that undelivered target signals may not be visible in the trace graph. The inclusion of undelivered target signals in the graph is merely for visualizing all target signals generated between two TE signals, and does not imply their visibility in the trace graph. Conversely, delivered target signals are usually visible in the trace graph.

[0229] The following is in accordance with Figure 13 The sequence of steps, from Figure A to Figure E, describes the image submission and refresh display process:

[0230] At time t1, the rising edge of the TE signal arrives.

[0231] On one hand, the display driver can execute the image sending of Figure A, as shown by the image sending mark A in the figure. It should be noted that if Figure A is the first frame image, the display driver can directly determine to execute the image sending of Figure A when the rising edge of the TE signal is detected; if Figure A is not the first frame image, the display driver can also determine to execute the image sending of Figure A when the rising edge of the TE signal is detected through S812-S817.

[0232] On the other hand, the display driver can execute S803-S804 to control the timer to start counting from 0.

[0233] At time t2, the falling edge of the TE signal arrives.

[0234] DDIC refreshes image A to the display panel, as shown by the refresh indicator A1 in the image.

[0235] At time t3, the rising edge of the TE signal arrives.

[0236] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0237] At time t4, the falling edge of the TE signal arrives.

[0238] Since image B processing is not yet complete, and the display driver has not yet sent image B, DDIC can refresh image A to the display panel again, as shown by refresh indicator A2 in the figure. Consequently, the display panel displays image A for two consecutive frames, resulting in display stuttering. In some implementations, even if DDIC does not refresh image A to the display panel again before the display driver sends image B, the display panel can still display image A. It should be noted that whether DDIC refreshes image A depends on the display's implementation logic. Different displays may have different logic; therefore, in some displays, DDIC will refresh image A, while in others, DDIC will not. The processing of other images described below follows the same principle.

[0239] At time t5, the processing of Figure B is completed, such as executing S806-S811 for Figure B.

[0240] The display driver can execute S812 and detects a processing lag.

[0241] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0242] Next, the display driver can execute S814, and at the timer's timing interval of 2.7ms, i.e. time t5, the target signal Z1 is detected, triggering the display driver to execute the image sending of Figure B, as shown by the image sending mark B in the figure.

[0243] At time t6, the rising edge of the TE signal arrives.

[0244] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0245] At time t7, the falling edge of the TE signal arrives.

[0246] DDIC refreshes image B to the display panel, as shown by the refresh icon B in the image.

[0247] At time t8, the processing of graph C is completed, such as executing S806-S811 for graph C.

[0248] The display driver can execute S812 and detects a processing lag.

[0249] Next, the display driver can execute S813 to detect that the conditions for triggering a pattern based on the target signal are met.

[0250] Next, the display driver can execute S814, and at the timer's timing interval of 5.5ms, i.e. time t8, the target signal Z2 is detected, triggering the display driver to execute the image sending of Figure C, as shown by the image sending mark C in the figure.

[0251] At time t9, the rising edge of the TE signal arrives.

[0252] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0253] At time t10, the falling edge of the TE signal arrives.

[0254] DDIC refreshes image C to the display panel, as shown by the refresh indicator C in the image. It can be seen that although there was a processing lag during the processing of image B, image B was not displayed on the display panel for multiple consecutive frames, and no display lag occurred.

[0255] At time t11, the rising edge of the TE signal arrives and the processing of Figure D is completed, such as executing S806-S811 for Figure D.

[0256] After completing the processing of Figure D, the display driver can execute S812 and detects a processing lag.

[0257] Next, the display driver can execute S813, detecting that the conditions for triggering image sending at a specific time are not met.

[0258] Next, the display driver can execute S815, which detects the rising edge of the TE signal at time t11 and triggers the display driver to send the image in Figure D, as shown by the image sending mark D in the figure.

[0259] Furthermore, due to the arrival of the TE signal, on the one hand, the display driver can execute S803-S804 to control the timer to start counting from 0; on the other hand, it can trigger the processing of subsequent images.

[0260] At time t12, the falling edge of the TE signal arrives.

[0261] DDIC refreshes image D to the display panel, as shown by the refresh indicator D in the image. It can be seen that although there was some processing lag during the processing of image C, image C was not displayed on the display panel for multiple consecutive frames, and no display lag occurred.

[0262] At time t13, the rising edge of the TE signal arrives, and the processing of Figure E is completed, such as executing S806-S811 for Figure E.

[0263] After completing the processing of Figure E, the display driver can execute S812 and detects that there is no processing lag.

[0264] Next, the display driver can execute S816, which triggers the display driver to send the image E when the rising edge of the TE signal arrives, i.e., at time t13, as shown by the image sending mark E in the figure.

[0265] Furthermore, due to the arrival of the TE signal, the display driver can execute S803-S804 to control the timer to start counting from 0.

[0266] At time t14, the falling edge of the TE signal arrives.

[0267] DDIC refreshes image E to the display panel, as shown by the refresh indicator E in the image. It can be seen that although there was some processing lag during the processing of image D, image D was not displayed on the display panel for multiple consecutive frames, and no display lag occurred.

[0268] In Example 1 above, processing stuttering occurred in all three frames from Figure B to Figure D. Figure 8 In this embodiment, only two frames of image A are displayed continuously on the display panel, meaning there is only one frame of display stuttering.

[0269] Example 2

[0270] See Figure 14 The TE signal has a frequency of 90Hz, so its period is approximately 11.1ms. The timer's timing frequency is 360Hz, so the timing intervals are 2.7ms, 5.5ms, 8.3ms, and 11.1ms after the rising edge of the TE signal, corresponding to the four target signals (including those that have been transmitted and those that haven't) between the rising edges of each TE signal in the diagram. That is, the timing interval can be reached four times within one TE cycle. Furthermore, there are continuous processing stutters from Figures B to D, each lasting 2.7ms.

[0271] It should be noted that the duration of the low level is the same in both the 120Hz and 90Hz TE signals. However, the 90Hz TE signal has a longer period, and correspondingly, the duration of the high level is longer. For example, Figure 14 The duration of the high level of the TE signal is compared to Figure 13 The high level of the TE signal lasts for a long time.

[0272] The following is in accordance with Figure 14 The sequence of steps, from Figure A to Figure D, describes the image submission and refresh display process:

[0273] At time t1, the rising edge of the TE signal arrives.

[0274] On one hand, the display driver can execute the image sending of Figure A, as shown by the image sending mark A in the figure. Similarly, if Figure A is the first frame image, the display driver can directly determine that the image sending of Figure A will be executed when the rising edge of the TE signal is detected; if Figure A is not the first frame image, the display driver can also determine, through S812-817, that the image sending of Figure A will be executed when the rising edge of the TE signal is detected.

[0275] On the other hand, the display driver can execute S803-S804 to control the timer to start counting from 0.

[0276] At time t2, the falling edge of the TE signal arrives.

[0277] DDIC refreshes image A to the display panel, as shown by the refresh indicator A in the image.

[0278] At time t3, the rising edge of the TE signal arrives.

[0279] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0280] At time t4, the processing of image B is completed, such as executing S806-S811 for image B.

[0281] The display driver can execute S812 and detects a processing lag.

[0282] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0283] Next, the display driver can execute S814, and at the timer's timing interval of 2.7ms, i.e. time t4, the target signal Z1 is detected, triggering the display driver to execute the image sending of Figure B, as shown by the image sending mark B1 in the figure.

[0284] At time t5, the falling edge of the TE signal arrives.

[0285] DDIC can refresh image B to the display panel, as shown by the refresh icon B in the image.

[0286] At time t6, the rising edge of the TE signal arrives.

[0287] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0288] At time t7, the falling edge of the TE signal arrives.

[0289] Since image C has not yet been processed and the display driver has not yet sent image C, DDIC can refresh image B to the display panel again, as shown by refresh indicator B2 in the figure. Consequently, image B is displayed on the display panel for two consecutive frames, resulting in display stuttering.

[0290] At time t8, the processing of image C is completed, such as executing S806-S811 for image C.

[0291] The display driver can execute S812 and detects a processing lag.

[0292] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0293] Next, the display driver can execute S814, and at the timer's timing interval of 5.5ms, i.e. time t8, the target signal Z2 is detected, triggering the display driver to execute the image sending of Figure C, as shown by the image sending mark C in the figure.

[0294] At time t9, the rising edge of the TE signal arrives.

[0295] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0296] At time t10, the falling edge of the TE signal arrives.

[0297] DDIC can refresh image C to the display panel, as shown by the refresh icon C in the image.

[0298] At time t11, the processing of image D is completed, such as after executing S806-S811 for image D.

[0299] The display driver can execute S812 and detects a processing lag.

[0300] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0301] Next, the display driver can execute S814, and at the timer's timing interval of 8.3ms, i.e. time t11, the target signal Z3 is detected, triggering the display driver to execute the image sending of Figure D, as shown by the image sending mark D in the figure.

[0302] At time t12, the rising edge of the TE signal arrives.

[0303] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0304] At time t13, the falling edge of the TE signal arrives.

[0305] DDIC can refresh image D to the display panel, as shown by the refresh indicator D in the image. It can be seen that although there is processing lag during the processing of image C, image C is not displayed on the display panel for multiple consecutive frames, and no display lag occurs.

[0306] In Example 2 above, the processing of Figures B through D all suffers from processing lag. Figure 8 In this embodiment, only two frames of image B are displayed continuously on the display panel, meaning there is only one frame of display stuttering.

[0307] Example 3

[0308] See Figure 15 The TE signal has a frequency of 60Hz, so its period is approximately 16.6ms. The timer's timing frequency is 360Hz, so the timing intervals are 2.7ms, 5.5ms, 8.3ms, 11.1ms, 13.9ms, and 16.6ms after the rising edge of the TE signal, corresponding to the six target signals (including those that have been transmitted and those that haven't) between the rising edges of each TE signal in the diagram. That is, the timing interval can be reached six times within one TE cycle. Furthermore, there are continuous processing stutters from Figures B to D, each lasting 5.4ms.

[0309] It should be noted that the aforementioned Figure 13 and Figure 14 In the example, it could be an LTPS / 7T-LTPO screen. However, Figure 15 This shows an LTPS screen, and the duration of the low level of the 60Hz TE signal in the LTPS screen, compared to... Figure 13 The duration of the low level of the TE signal at 120Hz, Figure 14 The duration of the low level of the 90Hz TE signal is the same. Meanwhile, the 60Hz TE signal has a longer period, and correspondingly, the duration of the high level in the LTPS screen is longer. For example, Figure 15 The duration of the high level of the TE signal is compared to Figure 13 and Figure 14 The high level of the TE signal lasts for a long time.

[0310] The following is in accordance with Figure 15 The sequence of steps, from Figure A to Figure D, describes the image submission and refresh display process:

[0311] At time t1, the rising edge of the TE signal arrives.

[0312] On one hand, the display driver can execute the image sending of Figure A, as shown by the image sending mark A in the figure. Similarly, if Figure A is the first frame image, the display driver can directly determine that the image sending of Figure A will be executed when the rising edge of the TE signal is detected; if Figure A is not the first frame image, the display driver can also determine, through S812-817, that the image sending of Figure A will be executed when the rising edge of the TE signal is detected.

[0313] On the other hand, the display driver can execute S803-S804 to control the timer to start counting from 0.

[0314] At time t2, the falling edge of the TE signal arrives.

[0315] DDIC refreshes image A to the display panel, as shown by the refresh indicator A in the image.

[0316] At time t3, the rising edge of the TE signal arrives.

[0317] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0318] At time t4, the processing of image B is completed, such as executing S806-S811 for image B.

[0319] The display driver can execute S812 and detects a processing lag.

[0320] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0321] Next, the display driver can execute S814, and at the timer's timing interval of 5.5ms, i.e. time t4, the target signal Z1 is detected, triggering the display driver to execute the image sending of Figure B, as shown by the image sending mark B in the figure.

[0322] At time t5, the falling edge of the TE signal arrives.

[0323] DDIC can refresh image B to the display panel, as shown by the refresh indicator B1 in the image.

[0324] At time t6, the rising edge of the TE signal arrives.

[0325] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0326] At time t7, the falling edge of the TE signal arrives.

[0327] Since image C has not yet been processed and the display driver has not yet sent image C, DDIC can refresh image B to the display panel again, as shown by refresh indicator B2 in the figure. Consequently, image B is displayed on the display panel for two consecutive frames, resulting in display stuttering.

[0328] At time t8, the processing of image C is completed, such as executing S806-S811 for image C.

[0329] The display driver can execute S812 and detects a processing lag.

[0330] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0331] Next, the display driver can execute S814, and at the timer's timing interval of 11.1ms, i.e. time t8, the target signal Z2 is detected, triggering the display driver to execute the image sending of Figure C, as shown by the image sending mark C in the figure.

[0332] At time t9, the rising edge of the TE signal arrives.

[0333] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0334] At time t10, the falling edge of the TE signal arrives.

[0335] DDIC can refresh image C to the display panel, as shown by the refresh icon C in the image.

[0336] At time t11, the rising edge of the TE signal arrives, completing the processing of image D, such as executing S806-S811 for image D.

[0337] The display driver can execute S812 and detects a processing lag.

[0338] Next, the display driver can execute S813, detecting that the conditions for triggering image sending at a specific time are not met.

[0339] Next, the display driver can execute S814, which triggers the display driver to send the image D when the rising edge of the TE signal arrives, i.e., at time t11, as shown by the image sending mark D in the figure.

[0340] At time t12, the falling edge of the TE signal arrives.

[0341] DDIC can refresh image D to the display panel, as shown by the refresh indicator D in the image. It can be seen that although there is processing lag during the processing of image C, image C is not displayed on the display panel for multiple consecutive frames, and no display lag occurs.

[0342] In Example 3 above, the processing of Figures B through D all suffers from processing lag. Figure 8 In this embodiment, only two frames of image B are displayed continuously on the display panel, meaning there is only one frame of display stuttering.

[0343] Example 4

[0344] Related to the previous text Figure 15 The difference is: See Figure 16 Figures B and C both exhibit processing lag, with lag durations of 2.7ms in Figure B and 5.4ms in Figure C. Furthermore, Figure 16 The image shown is of a 7T-LTPO screen. In a 7T-LTPO screen, the 60Hz TE signal is essentially the TE signal that is the last one in every two TE signals in the 120Hz TE signal, which is omitted. In other words, the low-level duration of the 60Hz TE signal in a 7T-LTPO screen is longer, approximately twice that of the low-level duration of the 120Hz TE signal.

[0345] The following is in accordance with Figure 16 The sequence of steps, from Figure A to Figure C, describes the image submission and refresh display process:

[0346] At time t1, the rising edge of the TE signal arrives.

[0347] On one hand, the display driver can execute the image sending of Figure A, as shown by the image sending mark A in the figure. Similarly, if Figure A is the first frame image, the display driver can directly determine that the image sending of Figure A will be executed when the rising edge of the TE signal is detected; if Figure A is not the first frame image, the display driver can also determine, through S812-817, that the image sending of Figure A will be executed when the rising edge of the TE signal is detected.

[0348] On the other hand, the display driver can execute S803-S804 to control the timer to start counting from 0.

[0349] At time t2, the falling edge of the TE signal arrives.

[0350] DDIC refreshes image A to the display panel, as shown by the refresh indicator A1 in the image.

[0351] At time t3, the rising edge of the TE signal arrives.

[0352] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0353] At time t4, the falling edge of the TE signal arrives.

[0354] Since the processing of image B has not yet been completed, and the display driver has not yet executed the image sending of image B, DDIC can refresh image A to the display panel again, as shown by the refresh indicator A2 in the figure. Consequently, the display panel displays image A for two consecutive frames, resulting in display stuttering.

[0355] At time t5, the processing of image B is completed, such as executing S806-S811 for image B.

[0356] The display driver can execute S812 and detects a processing lag.

[0357] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0358] Next, the display driver can execute S814, and at the timer's timing interval of 2.7ms, i.e. time t5, the target signal Z1 is detected, triggering the display driver to execute the image sending of Figure B, as shown by the image sending mark B in the figure.

[0359] At time t6, the rising edge of the TE signal arrives.

[0360] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0361] At time t7, the falling edge of the TE signal arrives.

[0362] DDIC can refresh image B to the display panel, as shown by the refresh icon B in the image.

[0363] At time t8, the processing of image C is completed, such as executing S806-S811 for image C.

[0364] The display driver can execute S812 and detects a processing lag.

[0365] Next, the display driver can execute S813 to detect that the conditions for triggering a graphic at a specific time are met.

[0366] Next, the display driver can execute S814, and at the timer's timing interval of 8.3ms, i.e. time t8, the target signal Z2 is detected, triggering the display driver to execute the image sending of Figure C, as shown by the image sending mark C in the figure.

[0367] At time t9, the rising edge of the TE signal arrives.

[0368] The display driver can execute S803-S804 to control the timer to start counting from 0.

[0369] At time t10, the falling edge of the TE signal arrives.

[0370] DDIC can refresh image C to the display panel, as shown by the refresh indicator C in the image. It can be seen that although there is some processing lag during the processing of image C, image C is not displayed on the display panel for multiple consecutive frames, and there is no display lag.

[0371] In Example 4 above, the processing of Figures B and C both experience processing lag. Figure 8 In this embodiment, only two frames of image A are displayed continuously on the display panel, meaning there is only one frame of display stuttering.

[0372] It should be understood that in Examples 1 to 4 above, the processing time of each image (such as Figure B and Figure C) coincides exactly with the rising edge of the TE signal or the timing of the timer. In actual implementation, however, they may not coincide. If they do not coincide, the display driver can send the image at the next rising edge of the TE signal or the next timing of the timer.

[0373] As can be seen from the above examples, by combining the TE signal and the target signal to trigger the image sending scheme, the display driver can not only send the image when the rising edge of the TE signal is detected, but also at a specific moment between the rising edges of two TE signals. By increasing the timing of image sending, display stuttering is reduced.

[0374] Extensive testing has shown that if each processing delay is within 2.77ms, theoretically, display lag can be reduced by 2 / 3 in a 120Hz scene, by 3 / 4 in a 90Hz scene, and by 5 / 6 in a 60Hz scene.

[0375] Furthermore, in scenarios with continuous processing stuttering, the screen will not continuously refresh repeated image frames, thus saving power. For example, in Example 1 above, if there is stuttering between images B and D, only two frames of image A or B will be repeatedly refreshed on the screen, instead of images B, C, and D being repeatedly refreshed, thus saving power.

[0376] In other words, for some images to be displayed, after obtaining the image data, the display driver can execute image delivery when the TE signal arrives. For other images to be displayed, after obtaining the image data, the display driver can execute image delivery when a specific time arrives.

[0377] Furthermore, if processing lag occurs and the conditions for image transmission at a specific time are not met, image transmission will be performed upon the arrival of the TE signal. This allows image transmission to be performed even when timely transmission at a specific time is not possible. Alternatively, if there is no processing lag and the previous image transmission occurred upon the arrival of the TE signal, image transmission will be performed upon the arrival of the TE signal. This allows control over the image transmission time interval.

[0378] Furthermore, if processing lag exists and the condition of sending images at a specific time is met, then image sending will be performed when the specific time arrives. This ensures timely image sending at the designated time. Alternatively, if there is no processing lag and the previous image was sent at a specific time, then image sending will be performed at the specified time. This allows control over the image sending time interval.

[0379] Furthermore, the display driver can perform image transmission upon detecting a target signal, which is generated at a specific time. Thus, the display driver can accurately trigger image transmission at a specific moment based on the target signal.

[0380] Furthermore, the display driver can generate target signals at various specific times. Simultaneously, when image transmission needs to be performed at a specific time, the display driver activates a specific image transmission switch (equivalent to activating target signal detection). This ensures that in scenarios requiring image transmission at a specific time, the target signal is detected, triggering image transmission.

[0381] In one specific implementation, a specific time can be indicated by the timing of a timer, and correspondingly, a target signal can be triggered when the timer's timing expires.

[0382] In addition, after the target signal is detected and the image is sent, the display driver can also enable the TE signal to send the image (which is equivalent to turning off the target signal detection), thereby avoiding the detection of the target signal and the triggering of image sending in scenarios where image sending is not required at a specific time.

[0383] Finally, it should be noted that, from the preceding text... Figure 7 In the initial embodiments, the electronic device only detects the target signal and triggers image transmission when the condition of image transmission before the arrival of the TE signal is met. However, in actual implementation, this is not a limitation. For example, the electronic device can also continuously detect the target signal and the TE signal, and after each acquisition of image data, trigger image transmission by the next detected target signal or TE signal. In this way, timely image transmission can be achieved even without detecting whether the condition of image transmission before the arrival of the TE signal is met.

[0384] With the TE signal frequency at 120Hz and the timer's timing frequency at 360Hz, the electronic device can switch to detecting the target signal after each rising edge of the TE signal, and switch back to detecting the TE signal after detecting two target signals. In this way, the target signal and the TE signal detected by the electronic device are as follows: Figure 17 As shown. The electronic device acquires Figure A between time t1 and time t2. If the rising edge of the TE signal is detected at time t2, the transmission of Figure A can be performed at time t2. Next, the electronic device acquires Figure B between time t3 and time t4. If the target signal is detected at time t4, the transmission of Figure B can be performed at time t4, without waiting for the next rising edge of the TE signal, thus improving the timeliness of transmission. Then, the electronic device acquires Figure C between time t5 and time t6. If the target signal is detected at time t6, the transmission of Figure C can be performed at time t6, again without waiting for the next rising edge of the TE signal, further improving the timeliness of transmission.

[0385] This application also provides an electronic device, which may include a memory and one or more processors (such as a CPU, GPU, NPU, etc.). The memory and processor are coupled. The memory is used to store computer program code, which includes computer instructions. When the processor executes the computer instructions, the electronic device can perform various functions or steps performed by the device in the above method embodiments.

[0386] This application also provides a chip system, such as... Figure 18As shown, the chip system 1800 includes at least one processor 1801 and at least one interface circuit 1802. The processor 1801 and the interface circuit 1802 are interconnected via lines. For example, the interface circuit 1802 can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit 1802 can be used to send signals to other devices (e.g., the processor 1801). Exemplarily, the interface circuit 1802 can read instructions stored in memory and send those instructions to the processor 1801. When the instructions are executed by the processor 1801, the electronic device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, which are not specifically limited in this application embodiment.

[0387] This application also provides a chip system including at least one processor and at least one interface circuit. The processor and the interface circuit are interconnected via lines. For example, the interface circuit can be used to receive signals from other devices (e.g., the memory of an electronic device). As another example, the interface circuit can be used to send signals to other devices (e.g., the processor). Exemplarily, the interface circuit can read instructions stored in the memory and send the instructions to the processor. When the instructions are executed by the processor, the electronic device can perform the steps in the above embodiments. Of course, the chip system may also include other discrete devices, and this application does not specifically limit this.

[0388] This embodiment also provides a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned method steps to implement the image processing method described above.

[0389] This embodiment also provides a computer program product that, when run on a computer, causes the computer to perform the aforementioned steps to implement the image processing method described above.

[0390] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the image processing methods in the above-described method embodiments.

[0391] In this embodiment, the electronic device, computer storage medium, computer program product or chip are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects of the corresponding method provided above, and will not be repeated here.

[0392] Through the above description of the embodiments, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0393] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0394] The unit described as a separate component may or may not be physically separate. The component shown as a unit can be one physical unit or multiple physical units, that is, it can be located in one place or distributed in multiple different places. Some or all of the units can be selected to achieve the purpose of the solution in this embodiment according to actual needs.

[0395] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0396] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0397] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. An image display method, characterized in that, Applied to an electronic device, the electronic device including a SoC and a display, the electronic device generating a hardware TE signal in a first cycle, the method includes: At a first moment, the electronic device generates a first hardware TE signal, and in response to the first hardware TE signal, the SoC sends first image data to the display screen; At a second moment, the electronic device generates a second hardware TE signal, wherein the second moment is after the first moment, and the second hardware TE signal is the next hardware TE signal after the first hardware TE signal; At the third moment, the electronic device generates a first software TE signal. In response to the first software TE signal, the SoC sends second image data to the display screen. The third moment is after the second moment, and the second image data is the next frame of image data after the first image data. At the fourth moment, the electronic device generates a third hardware TE signal, wherein the third moment is after the second moment, and the third hardware TE signal is the next hardware TE signal after the second hardware TE signal.

2. The method according to claim 1, characterized in that, The method further includes: After the first moment, the electronic device displays the first image data on the display screen.

3. The method according to claim 1 or 2, characterized in that, The method further includes: After the fourth moment, the electronic device displays the second image data on the display screen.

4. The method according to any one of claims 1-3, characterized in that, During the second and fourth time points, the SoC does not send image data to the display screen.

5. The method according to any one of claims 1-4, characterized in that, After the electronic device generates a third hardware TE signal, the method further includes: At the seventh moment, the electronic device generates a second software TE signal, and in response to the second software TE signal, the SoC sends third image data to the display screen; The third image data is the image data of the next frame after the second image data.

6. The method according to claim 5, characterized in that, After the SoC sends third image data to the display screen in response to the second software TE signal, the method further includes: At the eighth moment, the electronic device generates a fourth hardware TE signal; The fourth hardware TE signal is the next hardware TE signal after the third hardware TE signal.

7. The method according to claim 6, characterized in that, The method further includes: After the eighth moment, the electronic device displays the third image data on the display screen.

8. The method according to claim 6 or 7, characterized in that, At the eighth moment, the SoC does not send image data to the display screen.

9. The method according to any one of claims 1-8, characterized in that, At the fourth moment, after the electronic device generates the third hardware TE signal, the method further includes: At the tenth moment, the electronic device generates a fifth hardware TE signal, and in response to the fifth hardware TE signal, the SoC sends fourth image data to the display screen.

10. The method according to claim 9, characterized in that, The method further includes: After the tenth moment, the electronic device displays the fourth image data on the display screen.

11. The method according to claim 9 or 10, characterized in that, After the SoC sends fourth image data to the display screen in response to the fifth hardware TE signal, the method further includes: At the twelfth moment, the electronic device generates a sixth hardware TE signal, and in response to the sixth hardware TE signal, the SoC sends fifth image data to the display screen; Wherein, the fifth image data is the next frame of image data after the fourth image data, and the sixth hardware TE signal is the next hardware TE signal after the fifth hardware TE signal.

12. The method according to claim 11, characterized in that, The method further includes: After the twelfth moment, the electronic device displays the fifth image data on the display screen.

13. The method according to any one of claims 1-12, characterized in that, Before the electronic device generates the first software TE signal at the third time, the method further includes: After obtaining the second image data, the SoC detects whether the conditions for triggering image generation based on software TE signals are met; In response to the first software TE signal, the SoC sends second image data to the display screen, including: When the conditions for triggering image transmission based on the software TE signal are met, the SoC sends second image data to the display screen in response to the first software TE signal.

14. The method according to claim 13, characterized in that, The conditions for triggering the image based on the software TE signal include: The time interval between the last time image data was sent to the display screen and the thirteenth time when the SoC prepares to send the second image data to the display screen exceeds a preset frame length, and the period between the thirteenth time and the time of generating the next TE signal includes the time when the software TE signal is generated; or, The time interval between the last time image data was sent to the display screen and the thirteenth time when the SoC was preparing to send the second image data to the display screen did not exceed the preset frame length, and the last time image data was sent to the display screen based on the software TE signal.

15. An electronic device, characterized in that, include: A display screen, one or more processors, and one or more memories; the one or more processors are coupled to the display screen and the one or more memories; the one or more memories are used to store computer program code, the computer program code including computer instructions, which, when executed by the one or more processors, cause the electronic device to perform the method as described in any one of claims 1-14.

16. A chip system, characterized in that, The chip system is applied to an electronic device, the chip system including one or more processors, the processors being configured to invoke computer instructions to cause the electronic device to perform the method as described in any one of claims 1-14.

17. A computer-readable storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed on an electronic device, the electronic device causes the electronic device to perform the method as described in any one of claims 1-14.

18. A computer program product comprising computer instructions, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method as described in any one of claims 1-14.

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