Chip testing method and electronic equipment
By extracting application protocol data unit sequences from the benchmark card to generate test scripts, data interaction testing can be performed directly without bypassing the chip core. This solves the problems of long testing time and inaccurate data in existing technologies, and achieves efficient and accurate hardware performance evaluation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, chip testing requires burning a complete trading program, which is time-consuming and results in inaccurate data, leading to low testing efficiency, strong dependence, waste of resources, and high barriers to entry.
The application protocol data unit sequence is extracted from the benchmark card to generate a test script, bypassing the chip core to directly test the data interaction process, and the chip hardware performance is evaluated using the interaction time threshold.
It improves testing efficiency, reduces testing costs, simplifies the testing process, enables rapid and accurate evaluation of chip hardware performance, and reduces resource waste and dependence.
Smart Images
Figure CN121807635A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of hardware testing, and more particularly to a chip testing method and electronic device. Background Technology
[0002] Testing chips in payment devices needs to meet processing time requirements. However, related technologies require burning a complete transaction program before the testing process can be completed, which is time-consuming and the data is inaccurate. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a chip testing method and electronic device to improve testing efficiency.
[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A chip testing method, applied to electronic devices, the method comprising: Extract the application protocol data unit sequence from the benchmark card, which includes a test card whose chip has passed the target test; Obtain the interaction time threshold, and generate a test script based on the application protocol data unit sequence and the interaction time threshold; The test script is input into the chip to be predicted to instruct the chip to perform the test.
[0005] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows: An electronic device includes a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the various steps of the chip testing method described above.
[0006] The beneficial effects of this invention are as follows: In the complete process of chip data processing, the time consumed by data interaction accounts for the majority, while the processing time of the chip core typically accounts for only a small portion. Therefore, by obtaining the application protocol data unit sequence from a benchmark card capable of executing the complete test process and having passed the target test, the time consumption of the data interaction process can be tested independently, bypassing the core processing. This eliminates the need for complete chip core development followed by overall chip testing, reducing testing costs and omitting the core testing process, thereby improving testing efficiency. Attached Figure Description
[0007] Figure 1 This is a schematic diagram illustrating the support required for implementing chip testing methods in related technologies. Figure 2 This is a schematic diagram illustrating the support required for a chip testing method provided in an embodiment of the present invention; Figure 3 A flowchart illustrating the steps of a chip testing method provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the implementation steps of a chip testing method in a specific scenario, as provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0008] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0009] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0010] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.
[0011] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0012] In the development phase of payment chips, it is crucial to quickly and independently assess whether the hardware performance of the payment chip meets the requirements of relevant specifications. For example, the development of contactless chips requires determining whether they can meet the Level 2 (compliance verification of financial payment functions for terminal debit / credit application kernels) testing requirements of the EMVCo organization (the international organization responsible for managing EMV standards) to achieve Level 2 certification. Performance testing is one of the core components of L2 testing, requiring the chip to complete data interaction with the terminal within a specified, extremely short time.
[0013] Traditional performance evaluation methods in related technologies mainly include: 1. Setting up a complete L2 test environment: This requires burning a complete kernel program that supports EMV (Contactless Payment Card Standard) transaction processes onto the chip. 2. Preparing a complete set of test cards: This requires obtaining various test cards specified by the EMVCo organization. 3. Relying on multi-party collaboration: This requires the joint participation of software engineers (responsible for the kernel program), test engineers, and hardware engineers, resulting in a complex process and high coordination costs. (Refer to...) Figure 1 It provides the architecture diagram required for chip testing in related technologies. In order to complete the underlying interaction, it is necessary to first port the EMV kernel and burn an application that supports the EMV transaction process. It is also necessary to set up a special time-tracking tool to record the execution time of instructions. At the same time, it is necessary to configure a complete set of cards for testing to obtain the test results of various test cards. This process requires the collaboration of multiple personnel, including hardware personnel, driver personnel, EMV developers, testers, etc. The preliminary preparations required for testing are complex.
[0014] It is evident that the performance testing process in related technologies suffers from the following problems: 1. Inefficiency: Each evaluation requires the deployment of a complete software and hardware environment, resulting in cumbersome preparation and a long testing cycle. 2. Strong Dependency: It heavily relies on the maturity of the EMV kernel software. If the kernel software itself has logical defects or performance issues, it will interfere with the accurate assessment of the chip's hardware performance, making problem localization difficult. 3. Waste of Resources: In the early stages of chip selection, it may only be necessary to focus on its underlying RF performance and instruction processing speed, while a complete EMV kernel is not essential at this stage, leading to excessive resource investment. 4. High Barrier to Entry: It requires specialized Level 2 testing knowledge and expensive testing equipment and cards, which is not conducive to rapid and frequent iterative verification.
[0015] To address the aforementioned problems, this application provides a chip testing method and an electronic device. The chip testing method of this application is described in detail below.
[0016] The chip testing method in this application can be used in scenarios involving chip performance testing, particularly for payment chips. Please refer to... Figure 2This application involves testing the chip to be predicted. The chip testing method of this invention is described in detail below, with reference to the appendix. Figure 3 This includes steps 110-140.
[0017] Step 110: Extract the application protocol data unit sequence from the benchmark card, which includes a test card for which the chip has passed the target test.
[0018] The Application Protocol Data Unit (APDU) sequence is a standardized protocol format for data exchange between smart cards and readers. It defines the unified rules for the reader to send commands to the smart card and for the smart card to return results to the reader. An interaction is completed when the reader sends a command from the APDU sequence to the smart card and receives a response from the smart card. To improve testing efficiency, key APDU sequences can be selected from all APDU sequences. This can be done by pre-setting key APDU sequences, directly setting Get Processing Options (GPOs) within the APDU sequence as key APDU sequences, or determining key APDU sequences based on the read records of a benchmark card. GPOs include key command APDU instructions, which typically include retrieving supported transaction types, security verification requirements, card application version information, transaction limits, and transaction currency types.
[0019] Step 120: Obtain the interaction time threshold and generate a test script based on the application protocol data unit sequence and the interaction time threshold. Specifically, the interaction time threshold and the application protocol data unit sequence are encapsulated into independent, executable test scripts.
[0020] Step 130: Input the test script into the chip to be predicted to instruct the chip to perform the test.
[0021] In this way, the application protocol data unit sequence is obtained from the benchmark card that can execute the complete test process and has passed the target test. This allows for time-based testing of the data interaction process without going through the kernel processing. This eliminates the need to complete the chip kernel development and then perform overall chip testing, reducing testing costs and omitting the kernel testing process, thereby improving testing efficiency.
[0022] In one embodiment of this application, step 130, which involves inputting the test script into the chip to be predicted, includes step 1301.
[0023] Step 1301: Input the test script into the underlying firmware of the chip to be predicted, so as to instruct the underlying firmware to send the instructions in the application protocol data unit sequence to the contactless communication module of the chip to be predicted in sequence.
[0024] In this way, even before the chip kernel is fully developed, the test script can be directly input into the underlying firmware of the chip to be predicted. This allows the application protocol data unit sequence to be sent directly to the contactless communication module of the chip to complete the testing process without going through the chip kernel. The testing process no longer relies on the chip kernel's processing. In related technologies, the underlying layer requires a kernel program to complete the testing process. However, this application, by directly inputting the test script into the underlying firmware for execution, isolates the underlying testing process and uses APDUs obtained from the benchmark card for testing. This eliminates the need to build a kernel, solving the problem in related technologies where testing the underlying layer requires porting and compiling the kernel before testing, reducing testing costs, and eliminating the need for a complete kernel development process on the chip to be predicted.
[0025] In one embodiment of this application, obtaining the interaction time threshold in step 120 includes step 121.
[0026] Step 121: Obtain the test time threshold that needs to be met in the test conditions of the target test corresponding to the chip under test, and obtain the interaction time threshold by subtracting the kernel processing time from the test time threshold.
[0027] For example, if the test time threshold required in the target test is 100ms, and the kernel processing time is 10ms, then the interaction time threshold is 100-10=90ms, which means that the execution of the APDU needs to be completed within 90ms. In other words, if the test time threshold of 100ms is required to be met, the execution time of the underlying APDU needs to be within 90ms. This isolates the kernel testing process and allows for independent judgment of the chip's hardware performance.
[0028] In this way, to ensure the accuracy of the test results, the kernel processing time is also deducted from the test time threshold while bypassing the kernel test. The interaction time threshold used for test comparison is obtained, and the test results can be directly compared with the interaction time threshold. In this way, as long as the interaction time of transmitting the application protocol data unit sequence meets the interaction time threshold, it can be confirmed that the chip's hardware performance is normal. If the requirements are not met when the kernel is tested later, it can be located that the kernel program configuration is incorrect, which makes it easier to locate the specific part of the problem when the test conditions are not met.
[0029] In one embodiment of this application, step 130, which involves inputting the test script into the chip to be predicted, further includes steps 1302 to 1303.
[0030] Step 1302: Input the test script into the chip to be predicted to instruct the chip to perform the interaction process according to the application protocol data unit sequence and record the interaction duration.
[0031] Step 1303: Obtain the test results based on the interaction duration and the interaction time threshold.
[0032] In this way, the test script includes an application protocol data unit sequence, which instructs the chip under test to execute the interaction process according to the application protocol data unit sequence and record the interaction duration. The test result can then be obtained by comparing the interaction duration with an interaction time threshold, completing the test of the interaction process and determining whether the chip's hardware performance meets the test requirements. Alternatively, if the interaction time threshold is sent to the test script, the test chip can directly output the test result or send back the statistically obtained interaction duration. The test platform then obtains the test result based on the comparison between the received interaction duration and the interaction time threshold.
[0033] In one embodiment of this application, step 110, which involves extracting the application protocol data unit sequence from the base card, includes step 111.
[0034] Step 111: Extract the application protocol data unit sequence generated by the base card during contactless transactions from the base card.
[0035] In this way, the benchmark card first performs contactless transactions, and during the process of the benchmark card performing contactless transactions, the generated application protocol data unit sequence is obtained. That is, the benchmark card, which can complete the entire payment process, obtains the application protocol data unit sequence that is only related to the interaction process, without caring about the core transaction process of the chip in the benchmark card. Furthermore, since the benchmark card is a test card that has passed the target test, it can be ensured that the protocol data unit sequence it obtains is correct and feasible, thereby ensuring the accuracy of the test results of the chip to be predicted.
[0036] In one embodiment of this application, step 130, which involves inputting the test script into the chip to be predicted, includes step 1304.
[0037] Step 1304: Input the test script into the test program; the test program, through the underlying driver, sends the instructions in the application protocol data unit sequence to the contactless communication module of the chip to be predicted in sequence. The test program can bypass the complete EMV kernel state machine and directly send the instructions in the application protocol data unit sequence to the contactless communication module of the chip to be predicted through the underlying driver.
[0038] In this way, a test script is executed through a dedicated test program, enabling the interaction process to be completed by sending instructions in the protocol data unit sequence to the contactless communication module of the chip under test through the underlying driver; the test script is run by the test program, realizing the automated execution of the test.
[0039] In one embodiment of this application, step 130, which involves inputting the test script into the chip to be predicted, includes step 1305.
[0040] Step 1305: Input the test script into the chip to be predicted, so as to instruct the contactless communication module in the chip to execute the instructions in the application protocol data unit sequence one by one, and record the interaction time from the sending of the first instruction to the completion of the reception of the last instruction.
[0041] In this way, the chip to be predicted executes the test script, in which the instructions in the application protocol data unit sequence of the contactless communication module are executed one by one, and the interaction time from the start of the first instruction to the completion of the response to the last instruction is recorded. This avoids statistical omissions of the interaction time, thereby ensuring the accuracy of subsequent comparison with the interaction time threshold and guaranteeing the accuracy of the final test results.
[0042] In one embodiment of this application, step 1303 includes steps 1331 to 1332.
[0043] Step 1331: If the interaction duration is less than or equal to the interaction time threshold, the chip to be predicted is indicated as having passed the test.
[0044] Step 1332: Otherwise, a message will appear indicating that the chip to be predicted failed the test.
[0045] In this way, the test result of the chip to be predicted is determined by comparing the interaction duration with the interaction time threshold. It can be seen that the higher the chip performance, the faster the instruction execution speed and the less time is consumed. Therefore, if the interaction duration is less than or equal to the interaction time threshold, the chip performance of the chip to be predicted is considered to have passed the test. Conversely, if the interaction duration is greater than the interaction time threshold, the chip performance is considered to have failed the test. The chip hardware performance test of the chip to be predicted is transformed into a test of instruction processing time, thereby realizing the quantification of hardware performance.
[0046] In one embodiment of this application, step 101 is also included.
[0047] Step 101: Obtain the EMV LEVEL2 test as the target test.
[0048] By using EMV LEVEL2 testing as the target test, the contactless card chip can be tested to meet the corresponding testing requirements. This determines whether the subsequent development process can proceed normally, reduces testing costs, and also allows for the timely detection of chip problems, thereby reducing production costs and avoiding the need to continue developing chips with insufficient hardware performance.
[0049] In summary, the chip testing method provided in this application extracts application protocol data unit sequences from a benchmark card that has already undergone target testing, generates test scripts based on these sequences, and directly performs the interaction process through the application protocol data unit sequences. This bypasses the chip's kernel processing, thus eliminating the software dependency of the testing process. Eliminating the chip kernel processing also accelerates test execution and improves testing efficiency. Furthermore, it enables hardware performance testing without requiring complete chip development, reducing testing costs, facilitating problem localization, and allowing for independent evaluation of the chip's hardware performance. The implementation of this method does not rely on a complete chip kernel; instead, it directly and quickly evaluates whether the chip's underlying hardware performance meets the performance requirements of the target test by simulating the core transaction instruction flow.
[0050] The following details the application embodiments of this application. This application can apply the above solution to the testing process of contactless chips. Here, EMV Level 2 (L2) testing is used as an example. Please refer to... Figure 4 This includes the following steps 1 to 4.
[0051] Step 1, Benchmark Data Extraction Stage: From one or more representative EMV benchmark cards known to pass L2 performance testing, extract the key application protocol data unit sequence (APDU) during contactless transactions with the terminal. This key APDU sequence represents the most critical and time-consuming instruction interaction process in the L2 performance test. This is equivalent to Step 110 above.
[0052] Step 2, Test Script Generation Stage: The extracted APDU sequence is encapsulated with a predefined interaction time threshold to generate an independent, executable test script. The interaction time threshold is the time threshold remaining for APDU instruction processing after deducting the estimated kernel logic processing time from the total time requirement of the L2 performance test. This is equivalent to step 120 above.
[0053] Step 3, Instruction Injection and Execution Phase: The test script is loaded into the underlying firmware or test program of the chip to be predicted. This test program bypasses the complete EMV kernel state machine and directly sends each instruction in the APDU sequence to the chip's contactless communication module in sequence through the underlying driver. This is equivalent to step 130 above.
[0054] Step 4, Performance Evaluation Phase: Simultaneously with sending the commands, start a high-precision timer to measure the interaction time from sending the first command to receiving the last command response. This is equivalent to steps 1302 to 1303 above.
[0055] The measured interaction duration is compared with the interaction time threshold: if the interaction duration is less than or equal to the interaction time threshold, the hardware performance of the chip to be predicted is determined to meet the pre-requirements of L2 performance testing.
[0056] If the total time consumed exceeds the interaction time threshold, the hardware performance of the chip to be predicted is determined to not meet the pre-requirements of the L2 performance test.
[0057] In summary, this invention achieves the following effects: 1. Decoupling: This invention creatively decouples performance testing from the complex EMV application layer logic. It eliminates the need to develop, compile, and debug a complete EMV kernel, directly testing the underlying hardware and eliminating interference from software factors in performance evaluation. 2. High Efficiency and Speed: The testing process is greatly simplified, shortening the timeframe from hours to minutes. R&D personnel can frequently and quickly perform performance self-checks during chip selection and hardware debugging phases, accelerating development iterations. 3. Low Cost: It eliminates the need for a complete set of L2 test cards and a complex testing environment, relying only on a few benchmark cards, reducing testing costs and barriers to entry. 4. Precise Positioning: Due to the isolation of the kernel software, test results more accurately reflect the chip's RF performance, instruction processing speed, and hardware design quality, facilitating hardware engineers to quickly pinpoint performance bottlenecks. 5. Proactive Assessment: It allows for reliable assessment of chip hardware performance before the EMV kernel development is complete, providing early evidence for project decisions and reducing project risks.
[0058] Please refer to Figure 5 The present invention also provides an electronic device 200, including a memory 201 and a processor 202, and a computer program stored on the memory 201 and running on the processor 202. When the processor 202 executes the computer program, it implements the various steps in the chip testing method described above.
[0059] The beneficial effects of the electronic device of the present invention are the same as those of the method described above, and will not be repeated here.
[0060] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention's specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A chip testing method, characterized in that, Applied to electronic devices, the method includes: Extract the application protocol data unit sequence from the benchmark card, which includes a test card whose chip has passed the target test; Obtain the interaction time threshold, and generate a test script based on the application protocol data unit sequence and the interaction time threshold; The test script is input into the chip to be predicted to instruct the chip to perform the test.
2. The chip testing method according to claim 1, characterized in that, The step of inputting the test script into the chip to be predicted includes: The test script is input into the underlying firmware of the chip to be predicted, so as to instruct the underlying firmware to send the instructions in the application protocol data unit sequence to the contactless communication module of the chip to be predicted in sequence.
3. The chip testing method according to claim 1, characterized in that, The threshold for obtaining the interaction time includes: Obtain the test time threshold that needs to be met in the test conditions of the target test corresponding to the chip under test, and obtain the interaction time threshold by subtracting the kernel processing time from the test time threshold.
4. The chip testing method according to claim 1, characterized in that, The step of inputting the test script into the chip to be predicted also includes: The test script is input into the chip to be predicted, instructing the chip to perform the interaction process according to the application protocol data unit sequence and record the interaction duration; The test results are obtained based on the interaction duration and the interaction time threshold.
5. The chip testing method according to claim 1, characterized in that, The extraction of the application protocol data unit sequence from the base card includes: Extract the application protocol data unit sequence generated by the benchmark card during contactless transactions from the benchmark card.
6. The chip testing method according to claim 1, characterized in that, The step of inputting the test script into the chip to be predicted includes: The test script is input into the test program; the test program sends the instructions in the application protocol data unit sequence to the contactless communication module of the chip to be predicted in sequence through the underlying driver.
7. A chip testing method according to claim 1, characterized in that, The step of inputting the test script into the chip to be predicted includes: The test script is input into the chip to be predicted, so as to instruct the contactless communication module in the chip to execute the instructions in the application protocol data unit sequence one by one, and record the interaction time from the sending of the first instruction to the completion of the reception of the last instruction.
8. A chip testing method according to claim 4, characterized in that, The process of obtaining test results based on the interaction duration and the interaction time threshold includes: If the interaction duration is less than or equal to the interaction time threshold, the chip to be predicted is indicated as having passed the test. Otherwise, a message will be displayed indicating that the chip to be predicted failed the test.
9. A chip testing method according to claim 1, characterized in that, Also includes: The EMV LEVEL2 test is used as the target test.
10. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement each step of the chip testing method according to any one of claims 1 to 9.