Chip partition management method and device, electronic equipment and storage medium

Abstract

The invention relates to the technical field of computers, in particular to a chip partition management method and device, electronic equipment and a storage medium, and the method comprises the steps: collecting the working state data of a plurality of areas of a chip; based on the working state data, calculating an aging risk score corresponding to each region; and based on the aging risk score of each region, performing graded aging avoidance operation on the corresponding region. According to the embodiment of the invention, while the aging risk is managed, the influence on the overall performance of the chip can be reduced, and the refinement degree of chip life management is improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a chip partitioning management method and apparatus, electronic device and storage medium. Background Technology

[0002] With the continuous development of integrated circuit technology, chip reliability has become one of the important indicators for measuring chip performance. Especially in the design of complex system-on-chips (SoCs) or graphics processing units (GPUs), how to effectively extend the lifespan of chips is a problem that the industry continues to focus on.

[0003] To reduce chip aging and extend its lifespan, related technologies typically employ hardware-level voltage and frequency adjustments or operating system (OS)-level temperature control to reduce power consumption, thereby indirectly increasing the chip's lifespan. For example, some temperature control solutions monitor the overall chip temperature and implement global frequency or voltage reduction to prevent overheating.

[0004] However, such methods are often global control strategies, which are difficult to provide differentiated aging management for different functions or physical regions inside the chip. They may not be able to perform fine-grained avoidance or protection operations for local hot spots or areas with high aging risk. Summary of the Invention

[0005] In view of this, this disclosure proposes a chip partition management technology solution.

[0006] According to one aspect of this disclosure, a chip partition management method is provided, comprising:

[0007] Collect operating status data from multiple areas of the chip;

[0008] Based on the aforementioned working status data, calculate the aging risk score corresponding to each region;

[0009] Based on the aging risk scores of each region, graded aging avoidance operations are performed in the corresponding regions.

[0010] In one possible implementation, the operating status data includes at least one of temperature change rate data, voltage fluctuation data, and current data;

[0011] The calculation of the aging risk score for each region includes:

[0012] The contribution value of thermal cycling damage is determined based on the temperature change rate data; and / or, the contribution value of dielectric breakdown damage is determined based on the voltage fluctuation data; and / or, the contribution value of electromigration damage is determined based on the current data.

[0013] The aging risk score is determined by a weighted sum of one or more of the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

[0014] In one possible implementation, the weighting coefficients used in the weighted sum are pre-calibrated in the following manner:

[0015] Thermal cycling stress, high voltage stress, and high current stress were applied to chip samples of the same specifications as the chip until observable aging failure occurred.

[0016] Record the time before failure corresponding to each of the three stresses;

[0017] Normalization is performed using the reciprocals of the time before thermal cycling failure, the time before high voltage failure, and the time before high current failure as proportional benchmarks to obtain the weighting coefficients corresponding to the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

[0018] In one possible implementation, the step of performing graded aging avoidance operations on corresponding regions based on the aging risk scores of each region includes:

[0019] If the aging risk score is greater than the first score threshold, a performance degradation action will be performed on the corresponding area.

[0020] If the aging risk score is less than the first scoring threshold but greater than or equal to the second scoring threshold, then the status information of the corresponding area is recorded.

[0021] If the aging risk score is less than the second score threshold, then no avoidance operation will be performed on the corresponding area.

[0022] In one possible implementation, the step of performing graded aging avoidance operations on corresponding regions based on the aging risk scores of each region includes:

[0023] Determine the cumulative thermal age for each region, which is used to characterize the aging degree of each region;

[0024] Based on the aging risk score and cumulative thermal age of each region, a graded aging avoidance operation is implemented for each region.

[0025] In one possible implementation, determining the cumulative thermal age corresponding to each region includes:

[0026] In each sampling period, the thermal age increment for the sampling period is calculated based on the temperature of the current area and the risk penalty coefficient corresponding to the aging risk score.

[0027] The thermal age increment is added to the historical cumulative thermal age of the current region to obtain the cumulative thermal age of the current region.

[0028] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0029] If the cumulative thermal age is less than the dynamic aging threshold, the aging management status of the corresponding area is determined to be normal, and no avoidance operation is performed.

[0030] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0031] If the cumulative thermal age reaches or exceeds the dynamic aging threshold and the aging risk score is lower than the first risk threshold, then the aging management status of the corresponding area is determined to be a warning status.

[0032] Record the warning status of the corresponding area and mark the corresponding area as a avoidance zone. The avoidance zone is used to indicate the area that needs to be avoided when assigning tasks in the future.

[0033] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0034] If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score is between the first risk threshold and a higher second risk threshold, then the aging management status of the corresponding area is determined to be a critical state.

[0035] Reduce the computational load allocated to the corresponding region and mark the corresponding region as a avoidance zone.

[0036] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0037] If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score reaches or exceeds the second risk threshold, then the aging management status of the corresponding area is determined to be a high-risk status.

[0038] Suspend the functions of the corresponding area, start the cooling process for the corresponding area, and mark the corresponding area as a avoidance zone.

[0039] In one possible implementation, the method further includes:

[0040] After the cooling process is initiated in a high-risk area, the corresponding area enters a cooling state.

[0041] During the cooling state, a cooling countdown is executed, and after the countdown ends, the corresponding area is restored to its normal state.

[0042] In one possible implementation, the process of determining the dynamic aging threshold includes:

[0043] The preset base threshold and aging acceleration factor for the chip are read;

[0044] Obtain the current lifetime budget consumption percentage of the chip;

[0045] The base threshold, the aging acceleration factor, and the percentage of lifespan budget consumption are substituted into a preset adjustment model for calculation. The adjustment model is configured such that the calculated result increases as the current percentage of lifespan budget consumption increases.

[0046] The calculated value is used as the dynamic aging threshold at the current moment.

[0047] In one possible implementation, the method further includes:

[0048] If the current lifetime budget consumption percentage of the chip as a whole exceeds the global threshold, a graded aging avoidance operation is performed on the chip as a whole.

[0049] According to another aspect of this disclosure, a chip partition management device is provided, comprising:

[0050] The data acquisition module is used to collect operating status data from multiple areas of the chip;

[0051] The risk scoring calculation module is used to calculate the aging risk score corresponding to each area based on the working status data.

[0052] The avoidance operation module is used to perform graded aging avoidance operations on the corresponding areas based on the aging risk scores of each area.

[0053] According to another aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described method.

[0054] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0055] According to another aspect of this disclosure, a computer program product is provided, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described method.

[0056] In this embodiment, by collecting operating status data from multiple regions of the chip, calculating an aging risk score for each region based on the operating status data, and performing graded aging avoidance operations on the corresponding regions based on the aging risk scores, the aging risk of different regions within the chip can be independently assessed and responded to in a differentiated manner based on quantitative scores. This avoids uniform frequency reduction or power consumption reduction of the entire chip, which is beneficial for managing aging risks while reducing the impact on the overall chip performance and improving the precision of chip lifespan management.

[0057] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0058] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0059] Figure 1 A flowchart illustrating a chip partition management method according to an embodiment of the present disclosure is shown.

[0060] Figure 2 A management state transition diagram is shown according to an embodiment of this disclosure.

[0061] Figure 3 This diagram illustrates an architecture of a chip partition management system according to an embodiment of the present disclosure.

[0062] Figure 4 A flowchart illustrating a chip partition management method according to an embodiment of the present disclosure is shown.

[0063] Figure 5 A block diagram of a chip partition management apparatus according to an embodiment of the present disclosure is shown.

[0064] Figure 6 This is a block diagram illustrating an apparatus for chip partition management according to an exemplary embodiment. Detailed Implementation

[0065] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0066] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0067] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0068] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0069] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0070] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0071] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0072] In the field of chip reliability design, with the continuous development of integrated circuit technology, how to effectively manage and extend the lifespan of chips has become one of the key concerns of the industry. Typically, to slow down chip aging and improve overall lifespan, related technologies employ hardware-based voltage and frequency regulation, or rely on global temperature control drivers at the operating system level, to indirectly extend lifespan by reducing overall power consumption. For example, some temperature control mechanisms monitor the overall temperature of the chip and implement global frequency or voltage reduction operations when the temperature exceeds a threshold.

[0073] However, such methods often have certain limitations in practical applications. On the one hand, global temperature control strategies may have a relatively lagging response and typically involve unified control of the entire chip, making it difficult to differentiate the actual operating states of different functional modules or physical regions within the chip. On the other hand, while traditional frequency reduction or voltage reduction operations can reduce power consumption, they often come at the cost of sacrificing the overall computing performance of the chip and lack the ability to finely perceive and control aging hotspots or risk accumulation in localized areas. Furthermore, related technologies typically lack models and mechanisms capable of real-time quantitative assessment of aging risks in various regions within the chip and dynamically adjusting management strategies accordingly, making it difficult for chips to achieve proactive and adaptive lifetime optimization management throughout their lifecycle.

[0074] Based on this, this disclosure proposes a chip partitioning management technology method in an attempt to improve one or more of the above aspects.

[0075] For ease of description, in one or more embodiments of this specification, the execution subject of the chip partition management technology method can be firmware. The following description uses firmware as the execution subject to illustrate the implementation of this method. It is understood that using firmware as the execution subject is merely an illustrative example and should not be construed as a limitation of the method.

[0076] Figure 1 A flowchart illustrating a chip partition management method according to an embodiment of the present disclosure is shown. Figure 1 As shown, the method includes:

[0077] In step S11, the operating status data of multiple areas of the chip are collected;

[0078] Operating status data can include physical quantities or electrical parameters generated by various regions of the chip during operation, used to characterize the real-time operating status of the regions. Specifically, operating status data can include at least one of temperature change rate data, voltage fluctuation data, and current data. The temperature change rate reflects the rate of temperature change of a region over time, voltage fluctuation data characterizes the stability of the supply voltage, and current data indicates the magnitude or variation of the current flowing through the region.

[0079] For example, the rate of temperature change can be obtained by acquiring the temperature values ​​of a region using a temperature sensor and calculating the rate of change based on the temperature at consecutive time points. For instance, in one example, the temperature difference between the current sampling point and the previous sampling point is divided by the sampling time interval to obtain the temperature change per unit time. Voltage fluctuation data can be obtained by monitoring the voltage signal of a power network using a voltage sensor and calculating the amplitude of voltage fluctuation relative to a reference value. For example, in another example, the voltage waveform is acquired and its maximum deviation from the average value is calculated within a time window to characterize voltage ripple. Current data can be obtained by measuring the current flowing through a region using a current sensor. For example, the current value is acquired and its effective value or transient peak value is calculated to reflect current density or abrupt changes.

[0080] Collecting operational status data from multiple regions of a chip can be achieved by deploying corresponding sensors in each region. For example, a chip can be divided into multiple functional modules or physical partitions, each integrating a temperature sensor, voltage monitoring point, or current sensing circuit. During operation, firmware or hardware control units can trigger sensor data acquisition, for example, by periodically reading sensor values ​​through timed interrupts. This data can be used to subsequently calculate the aging risk score for each region. Temperature change rate may be associated with thermal cycling damage, voltage fluctuations may be associated with dielectric breakdown, and current data may be associated with electromigration, thus supporting the quantitative assessment and tiered management of chip aging risk.

[0081] A chip can be divided into multiple regions (more than one) for independent status monitoring and management. This division can be based on dimensions such as the chip's physical layout, functional modules, or logical partitions. For example, in a graphics processing unit (GPU) or system-on-a-chip (SoC), the chip can be divided according to its internal functional modules, such as video processing units, display controllers, memory interfaces, or high-speed input / output units. In this way, each region can correspond to a structural unit with relatively independent functions or physical locations, allowing for the collection of operational status data for each unit and the execution of differentiated aging management strategies.

[0082] In step S12, based on the working status data, the aging risk score corresponding to each region is calculated;

[0083] Aging risk scoring can be used to quantify the potential risk of aging damage to various regions of a chip due to stress during operation. The score value can characterize the load level of a region under current operating conditions relative to its expected lifespan.

[0084] Calculating aging risk scores based on operational status data can be achieved by inputting collected parameters such as temperature change rate data, voltage fluctuation data, and current data into a pre-defined calculation model or algorithm. For example, the calculation process may include mapping each data point to a corresponding damage contribution value. These contribution values ​​can reflect the impact of different physical mechanisms on aging, such as material fatigue caused by thermal cycling, dielectric breakdown, or electromigration. Then, multiple damage contribution values ​​can be combined using weighted summation or other methods to obtain a comprehensive aging risk score.

[0085] For example, in one specific implementation, the temperature change rate data can be input into a model related to thermomechanical fatigue, such as a relationship derived from the Coffin-Manson equation, to calculate the contribution value of thermal cycling damage.

[0086] In another example, voltage fluctuation data can be input into a model related to gate oxide breakdown, such as a relation derived from the E model, to calculate the dielectric breakdown damage contribution. For current data, it can be input into a model related to electromigration failure, such as a relation derived from the Black equation, to calculate the electromigration damage contribution. Parameters in these models, such as exponential terms or proportionality coefficients, can be calibrated by performing standard stress tests on chip samples (such as thermal cycling, high-voltage stress, or high-current tests according to JEDEC standards) to fit actual failure data. Finally, the thermal cycling damage contribution, dielectric breakdown damage contribution, and electromigration damage contribution can be multiplied by their respective weighting coefficients and summed to obtain the final aging risk score. The weighting coefficients can be determined by normalizing the inverse proportionality of the failure time obtained from the tests.

[0087] This calculation method allows the aging risk score to simultaneously consider the real-time impact of multiple stress factors, such as temperature, voltage, and current, on the aging of chip areas. This enables the score to more comprehensively characterize the aging risk status of the area, thereby providing a quantitative basis for subsequent differentiated area management operations.

[0088] For details on how to calculate the aging risk score for each region, please refer to the possible implementation methods provided in this disclosure, which will not be elaborated here.

[0089] In step S13, based on the aging risk score of each region, a graded aging avoidance operation is performed on the corresponding region.

[0090] Graded aging avoidance operation is used to perform different levels of management or protection actions based on the degree of aging risk of chip areas. It slows down the aging process of specific areas through differentiated intervention measures, while maintaining the overall function and performance of the chip as much as possible.

[0091] Based on the aging risk scores of each region, a tiered aging avoidance operation is implemented. This is achieved by comparing the score value with one or more preset thresholds and triggering control logic corresponding to the score range based on the comparison result. The core of this operation lies in applying different management strategies to regions with different risk levels, thereby achieving a multi-level response from simply recording monitoring information to implementing proactive performance adjustment or protection.

[0092] For example, multiple thresholds can be set for the aging risk score, such as a first threshold and a second threshold, to divide different risk level ranges. In one example, when the aging risk score of a certain area is greater than the first threshold, the area can be determined to be in a high-risk state, and performance degradation actions can be performed on it, such as reducing the operating voltage or operating frequency of the area to reduce its instantaneous power consumption and thermal stress. In another example, when the aging risk score of a certain area is less than the first threshold but greater than or equal to the second threshold, the area can be determined to be in a medium-risk state. In this case, its performance can be adjusted without immediate adjustment, and the status information of the area can be recorded for long-term tracking and analysis. In yet another example, when the aging risk score of a certain area is less than the second threshold, the area can be determined to be in a low-risk state. In this case, no specific avoidance operations can be performed, allowing it to maintain normal operation.

[0093] Furthermore, the graded aging avoidance operation can also be combined with the cumulative thermal age status of a region for decision-making. Specific implementation methods are provided in this disclosure. For example, based on determining that the cumulative thermal age of each region has reached a dynamically adjusted threshold, and combined with the interval to which its aging risk score belongs, a more refined state transition can be triggered, such as marking the region as a warning state, a critical state, or a high-risk state. For regions in a warning state, they can be marked as avoidance zones to prevent the allocation of new computational loads to them in subsequent task scheduling. For regions in a critical state, in addition to marking them as avoidance zones, the computational load allocated to these regions can be reduced. For regions in a high-risk state, their functionality can be suspended, and a cooling process can be initiated for these regions, while simultaneously marking them as avoidance zones. In this way, the graded aging avoidance operation can transform quantified risk scores into specific, hierarchical hardware management or task scheduling instructions, thereby achieving proactive avoidance of localized aging hotspots on the chip and refined lifetime management.

[0094] In this embodiment, by collecting operating status data from multiple regions of the chip, calculating an aging risk score for each region based on the operating status data, and performing graded aging avoidance operations on the corresponding regions based on the aging risk scores, the aging risk of different regions within the chip can be independently assessed and responded to in a differentiated manner based on quantitative scores. This avoids uniform frequency reduction or power consumption reduction of the entire chip, which is beneficial for managing aging risks while reducing the impact on the overall chip performance and improving the precision of chip lifespan management.

[0095] In one possible implementation, the operating status data includes at least one of temperature change rate data, voltage fluctuation data, and current data;

[0096] The calculation of the aging risk score for each region includes:

[0097] The contribution value of thermal cycling damage is determined based on the temperature change rate data; and / or, the contribution value of dielectric breakdown damage is determined based on the voltage fluctuation data; and / or, the contribution value of electromigration damage is determined based on the current data.

[0098] The aging risk score is determined by a weighted sum of one or more of the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

[0099] In some possible implementations, during the calculation of the aging risk score, the contribution value corresponding to a single operating condition data point can be determined, and then the aging risk score can be determined. Alternatively, multiple (i.e., more than one) different types of operating condition data can be collected, and their respective damage contribution values ​​corresponding to specific aging mechanisms can be determined. These contribution values ​​can then be combined into a total score. The damage contribution value can include determining the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

[0100] Determining the contribution of thermal cycling damage based on temperature change rate data can be done by inputting the temperature change rate into a calculation related to thermomechanical fatigue. For example, some implementations may use a simplified form derived from the Coffin-Manson model, where the damage contribution has a power-law or linear relationship with the temperature change rate. A higher temperature change rate indicates more severe thermal stress cycling of the chip material, potentially accelerating fatigue of solder joints or interconnect metals, and consequently, a higher thermal cycling damage contribution. For example, the thermal cycling damage contribution can be the temperature change rate, determined by the following formula:

[0101]

[0102] in, It is the partial derivative of temperature T with time t, representing the rate of change of temperature over time; T n T represents the temperature value at the current time step n. n－1 This represents the temperature value at the previous time step n-1. Δt represents the time step size, i.e., the time interval between the current time step and the previous time step.

[0103] Determining the contribution value of dielectric breakdown damage based on voltage fluctuation data can be accomplished by processing voltage fluctuation information and associating it with the gate oxide layer reliability model. Voltage fluctuations cause abrupt changes in the electric field within the oxide layer, exacerbating the risk of dielectric breakdown. In some models, such as the E-model, the breakdown time is exponentially related to the electric field strength. Therefore, when calculating the contribution value, an exponential term of the voltage fluctuation amplitude can be considered. For example, the contribution value of dielectric breakdown damage can be a voltage fluctuation term, which can be determined by the following formula:

[0104]

[0105] Where max|ΔV| represents the time interval [t] 0， t 0+τ The maximum magnitude of voltage change within the given interval. sup represents the supremum, i.e., the maximum value within the given interval. t is the time variable. t0 is the starting time point. τ is the length of the time interval. V(t) is the voltage value at time t. It is the voltage V(t) over the time interval [t] 0， t 0+τ The average value on [].

[0106] The contribution value of electromigration damage can be determined based on current data by analyzing current magnitude or variation information and applying an electromigration failure model. Current density is the primary driving force for electromigration in metallic interconnects. For example, based on the Black equation, there is a power-law relationship between failure time and current density. When calculating the contribution value, the current density can be estimated based on the collected current values ​​(e.g., RMS or peak values), and then the electromigration damage contribution value can be calculated using a power-law approach. For example, the electromigration damage contribution value can be determined using the following formula:

[0107]

[0108] Among them, I rms The root mean square (RMS) value of current is a measure of the effective value of alternating current. It is used to represent the energy equivalent of the current to the direct current value over a certain period of time. I(t) is the instantaneous current value at time t, which can be a function that changes with time.

[0109] After obtaining the contribution values ​​of thermal cycling damage, dielectric breakdown damage, and electromigration damage, respectively, the aging risk score can be determined based on the weighted sum of these three values. The weighting coefficients in the weighted sum (e.g., κ) T , κ V , κ I These coefficients can be used to adjust the relative importance of different aging mechanisms to the overall risk. These coefficients can be calibrated by performing standardized accelerated lifetime testing on chip samples. Multiplying the three contribution values ​​by their respective weights and then summing them yields a quantitative, comprehensive aging risk score. For example, the aging risk score RiskScore can be expressed by the following formula:

[0110]

[0111] Among them, κ T The weighting coefficient representing the rate of temperature change is used to adjust the contribution of the rate of temperature change to the risk score. V This represents the weighting coefficient for voltage fluctuations, used to adjust the contribution of voltage fluctuations to the risk score. κ I This represents the weighting factor for the current, used to adjust the impact of the current on the risk score.

[0112] In this embodiment, the contribution value of thermal cycling damage is determined based on the temperature change rate data; and / or, the contribution value of dielectric breakdown damage is determined based on the voltage fluctuation data; and / or, the contribution value of electromigration damage is determined based on the current data. The aging risk score is then determined by a weighted sum of one or more of the contribution values ​​of thermal cycling damage, dielectric breakdown damage, and electromigration damage. This allows one or more key stress factors affecting chip lifespan (such as temperature, voltage, and current) to be mapped to specific physical failure models for quantitative evaluation. For a single operating state data point, the actual aging risk under a single stress can be assessed. For multiple operating state data points, their contributions to aging risk can be combined through weighted summation. This results in a more comprehensive and accurate aging risk score that reflects the actual aging risk of the chip region under multi-stress coupling, providing a reliable quantitative basis for subsequent refined graded avoidance operations.

[0113] In one possible implementation, the weighting coefficients used in the weighted sum are pre-calibrated in the following manner:

[0114] Thermal cycling stress, high voltage stress, and high current stress were applied to chip samples of the same specifications as the chip until observable aging failure occurred.

[0115] Record the time before failure corresponding to each of the three stresses;

[0116] Normalization is performed using the reciprocals of the time before thermal cycling failure, the time before high voltage failure, and the time before high current failure as proportional benchmarks to obtain the weighting coefficients corresponding to the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

[0117] In some possible implementations, the weighting coefficients used in the weighted sum can be predetermined through experimental calibration. These weighting coefficients can be used to balance the relative contributions of the three different aging mechanisms—thermal cycling damage, dielectric breakdown damage, and electromigration damage—to the overall risk score, ensuring that the final aging risk score more closely reflects the failure characteristics of the chip in actual use.

[0118] Applying thermal cycling stress, high-voltage stress, and high-current stress to chip samples of the same specifications as the stated chip until observable aging failure occurs can be accomplished through accelerated life testing of representative chips in a controlled laboratory environment. Thermal cycling stress is applied by cyclically changing the chip's ambient temperature within an extreme temperature range to simulate thermomechanical fatigue caused by drastic temperature variations. High-voltage stress is applied by applying a DC or pulsed voltage exceeding the chip's rated operating voltage to accelerate the dielectric breakdown process of the gate oxide layer. High-current stress is applied by subjecting the chip to a continuous current exceeding its rated value to induce electromigration failure of the metal interconnects. These stress tests can follow industry standards, such as the relevant test specifications published by the Joint Electron Device Engineering Council (JEDEC).

[0119] Recording the time to failure for each of the three stresses means monitoring the chip sample's condition in each test and recording the time elapsed from the application of stress to the chip exhibiting a preset failure criterion (such as functional abnormality, parameter exceeding limits, or physical damage). The time to failure directly characterizes the chip's durability under that single stress; the shorter the time, the more sensitive the chip is to that stress.

[0120] Normalization is performed using the reciprocals of the time before thermal cycling failure, the time before high-voltage failure, and the time before high-current failure as proportional benchmarks to obtain weighting coefficients for the corresponding thermal cycling damage contribution, dielectric breakdown damage contribution, and electromigration damage contribution. This can be achieved through mathematical calculation. Since the reciprocal of the time before failure is related to the failure rate or risk rate, a larger value indicates a higher risk of failure caused by the corresponding stress per unit time. Using these three reciprocals as the original proportions, normalization can be performed, for example, by dividing them by the sum of the three, or by scaling them to a fixed sum (e.g., 1), thereby obtaining a set of weighting coefficients (e.g., κ). T , κV , κ I ).

[0121] For example, after completing a set of standard tests, if the time before thermal cycling failure is measured to be 1000 hours, the time before high voltage failure is 500 hours, and the time before high current failure is 2000 hours, then their reciprocals are 0.001, 0.002, and 0.0005, respectively. Normalizing these three values ​​yields a set of weighting coefficients, which are used to weight the contribution values ​​of each damage item in real-time scoring calculations.

[0122] For example, a set of weighting coefficients κ can be determined using the following formula. T , κ V , κ I :

[0123]

[0124] Among them, C T The coefficient representing the temperature dependence can be determined using the following formula:

[0125]

[0126] N f The reciprocal of the time before thermal cycling failure, the reciprocal of the time before high voltage failure, and the time before high current failure are represented by the mean time before failure (MTTF). α is the exponent, representing the degree of influence of the temperature change rate on the failure rate.

[0127] C V The coefficient representing the voltage relationship can be determined using the following formula:

[0128]

[0129] TTF TDDB γ represents the time before high-voltage failure leading to time-dependent dielectric breakdown; exp is an exponential function representing the nonlinear effect of voltage fluctuations on the failure rate; γ is the voltage acceleration factor, representing the degree of influence of voltage fluctuations on dielectric breakdown.

[0130] C I The coefficient represents the relationship with current and may be related to the electromigration properties of the material.

[0131]

[0132] MTTF EM This represents the time before electromigration failure due to high current, where m is an exponent indicating the degree of influence of current on the electromigration failure rate.

[0133] In this embodiment, thermal cycling stress, high voltage stress, and high current stress are applied to chip samples of the same specifications as the chip until observable aging failure occurs. The time before failure corresponding to each of the three stresses is recorded. Normalization is performed using the reciprocals of the time before thermal cycling failure, the reciprocals of the time before high voltage failure, and the reciprocals of the time before high current failure as proportional benchmarks to obtain weighting coefficients for the contribution values ​​of thermal cycling damage, dielectric breakdown damage, and electromigration damage. Therefore, the determination of the weighting coefficients is directly based on the failure data of the chip samples under actual accelerated stress, making the relative importance of each aging mechanism on which the weighted calculation is based more closely reflect the actual physical failure process of the chip. This improves the accuracy and reliability of the aging risk scoring model, enabling the scoring results to more effectively reflect the aging risk status of the chip under actual operating conditions.

[0134] In one possible implementation, the step of performing graded aging avoidance operations on corresponding regions based on the aging risk scores of each region includes:

[0135] If the aging risk score is greater than the first score threshold, a performance degradation action will be performed on the corresponding area.

[0136] If the aging risk score is less than the first scoring threshold but greater than or equal to the second scoring threshold, then the status information of the corresponding area is recorded.

[0137] If the aging risk score is less than the second score threshold, then no avoidance operation will be performed on the corresponding area.

[0138] In one possible implementation, the step of performing graded aging avoidance operations on corresponding regions based on the aging risk scores of each region includes:

[0139] Determine the cumulative thermal age for each region, which is used to characterize the aging degree of each region;

[0140] Based on the aging risk score and cumulative thermal age of each region, a graded aging avoidance operation is implemented for each region.

[0141] When implementing tiered aging avoidance operations based on aging risk scores, the scores can be compared with preset thresholds, and corresponding management strategies can be triggered based on the comparison results. Specifically, a first and a second scoring threshold can be set to divide different risk level ranges, thereby enabling differentiated response measures for areas with different risk levels.

[0142] When the aging risk score exceeds a first score threshold, the region is determined to be in a high-risk aging state. In this case, performance degradation actions are performed on the corresponding region, which may include reducing its operating frequency, decreasing its operating voltage, or limiting its computational load. These actions can alleviate excessive stress levels by reducing the region's instantaneous power consumption and heat generation, thereby slowing down the aging process of the region. For example, in one example, performance degradation actions could involve locking the region's clock frequency to a lower maximum value and disabling dynamic overclocking.

[0143] When the aging risk score is less than the first scoring threshold and greater than or equal to the second scoring threshold, the area can be determined to be in a medium-risk state. In this case, recording the status information of the corresponding area may include writing the area's score, temperature data, voltage data, and current timestamp to a specific log area or non-volatile memory. This operation is mainly used to track the risk trend of the area, providing a data basis for subsequent lifetime analysis and prediction, without immediately interfering with the normal operation of the area.

[0144] When the aging risk score is less than the second score threshold, the region can be determined to be in a low-risk state. In this case, no avoidance operation is performed on the corresponding region, meaning that the region can maintain its current performance configuration and workload, and continue to participate normally in the chip's computing tasks. This strategy minimizes unnecessary performance sacrifices when the risk is controllable.

[0145] For example, a first scoring threshold can be set to 70, and a second scoring threshold to 50. In one scenario, if a region's calculated aging risk score is 85 (greater than 70), a performance degradation action can be triggered, such as reducing the core's voltage by 50mV and limiting the maximum frequency to 80% of its nominal value. In another scenario, if a region's score is 60 (between 50 and 70), the region's identifier, score, and current temperature value can be logged to the system log. In yet another scenario, if a region's score is 40 (less than 50), no special action can be taken, and the region continues to operate in full-performance mode.

[0146] In this embodiment, performance degradation is performed on the corresponding region when the aging risk score is greater than a first scoring threshold; status information of the corresponding region is recorded when the aging risk score is less than the first scoring threshold but greater than or equal to a second scoring threshold; and no avoidance operation is performed on the corresponding region when the aging risk score is less than the second scoring threshold. Therefore, based on precise threshold comparisons of the quantified scores, accurate responses to regions with different risk levels can be achieved: proactive performance adjustment is implemented in high-risk regions to directly alleviate aging stress; status monitoring is performed in medium-risk regions to accumulate lifetime data; and unnecessary intervention is avoided in low-risk regions. This hierarchical strategy enables chip management to effectively delay local aging while minimizing the impact on overall performance, improving the precision and intelligence of aging management.

[0147] In one possible implementation, determining the cumulative thermal age for each region includes:

[0148] In each sampling period, the thermal age increment for the sampling period is calculated based on the temperature of the current area and the risk penalty coefficient corresponding to the aging risk score.

[0149] The thermal age increment is added to the historical cumulative thermal age of the current region to obtain the cumulative thermal age of the current region.

[0150] The decision-making process for graded aging avoidance operations can be further combined with parameters characterizing the long-term aging accumulation of a region. To this end, the cumulative thermal age corresponding to each region can be determined. This cumulative thermal age can be used to characterize the overall aging degree accumulated by each region due to temperature and other stresses in its operating history. It is a quantitative indicator that reflects the "consumption" life of a region as it grows over time.

[0151] Determining the cumulative thermal age of each region can be achieved by periodically calculating and accumulating the thermal age increment for each region. The thermal age increment represents the amount of aging accumulated in a region within a specific time period (e.g., a sampling interruption period). Calculating the thermal age increment can comprehensively consider the region's current temperature and its instantaneous risk status. For example, in each sampling period, the thermal age increment for that period can be calculated based on the current temperature data of the region and the risk penalty coefficient corresponding to the region's current aging risk score. The risk penalty coefficient can be mapped according to the level of the aging risk score; the higher the score and the higher the risk level, the larger the corresponding penalty coefficient can be set to characterize the effect of accelerated aging under high-risk conditions. Then, the calculated thermal age increment can be accumulated into the region's historical cumulative thermal age value to update the region's current cumulative thermal age.

[0152] For example, the specific calculation of the thermal age increment ΔAge can be achieved through the following formula:

[0153]

[0154] Here, T represents the temperature of the current region, in degrees Celsius (°C). 85°C is chosen as an example threshold, meaning that the chip begins to age significantly when the temperature exceeds 85°C. In practical applications, this threshold should be set according to the specific tolerance of the chip. "Otherwise" indicates other temperature ranges besides T > 85°C.

[0155] β is the risk penalty coefficient, reflecting the risk level corresponding to the current aging risk score of the region. For example, a high-risk region might be assigned a coefficient of 2.0, a medium-risk region 1.5, and a low-risk region 1.0. This coefficient can be adjusted according to the specific situation of the chip to more accurately reflect the effect of accelerated aging under different risk levels.

[0156] 0.01 is the temperature-to-time conversion factor, which defines the thermal age unit accumulated per degree Celsius per 10 milliseconds (ms). This factor can be adjusted according to the specific aging characteristics of the chip to ensure that the calculation of thermal age increments accurately reflects the actual aging of the chip.

[0157] This formula allows for the calculation of thermal age increments for each region of the chip within each sampling period, and these increments are accumulated into the historical cumulative thermal age of each region. This enables real-time updating and monitoring of the cumulative thermal age of each region of the chip, thus facilitating more effective aging management and lifespan prediction.

[0158] Based on the aging risk score and cumulative thermal age of each region, tiered aging avoidance operations can be implemented for each region. By combining these two dimensions (i.e., transient risk and cumulative loss), a more refined state decision-making model can be established. For example, the cumulative thermal age of a region can be compared with a dynamic aging threshold, while also referring to the range to which the region's aging risk score belongs, to jointly determine the management state that the region should enter and trigger the avoidance operation corresponding to that state.

[0159] In this embodiment, the cumulative thermal age of each region is determined to characterize the aging degree of each region, and graded aging avoidance operations are performed on each region based on its aging risk score and cumulative thermal age. Therefore, the decision-making process considers not only the instantaneous risk score reflecting real-time stress levels but also the thermal age history reflecting long-term cumulative damage, thus enabling a more comprehensive assessment of the aging status of a region. This two-dimensional assessment mechanism can more accurately distinguish whether a region is in a short-term risk fluctuation or a long-term severe aging stage, thereby triggering corresponding multi-level management actions, from early warning and load adjustment to function suspension. This achieves more refined and proactive management of chip lifespan, which is beneficial for extending overall lifespan while optimizing performance availability.

[0160] For example, several management states can be defined, such as normal state, warning state, critical state, high-risk state, and cooling state. Figure 2 This illustrates a management state transition diagram provided according to an embodiment of the present disclosure, such as... Figure 2 As shown, the initial state of the region is usually the normal state, and its triggering condition can be that the cumulative thermal age of the region is less than the dynamic aging threshold at the current moment.

[0161] When the cumulative thermal age of a region increases to or exceeds the dynamic aging threshold, its status will change. The specific status to which it changes depends on the current aging risk score of the region: if the aging risk score is lower than the preset first risk threshold (e.g., 60), the status changes to the warning status; if the aging risk score is between the first risk threshold (e.g., 60) and a higher second risk threshold (e.g., 70), the status changes to the critical status; if the aging risk score reaches or exceeds the second risk threshold (e.g., 70), the status changes to the high-risk status.

[0162] Upon entering a high-risk state, a cooling process for that area will be triggered, at which point the state will further transition to a cooling state. In the cooling state, a cooling countdown will be executed. After the countdown ends, the state will be reassessed based on the latest cumulative thermal age and aging risk score of the area after cooling: if the cumulative thermal age is below the latest dynamic aging threshold, the state will usually transition back to a normal state; if the cumulative thermal age is still above the threshold, it will re-enter the corresponding warning state (score < 60), critical state (60 ≤ score < 70), or high-risk state (score ≥ 70) based on the latest aging risk score.

[0163] Furthermore, status transitions can occur due to real-time changes in risk scores. For example, a region in a warning state (score < 60) may transition to a critical state if its aging risk score rises to between 60 and 70. Conversely, a region in a critical state (60 ≤ score < 70) may transition back to a warning state if its risk score drops below 60. Similarly, if a region in any warning, critical, or high-risk state experiences a reduction in its cumulative thermal age below the dynamic aging threshold due to management operations or data updates, its status can transition back to a normal state.

[0164] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0165] If the cumulative thermal age is less than the dynamic aging threshold, the aging management status of the corresponding area is determined to be normal, and no avoidance operation is performed.

[0166] The dynamic aging threshold can serve as a boundary value for determining whether a region requires active aging management. This threshold is not fixed but is a variable that can be dynamically adjusted based on the chip's usage status or lifespan depletion. For details, please refer to the possible implementation methods provided in this disclosure, which will not be elaborated here.

[0167] When the cumulative thermal age of a region is below this threshold, it usually indicates that the accumulated aging in that region has not yet reached the critical level that requires triggering special protection mechanisms. Therefore, the aging management status of the corresponding region can be determined to be normal, meaning that the current level of aging accumulation in that region is considered to be within an acceptable and expected range.

[0168] In this state, no avoidance operation is performed on this region. That is, this region will continue to operate normally with its current configuration parameters (such as voltage and frequency) and will continue to receive and process the computing tasks assigned to it. The consideration for this approach is that when the aging accumulation is not yet significant, premature performance limiting or task migration may be unnecessary and may unnecessarily sacrifice the chip's performance or energy efficiency.

[0169] In this embodiment, if the cumulative thermal age is less than a dynamic aging threshold, the aging management status of the corresponding region is determined to be normal, and no avoidance operation is performed. Thus, the firmware can accurately determine whether the cumulative damage of a region has reached a level requiring intervention based on a dynamically adjusted threshold that matches the current aging stage of the chip. When the cumulative thermal age does not exceed this threshold, it indicates that the region is still in a relatively healthy early or mid-life stage. Avoiding any avoidance operation at this time can maximize the maintenance of the chip's original performance and functional integrity, preventing unnecessary performance degradation or resource rescheduling overhead, thereby optimizing the chip's resource utilization and energy efficiency for most of its operating time.

[0170] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0171] If the cumulative thermal age reaches or exceeds the dynamic aging threshold and the aging risk score is lower than the first risk threshold, then the aging management status of the corresponding area is determined to be a warning status.

[0172] Record the warning status of the corresponding area and mark the corresponding area as a avoidance zone. The avoidance zone is used to indicate the area that needs to be avoided when assigning tasks in the future.

[0173] When regional aging management enters an early warning state, it indicates that the accumulated aging in the region has reached a level requiring attention, but its current operational stress is still within a relatively mild range. The strategy adopted at this time focuses on early warning and task scheduling avoidance, rather than immediate performance intervention.

[0174] The determination of a warning status is based on the simultaneous fulfillment of two conditions: first, the cumulative thermal age of the area reaches or exceeds the dynamic aging threshold, indicating that the area has accumulated a certain degree of lifespan depletion; second, the aging risk score of the area is lower than the first risk threshold, indicating that the instantaneous stresses it currently experiences, such as temperature, voltage, and current, are not at a high-risk level. This status means that although the area has accumulated significant historical damage, its current operating conditions are relatively stable, therefore, non-intrusive monitoring and scheduling avoidance measures are prioritized.

[0175] Recording the warning status of the corresponding area allows you to write information such as the area's identifier, the time it entered the warning state, its cumulative thermal age, and risk score to a specific management log or status register. This provides the system's health management module with traceable historical data, facilitating long-term trend analysis and lifespan prediction.

[0176] Marking a region as a "avoidance zone" involves setting an identifier in the chip's resource management or task scheduling system. This identifier indicates to higher-level management entities such as task schedulers, load balancers, or operating systems that the region is not suitable for accepting new computing tasks or workloads in the near future. For example, in a multi-core processor or GPU, firmware or drivers can mark cores or computing units in a warning state with an "avoidance" attribute in their internal task allocation table. When new threads or computing tasks need to be allocated, the scheduling algorithm will prioritize unmarked regions, thus avoiding applying additional workload to these aging regions and preventing their accumulated thermal age from increasing rapidly due to new loads.

[0177] In this embodiment, when the cumulative thermal age reaches or exceeds the dynamic aging threshold and the aging risk score is lower than the first risk threshold, the aging management status of the corresponding area is determined to be in a warning state. The warning state of the corresponding area is recorded, and the corresponding area is marked as an avoidance zone. The avoidance zone is used to indicate areas that need to be avoided during subsequent task allocation. This allows for a proactive and preventative management strategy for areas that have accumulated significant aging but currently have low operational risk. The status recording enables traceability of the aging process, and the "avoidance" mechanism at the resource scheduling level effectively reduces the additional pressure that the area may bear in the future without reducing its immediate performance, thereby slowing down the further increase in its aging rate and achieving an early balance between maintaining overall chip performance and extending the lifespan of local devices.

[0178] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0179] If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score is between the first risk threshold and a higher second risk threshold, then the aging management status of the corresponding area is determined to be a critical state.

[0180] Reduce the computational load allocated to the corresponding region and mark the corresponding region as a avoidance zone.

[0181] When a region simultaneously meets the criteria of high aging accumulation and moderate instantaneous operational risk, the management strategy will be upgraded to more proactive intervention. At this point, the region is identified as being in a critical state, indicating that its aging process has entered a stage that requires close monitoring and appropriate control.

[0182] The triggering of a critical state requires the simultaneous fulfillment of two conditions: first, the cumulative thermal age of the region reaches or exceeds the dynamic aging threshold, indicating that its lifespan has been significantly depleted; second, the aging risk score of the region is between a preset first risk threshold and a higher second risk threshold. This means that, compared to the warning state, the region not only has more historically accumulated damage, but is also currently experiencing moderate operational stress (such as a higher rate of temperature change or voltage fluctuations), making its overall risk situation more urgent.

[0183] Reducing the computational load allocated to a specific region can be achieved through various hardware or software mechanisms. This directly reduces the region's activity and power consumption per unit time, thereby lowering its heat generation and electrical stress, and ultimately slowing down its aging process. For example, in a multi-core processor, the firmware or operating system scheduler can adjust the number of threads or the amount of computational tasks allocated to that core, such as reducing its load to half the normal level. In another example, dynamic voltage and frequency adjustment techniques can be used to reduce the operating voltage and frequency of that region, allowing it to operate under gentler electrical conditions.

[0184] Similar to the warning status, the corresponding area also needs to be marked as a avoidance zone. This marking is also used to instruct the task scheduling system to prioritize avoiding this area when assigning new tasks.

[0185] In this embodiment, when the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score is between a first risk threshold and a higher second risk threshold, the aging management status of the corresponding region is determined to be critical. The computational load allocated to the corresponding region is reduced, and the corresponding region is marked as an avoidance zone. Thus, by proactively reducing its computational load, the instantaneous working stress and heat accumulation of the region are directly alleviated, fundamentally slowing the aging acceleration trend. Simultaneously, the avoidance marking at the resource scheduling level prevents additional pressure from subsequent task allocation. This combined strategy achieves a dynamic balance between performance and lifespan extension, effectively intervening in the damage process of medium-risk aging regions with acceptable performance degradation, and improving the proactiveness and refinement of chip reliability management.

[0186] In one possible implementation, performing graded aging avoidance operations on each region includes:

[0187] If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score reaches or exceeds the second risk threshold, then the aging management status of the corresponding area is determined to be a high-risk status.

[0188] Suspend the functions of the corresponding area, start the cooling process for the corresponding area, and mark the corresponding area as a avoidance zone.

[0189] When a region simultaneously faces severe aging accumulation and extremely high instantaneous operational risks, its management status can be determined as high-risk. This status means that the region is at a critical point where rapid or irreversible damage may occur, requiring immediate implementation of the highest level of protection measures to ensure the overall reliability of the chip and prevent failures.

[0190] The triggering conditions for a high-risk state are more stringent than those for a warning state and a critical state. It requires that the cumulative thermal age reach or exceed the dynamic aging threshold, and the aging risk score reach or exceed the second risk threshold simultaneously. The second risk threshold is higher than the first risk threshold. At this point, it indicates that the region has not only suffered significant historical lifespan depletion but is also currently exposed to extremely high temperature, voltage, or current stresses, such as sudden temperature rises, significant voltage surges, or excessive current densities. This drastically increases the risk of failures such as thermal fatigue, dielectric breakdown, or electromigration.

[0191] Therefore, the functionality of the corresponding region can be paused, that is, all ongoing and planned computing tasks in that region can be immediately stopped and placed into an inactive, silent state. Specific implementation methods may include: forcibly clearing the instruction pipeline in that region by firmware or hardware security logic, disabling its clock signal, or placing it in a minimum power hold mode. This immediately terminates any activity that might exacerbate its electrical and thermal stress, fundamentally blocking the continuous input of aging damage.

[0192] Building upon the pause function, further physical intervention can be implemented, namely initiating a cooling process targeting the corresponding area to actively reduce its temperature and alleviate thermal stress. This cooling process can be combined with hardware heat dissipation capabilities; for example, increasing the speed of the cooling fan associated with the area, activating microchannel coolant circulation integrated near the area, or adjusting the overall power consumption distribution of the chip to reduce the overall thermal load. This active cooling approach aims to bring the junction temperature of the area down from a dangerously high level.

[0193] At the same time, the corresponding area can be marked as a avoidance zone, clearly instructing all task scheduling and resource management modules to avoid allocating any workload to that area.

[0194] In this embodiment, when the cumulative thermal age reaches or exceeds the dynamic aging threshold and the aging risk score reaches or exceeds the second risk threshold, the aging management status of the corresponding area is determined to be high-risk. The function of the corresponding area is suspended, a cooling process is initiated for the corresponding area, and the corresponding area is marked as an avoidance zone. Thus, by suspending the function, the main source of activity leading to increased damage is eliminated; by initiating active cooling, existing thermal shocks are actively mitigated; and combined with mandatory avoidance marking at the resource level, a multi-layered defense is constructed to ensure that the area is completely removed from the workload until the danger is eliminated. This highest-level response mechanism minimizes the chain reaction that might be triggered by rapid failure of a local high-risk area, protecting the overall functional safety and data integrity of the chip, demonstrating the ultimate protection capability of the aging management system.

[0195] In one possible implementation, the method further includes:

[0196] After the cooling process is initiated in a high-risk area, the corresponding area enters a cooling state.

[0197] During the cooling state, a cooling countdown is executed, and after the countdown ends, the corresponding area is restored to its normal state.

[0198] In one possible implementation, the cooling state represents a temporary, restorative management phase. During this cooling state, a cooling countdown is executed, and after the countdown ends, the corresponding area is restored to its normal state. The cooling countdown can be a preset fixed duration or a duration dynamically calculated based on the area's overheating level or cumulative thermal age. The purpose of this countdown is to ensure that the area has sufficient time to reduce its temperature below a safe threshold and to allow the transient electrical state caused by previous high-stress operation to stabilize.

[0199] For example, the countdown duration can be set to range from several milliseconds to hundreds of milliseconds. During the countdown, the progress of the cooling process can be continuously monitored, but areas are generally prohibited from exiting the cooling state. When the countdown ends, the firmware determines that the active cooling phase has been completed. Subsequently, the corresponding area is restored to the normal state, that is, the "avoidance zone" mark of the area is removed (if it existed before), its accumulated thermal age is reset or reduced by a certain percentage to reflect the cooling effect, and the task scheduler is allowed to reconsider allocating load to it. The restored area will restart the aforementioned complete aging risk assessment and state transition process based on the updated accumulated thermal age and real-time collected working status data.

[0200] In this embodiment, a cooling process is initiated for high-risk areas to induce a cooling state, during which a cooling countdown is performed. After the countdown ends, the corresponding area is restored to its normal state. Thus, by suspending its function and performing active cooling, the continuous accumulation of damage under high risk can be effectively interrupted, causing the area's temperature and electrical stress to return to lower levels. The cooling countdown mechanism ensures the adequacy and controllability of the recovery process. Ultimately, the area is restored to its normal state, allowing it to be reintegrated into the system resource pool after the risk is mitigated. This avoids performance loss caused by permanently shielding the area, achieving an effective balance between emergency protection and resource reuse.

[0201] In one possible implementation, the process of determining the dynamic aging threshold includes:

[0202] The preset base threshold and aging acceleration factor for the chip are read;

[0203] Obtain the current lifetime budget consumption percentage of the chip;

[0204] The base threshold, the aging acceleration factor, and the percentage of lifespan budget consumption are substituted into a preset adjustment model for calculation. The adjustment model is configured such that the calculated result increases as the current percentage of lifespan budget consumption increases.

[0205] The calculated value is used as the dynamic aging threshold at the current moment.

[0206] A dynamic aging threshold can be a dynamic limit value used to determine whether the accumulated aging in a region has reached a level requiring intervention. This threshold is not fixed, but can be adjusted according to the actual wear and tear of the chip during use, so that the aging management strategy can match the actual condition of the chip at different stages of its life cycle.

[0207] When determining the dynamic aging threshold, a base threshold and an aging acceleration factor preset for the chip can be read. The base threshold can represent a reference value for the upper limit of thermal age that a region of the chip is allowed to accumulate in a brand new or initial state. The aging acceleration factor can be a coefficient used to adjust the rate at which the threshold changes with chip aging; this coefficient can be determined based on chip material properties or reliability test data, and this disclosure does not limit it.

[0208] In addition, the current lifetime budget consumption percentage of the chip can be obtained. The lifetime budget consumption percentage is a dynamic parameter that characterizes the proportion of the chip's total expected lifetime that has been consumed since it was put into use. This percentage can be estimated based on the chip's equivalent cumulative operating time under specific operating conditions (such as temperature, voltage stress, and current), for example, by accumulating the thermal age of each region and converting it into a percentage from the total chip design lifetime, or by tracking it through a lifetime model counter integrated inside the chip. This parameter can be updated periodically (e.g., every 24 hours) and stored in non-volatile memory to dynamically adjust the strictness of aging management, so that the protection strategy can be adapted to the specific stage of the chip's life cycle.

[0209] Furthermore, the base threshold, the aging acceleration factor, and the percentage of lifetime budget consumption can be substituted into a preset adjustment model for calculation. The adjustment model can be configured such that the calculated value increases with the current percentage of lifetime budget consumption. For example, in a specific implementation of the adjustment model, the dynamic aging threshold can be calculated using the following relationship:

[0210] Threshold = BaseThreshold × (1 + α2 × BudgetUsed)

[0211] Where BaseThreshold is the base threshold, α2 is the aging acceleration factor, and BudgetUsed is the percentage of lifetime budget consumed. As the chip's lifetime budget is consumed, the dynamic aging threshold will increase accordingly, allowing more thermal age to accumulate in older areas before triggering a state transition. This can be understood as a strategy to adapt to aging hardware and optimize the use of remaining lifetime, that is, to extract the remaining value of the chip as quickly as possible while reducing protection for the chip. In this case, the value of α2, the aging acceleration factor, can be a positive number. In addition, the model can also be designed so that the threshold decreases as consumption increases, that is, to adopt a strategy of more protection as the chip ages. In this case, the value of α2, the aging acceleration factor, can be a negative number, in order to protect older chips as much as possible and delay the chip's warranty period.

[0212] The calculated value is used as the dynamic aging threshold at the current moment for subsequent comparison with the cumulative thermal age of each region. For example, assume a preset base threshold of 8,640,000 time units for a certain chip, and an aging acceleration factor (α2) of 0.5. After the chip has been running for a period of time, its current budget used percentage is estimated to be 30% (i.e., 0.3) using a built-in counter or lifetime model. Substituting into the adjustment model, the dynamic aging threshold is calculated as: Dynamic aging threshold = 8,640,000 × (1 + 0.5 × 0.3) = 8,640,000 × 1.15 = 9,936,000 time units. This calculated value is then used as the dynamic aging threshold for determining whether a state transition has been triggered for all regions.

[0213] In this embodiment, by reading a preset base threshold and an aging acceleration factor for the chip, the current lifetime budget consumption percentage of the chip is obtained. The base threshold, the aging acceleration factor, and the lifetime budget consumption percentage are then substituted into a preset adjustment model for calculation. The adjustment model is configured such that the calculated result increases with the current lifetime budget consumption percentage, and the calculated result is used as the dynamic aging threshold at the current moment. Therefore, the dynamic aging threshold can be dynamically adjusted according to the chip's real-time lifetime consumption status, making the aging management strategy no longer static and rigid. This allows for the use of a relatively conservative threshold in the early stages of the chip's lifespan to protect new hardware, while a threshold more suited to its aging state can be used in the later stages of the chip's lifespan. This results in a more refined balance between performance usage and lifespan extension, improving the adaptability and intelligence of the aging management strategy.

[0214] In one possible implementation, the method further includes:

[0215] If the current lifetime budget consumption percentage of the chip as a whole exceeds the global threshold, a graded aging avoidance operation is performed on the chip as a whole.

[0216] In addition to monitoring and operating individual regions, chip aging management can also incorporate a higher-level protection mechanism at the chip-wide level. This mechanism activates a protective strategy applicable to the entire chip when its overall lifespan reaches a critical level, serving as a supplement and upgrade to regional-level management.

[0217] When the percentage of the chip's overall current lifetime budget consumed exceeds a global threshold, a graded aging avoidance operation is performed on the entire chip. The percentage of the chip's overall current lifetime budget consumed characterizes the proportion of the chip's total expected lifetime that has been consumed since it was put into use. This percentage can be calculated based on a statistical summary of aging damage in each region or estimated using an independent chip-level lifetime model. The global threshold is a preset threshold value used to trigger chip-level global protection. This value can be set at a high level, such as 90%, to ensure that global intervention is only activated when the overall lifetime consumption is very significant.

[0218] When the percentage of the chip's current lifespan budget consumed exceeds this global threshold, the chip is determined to have entered the late, high-risk stage of its lifecycle. At this point, management will no longer be limited to individual areas; instead, a tiered aging avoidance operation will be performed on the entire chip, meaning the protection strategy will be expanded from local to global.

[0219] The chip as a whole is considered as an entity requiring unified management. Based on a preset global strategy, uniform performance and power consumption adjustments can be performed on the entire chip. For example, global avoidance operations may include: synchronously reducing the operating voltage and frequency of the entire chip to a conservative safety level; or, forcing the chip into a deep power-saving state, suspending most non-critical computing tasks to significantly reduce overall power consumption and heat generation; or, activating the chip's highest-level heat dissipation scheme and limiting maximum power.

[0220] In this embodiment, a tiered aging avoidance operation is performed on the entire chip when the percentage of its current lifetime budget consumption exceeds a global threshold. Thus, when the overall chip lifetime is detected to be nearing its designed end, a unified protection strategy covering the entire chip can be implemented, transcending the scope of regional autonomy. This global intervention, as a backup for regional management, provides a safety net when the chip's lifespan is nearing its end and the risk of widespread aging increases. By proactively reducing the overall performance load, it minimizes the possibility of global failure, ensuring that the chip maintains basic functional safety and data integrity even as it approaches the end of its lifespan. This achieves tiered closed-loop management of aging risks across the entire chip lifecycle and spatial scope.

[0221] As mentioned above, the chip partition management method disclosed herein can be implemented based on a firmware engine. Figure 3 This diagram illustrates an architecture of a chip partition management system according to an embodiment of the present disclosure, such as... Figure 3 As shown, this system performs hardware aging management on the GPU chip. In this system, various sensors integrated on the GPU chip (GPU Die) continuously collect raw sensor data such as temperature, voltage, and current, and transmit this data to the embedded MCU. The embedded MCU, acting as the control core, runs algorithms in the firmware engine. This engine processes the sensor data based on preset configuration parameters (such as risk thresholds and weighting coefficients) to calculate the aging risk score for each region and update the thermal ridge map (i.e., the cumulative thermal age and other status information of each region) stored in the shared SRAM. Based on the evaluation results, the firmware engine generates control commands and sends them to the GPU scheduler, guiding it to adjust task allocation to avoid high-risk areas. In addition, it sends commands to the voltage regulator to adjust the voltage or frequency of specific regions, thus completing a closed-loop management system from status awareness and risk assessment to dynamic control.

[0222] Figure 4 A flowchart illustrating a chip partition management method according to an embodiment of the present disclosure is shown, such as... Figure 4 As shown, firstly, operating status data for each chip region is collected, including temperature, voltage, and current. Then, based on this data, a dynamic aging risk score is calculated, and the region status is divided into low-risk, medium-risk, or high-risk states according to the score value (e.g., using 50 and 70 as boundaries). Each state corresponds to a different risk penalty coefficient (β_low, β_med, β_high). Next, based on the current temperature data of the region and its risk state, the region's thermal age increment is calculated, and this increment is continuously accumulated to obtain the region's cumulative thermal age. Afterward, it is determined whether the region's cumulative thermal age reaches or exceeds the dynamic aging threshold: if it does not exceed it, the region remains in a normal state and continues to participate in regular operations, with the firmware continuously monitoring it; if it exceeds it, region-level protection operations are triggered, such as marking the region as an avoidance zone, reducing its load, temporarily disabling its function, or initiating local cooling. Specific implementation methods can be found in the possible implementations provided in this disclosure, and will not be elaborated here. Simultaneously, the operating time of each region under abnormal states (warning, critical, high-risk, etc.) can be accumulated, summarized, and converted into a chip-level lifetime budget consumption percentage. Finally, determine whether this percentage exceeds the global threshold of 90%. If it does not exceed the threshold, dynamically adjust the dynamic aging threshold used in the next cycle based on the percentage and continue regional management. If it exceeds the threshold, trigger a global protection strategy, such as implementing global frequency reduction or initiating chip-level cooling, to ensure the overall safety of the chip.

[0223] Figure 5A block diagram of a chip partition management apparatus according to an embodiment of the present disclosure is shown, such as Figure 5 As shown, the image processing device 20 includes:

[0224] Data acquisition module 21 is used to acquire working status data of multiple areas of the chip;

[0225] The risk scoring calculation module 22 is used to calculate the aging risk score corresponding to each area based on the working status data.

[0226] The avoidance operation module 23 is used to perform graded aging avoidance operations on the corresponding areas based on the aging risk scores of each area.

[0227] In one possible implementation, the operating status data includes at least one of temperature change rate data, voltage fluctuation data, and current data;

[0228] The risk scoring calculation module 22 is used for:

[0229] The contribution value of thermal cycling damage is determined based on the temperature change rate data; and / or, the contribution value of dielectric breakdown damage is determined based on the voltage fluctuation data; and / or, the contribution value of electromigration damage is determined based on the current data.

[0230] The aging risk score is determined by a weighted sum of one or more of the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

[0231] In one possible implementation, the weighting coefficients used in the weighted sum are pre-calibrated in the following manner:

[0232] Thermal cycling stress, high voltage stress, and high current stress were applied to chip samples of the same specifications as the chip until observable aging failure occurred.

[0233] Record the time before failure corresponding to each of the three stresses;

[0234] Normalization is performed using the reciprocals of the time before thermal cycling failure, the time before high voltage failure, and the time before high current failure as proportional benchmarks to obtain the weighting coefficients corresponding to the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

[0235] In one possible implementation, the avoidance operation module 23 is used to:

[0236] If the aging risk score is greater than the first score threshold, a performance degradation action will be performed on the corresponding area.

[0237] If the aging risk score is less than the first scoring threshold but greater than or equal to the second scoring threshold, then the status information of the corresponding area is recorded.

[0238] If the aging risk score is less than the second score threshold, then no avoidance operation will be performed on the corresponding area.

[0239] In one possible implementation, the avoidance operation module 23 is used to:

[0240] Determine the cumulative thermal age for each region, which is used to characterize the aging degree of each region;

[0241] Based on the aging risk score and cumulative thermal age of each region, a graded aging avoidance operation is implemented for each region.

[0242] In one possible implementation, the avoidance operation module 23 is used to:

[0243] In each sampling period, the thermal age increment for the sampling period is calculated based on the temperature of the current area and the risk penalty coefficient corresponding to the aging risk score.

[0244] The thermal age increment is added to the historical cumulative thermal age of the current region to obtain the cumulative thermal age of the current region.

[0245] In one possible implementation, the avoidance operation module 23 is used to:

[0246] If the cumulative thermal age is less than the dynamic aging threshold, the aging management status of the corresponding area is determined to be normal, and no avoidance operation is performed.

[0247] In one possible implementation, the avoidance operation module 23 is used to:

[0248] If the cumulative thermal age reaches or exceeds the dynamic aging threshold and the aging risk score is lower than the first risk threshold, then the aging management status of the corresponding area is determined to be a warning status.

[0249] Record the warning status of the corresponding area and mark the corresponding area as a avoidance zone. The avoidance zone is used to indicate the area that needs to be avoided when assigning tasks in the future.

[0250] In one possible implementation, the avoidance operation module 23 is used to:

[0251] If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score is between the first risk threshold and a higher second risk threshold, then the aging management status of the corresponding area is determined to be a critical state.

[0252] Reduce the computational load allocated to the corresponding region and mark the corresponding region as a avoidance zone.

[0253] In one possible implementation, the avoidance operation module 23 is used to:

[0254] If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score reaches or exceeds the second risk threshold, then the aging management status of the corresponding area is determined to be a high-risk status.

[0255] Suspend the functions of the corresponding area, start the cooling process for the corresponding area, and mark the corresponding area as a avoidance zone.

[0256] In one possible implementation, the device further includes a cooling module for:

[0257] After the cooling process is initiated in a high-risk area, the corresponding area enters a cooling state.

[0258] During the cooling state, a cooling countdown is executed, and after the countdown ends, the corresponding area is restored to its normal state.

[0259] In one possible implementation, the process of determining the dynamic aging threshold includes:

[0260] The preset base threshold and aging acceleration factor for the chip are read;

[0261] Obtain the current lifetime budget consumption percentage of the chip;

[0262] The base threshold, the aging acceleration factor, and the percentage of lifespan budget consumption are substituted into a preset adjustment model for calculation. The adjustment model is configured such that the calculated result increases as the current percentage of lifespan budget consumption increases.

[0263] The calculated value is used as the dynamic aging threshold at the current moment.

[0264] In one possible implementation, the device further includes:

[0265] The global avoidance module is used to perform a graded aging avoidance operation on the entire chip when the current lifetime budget consumption percentage of the chip as a whole exceeds a global threshold.

[0266] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0267] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0268] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0269] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0270] Figure 6 This is a block diagram illustrating an apparatus for chip partition management according to an exemplary embodiment. For example, apparatus 1900 can be provided as a server or terminal device. (Refer to...) Figure 6 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0271] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0272] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0273] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0274] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0275] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0276] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0277] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0278] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0279] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0280] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip partitioning management method, characterized in that, include: Collect operating status data from multiple areas of the chip; Based on the aforementioned working status data, calculate the aging risk score corresponding to each region; Based on the aging risk scores of each region, graded aging avoidance operations are performed in the corresponding regions.

2. The method according to claim 1, characterized in that, The operating status data includes at least one of temperature change rate data, voltage fluctuation data, and current data. The calculation of the aging risk score for each region includes: The contribution value of thermal cycling damage is determined based on the temperature change rate data; and / or, the contribution value of dielectric breakdown damage is determined based on the voltage fluctuation data; and / or, the contribution value of electromigration damage is determined based on the current data. The aging risk score is determined by a weighted sum of one or more of the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

3. The method according to claim 2, characterized in that, The weighting coefficients used in the weighted sum are pre-calibrated in the following manner: Thermal cycling stress, high voltage stress, and high current stress were applied to chip samples of the same specifications as the chip until observable aging failure occurred. Record the time before failure corresponding to each of the three stresses; Normalization is performed using the reciprocals of the time before thermal cycling failure, the time before high voltage failure, and the time before high current failure as proportional benchmarks to obtain the weighting coefficients corresponding to the thermal cycling damage contribution value, the dielectric breakdown damage contribution value, and the electromigration damage contribution value.

4. The method according to claim 1, characterized in that, The step of performing tiered aging avoidance operations on the corresponding regions based on the aging risk scores of each region includes: If the aging risk score is greater than the first score threshold, a performance degradation action will be performed on the corresponding area. If the aging risk score is less than the first scoring threshold but greater than or equal to the second scoring threshold, then the status information of the corresponding area is recorded. If the aging risk score is less than the second score threshold, then no avoidance operation will be performed on the corresponding area.

5. The method according to claim 1, characterized in that, The step of performing tiered aging avoidance operations on the corresponding regions based on the aging risk scores of each region includes: Determine the cumulative thermal age for each region, which is used to characterize the aging degree of each region; Based on the aging risk score and cumulative thermal age of each region, a graded aging avoidance operation is implemented for each region.

6. The method according to claim 5, characterized in that, Determining the cumulative thermal age for each region includes: In each sampling period, the thermal age increment for the sampling period is calculated based on the temperature of the current area and the risk penalty coefficient corresponding to the aging risk score. The thermal age increment is added to the historical cumulative thermal age of the current region to obtain the cumulative thermal age of the current region.

7. The method according to claim 5, characterized in that, The implementation of graded aging avoidance operations in each region includes: If the cumulative thermal age is less than the dynamic aging threshold, the aging management status of the corresponding area is determined to be normal, and no avoidance operation is performed.

8. The method according to claim 5, characterized in that, The implementation of graded aging avoidance operations in each region includes: If the cumulative thermal age reaches or exceeds the dynamic aging threshold and the aging risk score is lower than the first risk threshold, then the aging management status of the corresponding area is determined to be a warning status. Record the warning status of the corresponding area and mark the corresponding area as a avoidance zone. The avoidance zone is used to indicate the area that needs to be avoided when assigning tasks in the future.

9. The method according to claim 5, characterized in that, The implementation of graded aging avoidance operations in each region includes: If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score is between the first risk threshold and a higher second risk threshold, then the aging management status of the corresponding area is determined to be a critical state. Reduce the computational load allocated to the corresponding region and mark the corresponding region as a avoidance zone.

10. The method according to claim 5, characterized in that, The implementation of graded aging avoidance operations in each region includes: If the cumulative thermal age reaches or exceeds the dynamic aging threshold, and the aging risk score reaches or exceeds the second risk threshold, then the aging management status of the corresponding area is determined to be a high-risk status. Suspend the functions of the corresponding area, start the cooling process for the corresponding area, and mark the corresponding area as a avoidance zone.

11. The method according to claim 10, characterized in that, The method further includes: After the cooling process is initiated in a high-risk area, the corresponding area enters a cooling state. During the cooling state, a cooling countdown is executed, and after the countdown ends, the corresponding area is restored to its normal state.

12. The method according to any one of claims 7-10, characterized in that, The process of determining the dynamic aging threshold includes: Read the preset base threshold and aging acceleration factor for the chip; Obtain the current lifetime budget consumption percentage of the chip; The base threshold, the aging acceleration factor, and the percentage of lifespan budget consumption are substituted into a preset adjustment model for calculation. The adjustment model is configured such that the calculated result increases as the current percentage of lifespan budget consumption increases. The calculated value is used as the dynamic aging threshold at the current moment.

13. The method according to claim 1, characterized in that, The method further includes: If the current lifetime budget consumption percentage of the chip as a whole exceeds the global threshold, a graded aging avoidance operation is performed on the chip as a whole.

14. A chip partition management device, characterized in that, include: The data acquisition module is used to collect operating status data from multiple areas of the chip; The risk scoring calculation module is used to calculate the aging risk score corresponding to each area based on the working status data. The avoidance operation module is used to perform graded aging avoidance operations on the corresponding areas based on the aging risk scores of each area.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 13.

16. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 13.

17. A computer program product comprising a computer program, or a non-volatile computer-readable storage medium carrying a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 13.

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