Advanced extensible interface bus matrix and electronic equipment

Abstract

The invention provides an advanced extensible interface bus matrix and electronic equipment. The advanced extensible interface bus matrix comprises multiple levels of selection logic; wherein the first-stage selection logic is connected with a main device; the last stage of selection logic is connected with the slave device; wherein the first-level selection logic comprises an anti-deadlock logic and a decoding logic; the stage number of the multi-stage selection logic is determined according to floorplan. According to the advanced extensible interface bus matrix, the optimal logic data size can be guaranteed through the multi-stage selection logic, meanwhile, winding resources do not need to be added, the problem that back-end physical implementation is difficult can be solved, design redundancy can be avoided, and both the logic data size and the design redundancy can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, relates to an advanced extensible interface bus and an electronic device matrix. BACKGROUND

[0002] AXI (Advanced eXtensible Interface) is a bus protocol, and the AXI bus is an on-chip bus oriented to high performance, high bandwidth and low latency.

[0003] The AXI bus matrix (AXI Interconnect) is a hardware module for connecting multiple AXI master devices and slave devices, and its core function is to provide an efficient switching mechanism similar to the switching matrix in a network switch. It is implemented by interconnecting IP cores, supports routing data requests from multiple master devices to target slave devices, and thus optimizes system resource allocation and communication efficiency.

[0004] The existing AXI bus matrix, as shown in FIG. 1, needs to increase the wiring and logic resources to ensure the optimal amount of logical data, which has great challenges for back-end physical implementation. Figure 1 SUMMARY In order to solve one of the above technical defects, the present application provides an advanced extensible interface bus matrix and an electronic device.

[0005] In a first aspect, the present application provides an advanced extensible interface bus matrix, comprising: a multi-stage selection logic. The first-stage selection logic is connected to the master device.

[0006] The last-stage selection logic is connected to the slave device. The first-stage selection logic includes anti-locking logic and decoding logic, and the number of stages of the multi-stage selection logic is determined according to the floorplan. Optionally, the upper-stage selection logic outputs a selection signal to the lower-stage selection logic.

[0007] Optionally, the selection logic further includes a beat logic.

[0008] Optionally, the advanced extensible interface bus introduces a write address channel cache. The anti-locking logic is:

[0009] The anti-locking logic simultaneously receives a first command sent by the master device through the write address channel and a first data sent by the master device through the write data channel. The anti-locking logic simultaneously receives a first command sent by the master device through the write address channel and a first data sent by the master device through the write data channel. When a first command is received, the received first command is sent to the slave device, and the received first command is stored in the write address lane buffer, and the write address lane is blocked at the same time; The received first data is sent to the slave device; When the WLAST signal is high, the write address lane is unblocked, and the steps of when a first command is received, the received first command is sent to the slave device, and the received first command is stored in the write address lane buffer, and the write address lane is blocked at the same time, and subsequent steps are repeatedly executed.

[0010] Optionally, a flag bit is introduced in the write data lane of the advanced extensible interface bus; The initial value of the flag bit is a first value; When a first command is received, the flag bit is updated to a second value; The received first data is sent to the slave device, including: When the flag bit is the second value, the received first data is sent to the slave device; When the WLAST signal is high, the write address lane is unblocked, including: When the WLAST signal is high, the flag bit is updated to the first value; When the flag bit is the first value, the write address lane is unblocked.

[0011] Optionally, the received first command is sent to the slave device, including: The received first command is sent to the slave device through the lower selection logic; The received first data is sent to the slave device, including: The received first data is sent to the slave device through the lower selection logic.

[0012] Optionally, the first selection logic is connected to the master device through a master execution module; The last selection logic is connected to the slave device through a slave execution module; The master execution module is used for monitoring the master device and taking over the master device when the master device is abnormal; The slave execution module is used for monitoring the slave device and taking over the slave device when the slave device is abnormal.

[0013] Optionally, the slave execution module includes a write data buffer, a read data buffer, a write command first-in-first-out queue, a slave state machine, and a slave synchronization module; The write data buffer, the read data buffer, and the write command first-in-first-out queue are respectively connected to the advanced extensible interface bus matrix, and the write data buffer, the read data buffer, and the write command first-in-first-out queue are also respectively connected to the slave state machine. The slave state machine is further connected with the Advanced Extensible Interface Bus matrix, and the slave state machine is further connected with the slave device; The slave state machine is further connected with the Advanced Extensible Interface Bus matrix, and the slave state machine is further connected with the slave device; The slave state machine is configured to receive write command response data and / or read command response data of the slave device, wherein the write command response data at least comprises a first identification ID of the response write command, and the read command response data at least comprises a second ID of the response read command and a data read length of data corresponding to the read command; The write data buffer is configured to buffer the write command response data and process transmission of the write response channel; The read data buffer is configured to buffer a third ID of the read command and a target read length corresponding to the read command transmitted by the read address channel, buffer read command response data, and process transmission of the read data channel; The write command first-in-first-out queue is configured to store a fourth ID of the write command transmitted by the write address channel; The slave synchronization module is configured to synchronize a slave takeover enable signal of the slave device when the slave device is abnormal; The slave state machine is further configured to start a takeover of the slave device based on the read data buffer and / or the write data buffer and the write command first-in-first-out queue after synchronization to the slave takeover enable signal, and stop the takeover of the slave device when the slave takeover enable signal is released and a stop condition is met.

[0014] Optionally, the master execution module comprises a master state machine, a master synchronization module, and an interception module. The master synchronization module is connected with the interception module. The master state machine is connected with the interception module, and the interception module is connected with the master device. The master state machine is further connected with the Advanced Extensible Interface Bus matrix, and the master state machine is further connected with the master device. The master synchronization module is configured to synchronize a master takeover enable signal of the master device when the master device is abnormal. The master state machine is configured to store a data transmission length of first data transmitted through the write data channel, start a takeover of the master device based on the data transmission length after synchronization to the master takeover enable signal, and stop the takeover of the master device when the master takeover enable signal is released and a stop condition is met. The interception module is configured to intercept the first data transmitted by the write data channel before a handshake of address channel transmission is completed after starting the takeover of the master device.

[0015] In a second aspect, the application provides an electronic device comprising the Advanced Extensible Interface Bus matrix according to the first aspect.

[0016] The application provides a high-level extensible interface bus matrix and an electronic device, the high-level extensible interface bus matrix comprising: multi-stage selection logic; wherein the first-stage selection logic is connected with a master device; the last-stage selection logic is connected with a slave device; wherein the first-stage selection logic comprises anti-lock logic and decoding logic; the number of stages of the multi-stage selection logic is determined according to a floor plan. The high-level extensible interface bus matrix of the application can ensure optimal logic data volume without increasing wire winding and logic resources, can solve the problem of difficult back-end physical implementation, and can avoid design redundancy, achieving both. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings described herein are used to provide further understanding of the application, form a part of the application, and the illustrative embodiments of the application and the description thereof are used to explain the application, and do not constitute improper limitations on the application. In the drawings: Figure 1 It is a structural schematic diagram of an existing high-level extensible interface bus matrix; Figure 2 It is a structural schematic diagram of a first high-level extensible interface bus matrix provided by the embodiment of the application; Figure 3 It is a structural schematic diagram of a second high-level extensible interface bus matrix provided by the embodiment of the application; Figure 4 It is a principle schematic diagram of a first high-level extensible interface bus anti-lock method provided by the embodiment of the application; Figure 5 It is a principle schematic diagram of a second high-level extensible interface bus anti-lock method provided by the embodiment of the application; Figure 6 It is a principle schematic diagram of a third high-level extensible interface bus anti-lock method provided by the embodiment of the application; Figure 7 It is a principle schematic diagram of a fourth high-level extensible interface bus anti-lock method provided by the embodiment of the application; Figure 8 It is a structural schematic diagram of a third high-level extensible interface bus matrix provided by the embodiment of the application; Figure 9 It is a structural schematic diagram of a fourth high-level extensible interface bus matrix provided by the embodiment of the application; Figure 10 It is a structural schematic diagram of a first master execution module provided by the embodiment of the application; Figure 11 It is a structural schematic diagram of a second master execution module provided by the embodiment of the application; Figure 12 It is a structural schematic diagram of a third master execution module provided by the embodiment of the application; Figure 13 A first structure diagram of a slave execution module provided in an embodiment of the present application is shown in FIG. 1. Figure 14 A second structure diagram of a slave execution module provided in an embodiment of the present application is shown in FIG. 2. Figure 15 A third structure diagram of a slave execution module provided in an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0018] In order to make the technical solutions and advantages in the embodiments of the present application clearer, the exemplary embodiments of the present application are further described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0019] In the process of implementing the present application, the inventors found that the AXI bus matrix (AXI Interconnect) is a hardware module used to connect multiple AXI master devices and slave devices, and its core function is to provide an efficient switching mechanism, similar to the switching matrix in a network switch. It is implemented by interconnecting IP cores, supporting routing data requests from multiple master devices to target slave devices, thereby optimizing system resource allocation and communication efficiency. The existing AXI bus matrix, as shown in FIG. 1, needs to increase the number of wires and logic resources to ensure optimal logic data volume, which poses a great challenge to the back-end physical implementation. Figure 1

[0020] To solve the above problems, the present application provides a high-level extensible interface bus matrix and an electronic device. The high-level extensible interface bus matrix comprises: multi-stage selection logic; wherein the first stage selection logic is connected with the master device; the last stage selection logic is connected with the slave device; wherein the first stage selection logic comprises anti-locking logic and decoding logic; the number of stages of the multi-stage selection logic is determined according to the floorplan. The high-level extensible interface bus matrix of the present application can ensure optimal logic data volume without increasing the number of wires and logic resources through multi-stage selection logic, which can solve the problem of difficult back-end physical implementation and avoid design redundancy, achieving both.

[0021] Referring to FIG. 1, Figure 2 The present embodiment provides a high-level extensible interface (AXI) bus matrix, which comprises: multi-stage selection logic.

[0022] ​The number of stages of the multi-stage selection logic can be determined according to the floorplan. That is, the number of stages of the multi-stage selection logic and the branching of each stage of the selection logic are completely divided according to the back-end physical implementation of the floorplan. The embodiment does not limit the number of stages of the multi-stage selection logic and the branching of each stage of the selection logic. The embodiment also does not limit the determination scheme of the floorplan and the content of the floorplan.

[0023] The first stage of the selection logic is connected to the master device, and the last stage of the selection logic is connected to the slave device.

[0024] The first stage of the selection logic includes the anti-lock logic and the decoding logic, and the anti-lock logic is used for anti-lock, and the decoding logic is used for address decoding.

[0025] In the implementation, only the first stage of the selection logic includes the anti-lock logic and the decoding logic, and the anti-lock logic and the decoding logic are not included in the non-first stage of the selection logic. That is, only the most initial selection logic in the Advanced eXtensible Interface (AXI) bus matrix includes the anti-lock logic and the decoding logic, and the subsequent selection logic does not include the anti-lock logic and the decoding logic.

[0026] In addition, the Advanced eXtensible Interface (AXI) bus matrix provided by the embodiment can also not include the logic register.

[0027] The upper stage of the selection logic outputs the selection signal to the lower stage of the selection logic. That is, the upper stage of the selection logic is cascaded, and the selection signal output by the first stage of the selection logic is output along the path during the cascading.

[0028] In addition, in the implementation, each stage of the selection logic can further include the beat logic, so as to add the beat logic in the middle of the selection signal output along the path.

[0029] Taking 1 master device and 6 slave devices as an example, an exemplary implementation structure of the Advanced eXtensible Interface (AXI) bus matrix provided by the embodiment is shown in FIG. 6. Figure 3

[0030] In the implementation, the decoding logic can be address decode decoding logic.

[0031] The anti-lock logic can be a plurality of groups of CDAS (Cyclic Dependency Avoidance Schemes) anti-lock logic and / or SAS (Single Active Slave) logic (that is, write operation anti-lock logic).

[0032] ​The implementation scheme of the SAS (Single Active Slave) logic (i.e. the write operation anti-lock logic) is as follows: The write address channel of the advanced extensible interface bus introduces a write address channel buffer.

[0033] The anti-lock logic is as follows: The first command sent by the master through the write address channel and the first data sent by the master through the write data channel are received simultaneously. For the convenience of description, this process is recorded as step 401.

[0034] When a first command is received, the received first command is sent to the slave, and the received first command is stored in the write address channel buffer, and the write address channel is back-pressured. For the convenience of description, this process is recorded as step 402.

[0035] The received first data is sent to the slave. For the convenience of description, this process is recorded as step 403.

[0036] When the WLAST signal is high, the back-pressure of the write address channel is released. Then, the steps of receiving a first command, sending the received first command to the slave, storing the received first command in the write address channel buffer, and back-pressuring the write address channel (i.e. steps 402 to 404) are repeatedly executed until all data is received. For the convenience of description, this process is recorded as step 404.

[0037] In step 401, the first data is continuously received. The first command is also continuously received when the write address channel (AW) is not back-pressured.

[0038] The implementation process of storing the received first command in the write address channel (AW) buffer is as follows: if the write address channel (AW) buffer is empty, the received first command is directly stored in the write address channel (AW) buffer. If the write address channel (AW) buffer is not empty, the write address channel (AW) buffer is emptied first, and then the received first command is stored in the write address channel (AW) buffer.

[0039] When the WLAST signal is high, the process of releasing the back-pressure of the write address channel is as follows: According to the AXI protocol specification, the WLAST signal is part of the write data channel (W) and is sent together with the data (i.e., the first data). That is, in a write operation, when the master sends data (i.e., the first data) through the write data channel (W), the WLAST signal is pulled high (to a high level) during the transmission of the last data packet, indicating that the current data (i.e., the first data) transmission is the last data packet of the current write transaction. As part of the write data channel (W), the transmission of the WLAST signal is synchronized with the data (i.e., the first data), ensuring that the end of the data (i.e., the first data) transmission can be identified in a timely manner during the last stage of data transmission, avoiding data loss or misprocessing.

[0040] Therefore, in step 404, when the WLAST signal is high, it indicates that the first data corresponding to the first command in the write address channel buffer has been sent, and the back pressure on the write address channel (AW) can be released to receive the first data corresponding to the next first command, i.e., to repeat the steps of receiving a first command, sending the received first command to the slave device, storing the received first command in the write address channel buffer, and back-pressuring the write address channel (AW) (i.e., steps 402 to 404).

[0041] It should be noted that the above only describes the implementation of the SAS (Single Active Slave) logic (i.e., the write operation anti-locking logic) in the order of steps 401, 402, 403, and 404. In actual implementation, the embodiments and subsequent embodiments do not limit the execution order between steps 401, 402, 403, and 404.

[0042] For example, the master sends data through the write address channel (AW, e.g., the master AW channel in Figure 4 ) and the write data channel (W, e.g., the master W channel in Figure 4 ). For example, the master sends AW0 and AW1 through the write address channel (AW) at different times, and the master sends W01, W02, W03, W04, W11, and W12 through the write data channel (W) at different times.

[0043] Since AW0 and AW1 are not sent at the same time, they will not be received at the same time. W01, W02, W03, W04, W11, and W12 are not sent at the same time, so they will not be received at the same time.

[0044] As shown in Figure 5 , at t0, step 401 is performed to receive the first command (e.g., AW0) sent by the master through the write address channel (AW) at the same time. Figure 5The first data (such as AW0 in the middle) and the master device sent through the write data channel (W) are... Figure 5 (W01 in the middle), and as Figure 5 As shown, the WLAST signal of the write data channel (W) is low at time t0. When AW0 is received at time t0 (i.e., a first command is received), the received first command (such as...) will be sent to the data channel (W) via step 402. Figure 5 The AW0 in the middle is sent to the slave device, and at the same time, the first command received (such as...) is sent to the slave device. Figure 5 AW0 in the address channel cache (e.g.) is stored in the write address channel cache. Figure 4 In the AW channel cache), at the same time, the reverse pressure write address channel (AW, such as...) is also in the cache. Figure 4 The master device AW channel in the middle). At the same time, the first data received (such as) is processed through step 403. Figure 5 The W01 in the middle is sent to the slave device.

[0045] At time t1, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W02), and as Figure 5 As shown, at time t1, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 4 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 4 AW0 is still stored in the AW channel buffer. Meanwhile, at time t1, the received first data (such as...) will be processed through step 403. Figure 5 The W02 shown is sent to the slave device.

[0046] At time t2, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5 As shown in W03), and as Figure 5 As shown, at time t2, the WLAST signal of the write data channel (W) is low. This is because at this time, the write address channel (AW, as shown...) is also low. Figure 4 The master device's AW channel is back-pressurized, therefore the first command sent by the master device through the write address channel (AW) will not be received in step 401, and the write address channel buffer (such as...) Figure 4 AW0 is still stored in the AW channel buffer. Meanwhile, at time t2, the received first data (such as...) will be processed through step 403. Figure 5 The W03 shown is sent to the slave device.

[0047] At time t3, the first data sent by the master device through the write data channel (W) is still received via step 401 (e.g., ...). Figure 5as shown in W04), but as Figure 5 The WLAST signal of the write data channel (W) is high at time t3 as shown, so the back pressure of the write address channel (AW) is released through step 404. Since the back pressure of the write address channel (AW) is released, the first command sent by the master through the write address channel (AW) is also received in step 401 at time t3 (e.g., AW1 in Figure 4 ), while the write address channel buffer (e.g., the AW channel buffer in Figure 4 ) is emptied and AW1 is stored in the write address channel buffer (e.g., the AW channel buffer in Figure 4 ), while the write address channel (AW, e.g., the master AW channel in Figure 4 ) is back-pressured. At the same time, the received first command (e.g., AW1 in Figure 5 ) is sent to the slave through step 402 at time t3, and the received first data (e.g., W04 in Figure 5 ) is sent to the slave through step 403 at time t3.

[0048] The first data sent by the master through the write data channel (W) is still received in step 401 at time t4 (e.g., W11 in Figure 5 ), and the WLAST signal of the write data channel (W) is low at time t4 as shown in Figure 5 . Since the write address channel (AW, e.g., the master AW channel in Figure 4 ) is back-pressured at this time, the first command sent by the master through the write address channel (AW) is not received in step 401, and AW1 is still stored in the write address channel buffer (e.g., the AW channel buffer in Figure 4 ). At the same time, the received first data (e.g., W11 in Figure 5 ) is sent to the slave through step 403 at time t4.

[0049] The first data sent by the master through the write data channel (W) is still received in step 401 at time t5 (e.g., W12 in Figure 5 ), and the WLAST signal of the write data channel (W) is low at time t5 as shown in Figure 5 . Since the write address channel (AW, e.g., the master AW channel in Figure 4 ) is back-pressured at this time, the first command sent by the master through the write address channel (AW) is not received in step 401, and AW1 is still stored in the write address channel buffer (e.g., the AW channel buffer in Figure 4 ). At the same time, the received first data (e.g., W12 in Figure 5 ) is sent to the slave through step 403 at time t5.

[0050] … This is repeated until all write data sent by the master is received.

[0051] Taking 1 master and 3 slaves as an example, an exemplary schematic diagram of the anti-lock method of the high-level extensible interface bus is shown in Figure 5

[0052] In addition, in the specific implementation, the write data channel (W) of the high-level extensible interface bus can also introduce a flag bit, as shown in Figure 5 The flag bit occupies 1 bit. The initial value of the flag bit is a first value, for example, 0.

[0053] The flag bit represents whether the write address channel (AW) receives data (i.e., a first command).

[0054] In this case, step 401 will still receive the first command sent by the master through the write address channel (AW) and the first data sent by the master through the write data channel (W) at the same time. However, when a first command is received, the flag bit will be updated to a second value, for example, 1. That is, when the flag bit is 0, it means that the write address channel (AW) has not received data (i.e., a first command), and when the flag bit is 1, it means that the write address channel (AW) has received data (i.e., a first command).

[0055] In step 402, when a first command is received, the received first command is sent to the slave, at the same time, the received first command is stored in the write address channel buffer, and the write address channel (AW) is back-pressured.

[0056] In step 403, the implementation process of sending the received first data to the slave is as follows: when the flag bit is the second value, the received first data is sent to the slave. That is, only after the write address channel (AW) receives data (i.e., a first command) is the first data sent to the slave.

[0057] ​The process of releasing the back pressure of the write address channel (AW) in step 404 when the WLAST signal is high is as follows: when the WLAST signal is high, the flag bit is updated to a first value, and when the flag bit is the first value, the back pressure of the write address channel (AW) is released. That is, when the WLAST signal of the write data channel (W) is high, it means that the first data corresponding to the current first command has been received, and the first data received thereafter should correspond to a new first command, so the flag bit is updated to the first value, and the first data received thereafter is stopped from being sent to the slave device. Then, when the flag bit is the first value, the back pressure of the write address channel (AW) is released, so that after being released, when step 401 is performed again, the first command sent by the master device through the write address channel (AW) is received again. The process of receiving a first command, sending the received first command to the slave device, storing the received first command in the write address channel buffer (such as the AW channel buffer in Figure 4 ), back-pressuring the write address channel (AW), and the subsequent steps (i.e., steps 402 to 404) are repeated until all data is received.

[0058] If the first command is received again, the flag bit is updated to the second value again, and then after the flag bit is updated to the second value, the second value received thereafter is sent to the slave device.

[0059] Similarly, for the write address channel (AW), a write address channel buffer (such as the AW channel buffer) is introduced, and for the write data channel (W), a flag bit is introduced. The above only describes the order of steps 401, 402, 403, and 404, and the execution order of steps 401, 402, 403, and 404 is not limited in the specific implementation.

[0060] Still taking Figure 4 as an example, the master device sends data through the write address channel (AW, such as the master device AW channel in Figure 5 ) and the write data channel (W, such as the master device W channel in Figure 5 ) at the same time. For example, the master device sends AW0 and AW1 through the write address channel (AW) at different times, and the master device sends W01, W02, W03, W04, W11, and W12 through the write data channel (W) at different times. The initial value of the flag bit is 0.

[0061] At t0, the first command (such as AW0 in Figure 5 ) sent by the master device through the write address channel (AW) and the first data (such as W01 in Figure 4 ) sent by the master device through the write data channel (W) are received through step 401 at the same time, and Figure 4The WLAST signal of the write data channel (W) is low at time t0. When the AW0 (i.e. a first command) is received at time t0, the flag bit is updated to 1 (i.e. the second value), and the received first command (e.g. AW0 in Figure 4 ) is sent to the slave device through step 402, while the received first command (e.g. AW0 in Figure 4 ) is stored in the write address channel buffer (e.g. the AW channel buffer in Figure 5 ), and the write address channel (AW, e.g. the master AW channel in Figure 5 ) is blocked. At the same time, the received first data (e.g. W01 in Figure 5 ) is sent to the slave device through step 403.

[0062] At time t1, the first data (e.g. W02 in Figure 5 ) sent by the master through the write data channel (W) is still received through step 401, and the WLAST signal of the write data channel (W) is low at time t1 as shown in Figure 4 . Because the write address channel (AW, e.g. the master AW channel in Figure 4 ) is blocked at this time, the first command sent by the master through the write address channel (AW) is not received in step 401, and the AW0 is still stored in the write address channel buffer (e.g. the AW channel buffer in Figure 5 ). At the same time, the flag bit is 1 (i.e. the second value), so the received first data (e.g. W02 in Figure 5 ) is sent to the slave device through step 403 at time t1.

[0063] At time t2, the first data (e.g. W03 in Figure 5 ) sent by the master through the write data channel (W) is still received through step 401, and the WLAST signal of the write data channel (W) is low at time t2 as shown in Figure 4 . Because the write address channel (AW, e.g. the master AW channel in Figure 4 ) is blocked at this time, the first command sent by the master through the write address channel (AW) is not received in step 401, and the AW0 is still stored in the write address channel buffer (e.g. the AW channel buffer in Figure 5 ). At the same time, the flag bit is 1 (i.e. the second value), so the received first data (e.g. W03 in Figure 4 ) is sent to the slave device through step 403 at time t2.

[0064] At time t3, the first data (e.g. W04 in Figure 8 ) sent by the master through the write data channel (W) is still received through step 401, but the WLAST signal of the write data channel (W) is high at time t3 as shown in Figure 8The WLAST signal of the write data channel (W) is high at the time t3, so the flag bit is updated to 0 through the step 404, and the back pressure of the write address channel (AW) is released when the flag bit is 0. Since the back pressure of the write address channel (AW) is released, the first command (such as AW1 in Figure 8 ) sent by the master through the write address channel (AW) is also received in the step 401 at the time t3, at the same time, the write address channel buffer (such as the AW channel buffer in Figure 3 ) is emptied, and AW1 is stored in the write address channel buffer (such as the AW channel buffer in Figure 3 ), and the write address channel (AW, such as the master AW channel in Figure 3 ) is back pressured. When AW1 (i.e. a first command) is received at the time t3, the flag bit is updated to 1 (i.e. a second value). At the same time, the received first command (such as AW1 in Figure 3 ) is sent to the slave through the step 402 at the time t3, and the received first data (such as W04 shown in Figure 9 ) is sent to the slave through the step 403.

[0065] The first data (such as W11 shown in Figure 10 ) sent by the master through the write data channel (W) is still received through the step 401 at the time t4, and the WLAST signal of the write data channel (W) is low at the time t4 as shown in Figure 10 . Since the write address channel (AW, such as the master AW channel in Figure 10 ) is back pressured at this time, the first command sent by the master through the write address channel (AW) is not received in the step 401, and AW1 is still stored in the write address channel buffer (such as the AW channel buffer in Figure 10 ). At the same time, the flag bit is 1 (i.e. a second value), and the received first data (such as W11 shown in Figure 10 ) is sent to the slave through the step 403 at the time t4.

[0066] The first data (such as W12 shown in Figure 10 ) sent by the master through the write data channel (W) is still received through the step 401 at the time t5, and the WLAST signal of the write data channel (W) is low at the time t5 as shown in Figure 10 . Since the write address channel (AW, such as the master AW channel in Figure 10 ) is back pressured at this time, the first command sent by the master through the write address channel (AW) is not received in the step 401, and AW1 is still stored in the write address channel buffer (such as the AW channel buffer in Figure 10AW channel buffer) is still stored. At the same time, the flag bit is 1 (i.e. the second value), and the received first data (e.g. W12 as shown in Figure 10 ) is sent to the slave device through step 403 at t5.

[0067] … This is repeated until all the write data sent by the master device is received.

[0068] In this way, the current first command corresponding to the first data is represented by the write address channel buffer (e.g. the AW channel buffer in Figure 10 ), the current receipt of the first command is represented by the flag bit, and the anti-lock of the write operation is completed by one buffer and 1 bit.

[0069] Figure 10 Fig. 1 shows a feasible structure of the first stage selection logic of the Advanced eXtensible Interface (AXI) bus matrix provided by the embodiment, which implements the SAS (Single Active Slave) logic through steps 401 to 404, Figure 10 and other channels such as the read address channel (AR) and the like.

[0070] As shown in Figure 10 , the first stage selection logic of the Advanced eXtensible Interface bus matrix receives the first command sent by the master device through the write address channel (AW) and the first data sent by the master device through the write data channel (W) at the same time through step 401.

[0071] When a first command is received through 402, the received first command is sent to the slave device, the received first command is stored in the write address channel buffer, and the write address channel (AW) is back-pressured. When the received first command is sent to the slave device, if the slave device is a slave device directly output by the first stage selection logic (e.g. slave device 0 in Figure 11 ), the received first command is sent to the slave device 0; if the slave device is not a slave device directly output by the first stage selection logic (e.g. slave device 1, slave device 2, slave device 3, slave device 4, or slave device 5 in Figure 11 ), the received first command is sent to the slave device (e.g. slave device 2) through the lower stage selection logic.

[0072] The received first data is sent to the slave device through step 403. When the received first data is sent to the slave device, if the slave device is a slave device directly output by the first stage selection logic (e.g. slave device 0 in Figure 10if the slave is not the slave 0 (e.g., the slave is the slave 1, the slave 2, the slave 3, the slave 4, or the slave 5), then the received first data is sent to the slave through the lower level selection logic (e.g., if the slave is the slave 5, then the received first data is sent to the slave 5 through the second level selection logic and the third level selection logic). Figure 11

[0073] In addition, in the specific implementation, the AXI bus matrix provided by the embodiment is connected with the master and the slave. If one device is abnormal (e.g., is stuck), the AXI bus is hung up because the device cannot respond. In order to prevent the AXI bus from being hung up because the device cannot respond, when the first level selection logic is connected with the master, the first level selection logic is connected with the master through the master execution module; when the last level selection logic is connected with the slave, the last level selection logic is connected with the slave through the slave execution module, as shown in Figure 10

[0074] The master execution module is used for monitoring the master and taking over the master when the master is abnormal.

[0075] The slave execution module is used for monitoring the slave and taking over the slave when the slave is abnormal.

[0076] 1. Master execution module The master execution module is hung between the master and the AXI bus matrix, and is used for monitoring the master and taking over the master when the master is abnormal.

[0077] As shown in Figure 10 , the master execution module includes: a master state machine (e.g., the FSM in Figure 11 ), a master synchronization module (e.g., the Sync in Figure 12 ), and an interception module (e.g., the mst_wintercept in Figure 13 ).

[0078] The master synchronization module is connected with the interception module.

[0079] The master state machine is connected with the interception module, and the interception module is connected with the master.

[0080] The master state machine is also connected with the AXI bus matrix, and the master state machine is connected with the master.

[0081] 1. Master synchronization module ​​The main synchronization module is configured to synchronize a main takeover enable signal of the main device when the main device is abnormal.

[0082] That is, when the main device is normal, the main synchronization module does not receive the main takeover enable signal, as shown in Figure 13 At this time, the main state machine only transmits data and does not perform any processing.

[0083] When the main device needs to read data, the main device initiates a read command (including a read address, a length of read data, etc.), which enters the main state machine (such as the FSM in Figure 13 Meanwhile, the main state machine (such as the FSM in Figure 13 transmits the read command to the slave device through an address read channel (AR). Read data (which is read by the slave device based on the read command) and response information (which is response information of the slave device executing the read command) returned by a read data channel (R) also enter the main state machine (such as the FSM in Figure 13 Meanwhile, the main state machine (such as the FSM in Figure 13 transmits the read data and the response information to the main device.

[0084] When the main device needs to write data, the main device initiates a write command (including a to-be-written address, a length of write data, etc.), which enters the main state machine (such as the FSM in Figure 13 Meanwhile, the main state machine (such as the FSM in Figure 13 transmits the write command to the slave device through an address write channel (AW); in addition, the write data also enters the main state machine (such as the FSM in Figure 13 Meanwhile, the main state machine (such as the FSM in Figure 13 transmits the write command to the slave device through a write data channel (W). Response information (which is response information of the slave device executing the write command) returned by a write response channel (B) also enters the main state machine (such as the FSM in Figure 13 Meanwhile, the main state machine (such as the FSM in Figure 13 transmits the response information to the main device.

[0085] If the main device is abnormal (such as the main device being dead), the main device sends a main takeover enable signal (such as AXI_ISO_EN in Figure 13 The main synchronization module receives the main takeover enable signal (namely, AXI_ISO_EN) and synchronizes the main takeover enable signal (namely, AXI_ISO_EN) to the main state machine. In this way, Figure 13 synchronization of the main takeover enable signal between the main synchronization module and the main state machine is achieved.

[0086] 2) Main state machine The master state machine is configured to store a data transmission length of the first data transmitted through the write data channel, and enable the takeover of the master device based on the data transmission length after synchronizing to the master takeover enable signal. The master state machine stops the takeover of the master device after the master takeover enable signal is released and a stop condition is met.

[0087] The stop condition is that the transmission processing in the current module is completed.

[0088] For example, when the master device is normal, the master synchronization module does not receive the master takeover enable signal, as shown in FIG. 2, at this time, the master state machine only transmits data. For this case, when the read command is transmitted, no processing is performed in addition to the transmission. However, when the write command is transmitted, in addition to the transmission, the data transmission length of the first data transmitted through the write data channel (W) is stored. Figure 13

[0089] It should be noted that the ID (Identity, identity) of the write command is not recorded here, because the AXI 4 and subsequent protocols have the following requirements for write data: The transmission of the write data channel (W) must be strictly in address order, that is, the write data channel (W) has order preservation. That is, the write data must be transmitted in address order, that is, the data of the later write command cannot arrive at the slave device before the write command. Based on this requirement, the first data transmitted by the write data channel (W) must be the write command corresponding to the current write command, so there is no need to record the ID of the write command to know the write command corresponding to the data.

[0090] When the master state machine synchronizes to the master takeover enable signal, it indicates that the master device has abnormally and cannot continue to send commands and / or data, etc. At this time, the master state machine enables the takeover of the master device based on the data transmission length, and continues to respond to the advanced extensible interface (AXI) bus matrix instead of the master device. During this period, the master device can perform repair operations such as restarting, and when the master device is normal again and the transmission processing in the current module is completed, the transmission of the master takeover enable signal is stopped, at this time the master synchronization module no longer receives the master takeover enable signal (i.e. the master state machine is synchronized to the master takeover enable signal as shown in FIG. 2), the master state machine cannot synchronize to the master takeover enable signal, and the master state machine is released. After the master takeover enable signal is released and the transmission processing in the current module is completed, the master state machine stops the takeover of the master device and restores the data transmission of the master device. For this case, when the read command is transmitted, no processing is performed in addition to the transmission. However, when the write command is transmitted, in addition to the transmission, the data transmission length of the first data transmitted through the write data channel (W) is stored. Figure 13 Figure 13

[0091] ​​​After the master state machine takes over the master device, for a read command, the master device mainly receives the read data returned by the read data channel (R), so the master state machine can continue to receive the read data returned by the read data channel (R). For a write command, the master device needs to continue to send the write data, and there is no need to maintain the transmission of the write response channel (B), so the ready signal of the write response channel (B) can be continuously pulled high. For the write data, the master state machine is used to obtain the target sending length after synchronization to the master takeover enable signal. If the data sending length is different from the target sending length, the data is continuously transmitted through the write data channel (W). For example, the master state machine obtains the length of the write data in the current write command, and the length of the write data is the target sending length. According to the requirements of the AXI 4 and subsequent protocols, the data sending length of the first data sent through the write data channel (W) is also the data length actually sent by the current write command to the slave device. If the data sending length is the same as the target sending length, it means that the write data corresponding to the write command has been sent, and the master state machine does not need to continue to send, and only needs to receive the response information returned by the write response channel (B). If the data sending length is different from the target sending length (because the data sending is ended when the target sending length is reached, so in this case, the data sending length must be less than the target sending length), it means that the data is not sent, and then the master state machine continues to transmit the data through the write data channel (W).

[0092] 3) Intercept module (such as mst_wintercept in Figure 14 ) Intercept module, used for intercepting the first data sent by the write data channel before the address channel transmission handshake is completed after the takeover of the master device is started.

[0093] This is because the AXI protocol supports the out-of-order mechanism, under which the command and the data are not transmitted in sequence, and the data may be transmitted before the command. For this case, the intercept module intercepts the first data sent by the write data channel (W) before the address channel transmission handshake is completed, such as pulling down the wready, as shown in Figure 13 .

[0094] ‌In specific execution, the master execution module transmits the information (such as commands, data, etc.) sent by the master device and / or the information (such as data, responses, etc.) received by the master device in a transparent manner when the master device is normal. When the master device is abnormal, the master execution module takes over the master device, and the master execution module sends the information (such as commands, data, etc.) and / or receives the information (such as data, responses, etc.) instead of the master device, maintains the interaction between the master device and the advanced extensible interface (AXI) bus matrix, and avoids the AXI bus from being hung up due to the drag of the master device.

[0095] In addition, the main execution module can also be configured by a configuration file, a configuration interface, etc. For example, the main execution module can be configured by a configuration file, a configuration interface, etc. as shown in the following table. Figure 13

[0096] In addition, the process of the main execution module taking over the protection of the master device can be as follows: 501, store the data sending length of the first data sent through the write data channel (W).

[0097] The main state machine stores the data sending length of the first data sent through the write data channel (W).

[0098] 502, after synchronizing to the master takeover enable signal at the time of the master device exception, enable the takeover of the master device based on the data sending length.

[0099] When the takeover of the master device is enabled based on the data sending length, the first data sent by the write data channel (W) can be intercepted before the address channel transmission handshake is completed, and at the same time, the target sending length is obtained. If the data sending length is different from the target sending length, the data is continuously transmitted through the write data channel (W).

[0100] After the main state machine synchronizes to the master takeover enable signal at the time of the master device exception through the main synchronization module, the main state machine enables the takeover of the master device based on the data sending length. Specifically, the interception module intercepts the first data sent by the write data channel (W) before the address channel transmission handshake is completed, and at the same time, the main state machine obtains the target sending length. If the data sending length is different from the target sending length, the data is continuously transmitted through the write data channel (W).

[0101] 503, after the master takeover enable signal is released and the stop condition is met, stop the takeover of the master device.

[0102] After the main state machine determines that the master takeover enable signal is released and the stop condition is met through the main synchronization module, the main state machine stops the takeover of the master device.

[0103] After the main execution module receives the master takeover enable signal, on the one hand, the path between the abnormal master device and the advanced extensible interface (AXI) bus matrix is disconnected, and on the other hand, the transmission between the master device and the advanced extensible interface (AXI) bus matrix is maintained, so that the operation of the AXI bus is not affected after the master device is abnormal, thereby leaving time for the recovery of the abnormal master device.

[0104] ​In addition, the master execution module stores the data transmission length of the first data transmitted by the write data channel (W) when the master device is normal, so that the master execution module has a monitoring function, which can monitor the transmission state between the master device and the advanced extensible interface (AXI) bus matrix. If the transmission is abnormal according to the data transmission length (for example, the data transmission length does not change for a long time), an interrupt can be sent to give a warning.

[0105] 2, slave execution module The slave execution module is hung between the slave device and the advanced extensible interface (AXI) bus matrix, and is used for monitoring the slave device and taking over the slave device when the slave device is abnormal.

[0106] As shown in Figure 13 , the slave execution module includes a write data buffer (such as bid_buf in Figure 13 ), a read data buffer (such as rid_buf in Figure 13 ), a write command first-in-first-out queue (such as wr_fifo in Figure 13 ), a slave state machine (such as FSM in Figure 13 ), and a slave synchronization module (such as Sync in Figure 14 ).

[0107] The write data buffer, the read data buffer, and the write command first-in-first-out queue are respectively connected with the advanced extensible interface (AXI) bus matrix, and the write data buffer, the read data buffer, and the write command first-in-first-out queue are also respectively connected with the slave state machine.

[0108] The slave synchronization module is connected with the slave state machine.

[0109] The slave state machine is also connected with the advanced extensible interface (AXI) bus matrix, and the slave state machine is connected with the slave device.

[0110] 1) slave synchronization module The slave synchronization module is used for synchronizing the slave takeover enable signal of the slave device when the slave device is abnormal.

[0111] That is, when the slave device is normal, the slave synchronization module does not receive the slave takeover enable signal, as shown in Figure 13 , at this time, the slave state machine only transmits data and does not perform any processing.

[0112] When the slave device is normal, for a read demand, a read command (including a read address, a length of read data, etc.) transmitted by a read address channel (AR) enters the slave state machine (such as FSM in Figure 15 ), and the slave state machine (such as FSM in Figures 1 to 4The read command is transmitted to the slave device by the slave state machine (e.g., the FSM in the slave device). Figures 6 to 9 The read data is transmitted to the master device by the slave state machine (e.g., the FSM in the slave device). Figures 10 to 15 The read data is transmitted to the master device by the slave state machine (e.g., the FSM in the slave device).

[0113] For a write request, the write command (i.e., the first command, which includes the address to be written, the length of the data to be written, etc.) transmitted by the write address channel (AW) enters the slave state machine (e.g., the FSM in the slave device). Figures 10 to 15 The write command is transmitted to the slave device by the slave state machine (e.g., the FSM in the slave device). Figure 2 The write data transmitted by the write data channel (W) enters the slave state machine (e.g., the FSM in the slave device). Figure 1 The write data is transmitted to the slave device by the slave state machine (e.g., the FSM in the slave device). Figure 1 The write data is transmitted to the slave device by the slave state machine (e.g., the FSM in the slave device). Figure 1 The response information is transmitted to the master device by the slave state machine (e.g., the FSM in the slave device). Figure 1 The response information is transmitted to the master device by the slave state machine (e.g., the FSM in the slave device).

[0114] If the slave device is abnormal (e.g., the slave device is dead), the slave takeover enable signal (e.g., AXI_ISO_EN) is sent out. Figure 1 The slave takeover enable signal (e.g., AXI_ISO_EN) is synchronized to the slave state machine by the synchronization module, so that the slave state machine takes over the slave device.

[0115] 2) Write data buffer The write data buffer is used to buffer the write command response data and process the transmission of the write response channel.

[0116] The write command response data at least includes the first ID of the response write command.

[0117] It should be noted that the response data here is not the response information.

[0118] The response information is the feedback to the master device by the slave device after executing the write command according to the AXI protocol. In the AXI protocol, the slave device feeds back a response information to the master device through the write response channel (B) after executing the write command. The response information is carried by the BRESP[1:0] signal. The AXI protocol defines four response types: OKAY: indicates a successful normal access.

[0119] ‌EXOKAY: indicates exclusive access success.

[0120] ‌SLVERR: indicates slave error.

[0121] ‌DECERR: indicates interconnect decode error (usually generated by interconnect components).

[0122] The response data is generated from the execution module, and includes the first ID of the response write command. The response data is not required to be fed back to the master device, and is only used as auxiliary information after the slave device is taken over by the execution module, to assist the takeover work of the execution module.

[0123] For example, when the slave device is normal, the slave synchronization module does not receive the slave takeover enable signal, as shown in the figure, at this time, the slave state machine only transmits data in a transparent manner. If the slave device is executing the response data (such as response data 1) of a write command (such as write command 1, whose ID is ID1), the write data buffer will cache the first ID of the response write command (such as cache ID1), and the slave state machine will transmit the response data 1 to the master device through the write response channel (B). Figure 1

[0124] In addition, when the slave device is abnormal, the write data buffer will also take over the slave device to process the transmission of the write response channel.

[0125] 3) Read data buffer The read data buffer is used to cache the third ID of the read command transmitted by the read address channel and the target read length corresponding to the read command, cache the read command response data, and process the transmission of the read data channel.

[0126] The read command response data at least includes: the second ID of the response read command and the data read length of the data corresponding to the read command.

[0127] It should be noted that the response data here is not response information.

[0128] The response information is the response information required by the AXI protocol for the slave device to execute the read command and feed back to the master device. In the AXI protocol, after the slave device executes the read command, it will feed back a response information to the master device through the read data channel (R), which is carried by the RRESP[1:0] signal and returned synchronously with the read data. The AXI protocol defines four response types: OKAY: indicates normal access success (default response).

[0129] ‌EXOKAY: indicates exclusive access success (such as atomic operation).

[0130] ‌SLVERR: indicates slave error (such as illegal address or unaligned access). ​

[0131] ‌DECERR: Address decode error (no target slave).

[0132] The response data is generated from the execution module, and includes the second ID of the response read command and the data read length of the data corresponding to the read command. The response data is not required to be fed back to the master device, and is only used as auxiliary information after the slave execution module takes over the slave device, to assist the takeover work of the slave execution module.

[0133] For example, when the slave device is normal, the slave synchronization module does not receive the slave takeover enable signal, as shown in ​ At this time, the slave state machine only transmits data. If the read address channel (AR) transmits a read command (such as read command 2, with ID ID2, including read address 2, read data length 2, etc.), the read data buffer will cache the third ID (i.e., cache ID2) of the read command transmitted by the read address channel (AR). At the same time, the slave state machine (such as the FSM in ​ ) transmits the read command 2 to the slave device. After the slave device reads the data based on the read command 2 and obtains the response information, the read data buffer caches the third ID (such as ID2) of the read command transmitted by the read address channel (AR) and the target read length (such as length 2) corresponding to the read command, and caches the read command response data (such as the second ID of the response read command and the data read length of the data corresponding to the read command). At the same time, the slave state machine transmits the read data and the response information to the slave state machine (such as the FSM in ​ ), which is transmitted to the master device by the read data channel (R). ​

[0134] In addition, when the slave device is abnormal, the read data buffer also takes over the slave device to process the transmission of the read data channel (R).

[0135] 4) Write command first-in-first-out queue The write command first-in-first-out queue is used to store the fourth ID of the write command (i.e., the first command) transmitted by the write address channel.

[0136] For example, when the slave device is normal, the slave synchronization module does not receive the slave takeover enable signal, as shown in ​ At this time, the slave state machine only transmits data. If the write address channel (AW) transmits a write command (such as write command 1, with ID ID1, including to-be-written address 1, write data length 1, etc.), the write command first-in-first-out queue will store the fourth ID (i.e., cache ID1) of the write command transmitted by the write address channel (AW).

[0137] That is, the AXI bus related information is processed as follows: (1) Read transaction​ The ID of each read command (as the third ID) and the length of the required read (as the target read length) of the read address channel (AR) transmission are stored in the read data buffer.

[0138] The ID of the read command (as the second ID) and the length of the read (as the data read length) involved in the execution of each read command by the slave are also stored in the read data buffer.

[0139] In this way, through the read data buffer, it can be known which read commands are received by the slave through the third ID, and how long the data needs to be read by the slave for each read command received through the target read length. Through the second ID, it can be known which read commands are executed by the slave, and through the data read length, it can be known how long the data is actually read by the slave for each read command executed.

[0140] (2) Write transaction The ID of each write command (as the fourth ID) of the write address channel (AW) transmission is stored in the write command first-in-first-out queue.

[0141] The ID of the write command (as the first ID) involved in the execution of each write command by the slave is stored in the write data buffer.

[0142] In this way, through the fourth ID of the write command first-in-first-out queue, it can be known which write commands are received by the slave. Through the first ID of the write data buffer, it can be known which write commands are executed by the slave.

[0143] In addition, the storage of the ID of the write command (i.e., the fourth ID) of the write address channel (AW) transmission is implemented by a first-in-first-out queue (i.e., FIFO), and other data is implemented by a buffer (i.e., buffer), because AXI 4 and subsequent protocols have the following requirements for write data: the transmission of the write data channel (W) must be strictly in address order, i.e., the write data channel (W) has order preservation. The FIFO also has order preservation, so the ID of the write command of the write address channel (AW) transmission (i.e., the fourth ID) is stored by the first-in-first-out queue. Other channels support a disorder mechanism, under which commands and data are not transmitted in order, so they are stored by a buffer.

[0144] 5) Slave state machine The slave state machine is used to receive write command response data and / or read command response data of the slave.

[0145] The write command response data at least includes: the first ID of the response write command.

[0146] The read command response data at least includes: the second ID of the response read command and the data read length of the data corresponding to the read command.

[0147] For example, when the slave device is normal, the slave synchronization module does not receive the slave takeover enable signal, as shown in ​ At this time, the slave state machine only transmits data. When the slave device feeds back the read data after executing the read command, the slave state machine acquires the ID (i.e., the second ID) of the read command corresponding to the read data and the length (i.e., the data read length) of the read data while transmitting the read data, and then stores the second ID and the data read length in the read data buffer.

[0148] When the slave device feeds back the response information after executing the write command, the slave state machine acquires the ID (i.e., the first ID) of the write command corresponding to the response information while transmitting the response information, and then stores the first ID in the write data buffer.

[0149] When the slave state machine synchronizes to the slave takeover enable signal, it indicates that the slave device is abnormal and cannot continue to receive commands and / or data and feed back data and / or response information. At this time, the slave state machine starts to take over the slave device based on the read data buffer and / or the write data buffer and the write command first-in-first-out queue to continue to respond to the AXI bus in place of the slave device. During this period, the slave device can perform repair operations such as restarting, and when the slave device is normal again and the transmission processing in the current module is completed, the slave takeover enable signal is stopped, and at this time, the slave synchronization module does not receive the slave takeover enable signal (i.e., the slave ​ as shown in ​ as shown in), the slave state machine cannot synchronize to the slave takeover enable signal, and the slave state machine obtains that the slave takeover enable signal is released. When the slave takeover enable signal is released and the stop condition is met, the slave state machine stops the takeover of the slave device and restores the transmission of data of the slave device.

[0150] The stop condition is that the transmission processing in the current module is completed.

[0151] That is, the slave state machine is also used to start the takeover of the slave device based on the read data buffer and / or the write data buffer and the write command first-in-first-out queue after synchronizing to the slave takeover enable signal. After the slave takeover enable signal is released, the slave state machine does not immediately exit the takeover, but exits the takeover after the transmission processing in the current module is completed.

[0152] In order to avoid a long time of not being able to exit the takeover, after the slave takeover enable signal is released, the slave state machine does not accept the handshake signal of the address channel and only processes the data channel, and stops the takeover of the slave device after the transmission processing in the current module is completed.

[0153] (1) Read transaction After the slave is taken over by the state machine, the read data buffer takes over the slave to process the transmission of the read data channel (R) for the read command transmitted by the read address channel (AR), i.e. the read data buffer receives the read command transmitted by the read address channel (AR).

[0154] The state machine takes over the slave to respond to the read command. That is, the state machine, after synchronizing to the slave takeover enable signal (i.e. after the state machine takes over the slave), acquires all the second IDs, the third IDs, the data read length, and the target read length in the read data buffer. If the second takeover ID exists, the second response information of the second takeover ID is generated. The second takeover ID is the third ID but not the second ID. Alternatively, the second takeover ID is the second ID, but the corresponding data read length is different from the target read length.

[0155] The read data buffer stores the IDs (i.e., the third IDs) of all read commands transmitted by the read address channel (AR) and the lengths of data (i.e., the target read lengths) required to be read by the read commands, and also stores the IDs (i.e., the second IDs, which can be obtained from the read command response data) of all read commands that have been executed by the slave device and the lengths of data (i.e., the data read lengths, which can be obtained from the read command response data) that have been read by the slave device based on the read commands. If the slave device operates normally, the slave device will execute the read command of the read address channel (AR) transmission (at this time, the ID of the read command will be stored in the read data buffer as the third ID when transmitted from the read address channel, and will be stored in the read data buffer as the second ID after the read command is executed), and will read according to the target read length of the read command (at this time, the length of data required to be read by the read command will be stored in the read data buffer as the target read length, and the length of data actually read after the read command is executed will be stored in the read data buffer as the data read length), so that, in the normal state, the third ID is the same as the second ID (i.e., each read command is executed), and the data read length is the same as the target read length (i.e., each read command is read according to the requirement). When the slave device is abnormal, the slave state machine can know which read commands have been executed by the slave device and which read commands have not been executed by the slave device by comparing the second ID and the third ID. For the executed read commands, the slave state machine can know which read commands have been normally executed by the slave device and which read commands have not been executed by the slave device by comparing the data read length and the target read length. Therefore, after the slave state machine takes over the slave device, all the second IDs (such as ID3, ID4, and ID5), the third IDs (such as ID3 and ID4), the data read lengths (such as the data read length 3 corresponding to ID3, the data read length 4 corresponding to ID4, and the data read length 5 corresponding to ID5), and the target read lengths (such as the target read length 3 corresponding to ID3 and the target read length 4 corresponding to ID4) in the read data buffer are obtained. Among them, the data read length 3 is equal to the target read length 3, and the data read length 4 is less than the target read length 4 corresponding to ID3. Because ID5 is only a second ID but not a third ID, the read command corresponding to ID5 is received by the slave device but not executed by the slave device, and also has no data read length because it is not executed, so ID5 is determined as a second takeover ID (i.e., the ID of the read command that needs to be processed by the slave state machine after takeover). Because ID4 is both a second ID and a third ID, but the data read length 4 is less than the target read length 4, it indicates that the read command corresponding to ID4 is executed by the slave device but not completed (i.e., the amount of data read does not reach the amount of data indicated by the read command), so ID4 is determined as a second takeover ID (i.e., the ID of the read command that needs to be processed by the slave state machine after takeover).Because ID3 is the second ID and the third ID, and the data read length 3 = the target read length 3, it indicates that the read command corresponding to ID3 is executed from the slave device, and the execution is completed (i.e., the amount of data read has reached the amount of data indicated by the read command), at this time, ID3 is not determined as the second takeover ID, and ID3 is not processed from the state machine.

[0156] For the second takeover ID (such as ID4, ID5), the second response information 4 corresponding to the read command of ID4 and the second response information 5 corresponding to the read command of ID5 are generated from the state machine.

[0157] The read data buffer is used to return the second response information through the read data channel (R), that is, the read data buffer returns the second response information 4 and the second response information 5 through the read data channel (R).

[0158] Through the above process, the state machine from the slave device completes the takeover of the read transaction.

[0159] (2) Write transaction After the slave device is taken over by the state machine, the write command transmitted through the write address channel (AW) and the like is processed by the write data buffer to take over the transmission of the write data buffer from the slave device, that is, the write data buffer receives the write command transmitted through the write address channel (AW) and the like.

[0160] The state machine from the slave device takes over the slave device to respond to the write command. That is, the state machine from the slave device is used to obtain all the first IDs in the write data buffer (the first IDs can be obtained from the write command response data) and all the fourth IDs in the write command first-in-first-out queue after synchronization to the slave takeover enable signal (i.e., after the state machine from the slave device takes over the slave device). If there is a first takeover ID, the first response information of the first takeover ID is generated. The first takeover ID is the fourth ID, but not the first ID.

[0161] The write command first-in-first-out queue stores the IDs (i.e., the fourth IDs) of all the write commands transmitted by the write address channel (AW). The write data buffer stores the IDs (i.e., the first IDs) of all the write commands that have been executed by the slave device. If the slave device is operating normally, the slave device will execute the write command transmitted by the write address channel (AW) (at this time, the ID of the write command is stored in the write command first-in-first-out queue as the fourth ID when it is transmitted by the write address channel (AW), and is stored in the write data buffer as the fourth ID after the write command is executed), so the fourth ID is the same as the first ID (i.e., each write command is executed) in normal operation. It should be noted that the execution of each write command does not need to be recorded by the execution module, because the transmission of the write data channel (W) must be strictly in address order according to the order preservation requirement of the AXI 4 and subsequent protocols, that is, all the data of a previous write command is written before the data of a subsequent write command is written. As long as the currently executed write command changes, it means that the previous write command is not executed. As long as the currently executed write command does not change, it means that it is not executed, so there is no need to record the execution of the write command.

[0162] When the slave device is abnormal, the slave state machine can determine which write commands have been executed by the slave device and which write commands have not been executed by the slave device by comparing the fourth ID and the first ID. At the same time, it can also be determined whether the last write command is executed normally. Therefore, after the slave state machine takes over the slave device, all the fourth IDs (such as ID6, ID7, and ID8) in the write command first-in-first-out queue are obtained, and all the first IDs (such as ID6 and ID7) in the write data buffer are obtained. According to the ID6 and ID7 in the write data buffer, it can be known that the write command corresponding to ID6 and the write command corresponding to ID7 have been processed, and ID8 is the first takeover ID. At this time, the slave state machine will take over the slave device to respond to the write command corresponding to ID8, that is, the first response information 8 of ID8 is generated, and then the response information of the unresponded write command is completed.

[0163] The write data buffer is used to return the first response information through the write response channel (B), that is, the write data buffer returns the first response information 8 through the write response channel (B).

[0164] Through the above process, the slave state machine completes the takeover of the write transaction of the slave device.

[0165] In specific implementation, the slave execution module transmits information (such as data, response, etc.) sent by the slave device to the AXI bus and information (such as command, data, etc.) received by the slave device from the AXI bus when the slave device is normal. When the slave device is abnormal, the slave execution module takes over the slave device, and the slave execution module transmits information (such as data, response, etc.) sent by the slave device to the AXI bus and / or information (such as command, data, etc.) received by the slave device from the AXI bus, maintains the interaction between the slave device and the AXI bus, and avoids the AXI bus from being hung up due to the slave device being abnormal.

[0166] In specific implementation, when processing write transactions and read transactions, the slave execution module processes the write transactions and the read transactions in the order of priority of the write transactions being higher than that of the read transactions, such as a read data channel (R) and a write data channel (W), only one channel (preferentially processing the write data channel (W)) is processed at the same time, and another channel is processed only after the transmission response of the current channel is completed.

[0167] In addition, the slave execution module can also be configured through a configuration file, a configuration interface, etc., such as ​ as shown in the cfg_interface.

[0168] In addition, the process of the slave execution module taking over the slave device can be: 601, the third ID of the read command transmitted by the read address channel (AR) and the target read length corresponding to the read command are cached. The fourth ID of the write command transmitted by the write address channel (AW) is stored.

[0169] For example, the read data buffer caches the third ID of the read command transmitted by the read address channel (AR) and the target read length corresponding to the read command. The write command first-in-first-out queue stores the fourth ID of the write command transmitted by the write address channel (AW).

[0170] 602, the write command response data and / or the read command response data of the slave device are received.

[0171] The write command response data at least includes: the first ID of the response write command. The read command response data at least includes: the second ID of the response read command and the data read length of the data corresponding to the read command.

[0172] For example, the write data buffer receives and stores the write command response data of the slave device and / or the read data buffer receives and stores the read command response data.

[0173] 603, after synchronizing to the slave takeover enable signal when the slave device is abnormal, the takeover of the slave device is started based on the third ID, the target read length, the read command response data and / or the fourth ID, the write command response data.

[0174] The slave state machine enables the takeover of the slave device based on the third ID, the target read length, the read command response data and / or the fourth ID, the write command response data. Specifically, the slave state machine acquires all the first IDs in the write command response data. If the first takeover ID exists, the slave state machine generates first response information of the first takeover ID. The first response information is returned through the write response channel (B). The first takeover ID is the fourth ID, but not the first ID.

[0175] In addition, the slave state machine acquires all the second IDs and corresponding target read lengths in the read command response data. If the second takeover ID exists, the slave state machine generates second response information of the second takeover ID. The second response information is returned through the read data channel (R). The second takeover ID is the third ID, but not the second ID. Alternatively, the second takeover ID is the second ID, but the corresponding data read length is different from the target read length.

[0176] 604. After the slave takeover enable signal is released and the stop condition is met, the slave state machine stops the takeover of the slave device.

[0177] The stop condition is that the transmission processing in the current module is completed.

[0178] After the slave state machine determines that the slave takeover enable signal is released and the transmission processing in the current module is completed, the slave state machine stops the takeover of the slave device.

[0179] After receiving the slave takeover enable signal from the execution module, on one hand, the slave state machine disconnects the path between the abnormal slave device and the advanced extensible interface (AXI) bus matrix, and on the other hand, the slave state machine maintains the transmission between the slave device and the advanced extensible interface (AXI) bus matrix, so that the operation of the AXI bus is not affected after the slave device is abnormal, thereby leaving time for the recovery of the abnormal slave device.

[0180] In addition, the slave execution module caches the ID of the read command transmitted through the read address channel (AR) and the target read length corresponding to the read command, the read command response data, processes the transmission of the read data channel (R), and stores the ID of the write command transmitted through the write address channel (AW), so that the slave execution module also has a monitoring function, which can monitor the transmission state between the slave device and the advanced extensible interface (AXI) bus matrix throughout the process. If the transmission is abnormal according to the cached and stored data, an interrupt can be sent for early warning.

[0181] The master execution module can take over the master device after the master device is abnormal (such as being stuck), so as to ensure normal operation of the AXI bus during reset of the abnormal master device. The slave execution module can take over the slave device after the slave device is abnormal (such as being stuck), so as to ensure normal operation of the AXI bus during reset of the abnormal slave device. The master execution module and the slave execution module can realize the AXI bus isolation function, monitor the handshake transmission before reset of the master device and / or the slave device, respond to the transmission by the proxy master device and / or the slave device when the master device and / or the slave device are reset, and can process subsequent transmission, so as to avoid bus hang-up.

[0182] It should be noted that the data of each channel is unidirectional flow, for example, the read address channel (AR) is from the master device to the slave device, the read data channel (R) is from the slave device to the master device, the write address channel (AW) is from the master device to the slave device, the write data channel (W) is from the master device to the slave device, and the write response channel (B) is from the slave device to the master device. ​ 、 ​ The arrows in the middle connection line are unidirectional, from the master device to the slave device, which is described by taking one or more channels from the master device to the slave device as an example. ​ The arrows in the middle connection line are not limited to the channels, so that some channels are from the master device to the slave device, and some channels are from the slave device to the master device, so that ​ The arrows in the middle connection line are bidirectional.

[0183] The floorplan process does not consider the distance between modules in physical implementation, so that the existing floorplan has the problem of more resources in implementation. The advanced extensible interface (AXI) bus matrix provided in the embodiment only performs anti-lock and address decoding in the first stage selection logic, and the rest of the selection logic no longer performs anti-lock and address decoding, but only selection.

[0184] The advanced extensible interface (AXI) bus matrix provided in the embodiment includes one anti-lock logic and decoding logic in the first stage selection logic for one master device request node in the AXI bus, and once the first stage selection logic completes the determination of the anti-lock logic and the decoding logic, the determination type output by the logic can be used at the routing branch point of the subsequent selection logic, and no new anti-lock logic and decoding logic are added.

[0185] The advanced extensible interface (AXI) bus matrix provided in the embodiment is easier to complete the routing design in the physical implementation stage, has smaller amount of logic units, and is easier to converge timing.

[0186] The advanced extensible interface (AXI) bus matrix provided in the embodiment can shorten the chip design cycle and reduce the design complexity.

[0187] The embodiment provides a high-level extensible interface bus matrix, which comprises: multi-stage selection logic; wherein the first-stage selection logic is connected with a master device; the last-stage selection logic is connected with a slave device; wherein the first-stage selection logic comprises anti-lock logic and decoding logic; and the number of stages of the multi-stage selection logic is determined according to a floorplan.

[0188] Based on the same inventive concept of the high-level extensible interface bus matrix, the embodiment provides an electronic device, which comprises ​ The embodiment provides the high-level extensible interface bus matrix.

[0189] Specifically, the high-level extensible interface bus matrix comprises: multi-stage selection logic.

[0190] The first-stage selection logic is connected with a master device.

[0191] The last-stage selection logic is connected with a slave device.

[0192] The first-stage selection logic comprises anti-lock logic and decoding logic; and the number of stages of the multi-stage selection logic is determined according to a floorplan.

[0193] The upper-stage selection logic outputs a selection signal to the lower-stage selection logic.

[0194] The selection logic further comprises beat logic.

[0195] The write address channel of the high-level extensible interface bus introduces a write address channel buffer.

[0196] The anti-lock logic is as follows: The anti-lock logic simultaneously receives a first command sent by the master device through the write address channel and first data sent by the master device through the write data channel.

[0197] When a first command is received, the received first command is sent to the slave device, the received first command is stored in the write address channel buffer, and the write address channel is reversely pressed.

[0198] The received first data is sent to the slave device.

[0199] When the WLAST signal is high, the write address channel is unblocked, and the steps of sending the received first command to the slave device, storing the received first command in the write address channel buffer, and blocking the write address channel are repeated.

[0200] The write data channel of the high-level extensible interface bus introduces a flag bit.

[0201] The initial value of the flag bit is a first value.

[0202] When a first command is received, the flag bit is updated to a second value.

[0203] The received first data is sent to the slave device, including: When the flag bit is the second value, the received first data is sent to the slave device.

[0204] When the WLAST signal is high, the write address channel is unblocked, including: When the WLAST signal is high, the flag bit is updated to the first value.

[0205] When the flag bit is the first value, the write address channel is unblocked.

[0206] The received first command is sent to the slave device, including: The received first command is sent to the slave device through the lower-level selection logic.

[0207] The received first data is sent to the slave device, including: The received first data is sent to the slave device through the lower-level selection logic.

[0208] The first-level selection logic is connected to the master device through a master execution module.

[0209] The last-level selection logic is connected to the slave device through a slave execution module.

[0210] The master execution module is used to monitor the master device and take over the master device when the master device is abnormal.

[0211] The slave execution module is used to monitor the slave device and take over the slave device when the slave device is abnormal.

[0212] The slave execution module includes a write data buffer, a read data buffer, a write command first-in-first-out queue, a slave state machine, and a slave synchronization module.

[0213] The write data buffer, the read data buffer and the write command first-in-first-out queue are connected with the advanced extensible interface bus matrix, and the write data buffer, the read data buffer and the write command first-in-first-out queue are also connected with the slave state machine.

[0214] The slave state machine is connected with the slave device.

[0215] The slave state machine is also connected with the advanced extensible interface bus matrix, and the slave state machine is connected with the slave device.

[0216] The slave state machine is used for receiving write command response data and / or read command response data of the slave device, wherein the write command response data at least comprises a first identification ID of the response write command, and the read command response data at least comprises a second ID of the response read command and a data read length of data corresponding to the read command.

[0217] The write data buffer is used for buffering the write command response data and processing transmission of the write response channel.

[0218] The read data buffer is used for buffering a third ID of the read command and a target read length corresponding to the read command transmitted by the read address channel, buffering read command response data, and processing transmission of the read data channel.

[0219] The write command first-in-first-out queue is used for storing a fourth ID of the write command transmitted by the write address channel.

[0220] The slave synchronization module is used for synchronizing a slave takeover enable signal of the slave device when the slave device is abnormal.

[0221] The slave state machine is also used for starting a takeover of the slave device based on the read data buffer and / or the write data buffer and the write command first-in-first-out queue after synchronization to the slave takeover enable signal, and stopping the takeover of the slave device when the slave takeover enable signal is released and a stop condition is met.

[0222] The master execution module comprises a master state machine, a master synchronization module and an interception module.

[0223] The master synchronization module is connected with the interception module.

[0224] The master state machine is connected with the interception module, and the interception module is connected with the master device.

[0225] The master state machine is also connected with the advanced extensible interface bus matrix, and the master state machine is connected with the master device.

[0226] The master synchronization module is used for synchronizing a master takeover enable signal of the master device when the master device is abnormal.

[0227] A master state machine is configured to store a data transmission length of the first data transmitted through the write data channel, and enable the takeover of the master device based on the data transmission length after synchronization to the master takeover enable signal. The takeover of the master device is stopped after the master takeover enable signal is released and a stop condition is met.

[0228] An intercept module is configured to intercept the first data transmitted through the write data channel before a completion of an address channel transmission handshake after the takeover of the master device is enabled.

[0229] The electronic device provided by the embodiment can ensure the optimal amount of logical data through the multi-stage selection logic without increasing the wire winding and logical resources, can solve the problem of difficult physical implementation in the back end, and can avoid design redundancy, achieving both.

[0230] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) containing computer-usable program code. The solutions in the embodiments of the present application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0231] The present application is described with reference to flowcharts and / or block diagrams according to the methods, devices (systems), and computer program products of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a means for implementing the functions specified in the flowcharts and / or block diagrams. ​ The functions specified in one or more flows and / or blocks ​ The means for implementing the functions specified in one or more flows and / or blocks.

[0232] These computer program instructions can also be stored in a computer-readable memory capable of guiding a computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction means, which implements the functions specified in the flowcharts and / or block diagrams. ​ The functions specified in one or more flows and / or blocks ​ The means for implementing the functions specified in one or more flows and / or blocks.

[0233] These computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are performed on the computer or other programmable devices, to generate computer-implemented processes, in order to achieve the flowcharts ​ one flow or multiple flows and / or blocks ​ one block or multiple blocks.

[0234] In addition, the terms "first", "second", etc. are used only to describe various conditions, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0235] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0236] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. An advanced scalable interface bus matrix, characterized in that, The advanced scalable interface bus matrix includes: multi-level selection logic; The first-level selection logic is connected to the master device; The final selection logic is connected to the slave device; The first-level selection logic includes deadlock prevention logic and decoding logic; the number of levels in the multi-level selection logic is determined according to the floorplan.

2. The advanced scalable interface bus matrix according to claim 1, characterized in that, The higher-level selection logic outputs a selection signal to the lower-level selection logic.

3. The advanced scalable interface bus matrix according to claim 1, characterized in that, The selection logic also includes a timing logic.

4. The advanced scalable interface bus matrix according to claim 1, characterized in that, The write address channel of the Advanced Extensible Interface Bus introduces a write address channel cache; The deadlock prevention logic is as follows: Simultaneously receive the first command sent by the master device through the write address channel and the first data sent by the master device through the write data channel; When a first command is received, the received first command is sent to the slave device. At the same time, the received first command is stored in the write address channel buffer, and the write address channel is pressured back. Send the first received data to the slave device; When the WLAST signal is high, the reverse pressure of the write address channel is released, and the steps of sending the received first command to the slave device and storing the received first command in the write address channel buffer, as well as the reverse pressure of the write address channel and subsequent steps, are repeated.

5. The advanced scalable interface bus matrix according to claim 4, characterized in that, The write data channel of the Advanced Extensible Interface Bus introduces one flag bit; The initial value of the flag bit is a first value; When a first command is received, update the flag to the second value; Sending the received first data to the slave device includes: When the flag is at the second value, the received first data is sent to the slave device; The step of releasing the reverse pressure of the write address channel when the WLAST signal is high includes: When the WLAST signal is high, update the flag bit to the first value; When the flag is at its first value, the back pressure on the write address channel is released.

6. The advanced scalable interface bus matrix according to claim 4, characterized in that, Sending the received first command to the slave device includes: The first received command is sent to the slave device through the lower-level selection logic; Sending the received first data to the slave device includes: The first received data is sent to the slave device through the lower-level selection logic.

7. The advanced scalable interface bus matrix according to claim 1, characterized in that, The first-level selection logic is connected to the main device through the main execution module; The final-level selection logic is connected to the slave device via the execution module; The main execution module is used to monitor the main device and take over the main device when it malfunctions. The slave execution module is used to monitor the slave device and take over the slave device when it malfunctions.

8. The advanced scalable interface bus matrix according to claim 7, characterized in that, The execution module includes: a write data buffer, a read data buffer, a write command first-in-first-out queue, a slave state machine, and a slave synchronization module; Among them, the write data buffer, read data buffer, and write command first-in-first-out queue are connected to the advanced extensible interface bus matrix, and the write data buffer, read data buffer, and write command first-in-first-out queue are also connected to the slave state machine. Establish a path between the synchronization module and the slave state machine; The state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, it establishes a path with the slave device. The slave state machine is used to receive write command response data and / or read command response data from the slave device; wherein, the write command response data includes at least: a first identifier ID of the responding write command; the read command response data includes at least: a second ID of the responding read command and the data read length corresponding to the read command; The write data buffer is used to cache write command response data and handle the transmission of write response channels; The read data buffer is used to cache the third ID of the read command transmitted through the read address channel and the target read length corresponding to the read command, cache the read command response data, and process the transmission of the read data channel. The write command first-in-first-out queue is used to store the fourth ID of the write command transmitted through the write address channel; The slave synchronization module is used to synchronize the slave takeover enable signal of the slave device when the slave device is abnormal; The slave state machine is further configured to, after synchronizing to the slave takeover enable signal, enable the takeover of the slave device based on the read data buffer and / or write data buffer and the write command first-in-first-out queue; and stop the takeover of the slave device after the slave takeover enable signal is released and the stop condition is met.

9. The advanced scalable interface bus matrix according to claim 7, characterized in that, The main execution module includes: a main state machine, a main synchronization module, and an interception module; Among them, the main synchronization module and the interception module establish a communication path; The master state machine establishes a communication channel with the interception module, and at the same time, the interception module establishes a communication channel with the master device; The master state machine also establishes a path with the advanced scalable interface bus matrix, and at the same time, the master state machine establishes a path with the master device; The main synchronization module is used to synchronize the main takeover enable signal of the main device when the main device is abnormal; The master state machine is used to store the data transmission length of the first data sent through the write data channel. After synchronizing with the master takeover enable signal, it starts the takeover of the master device based on the data transmission length. After the master takeover enable signal is released and the stop condition is met, it stops the takeover of the master device. The interception module is used to intercept the first data sent by the write data channel before the address channel handshake is completed after the master device takes over.

10. An electronic device, characterized in that, Includes the Advanced Scalable Interface Bus Matrix as described in any one of claims 1-9.

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