Chip packaging structure, circuit board and electronic equipment
By using independent topologies for global and local buses, data transmission among multiple computing core chips is optimized, resolving issues of high latency and conflicts, improving computing power utilization, and supporting large-scale computing core deployment.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, multi-core computing chips suffer from high latency, easy collisions, and large communication hops during data transmission, especially for edge computing cores, which limits the number of computing cores and the utilization rate of computing power.
It adopts an independent topology of global bus and local bus, which transmits global data quickly through the global bus and local data through the local bus. It uses bridging units, buffers and demultiplexers to optimize the data transmission path and avoid conflicts and delays.
It achieves low-latency, high-efficiency data transmission, improves the computing power utilization of computing cores, supports the deployment of large-scale computing cores, and reduces the number of communication hops for edge computing cores.
Smart Images
Figure CN121807767A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of integrated circuits, in particular to a chip packaging structure, a circuit board and an electronic device. BACKGROUND
[0002] With the increasing demand for computing power, the number of computing cores in chips is also increasing. For chips with multiple computing cores in the prior art, when performing data communication, each computing core needs to pass the communication data in a "hop-by-hop" manner to complete the communication transmission.
[0003] Such a chip, when broadcasting global data, such as broadcasting loading instructions, external weight parameters, etc. to specific computing cores or part of the computing cores, can only pass the data one by one in sequence. The transmission process of the global data also needs to pass through computing cores that do not need to receive the global data, resulting in high data transmission delay. In addition, in addition to the global data, each computing core also generates local data during operation, such as intermediate results during operation of each computing core. The local data and the global data are transmitted one by one between each computing core along a transmission path, which is prone to conflict, thereby causing the computing core to stop and reducing the utilization rate of computing power. Moreover, the method of passing the data level by level limits the number of computing cores that can be arranged, as the communication hop number corresponding to the computing core arranged at the edge position is large. SUMMARY
[0004] The present application provides a chip packaging structure, a circuit board and an electronic device, which aims to solve the problems of high delay and easy conflict caused by the prior art chip using the same data transmission path to transmit global data and local data from one computing core to another, and the problem of limiting the maximum number of computing cores on the chip due to the large communication hop number of the computing core at the edge.
[0005] In an embodiment of the present application, a chip packaging structure is provided, comprising:
[0006] a computing core array including a plurality of computing cores, each computing core having a multiplexer at its input end, each multiplexer having a first input end and a second input end, the plurality of computing cores being divided into a plurality of clusters, each cluster including at least one computing core, and each cluster having a bridge unit;
[0007] a local bus for transmitting local data;
[0008] a global bus for transmitting global data;
[0009] The output end of the previous computing core between two adjacent computing cores is connected with the first input end of the multiplexer corresponding to the next data core through the local bus;
[0010] The input end of each bridge unit is connected with the global bus, and each output end of each bridge unit is connected with the second input end of each multiplexer in the corresponding cluster.
[0011] In the embodiment of the application, a plurality of global buses are included; the global bus is annular or linear; in the direction perpendicular to the chip packaging structure, the plurality of global buses cover the bridge units corresponding to each cluster.
[0012] In the embodiment of the application, each cluster includes only one computing core;
[0013] The bridge unit corresponding to each computing core includes a buffer;
[0014] Each buffer is arranged at the side of the corresponding computing core, and the output end of each buffer is connected with the second input end of the multiplexer of the corresponding computing core;
[0015] The input end of each buffer is connected with the global bus in the vertical direction.
[0016] In the embodiment of the application, each cluster includes at least two computing cores;
[0017] Each bridge unit includes a buffer and a demultiplexer; the output end of each buffer is connected with the input end of the demultiplexer in the bridge unit where the buffer is arranged;
[0018] In the direction parallel to the chip packaging structure, the buffer and the demultiplexer in each bridge unit are arranged at the center of the corresponding cluster;
[0019] Each demultiplexer includes a plurality of output ends, the number of the output ends of each demultiplexer is the same as the number of the computing cores in the corresponding cluster, and each output end of each demultiplexer is connected with the second input end of the multiplexer corresponding to each computing core in the corresponding cluster;
[0020] The input end of each buffer is connected with the global bus in the vertical direction.
[0021] In the embodiment of the application, the global bus is linear, and in the chip packaging structure, the global shared memory is arranged at both ends of the global bus, and the two ends of the global bus are respectively connected with the corresponding global shared memory.
[0022] In the embodiment of the present application, the global bus is ring-shaped, and the chip packaging structure is provided with a plurality of global shared memories at the side edges of the chip packaging structure. Each ring-shaped global bus is provided with an access point at a position corresponding to each global shared memory, and each ring-shaped global bus is connected to each global shared memory through the access point.
[0023] In the embodiment of the present application, the global bus is arranged at the top layer of the metal interconnection layer of the chip packaging structure, and the local bus is arranged at the bottom layer of the metal interconnection layer.
[0024] In the embodiment of the present application, in the direction perpendicular to the chip packaging structure, the chip packaging structure is provided with a signal repeater at a position corresponding to the signal attenuation critical point of each global bus, and each signal repeater is connected in series to the global bus in the vertical direction thereof through a vertical via;
[0025] In the direction perpendicular to the chip packaging structure, the chip packaging structure is provided with a flow register at a position corresponding to the timing bottleneck segment of each global bus, and each flow register is connected in series to the global bus in the vertical direction thereof through a vertical via.
[0026] In the embodiment of the present application, the line width of the global bus is greater than the line width of the local bus.
[0027] The line spacing of the global bus is greater than the line spacing of the local bus.
[0028] The present application also provides a circuit board provided with at least one chip packaging structure as described in any one of the above embodiments.
[0029] The present application also provides an electronic device comprising a circuit board and a chip packaging structure as described in any one of the above embodiments, wherein the chip packaging structure is electrically connected to the circuit board.
[0030] The chip packaging structure, the global bus and the local bus in the embodiment of the present application are independent topological structures. The bridge units in each cluster corresponding to one global bus are connected in parallel to the global bus. When transmitting global data to a specific computing core, the global data can be quickly transmitted based on the corresponding global bus and bridge unit, without being transmitted step by step through each computing core, so that the delay is low. In addition, the local data is transmitted through the local bus, and does not conflict with the global data, avoiding the pause of the computing core and improving the utilization rate of the computing power of each computing core. Moreover, since the global data can be positioned and sent based on the global bus and the corresponding bridge unit, even for the edge computing core, it does not need to wait for the forwarding and transmission of other computing cores, so that a large-scale computing core can be supported. BRIEF DESCRIPTION OF DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from the structures shown in the drawings without creative labor.
[0032] Figure 1 A partial schematic diagram of the global bus and the local bus of the chip packaging structure in an embodiment of the present application;
[0033] Figure 2 A global bus layout schematic diagram of the chip packaging structure in an embodiment of the present application;
[0034] Figure 3 A global bus layout schematic diagram of the chip packaging structure in another embodiment of the present application;
[0035] Figure 4 A global bus layout schematic diagram of the chip packaging structure in still another embodiment of the present application;
[0036] Figure 5 A structure schematic diagram of the bridge unit in an embodiment of the present application;
[0037] Figure 6 A structure schematic diagram of the bridge unit in another embodiment of the present application;
[0038] Figure 7 A partial cross-sectional schematic diagram of the chip packaging structure in an embodiment of the present application;
[0039] Figure 8 A global bus layout schematic diagram of the chip packaging structure in another embodiment of the present application.
[0040] Explanation of reference signs:
[0041] 100-global bus, 200-local bus, 300-bridge unit, 400-global bus controller, 500-signal repeater, 600-pipeline register.
[0042] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION
[0043] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work are within the scope of protection of the present application.
[0044] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly.
[0045] In addition, if the embodiments of the present application involve descriptions such as “first”, “second”, etc., the descriptions of “first”, “second”, etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first” and “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize it, and when the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist, and is also not within the scope of protection claimed by the present application.
[0046] As shown in FIG. 1, Figure 1 In the embodiments of the present application, the chip packaging structure includes:
[0047] a computing core array including a plurality of computing cores, each computing core being provided with a multiplexer at an input end, each multiplexer being provided with a first input end and a second input end, the plurality of computing cores being divided into a plurality of clusters, each cluster including at least one computing core, and each cluster being provided with a bridge unit 300; each bridge unit 300 including a same number of output ends as the number of multiplexers in the corresponding cluster;
[0048] a local bus 200 for transmitting local data;
[0049] a global bus 100 for transmitting global data;
[0050] the output end of a previous computing core between two adjacent computing cores is connected to the first input end of a multiplexer of a next computing core via the local bus 200;
[0051] The input end of each bridge unit 300 is connected with the global bus 100, and the output end of each bridge unit 300 is connected with the second input end of each multiplexer in the corresponding cluster.
[0052] In the embodiment of the present application, the compute tile / core is a core operation unit of the chip packaging structure, and each compute tile / core internally includes an operation logic unit (MAC Array) and a local memory (Local SRAM). The compute tile array refers to that the compute tiles in the chip packaging structure are arranged in the form of a matrix, for example, M rows * N rows. The specific number of compute tiles arranged in the chip packaging structure is not limited in the embodiment of the present application.
[0053] As shown in Figure 1 , each compute tile can be divided into multiple clusters, and each cluster can include at least one compute tile. For example, in the embodiment shown in Figure 1 , each cluster includes four compute tiles. It should be noted that in other embodiments, each cluster can also include more compute tiles or fewer compute tiles, or can include only one compute tile. In addition, Figure 1 only part of the clusters, part of the global bus 100 and part of the local bus 200 in the chip packaging structure are shown, which does not mean that the chip packaging structure in the embodiment of the present application only includes the clusters, the local bus 200 and the global bus 100 shown in the figure.
[0054] Continuing to refer to Figure 1 , in the embodiment of the present application, each compute tile is correspondingly provided with a multiplexer, such as compute tiles Core1-Core8, which are correspondingly provided with multiplexers Mux1-Mux8. The output end of each multiplexer is connected to the input end of its corresponding compute tile, such as the output end of the multiplexer is connected to the physical pin (Pin / Port) of the input end of its corresponding compute tile. In addition, the compute tile and the multiplexer are arranged on the substrate of the chip packaging structure, and in the horizontal direction of the substrate, each multiplexer can be arranged at the side of the corresponding compute tile.
[0055] As shown in Figure 1 , in the embodiment of the present application, the local bus 200 is used to transmit local data. The local data (Local Data) can also be referred to as neighbor data (Neighbor Data), which refers to dynamic operation data that needs to be streamed between adjacent compute tiles in the systolic array (Systolic Array) computing mode, such as
[0056] Input Activations: the input FeatureMaps data of each layer of the neural network, which flows along the horizontal or vertical direction in the computing core array.
[0057] Partial Sums: the intermediate accumulated results generated by the previous computing core operation, which need to be passed to the next core for continued accumulation operation.
[0058] Neighbor Data: the data output from the physically adjacent Upstream Core through the local bus 200 and reaching the input end of the current computing core.
[0059] As shown in Figure 1 In the embodiments of the present application, the global bus 100 is used to transmit global data. The global data refers to static parameter data and control instruction data that need to be shared, reused or broadcasted by multiple computing cores in the neural network computing process. For example:
[0060] Neural Network Weights: the convolution kernel parameters or fully connected layer weight matrix. The data volume of such data is large, and needs to be quickly loaded into the local memory of each computing core before the start of the calculation.
[0061] Bias: the bias parameter in the neural network operation.
[0062] Global Control Instructions: system-level broadcast instructions such as "full-array reset", "synchronous calculation start", "level configuration parameters", etc.
[0063] Continuing to refer to Figure 1 In the embodiments of the present application, the output end of the previous computing core in the two adjacent computing cores is connected to the first input end of the multiplexer corresponding to the next computing core through the local bus 200.
[0064] For example, the output end s2 of the computing core Core1 is first connected to the local bus 200, and then connected to the first input end bl of the multiplexer Mux2 from the local bus 200, the output end b3 of the multiplexer Mux2 is connected to the input end t1 of the computing core Core2, and the computing core Core1 can transmit local data to the Mux2 through the local bus 200, and then transmit to the Core2. For another example, the output end m2 of the computing core Core3 is first connected to the local bus 200, and then connected to the first input end d1 of the multiplexer Mux4 from the local bus 200, the output end d3 of the multiplexer Mux4 is connected to the input end n1 of the computing core Core4, and the computing core Core3 can transmit local data to the Mux4 through the local bus 200, and then transmit to the Core4. Similarly, the output end t2 of the computing core Core2 can transmit local data to the first input end of the multiplexer of the next computing core through the corresponding local bus 200; the output end n2 of the computing core Core4 can transmit local data to the first input end of the multiplexer of the next computing core through the corresponding local bus 200; the first input end al of the multiplexer Mux1 is used to receive the local data transmitted by the previous computing core through the local bus; and the first input end cl of the multiplexer Mux3 is used to receive the local data transmitted by the previous computing core through the local bus.
[0065] With reference to Figure 1 In the embodiment of the present application, each cluster is provided with a bridge unit 300, the input end of each bridge unit 300 is connected to the corresponding global bus 100, and the output end of each bridge unit 300 is connected to the second input end of each multiplexer in the corresponding cluster.
[0066] As shown in Figure 1 In the embodiment of the present application, each cluster has four computing cores, and the bridge unit 300 corresponding to each cluster is provided with four output ends. For example, in the orientation shown in Figure 1 The input end of the upper bridge unit 300 is connected to the corresponding global bus 100, and the four output ends z1, z2, z3, z4 of the upper bridge unit 300 are connected to the second input ends a2, b2, c2, d2 of Mux1, Mux2, Mux3, Mux4, respectively. For another example, the input end of the lower bridge unit 300 is connected to the corresponding global bus 100, and the four output ends z5, z6, z7, z8 of the lower bridge unit 300 are connected to the second input ends p1, p4, p2, p3 of Mux5, Mux6, Mux7, Mux8, respectively.
[0067] For example, if global data needs to be sent to the computing cores in Core1-Core4, the global data can be sent to the upper bridge unit 300 through the global bus 100 corresponding to the upper bridge unit 300, and then sent to the second input terminals a2, b2, c2, d2 of Mux1-Mux4 through the four output terminals z1, z2, z3, z4 of the upper bridge unit 300, and then sent to Core1-Core4 through the output terminals a3, b3, c3, d3 of Mux1-Mux4. For another example, if global data needs to be sent to the computing cores in Core5-Core8, the global data can be sent to the lower bridge unit 300 through the global bus 100 corresponding to the lower bridge unit 300, and then sent to the second input terminals p1, p4, p2, p3 of Mux5-Mux8 through the four output terminals z5, z6, z7, z8 of the lower bridge unit 300, and then sent to Core5-Core8 through the output terminals p5, p6, p7, p7 of Mux5-Mux8, respectively.
[0068] It should be noted that Figure 1 The electrical connection relationship between the local bus, the global bus, the computing cores and the multiplexers is only shown in the example, and does not represent the position in the physical structure of the chip packaging structure. The local bus 200, the global bus 100, the computing cores and the multiplexers are not in the same plane. The local bus 200 and the global bus 100 are located in different metal layers of the metal interconnection layer of the chip packaging structure, and the computing cores and the multiplexers are arranged on the substrate of the chip packaging structure.
[0069] Continuing to refer to Figure 2In the embodiment of the present application, the global bus 100 and the local bus 200 are independent topologies, for example, the global bus 100 and the local bus 200 can be located in different metal layers in the metal interconnection layer of the chip packaging structure when wiring, the bridge unit 300 corresponding to each cluster on the same global bus 100 is connected in parallel in the global bus 100. The global bus 100 is used to transmit global data, and the local bus 200 is used to transmit local data, so when transmitting global data to a specific computing core, it can be quickly transmitted based on its corresponding global bus 100 and bridge unit 300, without the need for step-by-step transmission through the computing core, so the delay is low; in addition, when transmitting local data, it is transmitted through the local bus 200, and there is no conflict with global data, avoiding the pause of the computing core and improving the computing power utilization rate of each computing core; moreover, since the global data can be positioned and sent based on the global bus 100 and the corresponding bridge unit 300, even for the edge computing core, it does not need to wait for other computing cores to forward and deliver, so it can support large-scale computing cores.
[0070] As shown in Figure 3 , Figure 4 , Figure 2 In the embodiment of the present application, a plurality of global buses 100 are included; the global bus 100 is ring-shaped or linear; in the direction perpendicular to the chip packaging structure, the upper side of the bridge unit 300 corresponding to each cluster is provided with a corresponding global bus.
[0071] In the embodiment of the present application, in the horizontal direction, the global bus 100 can be a horizontal straight line, and / or a vertical straight line, and / or a ring line.
[0072] For example, in the embodiment shown in Figure 3 , the global bus 100 is a vertical straight line, in the direction perpendicular to the chip packaging structure, the upper side of the bridge unit 300 corresponding to each cluster is provided with a global bus 100, and the input end of each bridge unit 300 can be connected to the corresponding global bus 100 vertically upward through a vertical via. The bridge unit 300 corresponding to the four clusters of the same global bus is connected in parallel in the global bus.
[0073] For another example, in the embodiment shown in Figure 4 , the global bus 100 is a horizontal straight line, in the direction perpendicular to the chip packaging structure, the upper side of the bridge unit 300 corresponding to each cluster is provided with a global bus 100, and the input end of each bridge unit 300 can be connected to the corresponding global bus 100 vertically upward through a vertical via. The bridge unit 300 corresponding to the four clusters of the same global bus is connected in parallel in the global bus.
[0074] For example, in Figure 2 In the illustrated embodiment, the global bus 100 is ring-shaped. In the direction perpendicular to the chip package structure, the inner ring-shaped global bus 100 covers the bridging units 300 of the four inner clusters. The input terminals of the four inner clusters of bridging units 300 can be vertically connected upwards to the inner ring-shaped global bus 100 via vertical vias, thus all four inner clusters of bridging units 300 are connected in parallel to the inner global bus 100. In the direction perpendicular to the chip package structure, the outer ring-shaped global bus 100 covers the bridging units 300 of the twelve outer clusters. The input terminals of the twelve outer clusters of bridging units 300 can be connected to the outer ring-shaped global bus 100 via vertical vias, thus all twelve outer clusters of bridging units 300 are connected in parallel to the outer global bus 100.
[0075] It should be noted that the global bus 100 in the chip packaging structure of this application may include only a horizontal linear global bus 100, only a vertical linear global bus 100, or only a ring-shaped global bus 100. It may also be any combination of horizontal linear, vertical linear, and ring-shaped global buses. All global buses 100, in the direction perpendicular to the chip packaging structure, can cover the bridge unit 300 corresponding to each cluster.
[0076] In the direction perpendicular to the chip package structure, each global bus 100 covers the bridge unit 300 corresponding to each cluster, and each bridge unit 300 can be connected in parallel to its corresponding global bus 100 through a vertical via. The data transmission distance between each bridge unit 300 and the global bus 100 is the vertical distance between the bridge unit 300 and the corresponding global bus 100. Therefore, the data transmission distance between each bridge unit 300 and the global bus 100 can be reduced, and the transmission speed of global data can be improved.
[0077] It should be noted that, in Figure 3 , Figure 4 , Figure 5 For ease of understanding, only the connection between each bridging unit 300 and its corresponding cluster is shown, omitting the individual computing cores and corresponding multiplexers in each cluster. In fact, the number of outputs of each bridging unit 300 is consistent with the number of computing cores in the cluster corresponding to that bridging unit 300, and each output of each bridging unit 300 is connected to the second input of the multiplexer corresponding to each computing core in its respective cluster.
[0078] In the embodiment of the present application, the component structure of the bridge unit 300 corresponding to each cluster is different based on the number of computing cores in the cluster.
[0079] As shown in Figure 5 In the embodiment of the present application, only one computing core is included in each cluster;
[0080] The bridge unit 300 corresponding to each computing core includes a buffer, and each buffer is arranged at the side of the corresponding computing core, and the output end of each buffer is connected to the second input end of the multiplexer of the corresponding computing core.
[0081] The input end of each buffer is connected to the global bus 100 in the vertical direction thereof.
[0082] Referring to Figure 6 In the embodiment of the present application, only one computing core is included in each cluster, that is, Core1 is a cluster, and Core2 is another cluster. At this time, the bridge unit 300 corresponding to Core1 and Core2 can include a buffer. For example, the buffer corresponding to Core1 is Buffer1, the input end of Buffer1 is vertically connected to the corresponding global bus 100 upward, and the output end of Buffer1 is connected to the second input end of the multiplexer Mux1 corresponding to Core1. The buffer corresponding to Core2 is Buffer2, the input end of Buffer2 is vertically connected to the corresponding global bus 100 upward, and the output end of Buffer2 is connected to the second input end of the multiplexer Mux2 corresponding to Core2.
[0083] In the embodiment of the present application, the buffer can latch, amplify and clock domain synchronize the global data in the global bus 100, so as to prevent signal attenuation after long distance transmission. Only one computing core is arranged in each cluster, that is, one buffer is arranged corresponding to each computing core, so as to ensure that the global data obtained by each computing core is complete and not attenuated.
[0084] As shown in Figure 6 In the embodiment of the present application, at least two computing cores are included in each cluster;
[0085] Each bridge unit 300 includes a buffer and a demultiplexer, and the output end of each buffer is connected to the input end of the demultiplexer in the bridge unit 300 where the buffer is arranged.
[0086] In the direction parallel to the chip packaging structure, the buffer and the demultiplexer in each bridge unit 300 are arranged at the center of the corresponding cluster;
[0087] Each demultiplexer includes multiple outputs. The number of outputs of each demultiplexer is the same as the number of computing cores in its corresponding cluster. Each output of each demultiplexer is connected to the second input of the multiplexer corresponding to each computing core in the corresponding cluster.
[0088] In the direction perpendicular to the chip package structure, the input of each buffer is connected to its corresponding global bus 100.
[0089] like Figure 6 As shown in the embodiment of this application, taking each cluster as an example including four computing cores Core1-Core4, the bridging unit 300 corresponding to each cluster includes a buffer and a demultiplexer DeMux. The input of the buffer is vertically connected in parallel to its corresponding global bus 100 in a direction perpendicular to the chip package structure, and the output is connected to the input of the DeMux. The DeMux has four outputs, which are respectively connected to the second inputs of Mux1-Mux4.
[0090] In this embodiment of the application, since each cluster includes multiple computing cores, it is necessary to set up a 1 to N demultiplexer DeMux in the bridging unit 300 corresponding to each cluster. Through the N outputs of the demultiplexer, global data is sent to the second inputs of the N multiplexers in the cluster.
[0091] In addition, in this embodiment of the application, when sending global data to a specific computing core, a global data address can be set in the global data. For example, the global data address can include two parts: one part is used to determine the address of the bridging unit 300, and the other part is used to determine each computing core corresponding to the bridging unit 300.
[0092] For example, with Figure 6 For example, the global data address can include 10 bits. The high 8 bits can be used to determine the address of the bridging unit 300, and the low 2 bits can be used to determine the various computing cores within the bridging unit 300. For example, 00 corresponds to Core1, 01 corresponds to Core2, 10 corresponds to Core3, and 11 corresponds to Core4. Thus, the address of the bridging unit 300 is first determined based on the high 8 bits of the global data address, and the data is sent to the broadcast buffer of the bridging unit 300. Then, it is sent to the demultiplexer DeMux of the bridging unit 300. Based on the low 2 bits of the address, it is sent to the corresponding multiplexers Mux1-Mux4, and finally, it is sent to the corresponding computing core.
[0093] In addition, in other embodiments, when global data needs to be sent to all computing cores in a certain cluster, a special Enable signal can also be sent, and when the demultiplexer receives the Enable signal, the four gates corresponding to the four computing cores in the cluster are all opened, and the four multiplexers can all receive the global data.
[0094] As shown in Figure 2 In an embodiment of the present application, when each cluster includes multiple computing cores, the bridge unit 300 corresponding to the cluster includes a buffer and a demultiplexer, the buffer can latch, amplify and clock domain synchronize the global data in the global bus 100, preventing signal attenuation after long distance transmission, and the demultiplexer can accurately determine the computing core receiving the global data.
[0095] As shown in Figure 3 , Figure 2 In an embodiment of the present application, the global bus 100 is linear, and the chip packaging structure includes global shared memories at both ends of the global bus 100, and the two ends of the global bus 100 are respectively connected with the corresponding global shared memories.
[0096] As shown in Figure 3 , Figure 2 The global shared memories can be arranged at the side edges of the chip packaging structure, such as the upper and lower side edges as shown in Figure 3 , and such as the left and right side edges as shown in Figure 4 , and the two ends of each global bus 100 are respectively connected with the corresponding global shared memories.
[0097] In an embodiment of the present application, when the global bus 100 is linear, the global shared memories are arranged at both ends of the global bus 100. When each computing core obtains global data, it only uses the corresponding global bus 100 to obtain the global data from each global shared memory, which can shorten the transmission distance of the global data and improve the transmission speed of the global data.
[0098] As shown in Figure 4 In another embodiment of the present application, the global bus 100 is annular. The chip packaging structure includes multiple global shared memories arranged at the side edges of the chip packaging structure, and each annular global bus 100 is provided with an access point at a position corresponding to each global shared memory, and each annular global bus 100 is connected with each global shared memory through the access point.
[0099] As shown in Figure 2As shown in the embodiment of the present application, when the global bus 100 is ring-shaped, the global shared memory can be arranged around the chip packaging structure. The position of the access point for accessing the global shared memory on each ring-shaped global bus 100 can correspond to the position of the global shared memory. For example, the global shared memory is arranged at the four corners of the chip packaging structure, and then each global bus 100 can be arranged with an access point at the position corresponding to the global shared memory at the four corners, and then the access point is connected to the corresponding global shared memory. In this way, no matter which computing core needs global data, it can quickly obtain the global data from each global shared memory through the corresponding global bus 100.
[0100] As shown in the embodiment of the present application, when the global bus 100 is ring-shaped, the global shared memory can be arranged around the chip packaging structure. The position of the access point for accessing the global shared memory on each ring-shaped global bus 100 can correspond to the position of the global shared memory. For example, the global shared memory is arranged at the four corners of the chip packaging structure, and then each global bus 100 can be arranged with an access point at the position corresponding to the global shared memory at the four corners, and then the access point is connected to the corresponding global shared memory. In this way, no matter which computing core needs global data, it can quickly obtain the global data from each global shared memory through the corresponding global bus 100. Figure 7 As shown in the embodiment of the present application, a global bus controller 400 can also be arranged between each global bus 100 and the global shared memory. For example, the global bus controller 400 can be integrated in the interface circuit of the global shared memory, and the output end of the global bus controller 400 is connected to the input end of the global bus 100. For another example, the global bus controller 400 can be an independent hardware module, the input end of the global bus controller 400 is connected to the global shared memory, and the output end is connected to the start end of the global bus 100 through metal layer wiring.
[0101] For example, in the embodiment of the present application, the chip packaging structure is provided with:
[0102] A plurality of global bus state monitoring modules, the signal collection end of each global bus state monitoring module is connected in parallel to each global bus 100, and is used to receive the global data request sent by the bridge unit 300 in each cluster on the global bus 100;
[0103] A global data packaging module, the data input port of the global data packaging module is connected to the data output port of each global shared memory, the data packet output port of the global data packaging module is connected to the start end of each global bus 100, and the global data packaging module is used to send global data for each global bus;
[0104] An external configuration interface;
[0105] A plurality of global bus controllers 400, each global bus controller 400 is provided with an arbitration logic circuit (Arbiter Logic), a state machine (FSM), a counter, a priority register stack and a hardware comparator;
[0106] The state machine in each global bus controller 400 is connected to the signal output end of the global bus state monitoring module on the corresponding global bus 100, and is connected to the input end of the global data packaging module, and is connected to the output end of the counter in the global bus controller 400, and is connected to the arbitration logic circuit;
[0107] The priority register in each global bus controller 400 is connected with the output end of the external configuration interface, for receiving the configuration instruction sent from the external configuration interface, such as configuring the priority of each bridge unit on the global bus where it is located;
[0108] The priority register stack in each global bus controller 400 is also connected with the hardware comparator in it;
[0109] The hardware comparator in each global bus controller 400 is also connected with the arbitration logic circuit in the global bus controller.
[0110] When a computing core sends a global data request to the global bus 100 corresponding to it, the global bus state detection module on the global bus 100 detects the global data request and outputs the state signal of the global bus 100, such as the current idle or the current occupation, to the state machine in the global bus controller corresponding to the global bus 100; after the state machine receives the global data request on the global bus 100 and the idle signal, it sends an arbitration signal to the arbitration logic circuit; the arbitration logic circuit determines the arbitration mode according to the arbitration signal sent by the state machine, such as the polling mode and the priority mode.
[0111] If it is the priority mode, the hardware comparator reads the priority values of each requested bridge unit 300 in the priority register stack, compares and filters out the bridge unit with the highest priority, and feeds back the bridge unit ID with the highest priority to the arbitration logic circuit;
[0112] If it is the polling mode, the counter counts in the order of the computing cores, and the state machine synchronously outputs the count signal to the counter, and the counter transmits the computing core ID corresponding to the current count signal to the arbitration logic circuit;
[0113] After the state machine receives the computing core ID finally arbitrated by the arbitration logic circuit, it outputs the bridge unit ID corresponding to the computing core to the data packet encapsulation module;
[0114] The global data encapsulation module activates, reads the original global data from the global shared memory, and encapsulates, and after the encapsulation is completed, sends it to the global bus 100.
[0115] In addition, in the embodiment of the present application, an address decoder or an ID comparator can also be arranged at the output end of the buffer of each bridge unit 300. The address decoder or the ID comparator in each bridge unit stores the ID of the bridge unit 300, for example, the high 8 bits in the global data can represent the ID of the bridge unit 300. When the global data package on the global bus 100 reaches any bridge unit 300, the address decoder or the ID comparator in the bridge unit 300 compares the high 8 bits of the global data package with the locally stored ID of the bridge unit 300. If they match, a high level is output; if they do not match, the data is discarded or transmitted downward.
[0116] In addition, it should be noted that for a cluster with only one computing core, the corresponding bridge unit 300 only has a buffer, and the output end of the buffer is connected to the second input end of the multiplexer of the corresponding computing core. In the embodiment, the address decoder or the ID comparator can be arranged between the output end of the buffer and the second input end of the multiplexer. When the address comparison of the address decoder or the ID comparator matches, a high level is output to the multiplexer to activate the multiplexer to capture the packaged data.
[0117] For a cluster including more than one computing core, the corresponding bridge unit 300 is provided with a buffer and a demultiplexer. In the embodiment, the address decoder or the ID comparator can be arranged between the output end of the buffer and the input end of the demultiplexer. When the address comparison of the address decoder or the ID comparator matches, a high level is output to the demultiplexer to activate the demultiplexer to capture the packaged data.
[0118] As shown in FIG. 1, Figure 7 In the embodiment of the present application, the global bus 100 is arranged at the top layer of the metal interconnection layer of the chip packaging structure, and the local bus 200 is arranged at the bottom layer of the metal interconnection layer.
[0119] As shown in FIG. 1, Figure 7 Figure 7 FIG. 2 shows a partial cross-sectional view of the chip packaging structure in the embodiment of the present application, in which the computing core Core, the buffer Buffer, and the multiplexer Mux are arranged in the substrate of the chip packaging structure, Figure 8 As shown in FIG. 2, the upper part of the substrate is the metal interconnection layer of the chip packaging structure, which has multiple metal layers, each of which is used for wiring, and each metal layer is connected to the computing core, the buffer, the multiplexer, and other devices in the substrate through a vertical via.
[0120] By placing the local bus 200 at the bottom of the metal interconnect layer, the computing cores can achieve shorter transmission distances when transmitting local data, making it more suitable for the rapid transmission of pulsed data streams (such as activation values) during the computing process. Besides the bottom layer, placing the local bus 200 in a lower metal layer (such as the first four layers below) can also meet the requirements for local data transmission.
[0121] In this embodiment, the global high-speed bus can be placed on the top layer of the metal interconnect layer. The traces on the topmost metal interconnect layer have larger line widths and spacings compared to the traces on the bottom metal layers, resulting in less attenuation during transmission of global data in the global bus 100. In addition, besides the topmost metal layer, the four metal layers above it also meet the transmission requirements of global data.
[0122] like Figure 8 As shown in the embodiments of this application, when the number of computing cores in the chip package structure is small, the global bus 100 can be directly set in the wiring channels reserved around each computing core on the substrate of the chip package structure. In this case, the global bus 100 only includes the outermost ring global bus 100, which does not pass through each computing core, and both the global bus 100 and the computing core are located on the substrate. For example, in a chip package structure with only 4 computing cores, the global bus 100 surrounds the 4 computing cores, and the input terminals of the multiplexers of each computing core are connected to the global bus 100 through horizontal traces. For this type of chip package structure with fewer computing cores, this structure of setting the global bus 100 in the reserved wiring channels around the chip package structure can be adopted, and the outermost ring of global buses 100 can meet the global data transmission of each computing core. However, when the number of computing cores is large, the outermost ring of global buses 100 alone cannot meet the global data transmission of all computing cores, so it is still necessary to set each global bus 100 in the metal interconnect layer above the computing core.
[0123] like Figure 1 As shown in this embodiment, in the direction perpendicular to the chip packaging structure, the chip packaging structure is provided with a signal repeater 500 at the position corresponding to the signal attenuation critical point of each global bus 100, and each signal repeater 500 is vertically connected in series in its vertical global bus 100.
[0124] In the direction perpendicular to the chip package structure, the chip package structure is provided with a pipeline register 600 at the position corresponding to the timing bottleneck segment of each global bus 100, and each pipeline register 600 is vertically connected in series in the global bus 100 in its vertical direction.
[0125] In the embodiments of the present application, the lengths of each global bus 100 are different, and the positions and numbers of signal attenuation points, critical points and timing bottleneck segments on each global bus 100 are also different. Therefore, the signal repeaters 500 and the pipeline registers 600 can be set based on the lengths of each global bus 100 and the signal attenuation degree of the global data transmission, so as to avoid the signal attenuation and timing convergence after long-distance transmission of a single global bus 100. The signal repeaters 500 and the pipeline registers 600 can be set in the substrate of the chip packaging structure and connected in series in the corresponding global bus 100 through vertical vias.
[0126] As shown in In the embodiments of the present application, the line width of the global bus 100 is greater than the line width of the local bus 200.
[0127] The line spacing of each global bus 100 is greater than the line spacing of each local bus 200.
[0128] In the embodiments of the present application, the global bus 100 is set in the metal interconnection layer of the chip packaging structure, and the line width and the line spacing of the global bus 100 are set to be greater than the line width and the line spacing of the lower metal layer, so as to provide a low-resistance signal transmission channel for the pipeline registers 600, the signal repeaters 500 and the like, and to avoid the signal attenuation and the timing convergence after long-distance transmission in cooperation with the signal amplification and temporary storage functions of the buffer.
[0129] In the chip packaging structure in the embodiments of the present application, the global bus 100 and the local bus 200 are independent topological structures, and the bridge units 300 in each cluster corresponding to the same global bus are connected in parallel in the global bus 100. When transmitting global data to a specific computing core, the global data can be quickly transmitted based on the corresponding global bus 100 and the bridge unit 300, without being transmitted through each computing core in stages, so that the delay is low. In addition, the local data is transmitted through the local bus 200, and does not conflict with the global data, so as to avoid the pause of the computing core and improve the computing power utilization rate of each computing core. Moreover, the global data can be positioned and sent based on the global bus 100 and the corresponding bridge unit 300, so that even for the edge computing core, it does not need to wait for the forwarding and transmission of other computing cores, and therefore a large-scale computing core can be supported.
[0130] The present application also provides a circuit board, which is provided with at least one chip packaging structure in any of the above embodiments.
[0131] Since the circuit board in the embodiments of the present application is provided with the chip packaging structure in any of the above embodiments, it has all the beneficial effects of the chip packaging structure in any of the above embodiments, which will not be described here.
[0132] The application further provides an electronic device, comprising a circuit board and the chip packaging structure in any of the above embodiments, and the chip packaging structure is electrically connected with the circuit board.
[0133] Since the electronic device in the embodiments of the application comprises the chip packaging structure in any of the above embodiments, all the beneficial effects of the chip packaging structure in any of the above embodiments are also possessed, which will not be repeated here.
[0134] The above is only optional embodiments of the application, and does not limit the patent scope of the application, and any equivalent structural transformation, direct / indirect application in other related technical fields made by using the content of the application specification and drawings under the inventive concept of the application are included in the patent protection scope of the application.
Claims
1. A chip packaging structure, characterized in that, include: A computing core array includes multiple computing cores. Each computing core has a multiplexer at its input terminal. Each multiplexer has a first input terminal and a second input terminal. The multiple computing cores are divided into multiple clusters. Each cluster includes at least one computing core. Each cluster has a bridging unit. Each bridging unit includes the same number of output terminals as the multiplexers in the corresponding cluster. Local bus, used to transmit local data; Global bus, used for transmitting global data; The output of the preceding computing core between two adjacent computing cores is connected to the first input of the multiplexer corresponding to the next data core through the local bus. Each bridging unit's input is connected to the global bus, and each bridging unit's output is connected to the second input of each multiplexer within the corresponding cluster.
2. The chip packaging structure as described in claim 1, characterized in that, Includes multiple global buses; the global buses are either ring-shaped or linear. In the direction perpendicular to the chip packaging structure, a corresponding global bus is provided above the bridging unit corresponding to each cluster.
3. The chip packaging structure as described in claim 2, characterized in that, Each cluster contains only one computing core; Each bridging unit corresponding to a computing core includes a buffer; Each buffer is located on the side of its corresponding computing core, and the output of each buffer is connected to the second input of the multiplexer of its corresponding computing core. The input of each buffer is connected to the global bus in its vertical direction.
4. The chip packaging structure as described in claim 2, characterized in that, Each cluster contains at least two computing cores; Each bridging unit includes a buffer and a demultiplexer; the output of each buffer is connected to the input of the demultiplexer in the bridging unit it belongs to; In a direction parallel to the chip package structure, the buffer and demultiplexer in each bridging unit are located at the center of their corresponding cluster; Each demultiplexer includes multiple output terminals. The number of output terminals of each demultiplexer is the same as the number of computing cores in its corresponding cluster. Each output terminal of each demultiplexer is connected to the second input terminal of the multiplexer corresponding to each computing core in the corresponding cluster. The input of each buffer is connected to the global bus in its vertical direction.
5. The chip packaging structure as described in claim 2, characterized in that, The global bus is linear. In the chip package structure, global shared memory is provided at both ends of the global bus, and each end of the global bus is connected to its corresponding global shared memory.
6. The chip packaging structure as described in claim 2, characterized in that, The global bus is ring-shaped. In the chip package structure, multiple global shared memories are provided on the side of the chip package structure. Each ring-shaped global bus has an access point at the position corresponding to each global shared memory. Each ring-shaped global bus is connected to each global shared memory through the access point.
7. The chip packaging structure as described in claim 1, characterized in that, The global bus is located on the top layer of the metal interconnect layer of the chip package structure, and the local bus is located on the bottom layer of the metal interconnect layer; The line width of the global bus is greater than the line width of the local bus; The spacing between lines on the global bus is greater than the spacing between lines on the local bus.
8. The chip packaging structure as described in claim 1, characterized in that, In the direction perpendicular to the chip package structure, the chip package structure is provided with a signal repeater at the position corresponding to the signal attenuation critical point of each global bus, and each signal repeater is connected in series in its vertical direction global bus through a vertical through hole; In the direction perpendicular to the chip package structure, the chip package structure has a pipeline register at the position corresponding to the timing bottleneck segment of each global bus, and each pipeline register is connected in series with the global bus in its vertical direction through a vertical via.
9. A circuit board, characterized in that, The circuit board is provided with at least one chip packaging structure as described in any one of claims 1-8.
10. An electronic device, characterized in that, It includes a circuit board and a chip package structure as described in any one of claims 1-8, wherein the chip package structure is electrically connected to the circuit board.