Single-particle simulation acceleration method based on FPGA

Abstract

The invention relates to the technical field of single-particle simulation acceleration, in particular to a single-particle simulation acceleration method based on an FPGA, and the method comprises the steps: carrying out the system segmentation; performing register error injection; calibrating the fault model; constructing a fault mode database; inserting a fault injection module; performing FPGA mapping verification; fault injection simulation based on the FPGA; and carrying out data statistics and analysis. According to the method, efficient fault injection is realized through system segmentation adaptive FPGA hardware parallel architecture, combination of fault model calibration and physical scene alignment and by-pass circuits. According to the method, the bottlenecks of time explosion of traditional software simulation and resource scarcity and chip vulnerability of irradiation testing are broken through, the single event effect evaluation period of a large-scale system is compressed to the hour level through the FPGA hardware acceleration characteristic, and the requirement for rapid verification of an integrated circuit under the advanced technology is met. Fault model parameters are calibrated through maximum likelihood estimation and Bayesian updating, the randomness of a real single-particle event is simulated in combination with a Poisson process, and it is ensured that a simulation result is highly consistent with a physical experiment.

Description

Technical Field

[0001] The embodiments of this application relate to the field of single-event simulation acceleration technology, and particularly to an FPGA-based single-event simulation acceleration method. Background Technology

[0002] In recent years, the global space industry has flourished, with various space missions constantly expanding, achieving significant breakthroughs in everything from deep space exploration to low-Earth orbit satellite communications and manned spaceflight. As the scale and complexity of these space missions continue to rise, aerospace electronic equipment faces unprecedented challenges. The high-energy particle and radiation environment in space places stringent requirements on the radiation resistance of large-scale aerospace integrated circuits. Among these, single-event effects are a key factor affecting the stable operation of aerospace electronic equipment.

[0003] Single-event effects (SEE), caused by high-energy particles colliding with the interior of semiconductor devices, can lead to faults such as single-event upsets (SWEs) and single-event transients (SETs). These faults can cause data errors and logic lock-ups, seriously threatening the normal operation of spacecraft. my country's Shijian-4 satellite experiences an average of 3 to 4 SWEs per day, resulting in data errors, communication interruptions, and other anomalies. The Fengyun-1B satellite's attitude control computer experienced multiple SWEs due to inadequate radiation resistance of its components, affecting its planned lifespan. Therefore, accurately assessing the impact of SWEs on aerospace chips is crucial for ensuring the reliability of spacecraft.

[0004] Traditional single-event effect assessments primarily rely on two technical approaches. The first is physical irradiation testing, which uses particle accelerators (such as heavy-ion accelerators and proton accelerators) to create simulated extreme radiation environments. The integrated circuit under test is placed within these environments, and the types, frequencies, and effects of faults caused by particle impacts are recorded, thereby obtaining key parameters such as the single-event flip cross section and latch-up threshold of the device. The second is software simulation technology, which uses circuit-level or behavioral-level simulation tools such as SPICE and Verilog-A to build detailed models of the integrated circuit. By injecting virtual charges or bit-flip signals, the single-event impact process is simulated, and the fault propagation path and system response are analyzed.

[0005] Physical irradiation testing relies on scarce and expensive particle acceleration equipment, with testing cycles lasting weeks or even months, and the cost per test is extremely high. Furthermore, high-energy particles can cause permanent damage to the device under test, making it unusable. While software simulation does not require physical equipment, the computational load increases exponentially with the scaling up of integrated circuits, and evaluation cycles often reach days to weeks, making it difficult to meet the verification needs of rapid iteration of devices under advanced processes. From a reliability perspective, traditional software simulation methods often use fixed fault models, such as defaulting to single-bit flip probabilities and ignoring multi-bit flip distributions. Parameter settings rely on experience rather than actual measurement and calibration, and the random temporal distribution characteristics of single-particle events are not considered. This leads to significant deviations between simulation results and real physical scenarios. Summary of the Invention

[0006] To address the aforementioned technical issues, embodiments of this application propose an FPGA-based single-event simulation acceleration method. This method aims to overcome the technical bottlenecks of time explosion in traditional software simulation and resource scarcity and chip vulnerability in irradiation testing. By leveraging the hardware acceleration capabilities of FPGAs, the method compresses the evaluation of single-event effects in large-scale systems to the hour level, reducing evaluation costs and adapting to the rapid verification requirements of integrated circuits under advanced processes. It ensures that the simulation results are highly consistent with physical experiments and accurately outputs quantitative data such as the distribution of sensitive areas of devices and flip-section curves.

[0007] To achieve the above objectives, embodiments of this application propose an FPGA-based single-event simulation acceleration method. The method includes: employing a partitioning strategy combining size constraints and hardened design correlation constraints to divide the processor system to be verified into multiple functional modules according to module size; performing single-event fault simulation on each functional module using register-level fault injection technology; after completing the initial experiment of register-level fault injection, parameterizing and calibrating the random fault model used for subsequent large-scale injection and FPGA simulation; statistically analyzing the module interface fault modes, fault propagation paths, and soft error rates obtained from the single-event fault simulation to construct a fault mode database; and creating a fault injection module consisting of a fault mode lookup table, a random number generator, and control logic for fault injection. The module simulates single-event random injection events using a random number generator and dynamically selects the target register and injection mode based on the fault probability distribution in the fault mode lookup table. It verifies the engineering feasibility and non-intrusiveness of the injection logic of the fault injection module, ensuring that resources, timing, and observability meet the simulation experiment requirements. All functional modules and the fault injection module are jointly deployed on an FPGA simulation system, achieving simultaneous injection simulation of multiple registers through parallel processing. During the simulation, real-time acquisition of module interface response data, fault propagation paths, and system state changes forms a complete simulation dataset. Deep mining of the simulation dataset extracts system response process characteristics, soft error rates, and sensitive modules for fault propagation under single-event effects, outputting a reliability assessment report for the processor system to be verified.

[0008] To achieve the above objectives, embodiments of this application also propose an electronic device, including a processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to execute the instructions such that the electronic device can implement the FPGA-based single-event simulation acceleration method described above.

[0009] To achieve the above objectives, embodiments of this application also propose a computer-readable storage medium storing a computer program that, when executed by a processor, enables the implementation of an FPGA-based single-event simulation acceleration method as described above.

[0010] Optionally, the size constraint is used to limit the logic size of each functional module to no more than a preset threshold based on the availability of logic units, memory units and interconnect bandwidth of the FPGA's hardware resources. The hardened design associativity constraint is used to preferentially divide the unhardened module into independent units based on whether there is a single-event fault resistance design inside the module, so as to ensure the targeting of single-event fault injection and the analyzability of system behavior.

[0011] Optionally, single-event fault simulation is performed on each functional module using register-level fault injection technology, including: Traverse the addresses of all registers within the functional module, and for each register, determine the number of fault injections based on a preset confidence calculation model. The confidence calculation model combines the register's criticality, operating frequency, and historical failure rate data within the functional module to dynamically adjust the injection strategy, thereby covering typical failure modes and reducing redundant fault injections. Assume the processor system to be verified has a total of The register, denoted as the first... The registers are , ,set up The confidence score is This is used to characterize its relative importance in system reliability, and the total number of error injection budgets is... Assigned to The number of errors in the annotation is , Physical flip rate , The probability of a single bit flip occurring is The overall probability of multi-bit flipping is The number of bits affected by multi-bit flipping is The distribution function at time is The confidence amplification factor is This is used to control the concentration of error allocation; the duration of a single simulation window is [duration missing]. The fault model parameter vector is , The observation dataset obtained from the error annotation experiment is ; ; in, The higher the register, the more space it is allocated. The more, the less wasted resources on unimportant registers, when At that time, the number of incorrect entries is calculated as follows: Proportional allocation, when At that time, magnify A higher percentage of register errors, with a greater focus on critical registers. This indicates rounding to the nearest whole number; For each time The injected events are randomly selected based on fault type and injection time. Fault types include single-bit flips and multi-bit flips, based on... Determine if it is a multi-bit flip; if it is, then from... Number of bits affected by extraction ; Assuming single-particle injection is a point process Poisson, then within a given simulation window... Intra-injection time The distribution is either uniform or arrives at exponential intervals according to Poisson events; ; ; in, The time interval between two injection events. For interval time greater than The probability, Let be the probability density function of the time interval; If the goal is to make the simulation within the time window Internal reproduction expected number of physical flips The expected number of injections should be: Using scaling factor Align the number of injections with the physical rate; ; in, Depend on and Decide, .

[0012] Optionally, after completing the initial experiment of register-level fault injection, the random fault model used for subsequent large-scale injection and FPGA simulation is parameterized and calibrated, including: Data aggregation integrates the original observations obtained from register error injection and the available external reference data, with each error-injected observation recorded as a vector; Group modeling is performed, with hierarchical models based on register function, physical layout, and operating frequency. Independent distributions are fitted for each group, and multi-bit flips and timing-related injections are modeled separately. Parameter estimation and statistical testing: the estimated distribution parameters are updated using maximum likelihood estimation or Bayesian estimation, and the goodness of fit is evaluated using chi-square test, KS test or confidence interval. If the sample is insufficient, Bayesian prior and confidence interval are used for expansion. Sensitivity analysis involves conducting Monte Carlo experiments by changing key parameters, including single-bit flip rate, multi-bit flip rate, and injection time distribution, to evaluate the key parameters that have the greatest impact on the sensitivity of the final SER and critical path, thereby determining the number of samples and confidence level required for subsequent simulations. Output and judgment criteria: Generate a set of calibrated fault models, including the injection probability distribution of each type of register, multi-bit flip model, time-related parameters, parameter confidence intervals and version descriptions. The calibrated model is characterized by being able to reproduce the SER error distribution of the reference experiment at a predetermined confidence level, and sensitivity analysis showing that no single uncalibrated parameter dominates the error. After calibration, the updated optimal parameter set is written back to the register-level injection model to dynamically adjust the confidence distribution and injection frequency allocation for the next round of injection. After multiple iterations, the obtained error injection probability model can be stably converged to the reliable parameter space, providing statistically consistent input data for the subsequent construction of the fault mode database. By performing statistical modeling and parameter calibration on the data obtained from the register-level error injection experiment, a highly reliable fault model consistent with the physical single-event effect is constructed.

[0013] Optionally, to determine whether a single injection observation results in a single bit flip, we assume that the bits are independent and identically distributed, with a probability of... If for A total of observed Secondary injection, in which If a single-bit flip occurs, then its likelihood function is... and MLE solution They are represented as follows: ; ; in, for The actual number of times the observation was incorrect. Indicates in The number of single-bit flips occurring during each error injection was precisely calculated from the initial error injection experimental data to determine the probability of a single-bit flip occurring in each register, avoiding assumptions based on experience. The resulting deviation makes the single-bit flip probability of the fault model consistent with the actual observation; If a set of multi-bit flipped size samples is observed Then for Performing the discrete distribution polynomial MLE, we obtain: ; in, Indicates the effect of multi-bit flipping The probability of each bit, i.e., the estimated value of the multi-bit flip distribution function. Indicates in In multi-bit flip events, the impact The number of multi-bit flip events per bit. This represents the total number of observed multi-bit flip events; If in the total simulation time Observed in After the second flip, the Poisson MLE representation is: ; in, Indicates the total simulation time Inside, observed The actual number of flips, for The maximum likelihood estimate; If the data is sparse, a Bayesian update is used to introduce priors. If observed Success and observation Failure, then posterior for: ; posterior mean for: ; in, , All parameters are preset Bayesian update parameters.

[0014] Optionally, statistical analysis is performed on the module interface failure modes, failure propagation paths, and soft error rates obtained from single-event fault simulations to construct a fault mode database, including: A fault mode lookup table (LUT) is established to record the fault types and their probabilities caused by different register injections. At the same time, a fault propagation path table is established to describe the logical relationship and impact range of fault transmission between functional modules, providing data support for subsequent simulations.

[0015] Optionally, verify the engineering feasibility and non-intrusiveness of the injection logic of the fault injection module, ensuring that resources, timing, and observability meet the simulation experiment requirements, including: Synthesis and resource assessment: Perform logic synthesis on the overall design including injected logic, record the usage of LUT, FF, BRAM, DSP and estimated power consumption, compare with the available resources of the target FPGA, and determine whether it is necessary to reduce the injected parallelism or adopt batch deployment. Static timing analysis is performed on the synthesized netlist to check setup and holdslack at the clock frequency of the critical path. Special attention is paid to the impact of injected control logic on the original clock domain. Constraints are set for all critical clock domains and the timing margin is verified to be within the safe range. Functional and non-invasive verification involves performing regression simulations on the gate-level / post-routenetlist, verifying functional consistency using fault-free baseline test vectors, and evaluating the impact of injected logic on circuit behavior and minimizing invasiveness if it adds observables or signal probes. Injection timing and synchronization tests are conducted to verify that the injected event can be accurately synchronized to the clock edge of the target register. Injection delay and repeatability are measured. If multiple clock domains exist, a cross-domain synchronization strategy is provided. Output and judgment criteria: Output mapping verification report, including resource usage table, timing slack report, functional regression results, injection to effectiveness delay statistics, observation point coverage and playback verification results. Passing conditions include: resource usage is less than or equal to the available FPGA amount, critical clock domain setupslack is greater than the specified threshold, functional consistency under fault-free baseline, and injection effectiveness delay is controllable and reproducible. If not met, return to the fault injection module insertion stage to trim the injection logic or adopt a batch injection strategy.

[0016] Optionally, the simulation dataset can be deeply mined to extract system response process characteristics, soft error rate, and sensitive modules for fault propagation under single-event effects, outputting a reliability assessment report of the processor system to be verified, including: The soft error rate is calculated by comparing the number of fault triggers in each functional module with the number of system malfunctions. Analyze the correlation between fault response time and system recovery mechanism to assess system reliability; By using visualization tools to display the distribution of failure modes and critical paths, a basis for system hardening design optimization is provided, and finally, a reliability assessment report of the processor system to be verified is output.

[0017] The embodiments of this application propose an FPGA-based single-event simulation acceleration method, which has the following advantages compared with traditional single-event simulation technology.

[0018] This application effectively solves the time explosion problem of traditional software simulation by using system partitioning and FPGA hardware parallel architecture. Traditional software simulation's computational overhead increases exponentially with circuit size, while this application decomposes the processor system to be verified into parallel-deployable functional modules according to FPGA resource constraints. Combined with efficient fault injection methods such as bypass circuit injection, the single-event effect evaluation cycle is significantly shortened. Compared to irradiation testing, which relies on scarce and expensive experimental environments and carries the risk of chip damage, this application eliminates the need for complex radiation environments, resulting in lower implementation costs. Compared to software simulation, the FPGA hardware acceleration characteristics increase simulation speed to the hourly level, enabling rapid single-event sensitivity evaluation of large-scale systems, significantly meeting the high-efficiency requirements of integrated circuit reliability verification under advanced processes.

[0019] To ensure the physical reliability of simulation results and support precise hardening, this application addresses the issue of subjective bias in model parameters in traditional simulations through a fault model calibration and physical scenario alignment mechanism. Utilizing maximum likelihood estimation and Bayesian update methods, key parameters such as single-bit flip probability and multi-bit flip distribution are calibrated based on initial error-injected data. Simultaneously, the randomness of single-event events is simulated using a Poisson process, ensuring consistency between the simulated error injection count and the actual physical flip rate. The simulation results can accurately locate single-event sensitive regions of devices, such as the drain region of cutoff MOS transistors and other critical nodes prone to flipping, and show good consistency with heavy-ion single-event effect experimental results. This high-reliability simulation output provides quantitative data such as sensitive region distribution and flip cross-section curves for integrated circuits, directly guiding radiation-hardening design and effectively reducing the soft error risk in electronic systems in aerospace and other fields. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies of this application will be briefly introduced below. Obviously, the following drawings are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings described herein are only used to explain this application and are not intended to limit this application.

[0021] Figure 1 This is a flowchart of a single-particle simulation acceleration method based on FPGA provided in one embodiment of this application; Figure 2 This is a detailed schematic diagram of a single-particle simulation acceleration method based on FPGA provided in one embodiment of this application; Figure 3 This is a timing diagram of the simulation stage provided in one embodiment of this application; Figure 4 This is an internal structure diagram of a fault injection module provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. Those skilled in the art will understand that many technical details have been presented in the embodiments of this application to facilitate better understanding. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The following embodiments can be combined with and referenced by each other without contradiction.

[0023] This application primarily addresses the following technical issues.

[0024] To address the "credibility deficiency" in traditional simulations, which relies on empirical parameter settings for fault models, lacks experimental calibration, and fails to simulate the random time characteristics of single-event events, resulting in significant deviations between simulation results and physical scenarios, it is necessary to solve the technical problem of how to improve the physical consistency of single-event simulation results and ensure the credibility of evaluation data by aligning the model calibration mechanism with the physical scenario.

[0025] To address the efficiency bottlenecks of traditional software simulation, which suffers from exponentially increasing computational overhead and excessively long evaluation cycles as circuit size increases, and the problems of physical irradiation testing, which heavily relies on scarce and expensive equipment, carries the risk of chip damage, and has a long cycle, it is necessary to solve the technical problem of how to achieve efficient acceleration of single-event effect evaluation for large-scale integrated circuits through hardware architecture optimization, thereby shortening the verification cycle and reducing costs.

[0026] To address these technical issues, one embodiment of this application proposes an FPGA-based method for accelerating single-event simulations. The implementation details of this FPGA-based method for accelerating single-event simulations are described below. The following implementation details are provided for ease of understanding only and are not essential for implementing this solution.

[0027] The specific process of the FPGA-based single-event simulation acceleration method proposed in this embodiment can be described as follows: Figure 1 As shown, its technical details are as follows: Figure 2 As shown, the method includes: Step 11: Using a segmentation strategy that combines size constraints and hardened design correlation constraints, the processor system to be verified is divided into multiple functional modules according to module size.

[0028] In practical implementation, when performing simulation, it is first necessary to adopt a partitioning strategy that combines scale constraints and hardened design correlation constraints to divide the processor system to be verified into multiple functional modules according to module size.

[0029] In one example, the partitioning strategy comprises two parts: size constraints and hardened design-related constraints. Size constraints limit the logic size of each functional module to a preset threshold based on the availability of logic units, memory units, and interconnect bandwidth in the FPGA's hardware resources. Hardened design-related constraints prioritize partitioning unhardened modules into independent units based on the presence of single-event fault (SIF) resistant designs (such as redundancy checks and error correction codes) within the module, ensuring the targeting of SIF injection and the analyzability of system behavior.

[0030] Step 12: Perform single-event fault simulation on each functional module using register-level fault injection technology.

[0031] In practical implementation, after the functional modules are divided, single-event fault simulation can be performed on each functional module using register-level fault injection technology. The timing of the simulation phase can be as follows: Figure 3 As shown.

[0032] When performing register-level fault injection, the addresses of all registers within the functional module are traversed. For each register, the number of fault injection attempts is determined based on a preset confidence calculation model. The confidence calculation model dynamically adjusts the injection strategy by combining the register's criticality in the functional module, its operating frequency, and historical failure rate data to cover typical fault modes and reduce redundant fault injections.

[0033] To facilitate a quantitative description of the register-level error injection process and the fault model calibration process, this embodiment defines the relevant parameters and symbols as follows.

[0034] Assume the processor system to be verified has a total of The register, denoted as the first... The registers are , , The importance of the system during operation, its historical failure behavior, and its operating frequency can all be quantified as parameters. These parameters can be used to build a confidence-driven dynamic injection model, and subsequent parameter estimation and correction can be performed.

[0035] set up The confidence score is This is used to characterize its relative importance in system reliability, and the total number of error injection budgets is... Assigned to The number of errors in the annotation is , The physical flip rate (Single Event Upset Rate) is , The probability of a single-bit flip (SBU) occurring is The overall probability of multi-bit flip (MBU) is The number of bits affected by multi-bit flipping is The distribution function at time is The confidence amplification factor is This is used to control the concentration of error allocation; the duration of a single simulation window is [duration missing]. The fault model parameter vector is , The observation dataset obtained from the error annotation experiment is .

[0036] This can be expressed by the formula: ; in, The higher the register, the more space it is allocated. The more, the less wasted resources on unimportant registers, when At that time, the number of incorrect entries is calculated as follows: Proportional distribution (uniform tilt), when At that time, magnify A higher percentage of register errors, with a greater focus on critical registers. This means rounding to the nearest integer while ensuring that the result is accurate. .

[0037] By prioritizing coverage of high-value registers within a limited budget and reducing redundant injections, the injection frequency allocation method is consistent with the confidence-weighted sampling approach, significantly improving critical path coverage.

[0038] For each time The injected events are randomly selected based on fault type and injection time. Fault types include single-bit flips and multi-bit flips, based on... Determine if it is a multi-bit flip; if it is, then from... Number of bits affected by extraction .

[0039] Assuming single-particle injection is a point process Poisson, then within a given simulation window... Intra-injection time The distribution is either uniform or exponentially spaced according to the arrival intervals of Poisson events, specifically expressed as: ; ; in, The time interval between two injection events. For interval time greater than The probability, Let be the probability density function of the time interval. The above formula generates injection times that conform to physical laws, avoiding overly dense or sparse injection times and ensuring the realism of the simulation scenario.

[0040] Establish injection probability and physical flip rate The mapping is used to facilitate subsequent calibration.

[0041] If the goal is to make the simulation within the time window Internal reproduction expected number of physical flips The expected number of injections should be: Using scaling factor Align the number of injections with the physical rate; ; in, Depend on and Decide, .

[0042] Step 13: After completing the initial test of register-level fault injection, parameterize and calibrate the random fault model used for subsequent large-scale injection and FPGA simulation.

[0043] In practice, after completing the initial experiment of register-level fault injection, the random fault model used for subsequent large-scale injection and FPGA simulation needs to be parameterized and calibrated.

[0044] Parameterizing and calibrating the stochastic fault model used for subsequent large-scale injection and FPGA simulation can align the simulated probability distribution with data from physical experiments or reliable sources, thereby reducing statistical bias and improving the reliability of simulation conclusions. The specific steps of this process are as follows.

[0045] Step 131: Data aggregation. Integrate the original observations obtained from register error injection with the available external reference data. Each error-injected observation is recorded as a vector.

[0046] For example assemble .

[0047] Step 132: Group modeling, hierarchically according to register function, physical layout and operating frequency, fit independent distributions respectively, and model multi-bit flipping and timing-related injection separately.

[0048] Step 133: Parameter estimation and statistical testing. Update the estimated distribution parameters using maximum likelihood estimation or Bayesian estimation. Evaluate the goodness of fit using chi-square test, KS test or confidence interval. If the sample is insufficient, expand it using Bayesian prior and confidence interval.

[0049] To determine whether a single injection observation results in a single bit flip, assuming independent and identically distributed, the probability is... If for A total of observed Secondary injection, in which If a single-bit flip occurs, then its likelihood function is... and MLE solution They are represented as follows: ; ; in, for The actual number of times the observation was incorrect. Indicates in The number of single-bit flips occurring during each error injection was precisely calculated from the initial error injection experimental data to determine the probability of a single-bit flip occurring in each register, avoiding assumptions based on experience. The resulting deviation makes the single-bit flip probability of the fault model consistent with the actual observation.

[0050] If a set of multi-bit flipped size samples is observed Then for Performing the discrete distribution polynomial MLE, we obtain: ; in, Indicates the effect of multi-bit flipping The probability of each bit, i.e., the estimated value of the multi-bit flip distribution function. Indicates in In multi-bit flip events, the impact The number of multi-bit flip events per bit. This represents the total number of observed multi-bit flip events.

[0051] If in the total simulation time Observed in After the second flip, the Poisson MLE representation is: ; in, Indicates the total simulation time Inside, observed The actual number of flips, for The maximum likelihood estimate.

[0052] If the data is sparse, a Bayesian update is used to introduce priors. If observed Success and observation Failure, then posterior for: ; posterior mean for: ; in, , All parameters are preset Bayesian update parameters.

[0053] Bayesian methods are often used in reliability modeling to solve small sample problems.

[0054] Step 134, Sensitivity Analysis: Monte Carlo experiments are conducted by changing key parameters, including single-bit flip rate, multi-bit flip rate, and injection time distribution, to evaluate the key parameters that have the greatest impact on the final SER and critical path sensitivity, thereby determining the number of samples and confidence level required for subsequent simulations.

[0055] Monte Carlo and variance decomposition are used to evaluate the contribution of parameters to the output. First-order Sobol exponent. Indicates input parameters Individual contribution to output variance, total effect express The total contribution after interacting with other parameters.

[0056] Sample size estimation: if at confidence level Lower estimate proportion The error does not exceed .

[0057] .

[0058] Step 135, Output and Judgment Criteria: Generate a set of calibrated fault models, including the injection probability distribution of each type of register, multi-bit flip model, time-dependent parameters, parameter confidence intervals, and version descriptions. The criterion for successful calibration is that the model can reproduce the SER error distribution of the reference experiment at a predetermined confidence level, and sensitivity analysis shows that no single uncalibrated parameter dominates the error.

[0059] Step 136: After calibration, the updated optimal parameter set is written back to the register-level injection model to dynamically adjust the confidence distribution and injection frequency allocation for the next round of injection. After multiple iterations, the obtained injection probability model can stably converge to the reliable parameter space, providing statistically consistent input data for the subsequent construction of the fault mode database. By performing statistical modeling and parameter calibration on the data obtained from the register-level injection experiment, a highly reliable fault model consistent with the physical single-event effect is constructed.

[0060] The updated optimal parameter set is represented as follows: .

[0061] For registers The error count has been updated to: ; in, For the first Registers in wheel simulation The number of times the annotation was incorrect. The confidence level is corrected based on the calibration results. This is the statistically calibrated single-event flip rate. This is a confidence amplification factor used to control the distribution concentration. This dynamic write-back mechanism enables the register-level error injection strategy to adaptively optimize based on actual observation data, thereby gradually approximating the single-event fault distribution characteristics in real physical environments.

[0062] Step 14: Perform statistical analysis on the module interface fault modes, fault propagation paths and soft error rates obtained from single-event fault simulation, and construct a fault mode database.

[0063] In practice, after parameterizing and calibrating the random fault model used for subsequent large-scale injection and FPGA simulation, statistical analysis can be performed on the module interface fault modes, fault propagation paths and soft error rates obtained from single-event fault simulation to build a fault mode database.

[0064] In one example, when building a fault mode database, it is necessary to create a fault mode lookup table (LUT) to record the fault types caused by different register injections and their probabilities of occurrence. At the same time, a fault propagation path table is created to describe the logical relationship and impact range of fault transmission between functional modules, providing data support for subsequent simulations.

[0065] Step 15: Create a fault injection module consisting of a fault mode lookup table, a random number generator, and control logic. The fault injection module simulates a single-particle random injection event through the random number generator and dynamically selects the target register and injection mode according to the fault probability distribution of the fault mode lookup table.

[0066] In the specific implementation, after the fault mode database is constructed, a fault injection module is made, consisting of a fault mode lookup table, a random number generator, and control logic. The fault injection module simulates single-event random injection events through the random number generator, and dynamically selects the target register and injection mode according to the fault probability distribution of the fault mode lookup table, so as to ensure that the fault injection process conforms to the randomness and statistical characteristics of the actual single-event effect.

[0067] In one example, the structure of the fault injection module can be as follows: Figure 4 As shown.

[0068] Step 16: Verify the engineering feasibility and non-intrusiveness of the injection logic of the fault injection module, and ensure that resources, timing and observability meet the requirements of the simulation experiment.

[0069] In practice, before the fault injection module and the function module under test are jointly placed on the FPGA for parallel operation, it is necessary to verify the engineering feasibility and non-intrusiveness of the injection logic, and ensure that the resources, timing and observability after implementation meet the simulation experiment requirements.

[0070] The specific steps for FPGA mapping verification are as follows.

[0071] Step 161, Synthesis and Resource Assessment: Perform logic synthesis on the overall design including the injected logic, record the usage of LUTs, FFs, BRAMs, DSPs and the estimated power consumption, compare with the available resources of the target FPGA, and determine whether it is necessary to reduce the injected parallelism or adopt batch deployment.

[0072] Step 162, Static Timing Analysis (STA): Perform static timing analysis on the synthesized netlist to check setup and holdslack at the critical path clock frequency. Pay special attention to the impact of injected control logic on the original clock domain. Set constraints for all critical clock domains and verify whether the timing margin is still within the safe range.

[0073] Step 163, Functional and Non-Intrusive Verification: Perform regression simulation on the gate-level / post-routenetlist, verify functional consistency using fault-free baseline test vectors, and if injected logic adds observables or signal probes, evaluate the impact of these probes on circuit behavior and minimize invasiveness.

[0074] Step 164: Inject timing and synchronization test. Verify that the injected event can be accurately synchronized to the clock edge of the target register. Measure the injection delay and repeatability. If multiple clock domains exist, provide a cross-domain synchronization strategy.

[0075] Step 165, Output and Judgment Criteria: Output a mapping verification report, including a resource usage table, timing slack report, functional regression results, injection-to-effectiveness delay statistics, observation point coverage, and playback verification results. Passing conditions include: resource usage is less than or equal to the available FPGA amount, critical clock domain setupslack is greater than the specified threshold, functional consistency under a fault-free baseline, and injection-to-effectiveness delay is controllable and reproducible. If not met, return to the fault injection module insertion stage to trim the injection logic or adopt a batch injection strategy.

[0076] Step 17: Deploy all functional modules and fault injection modules together in the FPGA simulation system. Implement simultaneous injection simulation of multiple registers through parallel processing. During the simulation, collect the response data of the module interfaces, fault propagation paths and system state changes in real time to form a complete simulation dataset.

[0077] In practical implementation, after verification is completed, each functional module and fault injection module can be jointly deployed in the FPGA simulation system. Simultaneous injection of multiple registers into the simulation is achieved through parallel processing. During the simulation, the response data of the module interface, the fault propagation path and the system state changes are collected in real time to form a complete simulation dataset.

[0078] Step 18: Deeply mine the simulation dataset to extract the system response process characteristics, soft error rate and sensitive modules of fault propagation under single-event effect, and output the reliability assessment report of the processor system to be verified.

[0079] In practical implementation, after completing the FPGA-based fault injection simulation, it is necessary to perform in-depth mining of the simulation dataset to extract the system response process characteristics, soft error rate, and sensitive modules of fault propagation under single-event effects, and output a reliability assessment report of the processor system to be verified.

[0080] In one example, in-depth analysis of the simulation dataset includes calculating the soft error rate by comparing the ratio of the number of fault triggers to the number of system malfunctions for each functional module, analyzing the correlation between fault response time and system recovery mechanism, evaluating system reliability, displaying the distribution of fault modes and critical paths through visualization tools, providing a basis for system hardening design optimization, and finally outputting a reliability assessment report of the processor system to be verified.

[0081] This embodiment proposes an FPGA-based method for accelerating single-event simulation, which has the following advantages compared with traditional single-event simulation techniques.

[0082] This embodiment effectively solves the time explosion problem of traditional software simulation by using system partitioning and FPGA hardware parallel architecture. Traditional software simulation's computational overhead increases exponentially with circuit size, while this embodiment breaks down the processor system to be verified into parallel-deployable functional modules according to FPGA resource constraints. Combined with efficient fault injection methods such as bypass circuit injection, the single-event effect evaluation cycle is significantly shortened. Compared to irradiation testing, which relies on scarce and expensive experimental environments and carries the risk of chip damage, this embodiment eliminates the need for complex radiation environments, resulting in lower implementation costs. Compared to software simulation, the FPGA hardware acceleration capabilities increase simulation speed to the hourly level, enabling rapid single-event sensitivity evaluation of large-scale systems and significantly meeting the high-efficiency requirements of integrated circuit reliability verification under advanced processes.

[0083] To ensure the physical reliability of simulation results and support precise hardening, this embodiment addresses the issue of subjective bias in model parameters in traditional simulations by employing a fault model calibration and physical scenario alignment mechanism. Utilizing maximum likelihood estimation and Bayesian update methods, key parameters such as single-bit flip probability and multi-bit flip distribution are calibrated based on initial error-injected data. Simultaneously, the randomness of single-event events is simulated using a Poisson process, ensuring consistency between the simulated error injection count and the actual physical flip rate. The simulation results can accurately locate single-event sensitive regions of devices, such as the drain region of cutoff MOS transistors and other critical nodes prone to flipping, and exhibit good consistency with heavy-ion single-event effect test results. This high-reliability simulation output provides quantitative data such as sensitive region distribution and flip cross-section curves for integrated circuits, directly guiding radiation-hardening design and effectively reducing the soft error risk in electronic systems in aerospace and other fields.

[0084] The steps described above are merely for clarity in describing the technical solution. In actual implementation, they can be combined into one step, or certain steps can be broken down into multiple steps, as long as they involve the same logical relationship, they are all within the scope of protection of this application. Any insignificant modifications or designs added to the algorithm or process, as long as they do not change the core of the algorithm or process, are also within the scope of protection of this application.

[0085] Another embodiment of this application provides an electronic device, such as Figure 5 As shown, it includes a processor 21 and a memory 22. The memory 22 stores instructions that the processor 21 can execute. When the processor 21 is configured to execute the instructions, the electronic device can implement an FPGA-based single-event simulation acceleration method as described in the above method embodiment.

[0086] The memory and processor are connected via a bus, which includes any number of interconnecting buses and bridges, connecting various circuits of one or more processors and the memory. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0087] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0088] Another embodiment of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, enables an FPGA-based single-event simulation acceleration method as described in the above method embodiments.

[0089] That is, those skilled in the art will understand that all or part of the steps in the above method embodiments can be implemented by a program instructing related hardware. The program is stored in a storage medium and includes several instructions to cause a device (such as a microcontroller, chip, etc.) or processor to execute all or part of the steps of the method described in the method embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0090] It will be understood by those skilled in the art that the above embodiments are specific implementations of this application, and various changes in form and detail can be made in practical applications without departing from the spirit and scope of this application. For those skilled in the art, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.

Claims

1. A method for accelerating single-event simulation based on FPGA, characterized in that, include: A partitioning strategy combining size constraints and hardened design correlation constraints is adopted to divide the processor system to be verified into multiple functional modules according to module size; Single-event fault simulations were performed on each functional module using register-level fault injection technology. After completing the initial experiment of register-level fault injection, the random fault model used for subsequent large-scale injection and FPGA simulation was parameterized and calibrated. Statistical analysis was performed on the module interface failure modes, failure propagation paths, and soft error rates obtained from single-event failure simulations to construct a failure mode database; A fault injection module consisting of a fault mode lookup table, a random number generator, and control logic is constructed. The fault injection module simulates a single-particle random injection event through the random number generator and dynamically selects the target register and injection mode according to the fault probability distribution of the fault mode lookup table. Verify the engineering feasibility and non-intrusiveness of the injection logic of the fault injection module, and ensure that resources, timing and observability meet the requirements of simulation experiments; The functional modules and fault injection modules are jointly deployed in the FPGA simulation system. Simultaneous injection of multiple registers into the simulation is achieved through parallel processing. During the simulation, the response data of the module interface, the fault propagation path and the system state changes are collected in real time to form a complete simulation dataset. The simulation dataset is deeply mined to extract the system response process characteristics, soft error rate, and sensitive modules of fault propagation under single-event effects, and output a reliability assessment report of the processor system to be verified.

2. The FPGA-based single-event simulation acceleration method according to claim 1, characterized in that, Size constraints are used to limit the logic size of each functional module to a preset threshold based on the availability of logic units, memory units, and interconnect bandwidth of FPGA hardware resources. Hardened design associativity constraints are used to prioritize the division of unhardened modules into independent units based on whether there is single-event fault resistance design inside the module, so as to ensure the targeting of single-event fault injection and the analyzability of system behavior.

3. The FPGA-based single-event simulation acceleration method according to claim 1, characterized in that, Single-event fault simulations were performed on each functional module using register-level fault injection techniques, including: Traverse the addresses of all registers within the functional module, and for each register, determine the number of fault injections based on a preset confidence calculation model. The confidence calculation model combines the register's criticality, operating frequency, and historical failure rate data within the functional module to dynamically adjust the injection strategy, thereby covering typical failure modes and reducing redundant fault injections. Assume the processor system to be verified has a total of The register, denoted as the first... The registers are , ,set up The confidence score is This is used to characterize its relative importance in system reliability, and the total number of error injection budgets is... Assigned to The number of errors in the annotation is , Physical flip rate , The probability of a single bit flip occurring is The overall probability of multi-bit flipping is The number of bits affected by multi-bit flipping is The distribution function at time is The confidence amplification factor is This is used to control the concentration of error allocation; the duration of a single simulation window is [duration missing]. The fault model parameter vector is , The observation dataset obtained from the error annotation experiment is ; ； in, The higher the register, the more space it receives. The more, the less wasted resources on unimportant registers, when At that time, the number of incorrect entries is calculated as follows: Proportional allocation, when At that time, magnify A higher percentage of register errors, with a greater focus on critical registers. This indicates rounding to the nearest whole number; For each time The injected events are randomly selected based on fault type and injection time. Fault types include single-bit flips and multi-bit flips, based on... Determine if it is a multi-bit flip; if it is, then from... Number of bits affected by extraction ; Assuming single-particle injection is a point process (Poisson), then within a given simulation window... Intra-injection time The distribution is either uniform or arrives at exponential intervals according to Poisson events; ； ； in, The time interval between two injection events. For interval time greater than The probability, Let be the probability density function of the time interval; If the goal is to make the simulation within the time window Internal reproduction expected number of physical flips The expected number of injections should be: Using scaling factor Align the number of injections with the physical rate; ； in, Depend on and Decide, .

4. The FPGA-based single-event simulation acceleration method according to claim 3, characterized in that, After completing the initial experiments on register-level fault injection, the random fault model used for subsequent large-scale injection and FPGA simulation was parameterized and calibrated, including: Data aggregation integrates the original observations obtained from register error injection and the available external reference data, with each error-injected observation recorded as a vector; Group modeling is performed, with hierarchical models based on register function, physical layout, and operating frequency. Independent distributions are fitted for each group, and multi-bit flips and timing-related injections are modeled separately. Parameter estimation and statistical testing: the estimated distribution parameters are updated using maximum likelihood estimation or Bayesian estimation, and the goodness of fit is evaluated using chi-square test, KS test or confidence interval. If the sample is insufficient, Bayesian prior and confidence interval are used for expansion. Sensitivity analysis involves conducting Monte Carlo experiments by changing key parameters, including single-bit flip rate, multi-bit flip rate, and injection time distribution, to evaluate the key parameters that have the greatest impact on the sensitivity of the final SER and critical path, thereby determining the number of samples and confidence level required for subsequent simulations. Output and judgment criteria: Generate a set of calibrated fault models, including the injection probability distribution of each type of register, multi-bit flip model, time-related parameters, parameter confidence intervals and version descriptions. The calibrated model is characterized by being able to reproduce the SER error distribution of the reference experiment at a predetermined confidence level, and sensitivity analysis showing that no single uncalibrated parameter dominates the error. After calibration, the updated optimal parameter set is written back to the register-level injection model to dynamically adjust the confidence distribution and injection frequency allocation for the next round of injection. After multiple iterations, the obtained error injection probability model can be stably converged to the reliable parameter space, providing statistically consistent input data for the subsequent construction of the fault mode database. By performing statistical modeling and parameter calibration on the data obtained from the register-level error injection experiment, a highly reliable fault model consistent with the physical single-event effect is constructed.

5. The FPGA-based single-event simulation acceleration method according to claim 4, characterized in that, To determine whether a single injection observation results in a single bit flip, assuming independent and identically distributed, the probability is... If for A total of observed Secondary injection, in which If a single-bit flip occurs, then its likelihood function is... and MLE solution They are represented as follows: ； ； in, for The actual number of times the observation was incorrect. Indicates in The number of single-bit flips occurring during each error injection was precisely calculated from the initial error injection experimental data to determine the probability of a single-bit flip occurring in each register, avoiding assumptions based on experience. The resulting deviation makes the single-bit flip probability of the fault model consistent with the actual observation; If a set of multi-bit flipped size samples is observed Then for Performing the discrete distribution polynomial MLE, we obtain: ； in, Indicates the effect of multi-bit flipping The probability of each bit, i.e., the estimated value of the multi-bit flip distribution function. Indicates in In multi-bit flip events, the impact The number of multi-bit flip events per bit. This represents the total number of observed multi-bit flip events; If in the total simulation time Observed in After the second flip, the Poisson MLE representation is: ； in, Indicates the total simulation time Inside, observed The actual number of flips, for The maximum likelihood estimate; If the data is sparse, a Bayesian update is used to introduce prior information. If observed Success and observation Failure, then posterior for: ； Posterior mean for: ； in, , All parameters are preset Bayesian update parameters.

6. The FPGA-based single-event simulation acceleration method according to claim 4, characterized in that, Statistical analysis was performed on the module interface failure modes, failure propagation paths, and soft error rates obtained from single-event fault simulations to construct a failure mode database, including: A fault mode lookup table (LUT) is established to record the fault types and their probabilities caused by different register injections. At the same time, a fault propagation path table is established to describe the logical relationship and impact range of fault transmission between functional modules, providing data support for subsequent simulations.

7. The FPGA-based single-event simulation acceleration method according to claim 6, characterized in that, Verify the engineering feasibility and non-intrusiveness of the injection logic of the fault injection module, ensuring that resources, timing, and observability meet the simulation experiment requirements, including: Synthesis and resource assessment: Perform logic synthesis on the overall design including injected logic, record the usage of LUT, FF, BRAM, DSP and estimated power consumption, compare with the available resources of the target FPGA, and determine whether it is necessary to reduce the injected parallelism or adopt batch deployment. Static timing analysis is performed on the synthesized netlist to check setup and holdslack at the clock frequency of the critical path. Special attention is paid to the impact of injected control logic on the original clock domain. Constraints are set for all critical clock domains and the timing margin is verified to be within the safe range. Functional and non-invasive verification involves performing regression simulations on the gate-level / post-routenetlist, verifying functional consistency using fault-free baseline test vectors, and evaluating the impact of injected logic on circuit behavior and minimizing invasiveness if it adds observables or signal probes. Injection timing and synchronization tests are conducted to verify that the injected event can be accurately synchronized to the clock edge of the target register. Injection delay and repeatability are measured. If multiple clock domains exist, a cross-domain synchronization strategy is provided. Output and judgment criteria: Output mapping verification report, including resource usage table, timing slack report, functional regression results, injection to effectiveness delay statistics, observation point coverage and playback verification results. Passing conditions include: resource usage is less than or equal to the available FPGA amount, critical clock domain setupslack is greater than the specified threshold, functional consistency under fault-free baseline, and injection effectiveness delay is controllable and reproducible. If not met, return to the fault injection module insertion stage to trim the injection logic or adopt a batch injection strategy.

8. The FPGA-based single-event simulation acceleration method according to claim 1, characterized in that, Deeply mine the simulation dataset to extract system response process characteristics, soft error rate, and sensitive modules for fault propagation under single-event effects, and output a reliability assessment report of the processor system to be verified, including: The soft error rate is calculated by comparing the number of fault triggers in each functional module with the number of system malfunctions. Analyze the correlation between fault response time and system recovery mechanism to assess system reliability; By using visualization tools to display the distribution of failure modes and critical paths, a basis for system hardening design optimization is provided, and finally, a reliability assessment report of the processor system to be verified is output.

9. An electronic device, characterized in that, include: A processor and a memory, wherein the memory stores instructions executable by the processor, and the processor is configured to, when executing the instructions, enable the electronic device to implement an FPGA-based single-event simulation acceleration method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it can implement an FPGA-based single-particle simulation acceleration method as described in any one of claims 1 to 8.

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