Modeling and optimizing method for FPGA (Field Programmable Gate Array) logic comprehensive implicit multipath selection structure

Abstract

A modeling and optimizing method for an implicit multi-path selection structure of FPGA logic integration relates to the technical field of digital circuits and mainly comprises the following steps: modeling the implicit multi-path selection structure into an address data matrix; carrying out data merging on an address data matrix obtained after modeling; judging the number N of data in the combined address data matrix, and if N is equal to 2n, constructing a balanced either-or multiplexer tree; if N is equal to 2n + 1, constructing a balanced one-out-of-two multiplexer tree and a top-layer one-out-of-two multiplexer; and if N does not meet the condition that N is equal to 2n or N is equal to 2n + 1, constructing an unbalanced one-out-of-two multiplexer tree. The circuit structure after address signal reconstruction is smaller in network level and smaller in area, and area occupation can be reduced after address signals are directly split, so that an implicit multi-path selection structure is simplified as much as possible.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, and in particular to a method for modeling and optimizing implicit multiplexing structures in FPGA logic synthesis. Background Technology

[0002] In FPGA design, multiplexers are common building blocks for data paths, widely used in processors, processor buses, network switches, and digital signal processing designs with resource sharing capabilities. In the behavioral description of logic circuits, the frequently used if, else, and case statements can all generate multiplexer circuits. Related data shows that multiplexers occupy more than 25% of the area in FPGA customer designs. Therefore, optimizing digital logic circuits based on multiplexers is an important research direction in the field of logic synthesis.

[0003] In logic synthesis tools, the number of resources is an important indicator of tool performance. In FPGA design, multiplexing structures are very common. When optimizing multiplexing structures, the first step is to identify the structure. Common multiplexing structures include explicit multiplexing structures 2:1Mux (two-to-one multiplexer) and Nto1Mux (multiple-to-one multiplexer), as well as implicit multiplexing structures Equal->Select (address selector). The characteristic of explicit multiplexing structures is that the data of each selection branch is explicit and can be directly obtained, so it is also called a complete multiplexing structure. Implicit multiplexing structures do not have complete selection branches and contain a large number of default items, so they are called incomplete multiplexing structures.

[0004] Existing multiplexer optimization methods can handle explicit two-to-one multiplexers and multiple-to-one multiplexers well, but there are no good analysis and optimization methods for implicit multiplexer structures containing a large number of default items.

[0005] Existing patent CN202510001843.1, "Optimization Method, Apparatus, Device and Medium for Multiplexer Trees," involves filtering selector paths from the multiplexer tree (the selector path is the signal transmission path with the highest level in the multiplexer tree) and then iteratively optimizing the multiplexer tree based on the selector paths. CN202310735390.6, "Optimization Method and System for Multiplexers Based on Improved Binary Decision Trees," optimizes multiplexers based on an improved binary decision tree algorithm, address matrix, data matrix, and area delay information, addressing the issues of large area and delay in hardware description language-mapped multiplexers. Summary of the Invention

[0006] The purpose of this invention is to propose a modeling and optimization method for implicit multiplexing structures in FPGA logic synthesis. For implicit multiplexing structures, different optimization methods are applied to maximize the reduction of circuit area and solve the problem of incomplete analysis and optimization of multiplexing structures.

[0007] The technical solution adopted by this invention to achieve its objective is a modeling and optimization method for implicit multiplexing structure in FPGA logic synthesis, comprising the following steps:

[0008] S1. Model the implicit multiplexing structure as an address data matrix;

[0009] S2. Merge the address data matrix obtained after modeling to generate a merged address data matrix;

[0010] S3. Determine the number of data N in the merged address data matrix. If the number of data N satisfies N=2 n Then construct a balanced two-to-one multiplexer tree; if the number of data N satisfies N=2 n +1, then construct a balanced 2-to-1 multiplexer tree plus a top-level 2-to-1 multiplexer; if the number of data N does not satisfy N=2 n Or N=2 n +1, then an unbalanced two-to-one multiplexer tree is constructed; where n is an integer.

[0011] Furthermore, step S1 specifically includes:

[0012] S101, Perform implicit multiplexing structure identification;

[0013] S102. Obtain the address and corresponding data signal and perform modeling;

[0014] S103, Generate address data matrix.

[0015] Furthermore, step S2 specifically includes:

[0016] S201, Traverse the address data matrix obtained in step S1;

[0017] S202. Determine whether the data already exists. If yes, proceed to step S203; otherwise, proceed to step S204.

[0018] S203, Merge addresses with identical data;

[0019] S204. Determine if the traversal has ended. If yes, proceed to step S205. If no, return to step S201.

[0020] S205. Generate the merged address data matrix.

[0021] Furthermore, in step S3, the number of data N satisfies N=2. n The specific method for constructing a balanced 2-to-1 multiplexer tree is as follows: the default item is treated as a selection branch with the same priority as the non-default item, and the address signal is reconstructed to construct a balanced 2-to-1 multiplexer tree.

[0022] The number of data is 2 n At that time, the reconstructed address signal has n bits. An explicit 2-to-1 multiplexer is generated using the merged address data matrix, forming a fully balanced 2-to-1 multiplexer tree. The optimized multiplexer count is calculated using the following formula:

[0023]

[0024] In the formula .

[0025] Furthermore, in step S3, the number of data N satisfies N=2. n When +1, the specific method for constructing a balanced binary multiplexer tree and adding a top-level binary multiplexer is as follows: treat the default item as a separate selection branch, construct the top-level binary multiplexer, and construct a balanced binary multiplexer tree for non-default items.

[0026] The number of data is 2 n When +1 is applied, the reconstructed address signal has n+1 bits, and the number of data items is 2. n In terms of implementation, an additional top-level 2-to-1 multiplexer is generated to distinguish between the default and non-default items. The formula for calculating the number of explicit 2-to-1 multiplexers generated after optimization is as follows:

[0027]

[0028] In the formula .

[0029] Furthermore, in step S3, the number of data N does not satisfy N=2. n Or N=2 n When +1, the specific method for constructing an unbalanced two-to-one multiplexer tree is as follows: the default item is directly split as a selection branch with the same priority as the non-default item, and an unbalanced two-to-one multiplexer tree is constructed.

[0030] The number of data points N does not satisfy N=2 n Or N=2 nWith a +1 value, a perfectly balanced 2-to-1 multiplexer tree cannot be generated. Therefore, the address signal is directly split to construct an unbalanced 2-to-1 multiplexer tree. After direct splitting, the number of bits in the new address signal is the same as the number of generated 2-to-1 multiplexers. The optimized formula for calculating the number of explicit 2-to-1 multiplexers is as follows:

[0031]

[0032] The beneficial effects of this invention are as follows:

[0033] This invention dynamically determines the actual data quantity after address signal merging in an implicit multiplexing structure. Based on the data quantity, it dynamically optimizes the address data matrix using either an address signal reconstruction optimization method or an address signal direct decomposition optimization method. The circuit structure after address signal reconstruction has a smaller network level and a smaller area. Direct address signal decomposition reduces area usage, thus simplifying the implicit multiplexing structure as much as possible. After applying the above optimization to 985 real-world user cases, the results show that the optimization achieved a net area saving of 11%, such as... Figure 6 As shown, the number of resources before optimization is taken as baseline 1. Attached Figure Description

[0034] Figure 1 The flowchart for modeling the implicit multiplexing structure as an address data matrix in step S1 of this embodiment of the invention is shown below.

[0035] Figure 2 This is a flowchart of step S2 of the present invention, which involves merging the address data matrix.

[0036] Figure 3 This is a detailed flowchart of step S3 in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the circuit structure before optimization in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the optimized circuit structure according to an embodiment of the present invention;

[0039] Figure 6 This is a diagram showing the comparison of resource quantity before and after optimization in a real-world user case of the present invention. Detailed Implementation

[0040] Figures 1-5 This invention illustrates a specific implementation of the FPGA logic synthesis implicit multiplexing structure modeling and optimization method, comprising the following steps:

[0041] S1. The implicit multiplexing structure is modeled as an address data matrix. The specific modeling process is as follows:

[0042] S101. Perform implicit multiplexing structure identification, that is, identify the Equal->Select implicit multiplexing structure in the netlist;

[0043] S102. Obtain the address and corresponding data signal and model them, that is, fill in the address and data in the table one by one, and use (-1) to represent the address of the default item;

[0044] S103. The generated address data matrix is ​​shown in the table below:

[0045] address data 000（0） a 001（1） b 010（2） c 011（3） a -1 b

[0046] S2. Merge the address data matrix obtained after modeling. The merging process is as follows:

[0047] S201, Traverse the address data matrix obtained in step S1;

[0048] S202. Determine whether the data already exists. If yes, proceed to step S203; otherwise, proceed to step S204.

[0049] S203, Merge addresses with identical data;

[0050] S204. Determine if the traversal has ended. If yes, proceed to step S205. If no, return to step S201.

[0051] S205. The merged address data matrix is ​​shown in the table below:

[0052] address data 000（0）、011（3） a 001（1）、-1 b 010（2） c

[0053] S3. Determine the number of data items N in the merged address data matrix.

[0054] If the number of data N satisfies N=2 n Then the default item is treated as a selection branch with the same priority as the non-default item for address signal reconstruction, and a balanced two-to-one multiplexer tree is constructed.

[0055] If the number of data N satisfies N=2 n If +1 is added, the default item will be treated as a separate selection branch, and a top-level binary multiplexer will be constructed. Non-default items will be used to construct a balanced binary multiplexer tree. In other words, this step constructs a balanced binary multiplexer tree plus a top-level binary multiplexer.

[0056] If the number of data N does not satisfy N=2 n Or N=2 nIf +1 is added, the default item will be split directly as a selection branch with the same priority as the non-default item, thus constructing an unbalanced two-to-one multiplexer tree.

[0057] n is an integer.

[0058] In this embodiment, Figure 4 The implicit multiplexing structure shown is optimized by modeling it as an address data matrix, address signal merging, and address signal reconstruction. The resulting circuit structure is shown below. Figure 5 In this embodiment, the number of data items in the merged address data matrix is ​​N=3, satisfying N=2. n +1=2 1 +1, i.e., n=1, the number of explicit 2-to-1 multiplexers generated after optimization. = =2, which means that a balanced 2-to-1 multiplexer and a top-level 2-to-1 multiplexer are constructed, for a total of 2 explicit 2-to-1 multiplexers.

[0059] This embodiment, after address signal reconstruction and optimization, reduces the number of network nodes and layers, resulting in significant area optimization.

Claims

1. A method for modeling and optimizing implicit multiplexing structures in FPGA logic synthesis, characterized in that, Includes the following steps: S1. Model the implicit multiplexing structure as an address data matrix; S2. Merge the address data matrix obtained after modeling to generate a merged address data matrix; S3. Determine the number of data N in the merged address data matrix. If the number of data N satisfies N=2 n Then construct a balanced binary multiplexer tree; If the number of data N satisfies N=2 n +1, then construct a balanced 2-to-1 multiplexer tree plus a top-level 2-to-1 multiplexer; if the number of data N does not satisfy N=2 n Or N=2 n +1, then an unbalanced two-to-one multiplexer tree is constructed; where n is an integer.

2. The FPGA logic synthesis implicit multiplexing structure modeling and optimization method according to claim 1, characterized in that, Step S1 specifically includes: S101, Perform implicit multiplexing structure identification; S102. Obtain the address and corresponding data signal and perform modeling; S103, Generate address data matrix.

3. The FPGA logic synthesis implicit multiplexing structure modeling and optimization method according to claim 1, characterized in that, Step S2 specifically includes: S201, Traverse the address data matrix obtained in step S1; S202. Determine whether the data already exists. If yes, proceed to step S203; otherwise, proceed to step S204. S203, Merge addresses with identical data; S204. Determine if the traversal has ended. If yes, proceed to step S205. If no, return to step S201. S205. Generate the merged address data matrix.

4. The FPGA logic synthesis implicit multiplexing structure modeling and optimization method according to claim 1, characterized in that, In step S3, the number of data N satisfies N=2. n The specific method for constructing a balanced 2-to-1 multiplexer tree is as follows: the default item is treated as a selection branch with the same priority as the non-default item, and the address signal is reconstructed to construct a balanced 2-to-1 multiplexer tree.

5. The FPGA logic synthesis implicit multiplexing structure modeling and optimization method according to claim 1, characterized in that, In step S3, the number of data N satisfies N=2. n When +1, the specific method for constructing a balanced binary multiplexer tree and adding a top-level binary multiplexer is as follows: treat the default item as a separate selection branch, construct the top-level binary multiplexer, and construct a balanced binary multiplexer tree for non-default items.

6. The FPGA logic synthesis implicit multiplexing structure modeling and optimization method according to claim 1, characterized in that, In step S3, the number of data N does not satisfy N=2. n Or N=2 n When +1, the specific method for constructing an unbalanced two-to-one multiplexer tree is as follows: the default item is directly split as a selection branch with the same priority as the non-default item, and an unbalanced two-to-one multiplexer tree is constructed.

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