FPGA (Field Programmable Gate Array) configuration problem positioning method and system and electronic equipment
By obtaining the FPGA verification configuration file and using EDA tools for legality verification, the problem of low efficiency and poor accuracy in FPGA configuration problem location is solved, realizing automated and accurate configuration problem location and repair.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-07
AI Technical Summary
Existing FPGA configuration problem localization methods are inefficient and inaccurate, and cannot effectively reuse the configuration constraints from the EDA verification stage on the FPGA hardware platform.
By obtaining the FPGA verification configuration file, using electronic design automation (EDA) tools to read the configuration data and perform legality verification, and using constraint randomization methods to locate configuration problems, automated problem localization is achieved.
It improves the efficiency, accuracy, and reliability of FPGA configuration problem localization, and realizes an automated closed loop from problem detection to repair.
Smart Images
Figure CN121809374A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of FPGA testing technology, and in particular to a method, system, and electronic device for locating FPGA configuration problems. Background Technology
[0002] Field-Programmable Gate Array (FPGA) verification is a critical step in the development process of Application-Specific Integrated Circuit (ASIC), especially in fields involving complex algorithms, where efficient FPGA positioning is of paramount importance.
[0003] Currently, in the early stages of Electronic Design Automation (EDA) verification, verification platforms are typically built based on Universal Verification Methodology (UVM) and SystemVerilog (SV) to verify random configuration data. However, the situation becomes significantly more complex when verification is migrated to FPGA hardware platforms. FPGA verification usually uses C language to generate and distribute configuration files, and the configuration constraints and checking mechanisms that have been fully verified in the EDA environment cannot be directly reused. Traditional FPGA configuration problem localization methods often rely on manual methods, which are inefficient, error-prone, and inaccurate. Summary of the Invention
[0004] This invention provides a method, system, and electronic device for locating FPGA configuration problems, which addresses the shortcomings of existing FPGA configuration problem location methods, such as low efficiency and poor accuracy.
[0005] This invention provides a method for locating FPGA configuration problems, including: Obtain the configuration file for FPGA verification; The configuration data in the configuration file is read using an electronic design automation (EDA) tool. The configuration data is validated using the EDA tool to obtain the validation result; The EDA tool is used to locate the configuration problem of the FPGA based on the verification results.
[0006] In some embodiments, before obtaining the configuration file for FPGA verification, the method further includes: The configuration data verified by the FPGA is saved as the configuration file, which can be transmitted independently.
[0007] In some embodiments, the configuration file is a text file, which includes the address of the FPGA's configuration register and the corresponding configuration value.
[0008] In some embodiments, the step of verifying the validity of the configuration data using the EDA tool to obtain a verification result includes: The configuration data is validated using the EDA tool with a constraint randomization method to obtain the validation result.
[0009] In some embodiments, locating the configuration problem of the FPGA using the EDA tool based on the verification result includes: If the verification result is unsuccessful, the constraint conflict information is output through the EDA tool, and the configuration problem of the FPGA is located based on the constraint conflict information.
[0010] In some embodiments, the step of outputting constraint conflict information through the EDA tool and locating configuration problems of the FPGA based on the constraint conflict information includes: The constraint conflict information is output to the FPGA, and the configuration problem is located based on the constraint conflict information. The configuration problem was corrected using the FPGA.
[0011] In some embodiments, the step of using the EDA tool to perform legality verification on the configuration data using a constraint randomization method includes: The EDA tool calls the constraint randomization function, uses the values of each configuration item in the configuration data as in-row constraints, and solves the problem based on the preset configuration constraints and the in-row constraints to obtain the solution result; wherein, the preset configuration constraints are configuration constraints that are verified by the EDA tool for unit testing or integration testing. Based on the solution results, the legality of the constraints of the configuration data is verified.
[0012] In some embodiments, the method further includes: After the EDA tool completes the legality verification of the configuration data, the verification process of the configuration data by the EDA tool is terminated.
[0013] This invention also provides an FPGA configuration problem localization system, comprising: The acquisition unit is used to acquire the configuration file for FPGA verification. A reading unit is used to read configuration data from the configuration file using electronic design automation (EDA) tools. The verification unit is used to verify the legality of the configuration data using the EDA tool and obtain the verification result; The positioning unit is used to locate the configuration problem of the FPGA based on the verification result using the EDA tool.
[0014] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the FPGA configuration problem localization method as described above.
[0015] The FPGA configuration problem localization method, system, and electronic device provided by this invention obtain the configuration file for verification of the Field Programmable Gate Array (FPGA); read the configuration data in the configuration file using an Electronic Design Automation (EDA) tool; verify the validity of the configuration data using the EDA tool to obtain the verification result; and locate the FPGA configuration problem based on the verification result using the EDA tool. This enables automated localization of FPGA configuration problems, improving the efficiency, accuracy, and reliability of FPGA configuration problem localization. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is one of the flowcharts illustrating the FPGA configuration problem localization method provided in this embodiment of the invention.
[0018] Figure 2 This is the second flowchart of the FPGA configuration problem localization method provided in this embodiment of the invention.
[0019] Figure 3 This is a schematic diagram of the FPGA configuration problem localization system provided in an embodiment of the present invention.
[0020] Figure 4 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0022] The terms "first," "second," etc., used in this invention are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, not limited in number; for example, the first object can be one or more. Furthermore, in this invention, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0023] Currently, configuration constraints that have been fully verified during the EDA verification phase cannot be directly ported to the FPGA platform. This is because FPGA verification typically uses C language or other hardware description languages to generate and distribute configuration files, leading to frequent configuration problems during the FPGA verification phase.
[0024] Currently, in FPGA verification, verifiers need to manually parse configuration constraints from design documents and generate random configuration files using C language, lacking an automated constraint checking mechanism. The randomized configuration files are distributed to the Design Under Test (DUT) and the comparison model to check the correctness of the DUT's behavior. However, configuration issues are one of the most common problems during the smoke test phase of FPGA verification. Due to the large number of configuration registers and complex constraints, manually searching for incorrect configuration values in a large number of registers is inefficient and prone to omissions, severely impacting the efficiency and reliability of FPGA verification.
[0025] To address this, embodiments of the present invention provide a method, system, and electronic device for locating FPGA configuration problems. This method involves acquiring a configuration file for FPGA verification; reading configuration data from the configuration file using an Electronic Design Automation (EDA) tool; verifying the validity of the configuration data using the EDA tool to obtain the verification result; and locating FPGA configuration problems based on the verification result using the EDA tool. This approach enables automated location of FPGA configuration problems, improving the efficiency, accuracy, and reliability of FPGA configuration problem location.
[0026] It should be noted that the FPGA configuration problem localization method provided in this embodiment of the invention can be applied to a test localization system, which includes an FPGA platform, EDA verification tools, a central processing unit (CPU), and scheduling software. The FPGA configuration problem localization methods provided in each embodiment can be executed by the aforementioned system; specifically, they can be executed by the CPU, scheduling software, etc., within the system.
[0027] Figure 1 This is one of the flowcharts illustrating the FPGA configuration problem localization method provided in an embodiment of the present invention. Figure 1 As shown, an FPGA configuration problem localization method is provided, applied to a test localization system, including the following steps: step 110, step 120, step 130, and step 140. This method's steps are merely one possible implementation of the invention.
[0028] Step 110: Obtain the configuration file for FPGA verification.
[0029] Among them, Field Programmable Gate Array (FPGA) is a type of programmable semiconductor integrated circuit. Its core feature is field programmability, which means that after the chip is manufactured, users or designers can configure its internal hardware logic structure and interconnect resources multiple times and flexibly in the field according to their needs, using specific design documents and software, thereby turning it into a customized digital circuit to achieve a specific function.
[0030] The configuration file contains all the configuration information generated for the design under test (DUT) on the FPGA verification platform.
[0031] In some embodiments, the configuration file is a text file, which includes the address of the FPGA's configuration register and the corresponding configuration value.
[0032] A text file is a computer file encoded from plain text characters. Its content can be directly opened and read by a text editor without requiring a special binary parser. On the FPGA verification platform, text files can be generated simply using standard file I / O functions; EDA tools provide simple and robust function libraries for reading and parsing text files. Configuration files are text files, offering high readability, strong cross-platform compatibility, and ease of generation and parsing.
[0033] The address of the configuration register is a unique identifier for the internal register of the DUT within the system address space. It is usually a hexadecimal or decimal value, similar to a memory address, used to locate a specific register. The configuration value is the specific data to be written to the register corresponding to the specified address, and it is usually also a value, such as hexadecimal, binary, or decimal. The configuration file is a list of address-configuration value pairs.
[0034] In some embodiments, before obtaining the configuration file for FPGA verification, the method further includes: The configuration data verified by the FPGA is saved as the configuration file, which can be transmitted independently.
[0035] The configuration file is an independent, readable file. Its format is predefined and transparent, rather than a closed binary format, ensuring high readability, good compatibility, and ease of automation. As long as the configuration file format is followed, any EDA tool or script capable of parsing this format can use it, without relying on vendor-specific proprietary tools or databases. The configuration file serves as a data bridge connecting the FPGA platform and the EDA platform, and is the core carrier for realizing asset reuse for verification, accurate problem reproduction, and process automation.
[0036] Understandably, by saving the configuration data verified by the FPGA as a configuration file, and ensuring that the configuration file can be transmitted independently, the traceability and reproducibility of the configuration data can be guaranteed, laying the foundation for cross-platform automated data processing and configuration problem localization.
[0037] Step 120: Read the configuration data in the configuration file using an Electronic Design Automation (EDA) tool.
[0038] EDA tools are software suites used for integrated circuit design and verification, specifically referring to EDA simulation and verification environments, especially verification platforms based on SV / UVM. These platforms contain various components for testing the DUT, such as configuration objects, sequences, and drivers.
[0039] Optionally, in the EDA simulation environment, a configuration file is obtained through a standardized file interface, the configuration file is parsed to obtain configuration data, and the configuration data is loaded into the simulator's memory space so that it can be accessed and processed by subsequent verification components.
[0040] Understandably, by reading configuration data from configuration files using electronic design automation (EDA) tools, cross-platform data integration can be achieved, laying a data foundation for subsequent automated and precise checks.
[0041] Step 130: Verify the legality of the configuration data using the EDA tool to obtain the verification result.
[0042] The verification result includes two possibilities: success or failure. In the case of failure, the verification result also includes detailed error information, such as the exception register ID and the violated constraints.
[0043] Optionally, the constraint solver built into the SV language can be used to check whether the configuration data read from the configuration file fully conforms to all the rules predefined for the DUT registers.
[0044] Step 140: Locate the configuration problem of the FPGA using the EDA tool based on the verification results.
[0045] Optionally, in the event of verification failure, the error report in the verification result is parsed to determine the error information, which includes at least the violation register, violation field, current value, and violated constraint; the configuration problem of the FPGA is located based on the error information.
[0046] Optionally, a fix can be generated based on the FPGA configuration issues, such as modifying the computational logic in the C code.
[0047] In this embodiment of the invention, by obtaining the configuration file for FPGA verification; reading the configuration data in the configuration file using an electronic design automation (EDA) tool; verifying the validity of the configuration data using the EDA tool to obtain the verification result; and locating the FPGA configuration problem using the EDA tool based on the verification result, the automated location of FPGA configuration problems can be achieved, improving the efficiency, accuracy, and reliability of FPGA configuration problem location.
[0048] In some embodiments, step 130 verifies the validity of the configuration data using the EDA tool to obtain a verification result, including: The configuration data is validated using the EDA tool with a constraint randomization method to obtain the validation result.
[0049] Among them, the constrained randomization method refers to automatically solving for legal random values that satisfy the constraints using EDA tools.
[0050] Optionally, the constraint solver can be invoked via EDA, and the validity of the configuration data can be verified according to the preset configuration constraints.
[0051] Specifically, the configuration value of the configuration register is determined based on the configuration data. The constraint solver is called through EDA, and the configuration value and preset configuration constraints are input into the constraint solver. The constraint solver determines whether a set of values completely consistent with the configuration value can be generated through randomization under the preset configuration constraints. If so, the verification is successful; otherwise, the verification fails.
[0052] In this embodiment of the invention, the configuration data is validated using a constraint randomization method through an EDA tool. The validation results are obtained, which can quickly and completely identify configuration errors that violate predefined rules and accurately locate the specific registers and fields that violate the rules, thus significantly improving the efficiency and reliability of FPGA configuration problem localization.
[0053] In some embodiments, locating the configuration problem of the FPGA using the EDA tool based on the verification result includes: If the verification result is unsuccessful, the constraint conflict information is output through the EDA tool, and the configuration problem of the FPGA is located based on the constraint conflict information.
[0054] Optionally, constraint conflict information includes, but is not limited to: conflict object, conflict value, and violated constraint; the conflict object refers to the violating register, and the conflict value refers to the field value of the violating register. For example, field B value C of register A violates constraint D.
[0055] Optionally, constraint conflict information can be mapped into FPGA verification code to locate the abnormal code segment; the root cause of configuration problems may be incorrect macro definitions, out-of-bounds array indices, incorrect bit-width operations, or logically incorrect calculation functions, etc.
[0056] In this embodiment of the invention, constraint conflict information is output by EDA tools, and FPGA configuration problems are located based on the constraint conflict information. This enables accurate root cause localization, improves the efficiency of FPGA configuration problem localization, and provides traceable and reproducible diagnostic evidence.
[0057] In some embodiments, the step of outputting constraint conflict information through the EDA tool and locating configuration problems of the FPGA based on the constraint conflict information includes: The constraint conflict information is output to the FPGA, and the configuration problem is located based on the constraint conflict information. The configuration problem was corrected using the FPGA.
[0058] Optionally, constraint conflict information can be output to the FPGA verification platform via automated scripts or communication interfaces.
[0059] Optionally, the FPGA verification platform receives constraint conflict information, generates corrected configuration data, and verifies the corrected configuration data.
[0060] In this embodiment of the invention, by outputting constraint conflict information to the FPGA, locating configuration problems based on the constraint conflict information, and correcting configuration problems through the FPGA, an automated closed loop from problem detection to problem repair can be achieved, improving the accuracy and reliability of problem repair.
[0061] In some embodiments, the step of using the EDA tool to perform legality verification on the configuration data using a constraint randomization method includes: The EDA tool calls the constraint randomization function, uses the values of each configuration item in the configuration data as in-row constraints, and solves the problem based on the preset configuration constraints and the in-row constraints to obtain the solution result; wherein, the preset configuration constraints are configuration constraints that are verified by the EDA tool for unit testing or integration testing. Based on the solution results, the legality of the constraints of the configuration data is verified.
[0062] The constraint randomization function can be the built-in `randomize` method in the SV language. Calling this function triggers the constraint solver of the EDA tool to start working, attempting to find a set of values for the variables within the object that satisfy all constraints.
[0063] In this context, a configuration item is the basic unit to be configured, and it can be a specific field in the DUT's registers. Inline constraints are used to lock the values of configuration items; for example, an inline constraint might state that the value of each configuration item must be read from a configuration file. Predefined configuration constraints are constraints representing design specifications pre-defined in the register model or verification component within the UVM verification environment. These predefined configuration constraints have been fully verified during unit testing or integration testing.
[0064] Optionally, the solution result can be a Boolean value; for example, 1 indicates success, meaning that all constraints, including inline constraints and preset configuration constraints, are satisfied; 0 indicates failure, meaning that there is a constraint conflict.
[0065] In this embodiment of the invention, by introducing the key technology of inline constraints, the constraint solver is transformed from a generator into a verifier, which enables the reuse of DUT verification tools and improves the efficiency and accuracy of FPGA configuration problem localization.
[0066] In some embodiments, the method further includes: After the EDA tool completes the legality verification of the configuration data, the verification process of the configuration data by the EDA tool is terminated.
[0067] It should be noted that in the EDA simulation environment, once the legality verification step is completed, regardless of whether the result is success or failure, all subsequent simulation activities are immediately stopped, and the current simulation task is exited. The entire EDA verification process only proceeds to the static check stage and does not enter the dynamic simulation stage. Furthermore, this embodiment of the invention adopts a rapid check and verification mechanism. The EDA tool only performs constraint randomization checks. If the configuration data violates predetermined constraints, an error is reported and constraint conflict information is output, thereby quickly locating the problem point without performing a complete simulation, significantly shortening the check time. If the EDA tool performs a complete simulation, it needs to call the DUT and reference model configuration data for calculation after performing constraint randomization checks and compare the calculation results, which will significantly extend the simulation time.
[0068] In this embodiment of the invention, after the EDA tool completes the legality verification of the configuration data, terminating the verification process of the configuration data by the EDA tool can avoid interference from irrelevant steps, simplify the verification process, improve verification efficiency, save computing resources, and reduce verification costs.
[0069] Figure 2 This is the second flowchart illustrating the FPGA configuration problem localization method provided in this embodiment of the invention. Figure 2 As shown, an FPGA configuration problem localization method is provided, applied to a test localization system. The system includes an FPGA verification platform and an EDA verification platform. The method includes: Generate a configuration file through the FPGA verification platform, distribute the configuration file, and write the configuration file out. Receive the configuration file through the EDA verification platform and read the configuration data from the configuration file; The EDA verification platform verifies the legality of configuration data using the constraint solver, obtains verification results, and eliminates configuration problems or identifies constraint conflicts based on the verification results. Based on the verification results, a revised configuration file is generated using the FPGA verification platform.
[0070] Specifically, through the EDA verification platform, inline constraints and preset configuration constraints are input into the constraint solver. The solver then solves based on these constraints, yielding the results, and the verification result is determined based on these results. It should be noted that writing the configuration file is equivalent to saving the FPGA verification configuration data as a configuration file. This can be done by writing the configuration file after a failure to compare on the FPGA verification platform, after generating the configuration data, or after sending the configuration data to the DUT and reference model. The EDA verification platform includes the aforementioned EDA tools.
[0071] Among them, inline constraints are determined based on the values of each configuration item in the configuration data; preset configuration constraints are configuration constraints verified by EDA tools to complete unit testing or integration testing.
[0072] In this embodiment of the invention, a configuration file is generated and distributed through an FPGA verification platform, and the configuration file is written out. The configuration file is received through an EDA verification platform, and the configuration data in the configuration file is read. The configuration data is validated for legality through a constraint solver using the EDA verification platform, and the validation result is obtained. Based on the validation result, configuration problems are eliminated or constraint conflicts are identified. Based on the validation result, a corrected configuration file is generated through the FPGA verification platform, thus realizing a closed loop of cross-platform problem verification and problem correction, and improving the efficiency and reliability of FPGA configuration problem localization.
[0073] The FPGA configuration problem localization system provided in the embodiments of the present invention is described below. The FPGA configuration problem localization system described below can be referred to in correspondence with the FPGA configuration problem localization method described above.
[0074] Figure 3 This is a schematic diagram of the FPGA configuration problem localization system provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the FPGA configuration problem localization system 300 includes: Acquisition unit 310 is used to acquire the configuration file for FPGA verification; Reading unit 320 is used to read configuration data in the configuration file using electronic design automation (EDA) tools; Verification unit 330 is used to perform legality verification on the configuration data using the EDA tool and obtain a verification result; The positioning unit 340 is used to locate the configuration problem of the FPGA based on the verification result using the EDA tool.
[0075] Optionally, the FPGA configuration problem localization system further includes: The storage unit is used to save the configuration data verified by the FPGA as the configuration file, which can be transmitted independently.
[0076] Optionally, the configuration file is a text file, which includes the address of the FPGA's configuration register and the corresponding configuration value.
[0077] Optionally, the step of verifying the validity of the configuration data using the EDA tool to obtain the verification result includes: The configuration data is validated using the EDA tool with a constraint randomization method to obtain the validation result.
[0078] Optionally, locating the configuration problem of the FPGA using the EDA tool based on the verification result includes: If the verification result is unsuccessful, the constraint conflict information is output through the EDA tool, and the configuration problem of the FPGA is located based on the constraint conflict information.
[0079] Optionally, the step of outputting constraint conflict information through the EDA tool and locating the configuration problem of the FPGA based on the constraint conflict information includes: The constraint conflict information is output to the FPGA, and the configuration problem is located based on the constraint conflict information. The configuration problem was corrected using the FPGA.
[0080] Optionally, the step of using the EDA tool to perform legality verification on the configuration data using a constrained randomization method includes: The EDA tool calls the constraint randomization function, uses the values of each configuration item in the configuration data as in-row constraints, and solves the problem based on the preset configuration constraints and the in-row constraints to obtain the solution result; wherein, the preset configuration constraints are configuration constraints that are verified by the EDA tool for unit testing or integration testing. Based on the solution results, the legality of the constraints of the configuration data is verified.
[0081] Optionally, the FPGA configuration problem localization system further includes: The termination unit is used to terminate the verification process of the configuration data by the EDA tool after the EDA tool has completed the legality verification of the configuration data.
[0082] It should be noted that the FPGA configuration problem localization system provided in this embodiment of the invention can implement all the method steps implemented in the above-mentioned FPGA configuration problem localization method embodiment, and can achieve the same technical effect. Here, the parts that are the same as those in the method embodiment and the beneficial effects will not be described in detail.
[0083] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention, such as... Figure 4As shown, the electronic device may include a processor 410, a communications interface 420, a memory 430, and a communication bus 440, wherein the processor 410, communications interface 420, and memory 430 communicate with each other via the communication bus 440. The processor 410 can call logic instructions in the memory 430 to execute an FPGA configuration problem localization method. This method includes: obtaining a configuration file for FPGA verification; reading configuration data from the configuration file using an electronic design automation (EDA) tool; verifying the validity of the configuration data using the EDA tool to obtain a verification result; and locating the FPGA configuration problem using the EDA tool based on the verification result.
[0084] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0085] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the FPGA configuration problem localization method provided by the above methods. The method includes: obtaining a configuration file for FPGA verification; reading configuration data in the configuration file using an electronic design automation (EDA) tool; performing a validity verification on the configuration data using the EDA tool to obtain a verification result; and locating the FPGA configuration problem using the EDA tool based on the verification result.
[0086] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the FPGA configuration problem localization method provided by the above methods. The method includes: obtaining a configuration file for field-programmable gate array (FPGA) verification; reading configuration data in the configuration file using an electronic design automation (EDA) tool; performing a validity verification on the configuration data using the EDA tool to obtain a verification result; and locating the FPGA configuration problem using the EDA tool based on the verification result.
[0087] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0088] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for locating FPGA configuration problems, characterized in that, include: Obtain the configuration file for FPGA verification; The configuration data in the configuration file is read using an electronic design automation (EDA) tool. The configuration data is validated using the EDA tool to obtain the validation result; The EDA tool is used to locate the configuration problem of the FPGA based on the verification results.
2. The FPGA configuration problem localization method according to claim 1, characterized in that, Before obtaining the configuration file for FPGA verification, the following steps are also included: The configuration data verified by the FPGA is saved as the configuration file, which can be transmitted independently.
3. The FPGA configuration problem localization method according to claim 2, characterized in that, The configuration file is a text file, which includes the address of the FPGA's configuration register and the corresponding configuration value.
4. The FPGA configuration problem localization method according to claim 1, characterized in that, The step of verifying the validity of the configuration data using the EDA tool to obtain the verification result includes: The configuration data is validated using the EDA tool with a constraint randomization method to obtain the validation result.
5. The FPGA configuration problem localization method according to claim 4, characterized in that, The step of locating the configuration problem of the FPGA using the EDA tool based on the verification results includes: If the verification result is unsuccessful, the constraint conflict information is output through the EDA tool, and the configuration problem of the FPGA is located based on the constraint conflict information.
6. The FPGA configuration problem localization method according to claim 5, characterized in that, The step of outputting constraint conflict information through the EDA tool and locating the configuration problem of the FPGA based on the constraint conflict information includes: The constraint conflict information is output to the FPGA, and the configuration problem is located based on the constraint conflict information. The configuration problem was corrected using the FPGA.
7. The FPGA configuration problem localization method according to claim 4, characterized in that, The step of using the EDA tool to perform legality verification on the configuration data using a constrained randomization method includes: The EDA tool calls the constraint randomization function, uses the values of each configuration item in the configuration data as in-row constraints, and solves the problem based on the preset configuration constraints and the in-row constraints to obtain the solution result; wherein, the preset configuration constraints are configuration constraints that are verified by the EDA tool for unit testing or integration testing. Based on the solution results, the legality of the constraints of the configuration data is verified.
8. The FPGA configuration problem localization method according to claim 1, characterized in that, The method further includes: After the EDA tool completes the legality verification of the configuration data, the verification process of the configuration data by the EDA tool is terminated.
9. An FPGA configuration problem localization system, characterized in that, include: The acquisition unit is used to acquire the configuration file for FPGA verification. A reading unit is used to read configuration data from the configuration file using electronic design automation (EDA) tools. The verification unit is used to verify the legality of the configuration data using the EDA tool and obtain the verification result. The positioning unit is used to locate the configuration problem of the FPGA based on the verification result using the EDA tool.
10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the FPGA configuration problem localization method as described in any one of claims 1 to 8.