Parasitic capacitance extraction method, device and equipment

Abstract

The invention relates to the technical field of integrated circuits, and discloses a stray capacitance extraction method, device and equipment, and the method comprises the steps: obtaining a target design layout, and carrying out the symmetric division of a design entity according to the symmetry of the design entity in the target design layout, and obtaining a symmetric entity group; wherein the symmetric entity group comprises a target entity serving as a capacitance extraction object and a symmetric entity symmetric with the target entity; and performing capacitance extraction on the target entity, and multiplexing capacitance information of the target entity to the symmetric entity to obtain parasitic capacitance information of the target design layout. The method has the beneficial effects that the design entities are divided into the plurality of symmetric entity groups based on the symmetry of the design entities in the target design layout, and capacitance extraction and information multiplexing are performed on the design entities according to the symmetric entity groups, so that the entity extraction quantity is reduced, the parasitic capacitance extraction process is effectively simplified, and the extraction efficiency is improved. And the capacitance information extraction efficiency is obviously improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method, device and equipment for extracting parasitic capacitance. BACKGROUND

[0002] In modern chip design processes, parasitic capacitance extraction is an important step for verifying the quality of chip design. By converting the geometric information in the chip design layout into a readable circuit model, engineers can predict and solve various potential problems caused by parasitic effects, thereby improving the performance and reliability of chips. With the increasing demand for computing power and the rapid development of chip manufacturing processes, the size and complexity of chip design have gradually increased, making the parasitic capacitance extraction process more complex, and the time cost and computing resource cost required for the process increasing exponentially, thereby limiting the iteration speed of chip design.

[0003] Therefore, there is an urgent need for a technical solution that can simplify the parasitic capacitance extraction process, thereby improving the efficiency of capacitance information extraction while maintaining the accuracy of the capacitance information. SUMMARY

[0004] The present application provides a method, device and equipment for extracting parasitic capacitance. Based on the symmetry of design entities in a target design layout, the design entities are divided into a plurality of symmetric entity groups, and the design entities are extracted and information is multiplexed according to the symmetric entity groups, thereby reducing the number of entity extraction, effectively simplifying the parasitic capacitance extraction process, and significantly improving the efficiency of capacitance information extraction.

[0005] To achieve the above purpose, the main technical solution adopted by the present application includes: In a first aspect, the present application provides a method for extracting parasitic capacitance, which comprises: obtaining a target design layout, and dividing design entities in the target design layout according to their symmetry to obtain symmetric entity groups; wherein the symmetric entity groups include target entities as objects for capacitance extraction and symmetric entities symmetric to the target entities; extracting capacitance from the target entities and multiplexing the capacitance information of the target entities to the symmetric entities to obtain parasitic capacitance information of the target design layout.

[0006] The parasitic capacitance extraction method provided in the embodiments of the present application divides the design entities into one or more symmetric entity groups according to the symmetry of the target design layout and the design entities in the target design layout, and each symmetric entity group includes two entities that are symmetric to each other; any design entity in the symmetric entity group is taken as a target entity, and the design entity that is symmetric to the target entity is taken as a symmetric entity; the target entity is subjected to capacitance information extraction to obtain the capacitance information of the target entity, and the capacitance information of the target entity is reused to the symmetric entity based on the symmetry between the entities, so that the parasitic capacitance information of the target design layout is obtained according to the capacitance information of the target entity and the symmetric entity in each symmetric entity group. Compared with the related art, in the case that the target design layout and the design entities therein have the same symmetry, the symmetric structure does not affect the capacitance value, and the design entities are divided into symmetric entity groups to reduce the number of entity extraction in the capacitance extraction process, so that the parasitic capacitance extraction process is simplified to capacitance extraction on part of the design entities in the target design layout, which effectively simplifies the parasitic capacitance extraction process and significantly improves the capacitance information extraction efficiency while ensuring the accuracy of the capacitance information.

[0007] Optionally, the target design layout corresponds to a global symmetric element in the case of overall symmetry, the design entity includes a self-symmetric entity based on the global symmetric element, or a first mutual symmetric entity and a second mutual symmetric entity based on the global symmetric element; the symmetric division of the design entity according to the symmetry of the design entity in the target design layout to obtain the symmetric entity group comprises: For the self-symmetric entity, the self-symmetric entity is symmetrically divided according to the global symmetric element to obtain a first self-symmetric entity part and a second self-symmetric entity part, and the first self-symmetric entity part and the second self-symmetric entity part form a self-symmetric entity group; For the first mutual symmetric entity and the second mutual symmetric entity, the first mutual symmetric entity and the second mutual symmetric entity form a mutual symmetric entity group; The symmetric entity group is obtained according to the self-symmetric entity group and the mutual symmetric entity group.

[0008] Optionally, the capacitance extraction on the target entity and the reuse of the capacitance information of the target entity to the symmetric entity to obtain the parasitic capacitance information of the target design layout comprises: For the self-symmetric entity group, the first self-symmetric entity part is taken as a target entity for capacitance extraction, and the capacitance information of the first self-symmetric entity part is reused to the second self-symmetric entity part to obtain the self-symmetric capacitance information of the self-symmetric entity group; For the group of mutually symmetrical entities, the first mutually symmetrical entity is used as the target entity for capacitance extraction, and the capacitance information of the first mutually symmetrical entity is reused in the second mutually symmetrical entity to obtain the mutually symmetrical capacitance information of the group of mutually symmetrical entities. The parasitic capacitance information is obtained based on the self-symmetric capacitance information and the mutual-symmetric capacitance information.

[0009] Optionally, the target design layout, while symmetrical overall, corresponds to globally symmetrical elements; the symmetry of the design entity is determined in the following ways: When the design entity intersects with the global symmetry element, the design entity is subjected to self-symmetry detection based on the global symmetry element to obtain the self-symmetry detection result of the design entity; When the design entity is separate from the global symmetry element, the design entity is subjected to mutual symmetry detection based on the global symmetry element to obtain the mutual symmetry detection result of the design entity; The symmetry of the design entity is determined based on the self-symmetry detection results and the mutual symmetry detection results.

[0010] Optionally, whether the target design layout is symmetrical can be determined by the following methods: Perform geometric symmetry analysis on the target design layout to obtain the overall self-symmetric elements of the target design layout; Based on the boundary conditions of the target design layout, a planning symmetry analysis is performed to obtain the boundary condition symmetry elements; When the overall self-symmetric element coincides with the boundary condition symmetric element, the target design layout is determined to be overall symmetric, and the overall self-symmetric element or the boundary condition symmetric element is taken as the global symmetric element.

[0011] Optionally, the design entity intersecting with the global symmetry element is taken as the element intersection entity; the step of performing self-symmetry detection on the design entity based on the global symmetry element to obtain the self-symmetry detection result of the design entity includes: Perform symmetric calculations on the intersecting entities to obtain the self-symmetric elements of the intersecting entities; The self-symmetry detection result is obtained by comparing the overlap between the global symmetric elements and the self-symmetric elements.

[0012] Optionally, design entities that are disjoint from the global symmetry element are considered as disjoint entities; the step of performing mutual symmetry detection on the design entities based on the global symmetry element to obtain the mutual symmetry detection result of the design entities includes: Symmetric entity matching is performed on the opposite side of the element-disjoint entity relative to the global symmetric element to obtain the symmetric entity to be verified corresponding to the element-disjoint entity; Symmetric calculations are performed on the element-disjoint entities and the symmetric entities to be verified to obtain the mutually symmetric elements between the element-disjoint entities and the symmetric entities to be verified. The mutual symmetry detection result is obtained by comparing the overlap between the global symmetric elements and the mutually symmetric elements.

[0013] Optionally, the design entity includes a multi-level entity, wherein the multi-level entity includes a top-level entity and a bottom-level entity; the method further includes: The symmetry of the top-level entity is determined based on the global symmetry elements; If the symmetry of the top-level entity satisfies the preset symmetry requirement, the child entities contained in the top-level entity are selected as entities to be inspected, and the symmetry of the entities to be inspected is determined according to the global symmetry element. If the symmetry of the entity to be inspected satisfies the preset symmetry requirement and the entity to be inspected contains child entities, select the child entities contained in the entity to be inspected as the entity to be inspected, and repeat the above process of symmetry determination and entity selection until the symmetry of the entity to be inspected does not satisfy the preset symmetry requirement, or the entity to be inspected is the bottom-level entity. The symmetry of the designed entity is obtained based on the symmetry of each of the multi-level entities.

[0014] Secondly, embodiments of this application provide a parasitic capacitance extraction device, the device comprising: The entity symmetry partitioning module is used to obtain the target design layout and symmetrically partition the design entities according to the symmetry of the design entities in the target design layout to obtain symmetrical entity groups; wherein, the symmetrical entity group includes the target entity as the capacitance extraction object and the symmetrical entity symmetrical to the target entity; The capacitance extraction and reuse module is used to extract the capacitance of the target entity and reuse the capacitance information of the target entity to the symmetrical entity to obtain the parasitic capacitance information of the target design layout.

[0015] Thirdly, embodiments of this application provide a computer device, including: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method described in any of the above embodiments.

[0016] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer instructions, which are used to cause a computer to perform the method described in any one of the above embodiments.

[0017] Fifthly, embodiments of this application provide a computer program product, including computer instructions, which are used to cause a computer to perform the method described in any of the above embodiments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 This is a step diagram of the parasitic capacitance extraction method provided in the embodiments of this application; Figure 2 This is a diagram illustrating the steps of symmetrically dividing the design entity in an embodiment of this application; Figure 3a This is a schematic diagram of the symmetrical partitioning process in an embodiment of this application; Figure 3b This is a schematic diagram of the symmetrical partitioning process in an embodiment of this application; Figure 3c This is a schematic diagram of the symmetrical partitioning process in an embodiment of this application; Figure 3d This is a schematic diagram of the symmetrical partitioning process in an embodiment of this application; Figure 4 This is a flowchart illustrating the steps of extracting capacitance and reusing capacitance information of the target entity in an embodiment of this application. Figure 5a This is a schematic diagram of the capacitance information extraction process in an embodiment of this application; Figure 5b This is a schematic diagram of the capacitance information extraction process in an embodiment of this application; Figure 5c This is a schematic diagram of the capacitance information extraction process in an embodiment of this application; Figure 6a This is a schematic diagram of the capacitance information extraction process in an embodiment of this application; Figure 6b This is a schematic diagram of the capacitance information extraction process in an embodiment of this application; Figure 6c This is a schematic diagram of the capacitance information extraction process in an embodiment of this application; Figure 7This is a diagram illustrating the steps for determining the symmetry of the design entity in an embodiment of this application. Figure 8 This is a diagram illustrating the steps in this application embodiment to determine whether the target design layout is symmetrical overall; Figure 9 This is a flowchart illustrating the steps for performing self-symmetry detection on the design entity in an embodiment of this application. Figure 10 This is a flowchart illustrating the steps for performing mutual symmetry detection on the design entity in an embodiment of this application. Figure 11 This is a flowchart illustrating the steps for symmetry detection of multi-level entities in an embodiment of this application. Figure 12 This is a flowchart of symmetry detection in an embodiment of this application; Figure 13 A block diagram of the parasitic capacitance extraction device provided in the embodiments of this application; Figure 14 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In modern chip design, parasitic capacitance extraction is a crucial step in verifying chip design quality. By converting the geometric information in the chip design layout into a readable circuit model, it helps engineers anticipate and resolve various potential problems caused by parasitic effects, thereby improving chip performance and reliability. With increasing computing power demands and rapid advancements in chip manufacturing processes, the scale and complexity of chip designs are gradually increasing, making the parasitic capacitance extraction process more complex. The time and computational resource costs required are growing exponentially, thus limiting the speed of chip design iteration. Therefore, there is an urgent need to propose a technical solution that simplifies the parasitic capacitance extraction process, thereby improving the efficiency of capacitance information extraction while maintaining its accuracy.

[0022] To address the aforementioned issues, this application provides a method, apparatus, and device for extracting parasitic capacitance. The method includes: acquiring a target design layout; dividing the design entities symmetrically according to the symmetry of the design entities in the target design layout to obtain a symmetrical entity group; wherein the symmetrical entity group includes a target entity as the object of capacitance extraction and symmetrical entities symmetrical to the target entity; extracting capacitance from the target entity and reusing the capacitance information of the target entity to the symmetrical entities to obtain parasitic capacitance information of the target design layout.

[0023] The parasitic capacitance extraction method provided in this application divides the design entities into one or more symmetrical entity groups based on the symmetry of the target design layout and the design entities therein. Each symmetrical entity group includes two mutually symmetrical entities. Any design entity in the symmetrical entity group is taken as the target entity, and the design entity symmetrical to the target entity is taken as the symmetrical entity. The capacitance information of the target entity is extracted to obtain the capacitance information of the target entity. Based on the symmetry between the entities, the capacitance information of the target entity is reused to the symmetrical entity. Thus, the parasitic capacitance information of the target design layout is obtained according to the capacitance information of the target entity and the symmetrical entity in each symmetrical entity group.

[0024] Compared with related technologies, this application, when the target design layout and the design entities therein have the same symmetry, utilizes the characteristic that symmetrical structures do not affect capacitance values. By dividing the design entities into symmetrical entity groups, the number of entities extracted during the capacitance extraction process is reduced, thereby simplifying the parasitic capacitance extraction process to extracting capacitance from a portion of the design entities in the target design layout. This effectively simplifies the parasitic capacitance extraction process and significantly improves the efficiency of capacitance information extraction while ensuring the accuracy of capacitance information.

[0025] According to an embodiment of this application, a method for extracting parasitic capacitance is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0026] Reference Figure 1 As shown, this embodiment provides a method for extracting parasitic capacitance, the method comprising: S100. Obtain the target design layout, and divide the design entities symmetrically according to the symmetry of the design entities in the target design layout to obtain a symmetrical entity group; wherein, the symmetrical entity group includes the target entity as the capacitor extraction object and the symmetrical entity that is symmetrical to the target entity.

[0027] S200. Extract the capacitance of the target entity and reuse the capacitance information of the target entity to the symmetric entity to obtain the parasitic capacitance information of the target design layout.

[0028] The target design layout can be a chip design layout that needs to be verified by extracting parasitic capacitance information. The design entity can be a data model representing the physical structure and electrical connections within the chip design, including network objects, node objects, and conductor objects. A network object can contain one or more node objects, and a node object can contain one or more conductor objects. It is understood that for any node object, if all its contained conductor objects are symmetrical based on the same symmetry element, then that node object is symmetrical based on that same symmetry element. Similarly, for any network object, if all its contained node objects are symmetrical based on the same symmetry element, then that network object is symmetrical based on that same symmetry element. For the target design layout, if all its contained network objects are symmetrical based on the same symmetry element, then the target design layout is symmetrical based on that same symmetry element. It should be noted that when the design entity is mirror-symmetric, the symmetry element is the mirror plane of the design entity; when the design entity is centrally symmetric, the symmetry element is the center of symmetry of the design entity.

[0029] A symmetric entity group can be obtained by dividing design entities based on their symmetry. Each symmetric entity group includes one or two design entities, and the symmetry of the design entities includes mirror symmetry and central symmetry. When a symmetric entity group includes only one design entity, that design entity can be a self-symmetric entity, which is mirror-symmetric based on the global symmetry of the target design layout, or centrally symmetric based on the global symmetry center of the target design layout. When a symmetric entity group includes two design entities, these design entities can be mutually symmetric entities, which are mirror-symmetric based on the global symmetry of the target design layout, or centrally symmetric based on the global symmetry center of the target design layout. It can be understood that design entities belonging to the same symmetric entity group have the same conductor layer definition and attribute settings, and have the same length in the symmetry direction and symmetric coordinates in the direction perpendicular to the symmetry direction. Here, the conductor layer definition can be the conductor layer to which the design entity belongs in the chip design, and the same conductor layer definition can mean that design entities belonging to the same symmetric entity group all belong to the same conductor layer in the chip design. Attribute settings can be metadata attached to a design entity, used to represent the non-geometric information of the design entity in the target design layout, and can include electrical attributes, design constraints, and parasitic parameters.

[0030] Specifically, the target design layout to be tested is obtained, and symmetry detection is performed on the target design layout to determine the symmetry of the target design layout and its design entities. When the target design layout is symmetrical as a whole, it corresponds to a global symmetry element, and all design entities in the target design layout are symmetrical based on this global symmetry element. It can be understood that, when the target design layout is symmetrical as a whole, if it corresponds to only one global symmetry mirror, the target design layout is mirror-symmetric based on the global symmetry mirror; if it corresponds to two mutually perpendicular global symmetry mirrors, and all design entities in the target design layout are symmetrical based on either global symmetry mirror, the target design layout is doubly mirror-symmetric based on the global symmetry mirror. When the target design layout is centrally symmetrical as a whole, it is centrally symmetric based on the global symmetry center.

[0031] It should be noted that when using the capacitance extraction algorithm to extract capacitance information from a target design layout, if the target design layout contains symmetrical entity structures, the capacitance information of these symmetrical entities is symmetrical, and the capacitance value is independent of the symmetry direction. Therefore, when the target design layout is mirror-symmetrical based on a global symmetry mirror, the capacitance information obtained from extracting the capacitance of entities on either side of the global symmetry mirror can be reused on the other side of the global symmetry mirror. Similarly, when the target design layout is doubly mirror-symmetrical based on two global symmetry mirrors, the two global symmetry mirrors divide the target design layout into four symmetrical partitions. Each symmetrical partition contains the same design entities, and the capacitance information in each partition is symmetrical with that of the adjacent symmetrical partition. The capacitance information obtained from extracting the capacitance of entities in any of the four symmetrical partitions can be reused in other symmetrical partitions. When the target design layout is centrally symmetrical based on a global symmetry center, the target design layout can be divided into multiple symmetrical partitions of the same size using the global symmetry center as the origin. The capacitance information of any symmetrical partition can be reused in another symmetrical partition that is centrally symmetrical with it based on the global symmetry center.

[0032] Furthermore, based on the symmetry of the design entities within the target design layout, the design entities are symmetrically divided to obtain one or more symmetrical entity groups. Each symmetrical entity group includes the target entity and symmetrical entities that are symmetrical to the target entity. The target entity can be used as the capacitance extraction object, and actual calculations are performed during the capacitance extraction process. It should be noted that the target entity and symmetrical entities can be any design entity in the target design layout, or a portion of the entity structure within any design entity. It can be understood that when the target design layout is mirror-symmetrical based on a global symmetry mirror, the target entity can be located on either side of the global symmetry mirror; while when all target entities are distributed on the same side of the global symmetry mirror, after graphically merging the target entities in all symmetrical entity groups, the complete entity structure of the target design layout on either side of the global symmetry mirror can be obtained. Similarly, when the target design layout is doubly mirror-symmetric based on two globally symmetric mirrors, the target entity can be located in any symmetric partition of the target design layout. When all target entities are distributed within the same symmetric partition of the target design layout, merging the target entities in all symmetric entity groups yields the complete entity structure of the target design layout within any symmetric partition. When the target design layout is centrally symmetric based on a global symmetry center, the target entity can also be located in any symmetric partition of the target design layout.

[0033] This embodiment utilizes the characteristic that symmetrical structures do not affect capacitance values. Design entities on the target design layout are divided into one or more symmetrical entity groups. One or more target entities that can represent the capacitance information of the target design layout are then selected to obtain parasitic capacitance information. This effectively reduces the number of entities extracted during capacitance extraction, simplifying the parasitic capacitance extraction process to extracting capacitance from a subset of design entities in the target design layout. This significantly simplifies the parasitic capacitance extraction process while ensuring the accuracy of capacitance information, thus significantly improving the efficiency of capacitance information extraction. For example, when the target design layout is mirror-symmetric based on a globally symmetrical mirror plane or centrally symmetrical based on a globally symmetrical center, the efficiency of capacitance information extraction can be increased to twice the original efficiency. When the target design layout is doubly mirror-symmetric based on two globally symmetrical mirror planes, the efficiency of capacitance information extraction can be increased to four times the original efficiency.

[0034] Further, for a target entity in any symmetric entity group, capacitance extraction is performed on the target entity based on all design entities in the target design layout except the target entity itself, to obtain the capacitance information of the target entity. In some embodiments, the capacitance extraction method can be a random walk algorithm, using the target entity as the starting point, controlling particles to perform random walk sampling in the dielectric space defined by the target design layout, and determining the coupling capacitance value between the target entity and other design entities based on the probability of the particles being absorbed by other design entities, thereby obtaining the capacitance information of the target entity. Based on the symmetry between the design entities in any symmetric entity group, the capacitance information of the symmetric entities and the capacitance information of the target entity are symmetric based on global symmetric elements. Therefore, the capacitance information of the target entity can be reused to the symmetric entities through symmetric mapping, thereby obtaining the capacitance information of the symmetric entities, and thus obtaining the parasitic capacitance information of the target design layout.

[0035] The parasitic capacitance extraction method provided in this embodiment divides the design entities into one or more symmetrical entity groups based on the symmetry of the target design layout and the design entities therein. Each symmetrical entity group includes two mutually symmetrical entities. Any design entity in the symmetrical entity group is taken as the target entity, and the design entity symmetrical to the target entity is taken as the symmetrical entity. The capacitance information of the target entity is extracted to obtain the capacitance information of the target entity. Based on the symmetry between the entities, the capacitance information of the target entity is reused to the symmetrical entity. Thus, the parasitic capacitance information of the target design layout is obtained according to the capacitance information of the target entity and the symmetrical entity in each symmetrical entity group.

[0036] Compared with related technologies, this application, when the target design layout and the design entities therein have the same symmetry, utilizes the characteristic that symmetrical structures do not affect capacitance values. By dividing the design entities into symmetrical entity groups, the number of entities extracted during the capacitance extraction process is reduced, thereby simplifying the parasitic capacitance extraction process to extracting capacitance from a portion of the design entities in the target design layout. This effectively simplifies the parasitic capacitance extraction process and significantly improves the efficiency of capacitance information extraction while ensuring the accuracy of capacitance information.

[0037] Reference Figure 2 As shown in one embodiment of this application, the target design layout, when symmetrical overall, corresponds to globally symmetrical elements. The design entities include self-symmetrical entities based on the global symmetrical elements, or first mutually symmetrical entities and second mutually symmetrical entities based on the global symmetrical elements. The design entities are symmetrically divided according to the symmetry of the design entities in the target design layout to obtain a symmetrical entity group, including: S110. For a self-symmetric entity, the self-symmetric entity is symmetrically divided according to the global symmetry element to obtain a first self-symmetric entity part and a second self-symmetric entity part, which together form a self-symmetric entity group.

[0038] S120. For the first mutually symmetric entity and the second mutually symmetric entity, form a mutually symmetric entity group.

[0039] S130. Obtain a symmetric entity group based on the self-symmetric entity group and the mutually symmetric entity group.

[0040] Among them, a self-symmetric entity can be an element-intersecting entity in the target design layout that intersects with a globally symmetric element, based on the symmetry between the globally symmetric element and itself. A mutually symmetric entity can be an element-separated entity in the target design layout that is separate from a globally symmetric element, based on the symmetry between the globally symmetric element and another element-separated entity, with the mutually symmetric entity and the other element-separated entity located on different sides of the globally symmetric element.

[0041] Specifically, since self-symmetric entities are based on global symmetry elements and their own symmetry, the two parts of a self-symmetric entity divided by these global symmetry elements have symmetrical capacitance information in the target design layout. Therefore, when performing symmetrical partitioning, a self-symmetric entity can be divided into a first self-symmetric entity part and a second self-symmetric entity part that are symmetrical according to global symmetry elements, and these two parts can be combined into a self-symmetric entity group. It can be understood that the first and second self-symmetric entity parts are symmetric based on global symmetry elements, their respective capacitance information is symmetrical and can be reused, and both the first and second self-symmetric entity parts can serve as target entities or symmetric entities.

[0042] Furthermore, since the first and second mutually symmetric entities are mutually symmetric based on global symmetric elements, they possess symmetrical capacitance information in the target design layout. Therefore, the first and second mutually symmetric entities can form a mutually symmetric entity group. It is understood that within any mutually symmetric entity group, the capacitance information of the first mutually symmetric entity and its symmetrical second mutually symmetric entity can be reused. Both the first and second mutually symmetric entities can serve as target entities or symmetric entities.

[0043] For example, there is a target design layout with overall mirror symmetry, in which design entities A1, A2, B, C1, and C2 are distributed, wherein design entities A1 and C1 have the same conductor layer definition and attribute settings, and design entities A2 and C2 have the same conductor layer definition and attribute settings, such as... Figure 3a As shown. With the rightward direction parallel to the paper as the positive x-axis and the upward direction parallel to the paper as the positive y-axis, the globally symmetric mirror plane of this target design layout is located at... Figure 3aThe central plane is perpendicular to the x-direction. Design entity B is self-symmetrical in the x-direction based on a globally symmetrical mirror plane; therefore, design entity B is a self-symmetrical entity. Design entities A1 and C1 are mutually symmetrical in the x-direction based on a globally symmetrical mirror plane; design entities A2 and C2 are mutually symmetrical in the x-direction based on a globally symmetrical mirror plane; therefore, design entities A1, A2, C1, and C2 are all mutually symmetrical entities. For the self-symmetrical entity B, it can be divided into a first self-symmetrical entity part B1 and a second self-symmetrical entity part B2 based on the globally symmetrical mirror plane, and the first self-symmetrical entity part B1 and the second self-symmetrical entity part B2 can be combined into a self-symmetrical entity group, such as... Figure 3b As shown, both the first self-symmetric entity part B1 and the second self-symmetric entity part B2 can be used as target entities. For mutually symmetric entities A1, A2, C1, and C2, mutually symmetric entities A1 and C1 can be combined into a mutually symmetric entity group, where both A1 and C1 can be used as target entities; similarly, mutually symmetric entities A2 and C2 can be combined into a mutually symmetric entity group, where both A2 and C2 can be used as target entities.

[0044] Similarly, there is another overall mirror-symmetric target design layout, in which design entities A, B, C, D, and E are distributed, where design entities A and E have the same conductor layer definition and attribute settings, and design entities B and D have the same conductor layer definition and attribute settings, such as... Figure 3c As shown. With the rightward direction parallel to the paper as the positive x-axis and the upward direction parallel to the paper as the positive y-axis, the globally symmetric mirror plane of this target design layout is located at... Figure 3c The central plane is perpendicular to the x-direction. Design entity C is self-symmetrical in the x-direction based on a globally symmetrical mirror plane; therefore, design entity C is a self-symmetrical entity. Design entities A and E are mutually symmetrical in the x-direction based on a globally symmetrical mirror plane; design entities B and D are mutually symmetrical in the x-direction based on a globally symmetrical mirror plane; therefore, design entities A, B, D, and E are all mutually symmetrical entities. For the self-symmetrical entity C, it can be divided into a first self-symmetrical entity part C1 and a second self-symmetrical entity part C2 based on the globally symmetrical mirror plane. The first self-symmetrical entity part C1 and the second self-symmetrical entity part C2 can then be combined to form a self-symmetrical entity group, such as... Figure 3d As shown, both the first self-symmetric entity C1 and the second self-symmetric entity C2 can be used as target entities. For mutually symmetric entities A, B, D, and E, mutually symmetric entities A and E can be grouped into a mutually symmetric entity group, where both A and E can be used as target entities; similarly, mutually symmetric entities B and D can be grouped into a mutually symmetric entity group, where both B and D can be used as target entities.

[0045] Reference Figure 4As shown, in one embodiment of this application, capacitance is extracted from the target entity, and the capacitance information of the target entity is reused in a symmetric entity to obtain parasitic capacitance information of the target design layout, including: S210. For a self-symmetric entity group, the capacitance is extracted using the first self-symmetric entity part as the target entity, and the capacitance information of the first self-symmetric entity part is reused in the second self-symmetric entity part to obtain the self-symmetric capacitance information of the self-symmetric entity group.

[0046] S220. For a group of mutually symmetrical entities, the first mutually symmetrical entity is used as the target entity for capacitance extraction, and the capacitance information of the first mutually symmetrical entity is reused in the second mutually symmetrical entity to obtain the mutually symmetrical capacitance information of the group of mutually symmetrical entities.

[0047] S230. Obtain parasitic capacitance information based on self-symmetric capacitance information and mutual-symmetric capacitance information.

[0048] Specifically, for a group of self-symmetric entities, both the first and second self-symmetric entities within any group can be considered as target entities or symmetric entities. When the first self-symmetric entity is taken as the target entity, capacitance extraction is performed on it to obtain its capacitance information. Symmetric mapping of this capacitance information yields the capacitance information of the second self-symmetric entity. Similarly, when the second self-symmetric entity is taken as the target entity, capacitance extraction is performed on it to obtain its capacitance information. Symmetric mapping of this capacitance information yields the capacitance information of the first self-symmetric entity. Based on the individual capacitance information of the first and second self-symmetric entities, the self-symmetric capacitance information of the group is obtained, which is the capacitance information of the self-symmetric entity corresponding to both the first and second self-symmetric entities.

[0049] Furthermore, for a group of mutually symmetric entities, both the first and second mutually symmetric entities within any group can be used as target entities or symmetric entities. When the first mutually symmetric entity in any group is used as the target entity, capacitance extraction is performed on the first mutually symmetric entity to obtain its capacitance information. Symmetric mapping of the capacitance information of the first mutually symmetric entity yields the capacitance information of the second mutually symmetric entity, which is symmetric to the first. Similarly, when the second mutually symmetric entity in any group is used as the target entity, capacitance extraction is performed on the second mutually symmetric entity to obtain its capacitance information. Symmetric mapping of the capacitance information of the second mutually symmetric entity yields the capacitance information of the first mutually symmetric entity.

[0050] For example, for such Figure 3a The target design layout shown can be used to obtain the capacitance information of the self-symmetric entity B through a random walk algorithm. The first self-symmetric entity part B1 can be taken as the target entity, and the coupling capacitance values ​​between the target entity and other design entities A1, A2, C1, and C2 can be calculated to obtain the capacitance information of the first self-symmetric entity part B1. Figure 5a As shown by the blue arrow in the middle. Based on the symmetry between the first self-symmetric entity part B1 and the second self-symmetric entity part B2, the capacitance information of the first self-symmetric entity part B1 can be multiplexed to the second self-symmetric entity part B2 through symmetric mapping, thereby obtaining the capacitance information of the self-symmetric entity B. In some embodiments, the self-symmetric entity B can also be directly used as the target entity for capacitance extraction, thereby directly obtaining the capacitance information of the self-symmetric entity B.

[0051] When obtaining the capacitance information of mutually symmetric entities A1 and C1 using a random walk algorithm, mutually symmetric entity A1 can be used as the target entity. The coupling capacitance values ​​between the target entity and other design entities A2, B, C1, and C2 are calculated to obtain the capacitance information of mutually symmetric entity A1. Figure 5a As shown by the green arrow extending from design entity A1. Based on the symmetry between mutually symmetric entities A1 and C1, the capacitance information of mutually symmetric entity A1 can be reused to mutually symmetric entity C1 through symmetric mapping, as follows. Figure 5b As shown by the yellow dashed arrow extending from design entity C1, this reduces the steps required to extract the capacitance of the mutually symmetrical entity C1. Similarly, the capacitance information of mutually symmetrical entities A2 and C2 can also be obtained in the same way. The final sampling method for this target design layout can be referred to... Figure 5c As shown.

[0052] Similarly, for such Figure 3c The target design layout shown can be used to obtain the capacitance information of the self-symmetric entity C through a random walk algorithm. The first self-symmetric entity part C1 can be taken as the target entity, and the coupling capacitance values ​​between the target entity and other design entities A, B, D, and E can be calculated to obtain the capacitance information of the first self-symmetric entity part C1. Figure 6a As shown by the blue arrow in the middle. Based on the symmetry between the first self-symmetric entity part C1 and the second self-symmetric entity part C2, the capacitance information of the first self-symmetric entity part C1 can be multiplexed to the second self-symmetric entity part C2 through symmetric mapping, thereby obtaining the capacitance information of the self-symmetric entity C. In some embodiments, the self-symmetric entity C can also be directly used as the target entity for capacitance extraction, thereby directly obtaining the capacitance information of the self-symmetric entity C.

[0053] When obtaining the capacitance information of mutually symmetric entities A and E using a random walk algorithm, mutually symmetric entity A can be taken as the target entity. The coupling capacitance values ​​between the target entity and other design entities B, C, D, and E are calculated to obtain the capacitance information of mutually symmetric entity A. Figure 6a As shown by the green arrow. Based on the symmetry between mutually symmetric entities A and E, the capacitance information of mutually symmetric entity A can be multiplexed to mutually symmetric entity E through symmetric mapping, such as... Figure 6b As shown by the green dashed arrow, this reduces the steps required to extract the capacitance of the mutually symmetric entity E. Similarly, the capacitance information of mutually symmetric entities B and D can also be obtained in the same way, as described above. Figure 6a medium gray arrow and Figure 6b As indicated by the yellow dashed arrow, the final sampling method for the target design layout can be referenced. Figure 6c As shown.

[0054] Reference Figure 7 As shown, in one embodiment of this application, the target design layout has globally symmetrical elements when the overall layout is symmetrical; the symmetry of the design entity is determined in the following way: S310. When the design entity intersects with a global symmetry element, perform a self-symmetry check on the design entity based on the global symmetry element to obtain the self-symmetry check result of the design entity.

[0055] S320. When the design entity is separate from the global symmetry element, perform mutual symmetry detection on the design entity based on the global symmetry element to obtain the mutual symmetry detection result of the design entity.

[0056] S330. Determine the symmetry of the design entity based on the self-symmetry test results and the mutual symmetry test results.

[0057] Specifically, for intersecting entities that intersect with a globally symmetric element, a self-symmetry detection is performed on the intersecting entity based on the globally symmetric element to determine whether the intersecting entity is symmetric based on the globally symmetric element, thus obtaining the self-symmetry detection result. It can be understood that if the parts of the intersecting entity on both sides of the globally symmetric element are symmetric based on the globally symmetric element, then the intersecting entity is a self-symmetric entity; otherwise, it is not.

[0058] Furthermore, for elements separate from the globally symmetric element, a mutual symmetry test is performed on the element separate from the design entity on the other side of the globally symmetric element to determine whether the element separate from the design entity on the other side of the globally symmetric element is symmetrical, thus obtaining the mutual symmetry test result. It can be understood that if an element separate from the design entity is symmetrical to the design entity on the other side of the globally symmetric element based on the globally symmetric element, then both the element separate from the design entity and its symmetrical design entity are mutually symmetric entities; otherwise, they are not.

[0059] It should be noted that, when the target design layout is symmetrical overall, the target design layout only possesses symmetry when all design entities in the target design layout are self-symmetrical or mutually symmetrical based on globally symmetrical elements. This simplifies the parasitic capacitance extraction process using the parasitic capacitance extraction method provided in this embodiment. It is understood that when there are multiple layers of inclusion relationships between design entities, the symmetry of any level of design entity depends on its next-level design entity. A next-level design entity only possesses symmetry when it is symmetrical to the next-level design entity based on the same symmetry element.

[0060] Reference Figure 8 As shown in one embodiment of this application, the determination of whether the target design layout is symmetrical is made in the following way: S302. Perform geometric symmetry analysis on the target design layout to obtain the overall self-symmetric elements of the target design layout.

[0061] S304. Perform planning symmetry analysis based on the boundary conditions of the target design layout to obtain the boundary condition symmetry elements.

[0062] S306. When the overall self-symmetric element and the boundary condition symmetric element coincide, the target design layout is determined to be overall symmetric, and the overall self-symmetric element or the boundary condition symmetric element is taken as the global symmetric element.

[0063] The boundary conditions of the target design layout can be constraints set according to design requirements during the chip design process, including physical geometric boundaries, electrical boundaries, and manufacturing process boundaries, which are used to determine the physical layout in the target design layout and to verify the target design layout.

[0064] Specifically, based on the dimensions of the target design layout, the geometric midpoint of the target design layout in any direction is determined, and the overall self-symmetric element of the target design layout in any direction is obtained based on the geometric midpoint. It is understood that the target design layout may correspond to one or more overall self-symmetric elements. In some embodiments, determining the geometric midpoint may include: performing a bounding box calculation on the target design layout to obtain the minimum bounding box containing the target design layout; and determining the geometric midpoint of the target design layout in any direction based on the midpoint of this minimum bounding box. For example, the bounding box calculation may be performed using a bounding box algorithm, which may include AABB (Axis-Aligned Bounding Box), bounding spheres, and OBB (Oriented Bounding Box), etc. The minimum bounding box may be obtained by any of the above bounding box algorithms, completely enclosing the target design layout and having the smallest volume.

[0065] Furthermore, the target design layout corresponds to boundary conditions used for physics simulation. These boundary conditions pre-define symmetry elements of the physics field corresponding to the target design layout. The boundary condition symmetry elements are obtained based on these pre-define symmetry elements. It can be understood that the boundary condition symmetry elements represent the symmetry of the physics field corresponding to the target design layout.

[0066] Furthermore, the overlap between the overall self-symmetric elements and the boundary condition symmetric elements is determined. If the overall self-symmetric elements and the boundary condition symmetric elements overlap, the target design layout exhibits consistent symmetry in both geometric and physical dimensions, and can be considered as globally symmetric. It is understandable that since the overall self-symmetric elements and the boundary condition symmetric elements overlap, both can be considered as global symmetric elements of the target design layout.

[0067] Reference Figure 9 As shown, in one embodiment of this application, the design entity intersecting with a globally symmetric element is taken as the element intersection entity; self-symmetry detection is performed on the design entity based on the globally symmetric element to obtain the self-symmetry detection result of the design entity, including: S312. Perform symmetric calculations on intersecting entities to obtain the self-symmetric elements of the intersecting entities.

[0068] S314. Based on the overlap comparison of global symmetric elements and self-symmetric elements, the self-symmetry detection result is obtained.

[0069] Specifically, based on the dimensions of the intersecting entities, the geometric midpoint of the intersecting entities in any direction is determined, and the self-symmetric element of the intersecting entities in any direction is obtained based on the geometric midpoint. It is understood that the intersecting entities may correspond to one or more self-symmetric elements. In some embodiments, determining the geometric midpoint may include: performing a bounding box calculation on the intersecting entities to obtain a minimum bounding box containing the intersecting entities; and determining the geometric midpoint of the intersecting entities in any direction based on the midpoint of this minimum bounding box in any direction.

[0070] Furthermore, the overlap between self-symmetric elements and global symmetric elements is determined, and the self-symmetry detection result is obtained based on the relative relationship between the self-symmetric elements and global symmetric elements. If a self-symmetric element and a global symmetric element overlap, the intersecting entity of that element is self-symmetric based on the global symmetric element.

[0071] Reference Figure 10 As shown, in one embodiment of this application, design entities that are separate from global symmetry elements are considered as separate entities; mutual symmetry detection is performed on the design entities based on global symmetry elements to obtain the mutual symmetry detection results of the design entities, including: S322. Perform symmetric entity matching on the opposite side of the element-separated entity relative to the global symmetric element to obtain the symmetric entity to be verified corresponding to the element-separated entity.

[0072] S324. Perform symmetric calculations on the element-separated entity and the symmetric entity to be verified to obtain the mutually symmetric elements between the element-separated entity and the symmetric entity to be verified.

[0073] S326. Based on the overlap comparison of globally symmetric elements and mutually symmetric elements, the mutually symmetric detection result is obtained.

[0074] Specifically, for disjoint entities, symmetric entity matching is performed on their opposite side relative to the global symmetric element to obtain the corresponding symmetric entities to be verified. Symmetric entity matching can include geometric matching and attribute matching. Geometric matching can include: performing entity matching based on the coordinates and length of the disjoint entities along the symmetric direction represented by the global symmetric element, and marking design entities with the same length in the symmetric direction as the disjoint entities and symmetric coordinates in the direction perpendicular to the symmetric direction with geometric symmetry. Attribute matching can include: marking design entities with the same entity attributes as the disjoint entities with attribute symmetry; where entity attributes can include conductor layer definition, number of contained entities, and other attribute settings. Design entities that have both geometric symmetry marking and attribute symmetry marking are taken as symmetric entities to be verified.

[0075] Furthermore, in the symmetry direction represented by the global symmetry element, the symmetry midpoint between the disjoint element entity and the symmetry entity to be verified is obtained based on their respective geometric midpoints, thereby obtaining mutually symmetric elements perpendicular to the symmetry direction. In some embodiments, mutually symmetric elements can be obtained by box calculation, including: performing box calculation on the disjoint element entity to obtain a first box containing the disjoint element entity, wherein the first box may have a first geometric midpoint in the symmetry direction; performing box calculation on the symmetry entity to be verified to obtain a second box, wherein the second box may have a second geometric midpoint in the symmetry direction; extracting the midpoint of the line connecting the first and second geometric midpoints in the symmetry direction to obtain the symmetry midpoint between the disjoint element entity and the symmetry entity to be verified, and obtaining mutually symmetric elements based on the symmetry midpoint in the direction perpendicular to the symmetry direction.

[0076] Furthermore, the overlap of mutually symmetric elements and globally symmetric elements is determined, and the mutual symmetry detection result is obtained based on the relative relationship between the mutually symmetric elements and the globally symmetric elements. If the mutually symmetric element and the globally symmetric element overlap, the entity with that element and the symmetric entity to be verified are mutually symmetric based on the globally symmetric element.

[0077] ReferenceFigure 11 As shown, in one embodiment of this application, the design entity includes a multi-level entity, which contains a top-level entity and a bottom-level entity; the method further includes: S340. Determine the symmetry of the top-level entity based on the global symmetric elements.

[0078] S350. If the symmetry of the top-level entity meets the preset symmetry requirements, select the child entities contained in the top-level entity as the entities to be inspected, and determine the symmetry of the entities to be inspected based on the global symmetry elements.

[0079] S360. If the symmetry of the entity to be inspected meets the preset symmetry requirement and the entity to be inspected contains child entities, select the child entities contained in the entity to be inspected as the entity to be inspected, and repeat the above process of symmetry determination and entity selection until the symmetry of the entity to be inspected does not meet the preset symmetry requirement, or the entity to be inspected is a bottom-level entity.

[0080] S370. Obtain the symmetry of the designed entity based on the symmetry of each of the multi-level entities.

[0081] The preset symmetry requirement can be that the design entity is self-symmetrical based on the global symmetry element, or mutually symmetrical with the design entity on the other side based on the global symmetry element.

[0082] Reference Figure 12 As shown, when the target design layout contains multi-level design entities, the top-level entity in the target design layout is first selected. Symmetry is then checked against the top-level entity based on its relationship with global symmetry elements to determine if its symmetry meets the preset symmetry requirements. If the top-level entity's symmetry meets the preset symmetry requirements, child entities contained within the top-level entity are selected as entities to be inspected based on the hierarchical inclusion relationship between the multi-level entities. Symmetry is then checked against the entities to be inspected based on their relationship with global symmetry elements. If the symmetry of the entities to be inspected meets the preset symmetry requirements, it is determined whether the entities to be inspected contain child entities. If the entities to be inspected contain child entities, these child entities are selected as entities to be inspected, and the aforementioned symmetry determination and entity selection process is repeated for each layer of entities to be inspected. If the symmetry of any entity to be inspected does not meet the preset symmetry requirements, the process is stopped, and the target design layout is determined to lack symmetry, making the method provided in this embodiment unsuitable. If the symmetry of the underlying entities meets the preset symmetry requirements, it means that the multi-level entities in the target design layout are self-symmetrical or mutually symmetrical based on the global symmetric elements. Therefore, it is determined that the target design layout has symmetry, and the method provided in this embodiment can be used.

[0083] For example, the design entities of the target design layout include network objects, node objects, and conductor objects. Network objects contain node objects, and node objects contain conductor objects. The conductor object is the smallest unit in the design entity. If the target design layout is globally symmetrical, a symmetry check is performed on each network object. If any network object is not symmetrical based on the global symmetry element, the target design layout lacks symmetry, and the symmetry check process is terminated. If all network objects are symmetrical based on the global symmetry element, a symmetry check is performed on each node object. If any node object is not symmetrical based on the global symmetry element, the target design layout lacks symmetry, and the symmetry check process is terminated. If all node objects are symmetrical based on the global symmetry element, a symmetry check is performed on each conductor object. If any conductor object is not symmetrical based on the global symmetry element, the target design layout lacks symmetry, and the symmetry check process is terminated. If all conductor objects are symmetrical based on the global symmetry element, all design entities in the target design layout are symmetrical based on the global symmetry element, and the target design layout possesses symmetry.

[0084] Accordingly, please refer to Figure 13 This application provides a parasitic capacitance extraction device, which includes: The entity symmetry partitioning module 1310 is used to obtain the target design layout and symmetrically partition the design entities according to the symmetry of the design entities in the target design layout to obtain symmetrical entity groups; wherein, the symmetrical entity group includes the target entity as the capacitor extraction object and the symmetrical entity that is symmetrical to the target entity. The capacitance extraction and reuse module 1320 is used to extract the capacitance of the target entity and reuse the capacitance information of the target entity to the symmetrical entity to obtain the parasitic capacitance information of the target design layout.

[0085] In some optional implementations, the solid symmetric partitioning module 1310 includes: Self-symmetric grouping unit is used to symmetrically divide a self-symmetric entity according to a global symmetry element to obtain a first self-symmetric entity part and a second self-symmetric entity part, which together form a self-symmetric entity group.

[0086] A mutually symmetric grouping unit is used to group a first mutually symmetric entity and a second mutually symmetric entity into a mutually symmetric entity group.

[0087] The entity group acquisition unit is used to obtain a symmetric entity group based on the self-symmetric entity group and the mutually symmetric entity group.

[0088] In some alternative implementations, the capacitance extraction and multiplexing module 1320 includes: The self-symmetric capacitance extraction unit is used to extract capacitance from a group of self-symmetric entities, using the first self-symmetric entity portion as the target entity, and to reuse the capacitance information of the first self-symmetric entity portion to the second self-symmetric entity portion, thereby obtaining the self-symmetric capacitance information of the group of self-symmetric entities.

[0089] The mutual symmetry capacitance extraction unit is used to extract capacitance from a group of mutual symmetry entities, with the first mutual symmetry entity as the target entity, and to reuse the capacitance information of the first mutual symmetry entity to the second mutual symmetry entity to obtain the mutual symmetry capacitance information of the group of mutual symmetry entities.

[0090] The capacitance information acquisition unit is used to obtain parasitic capacitance information based on self-symmetric capacitance information and mutual-symmetric capacitance information.

[0091] In some alternative implementations, the device further includes a layout symmetry detection module, comprising: The self-symmetry detection unit is used to perform self-symmetry detection on the design entity based on the global symmetry element when the design entity intersects with the global symmetry element, and obtain the self-symmetry detection result of the design entity.

[0092] The mutual symmetry detection unit is used to perform mutual symmetry detection on the design entity based on the global symmetry element when the design entity is separate from the global symmetry element, and obtain the mutual symmetry detection result of the design entity.

[0093] The detection result acquisition unit is used to determine the symmetry of the design entity based on the self-symmetric detection results and the mutual symmetric detection results.

[0094] In some optional implementations, the layout symmetry detection module further includes an overall symmetry detection unit, comprising: The overall element calculation sub-unit is used to perform geometric symmetry analysis on the target design layout to obtain the overall self-symmetric elements of the target design layout.

[0095] The boundary element calculation sub-unit is used to perform planning symmetry analysis based on the boundary conditions of the target design layout to obtain the boundary condition symmetry elements.

[0096] The element coincidence judgment sub-unit is used to determine that the target design layout is symmetrical when the overall self-symmetric element and the boundary condition symmetric element coincide, and to treat the overall self-symmetric element or the boundary condition symmetric element as the global symmetric element.

[0097] In some alternative implementations, the self-symmetry detection unit includes: The self-symmetric element calculation sub-unit is used to perform symmetric calculations on intersecting entities to obtain the self-symmetric elements of the intersecting entities.

[0098] The element overlap comparison sub-unit is used to perform overlap comparison based on globally symmetric elements and self-symmetric elements to obtain self-symmetry detection results.

[0099] In some alternative implementations, the mutual symmetry detection unit includes: The symmetric entity matching subunit is used to perform symmetric entity matching on the opposite side of the element-disjoint entity relative to the global symmetric element, and obtain the symmetric entity to be verified corresponding to the element-disjoint entity.

[0100] The mutual symmetric element calculation subunit is used to perform symmetric calculations on element-disjoint entities and symmetric entities to be verified, and obtain the mutual symmetric elements between the element-disjoint entities and the symmetric entities to be verified.

[0101] The element overlap comparison sub-unit is used to perform overlap comparison based on globally symmetric elements and mutually symmetric elements to obtain mutually symmetric detection results.

[0102] In some optional implementations, the layout symmetry detection module further includes: The top-level symmetry detection unit is used to determine the symmetry of the top-level entity based on the global symmetry elements.

[0103] The child-level symmetry detection unit is used to select the child-level entities contained in the top-level entity as the entities to be inspected, provided that the symmetry of the top-level entity meets the preset symmetry requirements, and to determine the symmetry of the entities to be inspected based on the global symmetry elements.

[0104] The iterative detection unit is used to select the child entities contained in the entity to be inspected as the entity to be inspected when the symmetry of the entity to be inspected meets the preset symmetry requirement and the entity to be inspected contains child entities. The process of determining symmetry and selecting entities is repeated until the symmetry of the entity to be inspected does not meet the preset symmetry requirement or the entity to be inspected is a bottom-level entity.

[0105] The entity symmetry detection unit is used to obtain the symmetry of the designed entity based on the symmetry of the entities at multiple levels.

[0106] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0107] In this embodiment, the parasitic capacitance extraction device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0108] Please see Figure 14 , Figure 14This is a schematic diagram of the structure of a computer device provided in an embodiment of this application, such as... Figure 14 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 14 Take a processor 10 as an example.

[0109] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0110] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0111] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0113] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0114] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0115] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0116] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0117] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0118] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0119] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for extracting parasitic capacitance, characterized in that, The method includes: Obtain the target design layout, and divide the design entities symmetrically according to the symmetry of the design entities in the target design layout to obtain a symmetrical entity group; wherein, the symmetrical entity group includes the target entity as the capacitor extraction object and the symmetrical entity that is symmetrical to the target entity; Capacitance is extracted from the target entity, and the capacitance information of the target entity is reused in the symmetric entity to obtain the parasitic capacitance information of the target design layout.

2. The method according to claim 1, characterized in that, The target design layout, when symmetrical overall, corresponds to globally symmetrical elements. The design entities include self-symmetrical entities based on the globally symmetrical elements, or first mutually symmetrical entities and second mutually symmetrical entities based on the globally symmetrical elements. The step of symmetrically dividing the design entities according to the symmetry of the design entities in the target design layout to obtain symmetrical entity groups includes: For the self-symmetric entity, the self-symmetric entity is symmetrically divided according to the global symmetry element to obtain a first self-symmetric entity part and a second self-symmetric entity part, which together form a self-symmetric entity group. For the first mutually symmetric entity and the second mutually symmetric entity, the first mutually symmetric entity and the second mutually symmetric entity are grouped into a mutually symmetric entity group; The symmetric entity group is obtained based on the self-symmetric entity group and the mutually symmetric entity group.

3. The method according to claim 2, characterized in that, The step of extracting capacitance from the target entity and reusing the capacitance information of the target entity to the symmetric entity to obtain the parasitic capacitance information of the target design layout includes: For the self-symmetric entity group, the first self-symmetric entity part is used as the target entity for capacitance extraction, and the capacitance information of the first self-symmetric entity part is reused in the second self-symmetric entity part to obtain the self-symmetric capacitance information of the self-symmetric entity group. For the group of mutually symmetrical entities, the first mutually symmetrical entity is used as the target entity for capacitance extraction, and the capacitance information of the first mutually symmetrical entity is reused in the second mutually symmetrical entity to obtain the mutually symmetrical capacitance information of the group of mutually symmetrical entities. The parasitic capacitance information is obtained based on the self-symmetric capacitance information and the mutual-symmetric capacitance information.

4. The method according to claim 1, characterized in that, The target design layout, while being symmetrical overall, has corresponding globally symmetrical elements; The symmetry of the design entity is determined in the following way: When the design entity intersects with the global symmetry element, the design entity is subjected to self-symmetry detection based on the global symmetry element to obtain the self-symmetry detection result of the design entity; When the design entity is separate from the global symmetry element, the design entity is subjected to mutual symmetry detection based on the global symmetry element to obtain the mutual symmetry detection result of the design entity; The symmetry of the design entity is determined based on the self-symmetry detection results and the mutual symmetry detection results.

5. The method according to claim 4, characterized in that, The following methods can be used to determine whether the target design layout is symmetrical as a whole: Perform geometric symmetry analysis on the target design layout to obtain the overall self-symmetric elements of the target design layout; Based on the boundary conditions of the target design layout, a planning symmetry analysis is performed to obtain the boundary condition symmetry elements; When the overall self-symmetric element coincides with the boundary condition symmetric element, the target design layout is determined to be overall symmetric, and the overall self-symmetric element or the boundary condition symmetric element is taken as the global symmetric element.

6. The method according to claim 4, characterized in that, The design entity intersecting with the global symmetry element is taken as the element intersection entity; the step of performing self-symmetry detection on the design entity based on the global symmetry element to obtain the self-symmetry detection result of the design entity includes: Perform symmetric calculations on the intersecting entities to obtain the self-symmetric elements of the intersecting entities; The self-symmetry detection result is obtained by comparing the overlap between the global symmetric elements and the self-symmetric elements.

7. The method according to claim 4, characterized in that, Design entities that are disjoint from the global symmetry element are defined as disjoint entities; the mutual symmetry detection of the design entities based on the global symmetry element to obtain the mutual symmetry detection result of the design entities includes: Symmetric entity matching is performed on the opposite side of the element-disjoint entity relative to the global symmetric element to obtain the symmetric entity to be verified corresponding to the element-disjoint entity; Symmetric calculations are performed on the element-disjoint entities and the symmetric entities to be verified to obtain the mutually symmetric elements between the element-disjoint entities and the symmetric entities to be verified. The mutual symmetry detection result is obtained by comparing the overlap between the global symmetric elements and the mutually symmetric elements.

8. The method according to claim 4, characterized in that, The design entity includes a multi-level entity, which contains a top-level entity and a bottom-level entity; the method further includes: The symmetry of the top-level entity is determined based on the global symmetry elements; If the symmetry of the top-level entity satisfies the preset symmetry requirement, the child entities contained in the top-level entity are selected as entities to be inspected, and the symmetry of the entities to be inspected is determined according to the global symmetry element. If the symmetry of the entity to be inspected satisfies the preset symmetry requirement and the entity to be inspected contains child entities, select the child entities contained in the entity to be inspected as the entity to be inspected, and repeat the above process of symmetry determination and entity selection until the symmetry of the entity to be inspected does not satisfy the preset symmetry requirement, or the entity to be inspected is the bottom-level entity. The symmetry of the designed entity is obtained based on the symmetry of each of the multi-level entities.

9. A parasitic capacitance extraction device, characterized in that, The device includes: The entity symmetry partitioning module is used to obtain the target design layout and symmetrically partition the design entities according to the symmetry of the design entities in the target design layout to obtain symmetrical entity groups; wherein, the symmetrical entity group includes the target entity as the capacitance extraction object and the symmetrical entity symmetrical to the target entity; The capacitance extraction and reuse module is used to extract the capacitance of the target entity and reuse the capacitance information of the target entity to the symmetrical entity to obtain the parasitic capacitance information of the target design layout.

10. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 8.

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