Control method of two-phase staggered totem pole PFC circuit for vehicle-mounted charger

Abstract

The invention discloses a control method of a two-phase staggered totem pole PFC (power factor correction) circuit for a vehicle-mounted charger, which is characterized in that a selective harmonic feedforward control module is additionally arranged on the basis of traditional voltage-current double closed-loop control, and third, fifth, seventh, eleventh and thirteenth harmonic components are extracted from a power grid voltage signal by adopting an SOGI filter bank; and in the embedded system, harmonic amplitude identification is completed through main circulation, and a service program is interrupted to execute a real-time compensation double-rate cooperation strategy. The effective value of each harmonic component is compared with a preset threshold value, an enabling signal is only generated for the overproof harmonic wave, SOGI filtering operation is executed, a generated harmonic wave feed-forward signal is added with a fundamental wave feed-forward signal and a current loop control signal to generate a PWM modulation signal, and a main circuit switch tube is driven. According to the method, current distortion caused by power grid background harmonic waves is suppressed, meanwhile, introduction of high-frequency noise and phase errors is effectively avoided, and the robustness, the electric energy quality and the computing resource utilization rate of the vehicle-mounted charger under the non-ideal power grid condition are improved.

Description

Technical Field

[0001] This invention relates to a control method for a two-phase interleaved totem pole PFC circuit for an on-board charger, belonging to the field of power electronic converter control. Background Technology

[0002] With the increasing popularity of electric vehicles, the power density and efficiency requirements of on-board chargers (OBCs) are rising. Totem-pole power accelerators (PFCs) have become a research hotspot due to their high efficiency. However, when background harmonic voltages exist in the power grid, traditional PFC control methods can cause severe distortion of the input current, deteriorating system performance and potentially triggering electromagnetic interference (EMI) problems.

[0003] In existing technologies, grid voltage feedforward is commonly used to improve system dynamic response. However, traditional feedforward methods typically introduce the full-band grid voltage signal directly. To reduce costs, on-board chargers often use sampling chips or peripherals with low sampling bandwidth and low hold delay. This results in significant phase errors in mid-to-high frequency signal sampling, and introduces high-frequency noise and disturbances from the grid sampling signal into the control system. In a grid environment rich in harmonics, this can lead to system instability or degraded current waveform quality. To reduce the impact of high-frequency noise, other filters are typically used for noise reduction in the feedforward signal. However, these filters introduce phase delay and reduce the system's high-frequency phase margin. Clearly, only by retaining specific grid voltage harmonic signals that need to be suppressed can the contradictory problems in filter design be reasonably resolved. Summary of the Invention

[0004] The present invention provides a control method for a two-phase interleaved totem pole PFC circuit for an on-board charger in order to solve the problems existing in the prior art.

[0005] The technical solutions adopted in this invention are as follows:

[0006] A control method for a two-phase interleaved totem pole PFC circuit for an on-board charger includes the following steps:

[0007] Sample DC-side voltage signal, grid voltage signal, and two inductor current signals;

[0008] A current amplitude reference signal is generated based on the DC side voltage signal. The current amplitude reference signal is multiplied by the unit sine wave signal output by the phase-locked loop to obtain the inductor current reference signal.

[0009] The inductor current reference signal and the two inductor current signals are respectively input into the current inner loop controller to generate the current loop control signal;

[0010] In the main loop of the embedded system, multiple harmonic components are extracted from the grid voltage signal through the SOGI filter bank and the effective value of each harmonic component is calculated.

[0011] The effective value of each harmonic component is compared with a preset harmonic threshold, and an enable signal is generated for harmonic components that exceed the harmonic threshold.

[0012] In the interrupt routine of the embedded system, SOGI filtering operation of the corresponding subharmonic component is performed according to the frequency indicated by the enable signal to generate a harmonic feedforward signal.

[0013] The current loop control signal, the fundamental feedforward signal extracted from the grid voltage signal, and the enabled harmonic feedforward signals are added together to generate a PWM modulation signal, which drives the switching transistors of the two-phase interleaved parallel totem pole PFC main circuit.

[0014] Furthermore, the multiple harmonic components are the 3rd, 5th, 7th, 11th, and 13th harmonic components.

[0015] Furthermore, the preset harmonic threshold value ranges from 0.05V to 20V, and the threshold design is adjusted according to the specific strength of the power grid.

[0016] Furthermore, the enable signal is implemented through a feedforward coefficient. The feedforward coefficient is set to 1 for harmonic components that exceed the harmonic threshold, and otherwise the feedforward coefficient is set to 0.

[0017] Furthermore, the relationship between extracting harmonic components and calculating their effective values ​​in the main loop and performing SOGI filtering operations in the interrupt routine is as follows:

[0018] The main loop identifies the harmonic amplitude and generates the enable signal. The interrupt service routine performs real-time SOGI filtering operations on the specified harmonic frequency based on the enable signal.

[0019] Furthermore, the transfer function of a single SOGI filter in the SOGI filter bank is:

[0020] ,

[0021] Where s is the Laplace operator, ω r ω is the angular frequency corresponding to the harmonic frequency. c ω is the resonant angular frequency, and k is the damping coefficient.

[0022] Furthermore, the SOGI filter bank is configured only for odd-order harmonics and does not extract even-order harmonic components.

[0023] Furthermore, the highest order of the multiple harmonic components is 13.

[0024] The present invention has the following beneficial effects:

[0025] (1) By using the SOGI filter bank to decompose the grid voltage in the frequency domain, the fundamental frequency and specific low-order harmonic components can be accurately extracted. The enable mechanism based on the harmonic threshold ensures that only the excessive harmonics are compensated, effectively suppressing the current distortion caused by the background harmonics of the grid, while significantly reducing the introduction of high-frequency noise and disturbances, and improving power quality.

[0026] (2) The selective feedforward mechanism avoids introducing unnecessary control complexity when the power grid quality is good, and reduces the impact of filter phase error caused by changes in the hardware system. The dual-rate processing architecture decouples harmonic identification from real-time processing, which reduces the computational burden of the main loop and ensures the real-time response capability of the interrupt service routine.

[0027] (3) Harmonic identification is performed in the slow main loop, and the SOGI operation of the corresponding frequency is activated in the fast interrupt only when an excessive harmonic is detected, realizing the on-demand allocation of control task. This "identification-enable-compensation" collaborative mechanism significantly reduces the performance requirements of the digital controller and is suitable for cost-sensitive OBC application scenarios.

[0028] (4) This invention uses SOGI filter bank to accurately extract the 3rd, 5th and 7th low odd harmonics and achieve selective feedforward by judging the effective value threshold, which effectively reduces the input current distortion rate under non-ideal power grid. At the same time, it avoids the problem of high frequency noise introduced by traditional full feedforward. It balances the compensation real-time performance and system operation burden by embedded dual timing division of labor, and improves the operation stability of the two-phase interleaved parallel totem pole PFC circuit in non-ideal power grid and weak power grid scenarios. Attached Figure Description

[0029] Figure 1 This is the overall control block diagram of the two-phase interlaced totem pole PFC system.

[0030] Figure 2 This is a schematic diagram of the internal structure of a multiplexed SOGI filter.

[0031] Figure 3 This is a flowchart of the logic judgment for selective harmonic feedforward control.

[0032] Figure 4 This is a waveform diagram of the mains voltage used for testing.

[0033] Figure 5 The graph shows the Total Harmonic Distortion (THD) results for the grid voltage waveform.

[0034] Figure 6To enable the PFC input grid current waveform for the 1st, 3rd, 5th, 7th, and 15th harmonic voltage feedforward method.

[0035] Figure 7 The graph shows the THD measurement results of the PFC input grid current for enabling the feedforward method of harmonic voltages 1, 3, 5, 7, and 15.

[0036] Figure 8 The waveform of the PFC input grid current is shown for the proposed method of enabling only the first and fifth harmonic voltage feedforwards.

[0037] Figure 9 The THD results of the PFC input grid current for the proposed feedforward method are shown in the figure.

[0038] Figure 10 The waveform of the PFC input grid current is shown in the PFC method for fully feedforwarding grid voltage.

[0039] Figure 11 The graph shows the THD measurement results of the PFC input grid current in the method of fully feeding forward grid voltage.

[0040] Figure 12 The waveform diagram shows the application of the feedforward algorithm in a real power grid. Detailed Implementation

[0041] The invention will now be further described with reference to the accompanying drawings.

[0042] like Figure 1 As shown, this invention provides a control method for a two-phase interleaved totem pole PFC circuit in an on-board charger. The method aims to solve problems such as current distortion and high-frequency noise interference inherent in traditional PFC control under non-ideal power grid conditions. Its core is to achieve a balance between high power quality and system stability through the synergy of a selective harmonic feedforward mechanism and dual closed-loop control. The implementation process of this invention will be described in detail below with reference to the accompanying drawings.

[0043] The implementation of this invention relies on the hardware support of a two-phase interlaced totem pole PFC system, such as... Figure 1 As shown, the system mainly includes a two-phase interleaved parallel totem-pole PFC main circuit, a voltage and current sampling circuit, a digital signal processor (DSP), and a drive circuit. The main circuit includes inductors L1 and L2, an output capacitor Cout, and six switching transistors S1 to S6. S1 and S2 are turned on according to the traditional totem-pole control logic. S2 is enabled during the positive half-cycle of the power grid, and S1 is enabled during the negative half-cycle. S3 to S6 are fast switching transistors used to respond to PWM modulation signals to achieve power conversion.

[0044] The sampling circuit is responsible for acquiring the DC side voltage Vdc, the mains voltage Vgrid, and the two inductor currents i. L1 i L2The sampling chips or peripherals used are adapted to the design requirements of low bandwidth and low latency, which meets the cost control goals of vehicle chargers, while avoiding significant phase errors caused by mid-to-high frequency signal sampling.

[0045] The specific control process is as follows:

[0046] First, signal sampling is performed. The sampling circuit collects DC side voltage signal, grid voltage signal and two inductor current signals in real time, and converts the collected analog signals into digital signals and transmits them to the signal processing unit of the DSP to provide a data basis for the execution of subsequent control algorithms.

[0047] Based on the acquired DC-side voltage signal, a current amplitude reference signal I is generated through the DC voltage outer loop PI controller. ref_mag The reference value for the outer voltage loop is the preset target DC output voltage U. O * The feedback value is the actual sampled DC-side voltage V. dc The proportional parameter of the controller is k p,v The integration parameter is k i,v PI control is used to eliminate DC voltage deviations and ensure stable output voltage. Subsequently, the current amplitude reference signal I is used. ref_mag Multiplying the signal by the unit sine wave output from the phase-locked loop (SPLL) yields the inductor current reference signal i. ref ,like Figure 1 As shown, the SPLL module tracks the grid voltage V grid The phase of the inductor current reference signal iref is generated to be in phase with the grid fundamental wave. This ensures that the phase of the inductor current reference signal iref is consistent with the grid voltage, providing a prerequisite for power factor correction.

[0048] The above inductor current reference signal i ref With two inductor current signals i L1 i L2 The inputs are given to the inner current loop PI controller, with the proportional parameter k of the inner current loop being k. p,i The integration parameter is k i,i By calculating the deviation between the reference current and the actual inductor current and performing PI regulation, a current loop control signal is generated. This signal can quickly respond to the current deviation and ensure that the inductor current stably tracks the reference signal.

[0049] In the main loop of the embedded system, the mains voltage signal V is processed by the SOGI filter bank. grid Perform frequency domain decomposition, such as Figure 2As shown, the SOGI filter bank consists of multiple parallel SOGI filters. Each filter is tuned to the fundamental frequency of the power grid (50Hz) and the 3rd, 5th, 7th, 11th and 13th odd harmonic frequencies, respectively. No filters are configured for even harmonics because the even harmonics in the power grid are mostly caused by detection errors and do not require compensation.

[0050] The transfer function of a single SOGI filter is:

[0051] ,

[0052] Where s is the Laplace operator, ω r The angular frequency corresponding to the harmonic frequency (e.g., ωr = 3ω0 for the 3rd harmonic, where ω0 is the fundamental angular frequency), ω c Let be the resonant angular frequency, and k be the damping coefficient, used to determine the filter bandwidth. In practical applications, this continuous-domain transfer function can be converted into a discrete-domain transfer function using digital methods such as bilinear transform, so that it can be implemented in a DSP. The general form of the discrete-domain transfer function is (where A, B, C, D, and E are the discretized coefficients):

[0053] ,

[0054] When the SOGI filter bank is working, it extracts the fundamental component and the aforementioned low-order odd harmonic components from the grid voltage in parallel, and obtains the effective voltage value of each harmonic component through the effective value calculation algorithm. This calculation process is a slow task and does not need to be repeated in every power frequency cycle. It only needs to be completed periodically in the main loop, which will not increase the system's computational burden.

[0055] The effective voltage values ​​of each harmonic component are compared with preset effective harmonic voltage thresholds (ranging from 0.05V to 2V, adjustable according to actual hardware parameters). Figure 3 The logic judgment process shown is as follows: if the effective value of a certain harmonic component exceeds the threshold, the corresponding enable signal EN_n (n=1,3,5…)=1 is generated. The enable signal is implemented through the feedforward coefficient, and the corresponding feedforward coefficient is set to 1. If the threshold is not exceeded, the enable signal is 0 and the corresponding feedforward coefficient is set to 0, thereby realizing the "on-demand allocation" of harmonic compensation.

[0056] In the fast interrupt routine of the embedded system, SOGI filtering operations for the corresponding subharmonic components are executed according to the frequency indicated by the aforementioned enable signal. The main loop and the interrupt routine have a clear division of labor: the main loop identifies the harmonic amplitude and generates the enable signal, while the interrupt service routine focuses on the real-time SOGI filtering operation to ensure the timely generation of the harmonic feedforward signal. Specifically, when the enable signal is 1, the corresponding SOGI filter in the interrupt routine is activated, performing real-time filtering on the mains voltage signal and outputting an accurate harmonic feedforward signal; when the enable signal is 0, the corresponding SOGI filtering operation is not executed to avoid unnecessary calculations consuming system resources.

[0057] Finally, the current loop control signal, the fundamental wave feedforward signal extracted from the grid voltage signal (which can be generated by a low-pass filter or a fundamental wave SOGI filter), and the enabled harmonic feedforward signals are added together to generate a total modulation signal. This total modulation signal is compared with a triangular carrier wave to generate a PWM modulation signal, which is transmitted through the drive circuit to the switching transistors S3~S6 of the two-phase interleaved parallel totem pole PFC main circuit to control the on / off timing of the switching transistors, thereby realizing the conversion and transmission of electrical energy.

[0058] like Figure 4 The waveform shown is the grid voltage waveform used for testing. Because the grid contains harmonic sources and weak damping, it contains a relatively high content of medium- and high-frequency harmonic voltages. When a certain harmonic voltage exists in the grid, the linear load will have a current at the corresponding harmonic frequency.

[0059] like Figure 5 The THD measurements of the grid voltage waveform are shown. The 5th and 15th harmonics are severely exceeded, and the 3rd and 7th harmonics are also present.

[0060] like Figure 6 The figure shows the PFC input grid current waveform when the 1st, 3rd, 5th, 7th, and 15th harmonic voltage feedforward method is enabled.

[0061] like Figure 7 The figure shown is the THD measurement result of the PFC input grid current when the 1st, 3rd, 5th, 7th, and 15th harmonic voltage feedforward method is enabled. Among them, the 3rd, 5th, 7th, and 15th harmonics exceed the standard, and the overall THD is 5.1%, which exceeds the national general requirement of 5%.

[0062] like Figure 8 The figure shown is the PFC input grid current waveform when only the first and fifth harmonic voltage feedforward methods are enabled.

[0063] like Figure 9 The figure shows the THD results of the PFC input grid current with the proposed feedforward method. Without enabling the 15th order voltage exceeding the measurement bandwidth, the input current with less harmonic current can be obtained, and the THD is only 4.73%.

[0064] like Figure 10 The figure shows the waveform of the PFC input grid current in the method of fully feeding forward grid voltage.

[0065] like Figure 11 The figure shown is a graph of the THD measurement results of the PFC input grid current using the full grid voltage feedforward method.

[0066] Figure 11 and Figure 9 In comparison, the 7th and 15th harmonic voltages of the fully feedforward method are significantly higher. Therefore, the proposed method that only enables the 1st and 5th harmonic voltages is more beneficial in avoiding the influence of high-frequency harmonics. If higher-order harmonics exceed the threshold, corresponding harmonic feedforward must also be enabled. However, introducing feedforward below the threshold condition will actually worsen the mitigation effect. It should be noted that because the inductor has higher high-frequency impedance and a higher harmonic content, the harmonic voltage threshold must also be set higher.

[0067] Figure 12 To demonstrate the reliable operation of the feedforward algorithm in a real power grid, oscilloscope photos were taken directly to show the waveforms.

[0068] It should be noted that the specific values ​​of the preset harmonic voltage effective value threshold, the damping coefficient k of the SOGI filter, and the resonant angular frequency ω in this invention are not specified. c These parameters can be adjusted according to the power level, hardware configuration, and actual power grid environment of the vehicle charger. As long as they follow the control logic and method of this invention, they are all within the protection scope of this invention.

[0069] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements without departing from the principle of the present invention, and these improvements should also be considered within the scope of protection of the present invention.

Claims

1. A control method for a two-phase interleaved totem-pole PFC circuit in an on-board charger, characterized in that: Includes the following steps: Sample DC-side voltage signal, grid voltage signal, and two inductor current signals; A current amplitude reference signal is generated based on the DC side voltage signal. The current amplitude reference signal is multiplied by the unit sine wave signal output by the phase-locked loop to obtain the inductor current reference signal. The inductor current reference signal and the two inductor current signals are respectively input into the current inner loop controller to generate the current loop control signal; In the main loop of the embedded system, multiple harmonic components are extracted from the grid voltage signal through the SOGI filter bank and the effective value of each harmonic component is calculated. The effective value of each harmonic component is compared with a preset threshold value of the effective value of the harmonic voltage, and an enable signal is generated for the harmonic components that exceed the threshold value. In the interrupt routine of the embedded system, SOGI filtering operation of the corresponding subharmonic component is performed according to the frequency indicated by the enable signal to generate a harmonic feedforward signal. The current loop control signal, the fundamental feedforward signal extracted from the grid voltage signal, and the enabled harmonic feedforward signals are added together to generate a PWM modulation signal, which drives the switching transistors of the two-phase interleaved parallel totem pole PFC main circuit.

2. The control method for a two-phase interleaved totem pole PFC circuit for an on-board charger as described in claim 1, characterized in that: The multiple harmonic components are the 3rd, 5th, 7th, 11th and 13th harmonic components.

3. The control method for a two-phase interleaved totem pole PFC circuit for an on-board charger as described in claim 1, characterized in that: The preset effective value threshold for harmonic voltage ranges from 0.05V to 20V, and the threshold design is adjusted according to the specific strength of the power grid.

4. The control method for a two-phase interleaved totem pole PFC circuit for an on-board charger as described in claim 1, characterized in that: The enable signal is implemented through a feedforward coefficient. The feedforward coefficient is set to 1 for harmonic components that exceed the harmonic threshold, and otherwise the feedforward coefficient is set to 0.

5. The control method for a two-phase interleaved totem pole PFC circuit for an on-board charger as described in claim 1, characterized in that: The relationship between extracting harmonic components and calculating their effective values ​​in the main loop and performing SOGI filtering operations in the interrupt routine is as follows: The main loop identifies the harmonic amplitude and generates the enable signal. The interrupt service routine performs real-time SOGI filtering operations on the specified harmonic frequency based on the enable signal.

6. The control method for a two-phase interleaved totem pole PFC circuit for an on-board charger as described in claim 1, characterized in that: The transfer function of a single SOGI filter in the SOGI filter bank is: ， Where s is the Laplace operator, ω r ω is the angular frequency corresponding to the harmonic frequency. c ω is the resonant angular frequency, and k is the damping coefficient.

7. The control method for a two-phase interleaved totem pole PFC circuit for an on-board charger as described in claim 1, characterized in that: The SOGI filter bank is configured only for odd-order harmonics and does not extract even-order harmonic components.

8. The control method for a two-phase interleaved totem pole PFC circuit for an on-board charger as described in claim 1, characterized in that: The highest order of the multiple harmonic components is 13.

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