H-bridge low-frequency switch control method of cascaded half-bridge converter

Abstract

The invention discloses an H-bridge low-frequency switch control method of a cascaded half-bridge converter, which is characterized in that a direct-current side adopts an in-phase carrier laminated modulation strategy, zero level duration is increased at a signal zero crossing point, the action times of a direct-current side switching device near the zero crossing point are reduced, and the switching loss of an H-bridge under closed-loop control is effectively inhibited. An alternating current side phase control algorithm is provided for multiple bridge arms, the bridge arms are divided into a leading group and a lagging group, control signals of sub-modules are redistributed based on fundamental wave phases, meanwhile, two groups of phase-complementary power frequency control signals are distributed for H bridges of the bridge arms, and on the premise that the output characteristics of the converter are not affected, the control signals of the sub-modules are distributed to the H bridges of the bridge arms. All H-bridge switching tubes only act twice in a fundamental wave period, strict power frequency switching and zero voltage switching are achieved, and switching loss is reduced to the minimum. And meanwhile, a battery online energy balancing function based on SOC sorting is integrated, so that the reliability of the converter is improved and the service life of the converter is prolonged on the premise of keeping relatively high output waveform quality, and the switching frequency of an H bridge under closed-loop control is reduced.

Description

Technical Field

[0001] This invention relates to a low-frequency switching control method for the H-bridge of a cascaded half-bridge converter, belonging to the field of power electronic converter technology. Background Technology

[0002] Driven by the global energy structure transformation and the strategic goals of "carbon peaking and carbon neutrality," the proportion of distributed renewable energy generation, represented by photovoltaic and wind power, continues to increase. However, the inherent intermittency and volatility of renewable energy pose a severe challenge to the stable operation of the power grid. Against this backdrop, electrochemical energy storage systems, due to their flexible adjustment, rapid response, and convenient deployment, have become a key technological support for smoothing renewable energy output and improving the grid's absorption capacity.

[0003] As the core energy conversion device connecting energy storage batteries and the power grid, the energy storage converter's topology and control performance directly determine the efficiency, cost, and reliability of the entire energy storage system. For medium-to-high voltage, large-capacity energy storage applications, multilevel converter technology exhibits significant advantages. This technology cascades several power units, utilizing low-voltage switching devices to synthesize a high-voltage, low-harmonic-content output voltage, thereby effectively reducing the size of the output filter, suppressing electromagnetic interference, and minimizing voltage stress and cost on the switching devices.

[0004] In multilevel topologies, cascaded H-bridge converters have attracted considerable attention due to their high modularity and relatively simple control. However, traditional CHB topologies require four additional switches for each additional level pair. When applied to battery energy storage systems, a large number of H-bridge units need to be connected in series to achieve the required output voltage level, resulting in a significant increase in the number of switching devices, system size, cost, and control complexity. To overcome the shortcomings of CHB topologies, a cascaded half-bridge topology has been proposed in recent years. This topology uses grouped series half-bridge submodules on the DC input side, with each group of submodules supplying one H-bridge inverter unit; on the AC output side, multiple H-bridge units are then connected in series for output. This structure separates the multilevel generation and inversion functions. By rationally configuring the number of battery packs and the number of submodules in each group, an optimal balance can be achieved between the number of switching devices and the voltage stress borne by a single H-bridge, reducing system cost and dependence on high-voltage devices. Since each H-bridge only bears the DC voltage of its corresponding battery pack, rather than the total DC voltage of the system, mature and more reliable medium- and low-voltage switching devices can be widely used.

[0005] In the control strategy of this cascaded half-bridge topology, the subsequent H-bridge typically employs a control strategy based on the zero-crossing point of the modulation wave. Under ideal open-loop control conditions, the modulation wave is a standard sine wave, with only two zero-crossing points within one fundamental cycle. Therefore, the H-bridge can operate strictly at the power frequency with extremely low switching losses. However, when this topology operates in scenarios requiring precise closed-loop control of the output voltage or current (such as high-precision motor drives and grid-connected inverters), its H-bridge zero-crossing control strategy has theoretical flaws. To achieve fast dynamic response and high-precision output waveform tracking, the modulation wave signal output by the closed-loop controller is no longer an ideal sine wave but contains abundant high-order harmonic components to compensate for the error between the open-loop output and the reference waveform. This waveform distortion of the modulation wave generates high-frequency oscillations near the fundamental frequency zero-crossing point, producing a large number of "false" zero-crossing points. If zero-crossing detection is used to control the H-bridge switching state, the H-bridge switches will be forced to frequently operate following the zero-crossing points, deteriorating from an ideal power frequency switching state to a high-frequency switching state related to the degree of modulation wave distortion. Since the switching losses of a switching transistor are directly proportional to the switching frequency, this unexpected change in operating conditions will significantly increase the switching losses, directly affecting its lifespan and reducing the reliability of the converter. Furthermore, high-frequency switching operations will generate severe electromagnetic interference, threatening the stable operation of surrounding equipment.

[0006] In summary, the control strategy of the H-bridge in this cascaded half-bridge topology has inherent defects in closed-loop control applications, severely limiting its potential in high-performance and high-reliability applications. A novel control method suitable for this type of topology is urgently needed to fundamentally solve the problem of H-bridge switching frequency runaway in closed-loop applications while leveraging its advantages. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a low-frequency switching control method for the H-bridge of a cascaded half-bridge converter, so that the switching frequency of the H-bridge of the multi-bridge arm system is strictly limited to the power frequency in the closed-loop operation state, thereby significantly reducing switching losses while maintaining high-quality power output and efficient battery management capabilities.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A low-frequency switching control method for an H-bridge of a cascaded half-bridge converter, wherein the DC input side of the cascaded half-bridge converter is composed of M battery packs connected in series, each battery pack consisting of... The system consists of several half-bridge submodules connected in series. Each half-bridge module adopts a half-bridge structure containing an independent energy storage battery and two switching transistors. M and All values ​​are integers not less than 2; the AC output side consists of M H-bridge inverter units connected in series on the AC side, with the number of H-bridge inverter units matching the number of battery packs. The DC input terminal of each H-bridge inverter unit is directly connected to the output terminal of the corresponding battery pack, and each H-bridge inverter unit independently bears the DC voltage of the corresponding battery pack; the total output AC voltage of the cascaded half-bridge converter is the sum of the AC voltages of all H-bridge inverter units, and an LC low-pass filter is connected after the AC output side to filter the voltage waveform on the AC output side into the required load voltage waveform; the control method includes: To address the issue of excessively high H-bridge switching frequency caused by modulation waveform distortion under closed-loop control, a collaborative optimization strategy of DC-side in-phase carrier stacked modulation (PDLSPWM) and AC-side phase control algorithm is employed to minimize the power frequency switching and switching losses of the H-bridge. Specifically, the DC-side uses in-phase stacked carrier stacked modulation to generate half-bridge submodule control signals to suppress H-bridge switching losses. The AC-side phase control algorithm, designed for multi-arm systems, strictly limits the H-bridge switching frequency to the fundamental frequency through arm grouping, power frequency square wave signal generation, and dynamic carrier reallocation, and integrates battery energy balancing functionality. PDLSPWM is used to generate control signals for the DC-side half-bridge switching devices. Assuming the number of DC-side sub-modules is N, the controller compares the modulated wave with 2N consecutively stacked triangular carriers with the same phase and frequency and amplitude in the range of [-N,N]. Each half-bridge sub-module is assigned a positive carrier and a load wave, and the comparison result with the modulated wave is logically ORed and regarded as the same set of waveforms. A phase control algorithm is used to generate control signals for the AC-side H-bridge switching devices. All bridge arms are divided into two groups. Based on the phase of the output fundamental wave (or reference sine wave), two square wave signals with the same frequency but complementary phases are generated as the driving signals for the two groups of bridge arms. The bridge arm whose driving signal phase leads the fundamental wave phase is the leading bridge arm, and vice versa. To generate the correct output level and reduce output fluctuations, the DC-side carrier allocation method is subject to the following restrictions: the zero-crossing phase when the fundamental wave crosses the negative half-axis to the positive half-axis is taken as 0°. When the fundamental wave phase is in the range of [-90°, 90°], the carriers in the amplitude range of [-4, -3], [-3, -2], [0, 1], [1, 2] must be allocated to the sub-modules belonging to the leading bridge arm, and the carriers in the amplitude range of [-2, -1], [-1, 0], [2, 3], [3, 4] are allocated to the sub-modules belonging to the lagging bridge arm. When the fundamental wave phase is in the range of [90°, 270°], the allocation method is reversed. Simultaneously, an online battery energy balancing strategy based on SOC sorting is integrated. At a preset energy balancing time, by comparing the SOC values ​​of each submodule, and under the premise of satisfying carrier allocation constraints, the carrier with lower amplitude is allocated to the submodule with higher SOC, so that it generates a larger power change within a balancing cycle, thereby achieving dynamic battery energy balancing.

[0009] The preferred in-phase carrier stacked modulation strategy is as follows: Each submodule corresponds to a positive carrier wave and a load wave. 2N carrier waves are arranged in a continuous, equally spaced stacked manner in the amplitude dimension, with absolute amplitude values ​​covering the range [0, N]. All carrier waves have the same frequency and phase. The reference sinusoidal modulated wave v output by the closed-loop controller... ref Each is compared with the 2N triangular carrier waves. Since the half-bridge module can only output non-negative voltages, when v... ref When v is positive, the modulation logic is positive logic, that is, when v is positive. ref When the voltage is greater than a certain carrier wave, a control signal of "1" is generated, corresponding to the upper transistor of the submodule being turned on and the lower transistor being turned off, and the submodule outputs the battery voltage; when v ref When the voltage is less than a certain carrier wave, a control signal of "0" is generated, corresponding to the upper transistor of the submodule being turned off and the lower transistor being turned on, the submodule being short-circuited, and the output being 0; conversely, when v is greater than a certain carrier wave, a control signal of "0" is generated, corresponding to the upper transistor of the submodule being turned off and the lower transistor being turned on, the submodule being short-circuited, and the output being 0; ref When v is negative, the modulation logic is negative logic. ref When the signal is greater than a certain carrier wave, a control signal of "0" is generated, and so on.

[0010] The preferred AC-side phase control algorithm is as follows: The leading arm switches its state before the fundamental voltage crosses zero from the negative half-cycle to the positive half-cycle, while the lagging arm switches its state after the fundamental voltage crosses zero from the positive half-cycle to the negative half-cycle. A control signal of "1" indicates that the arm outputs a non-negative voltage, and a control signal of "0" indicates that the arm outputs a non-positive voltage. The state is maintained when the fundamental phase θ satisfies -90°≤θ<90° and the instantaneous fundamental value V... o >-V th Or when 90°≤θ< 270° and V o >V th At that time, the advance arm control signal is in the "1" state, where -V th V th These are the preset negative and positive voltage thresholds, V. th Take a constant of 1; for the rest of the time within one cycle, the advance arm control signal is in the "0" state; when the fundamental phase θ satisfies 90°≤θ<270° and the fundamental instantaneous value V o >-V th Or when -90°≤θ<90° and V o >V thAt the specified time, the lagging bridge arm control signal is in the "1" state; at other times, the lagging bridge arm control signal is in the "0" state. Through the above logic judgment, the control signals of the two bridge arms are two sets of square waves with different phases but the duty cycle of the two bridge arms is 0.5. Therefore, for any switch of the H-bridge, it only operates twice in one fundamental cycle, and the conduction time of all H-bridge switches is equal. The positive or negative value of the bridge arm output voltage is determined by the instantaneous value and phase of the fundamental wave, and is independent of the modulation wave.

[0011] The preferred online energy balancing strategy for batteries based on SOC ranking is as follows: With a preset equalization time interval The system executes periodically. At the equalization trigger moment, it sorts the SOC parameters of all energy storage batteries in the leading and lagging arms. When the converter is operating in discharge mode, according to the above allocation method, carriers in the amplitude range of [-4,-3], [-3,-2], [0,1], [1,2] are allocated to the two half-bridge submodules with the highest SOC in the leading arm, and carriers in the amplitude range of [-2,-1], [-1,0], [2,3], [3,4] are allocated to the two half-bridge submodules with the highest SOC in the lagging arm. The remaining N-4 half-bridge submodules are then sorted from high to low SOC. For carriers with an absolute amplitude value greater than 4, carriers closer to the horizontal axis are allocated to the half-bridge submodule with the highest SOC, and carriers farther from the horizontal axis are allocated to the half-bridge submodule with the lowest SOC. The above allocation logic is reversed in charging mode. Through the above equalization strategy, energy equalization of all energy storage batteries in the converter can be achieved.

[0012] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects: 1. The H-bridge of this invention operates at the power frequency, and the number of switching cycles in one cycle is greatly reduced compared to the high-frequency switching mode, which helps to improve system efficiency and reduce converter losses.

[0013] 2. The low-frequency switching characteristics of this invention reduce the thermal and electrical stresses of the H-bridge power devices, thereby improving the lifespan and reliability of the entire converter.

[0014] 3. The PDLSPWM used on the DC side of this invention is a high-performance modulation strategy. The multi-level waveforms it generates are superior to the equivalent POD method in terms of harmonic characteristics, thereby improving the output waveform quality of the converter.

[0015] 4. This invention adopts a carrier allocation and redistribution mechanism that is naturally compatible with the battery energy balancing algorithm based on SOC sorting, thereby realizing lossless online battery energy management and improving the functional integration of the converter.

[0016] 5. The control method of this invention is not limited to specific topology parameters, but can be flexibly applied to different levels and number of bridge arms, and has strong universality. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the system topology and control principle of the H-bridge low-frequency switching control method for a cascaded half-bridge converter according to the present invention; Figure 2 This is a schematic diagram of the system topology and control principle of an embodiment of the present invention; Figure 3 This is a schematic diagram of the output level near the zero crossing point and the H-bridge state under PD modulation in an embodiment of the present invention; Figure 4 This is a schematic diagram of the H-bridge power frequency switch control algorithm according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the battery energy balancing strategy according to an embodiment of the present invention. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] like Figure 1 As shown, this invention proposes a low-frequency switching control method for the H-bridge of a cascaded half-bridge converter, through collaborative innovation of DC-side modulation strategy and AC-side H-bridge control algorithm. First, the modulation strategy of the DC-side switching devices is optimized to in-phase carrier stacking. Second, a novel phase control algorithm is introduced on the AC side to force the H-bridge switching frequency to the power frequency and adjust the carrier allocation method to generate correct multi-level output. This invention also integrates an online battery energy balancing function based on SOC ranking, achieving collaborative optimization.

[0020] The DC side employs a phase-shifted cascaded modulation (PDLSPWM) strategy to generate the control signals for the half-bridge submodules, instead of the traditional sinusoidal half-wave modulation (which has positive and negative reverse cascading characteristics, i.e., POD properties) suitable for half-bridge topologies. This strategy is characterized by providing 2N triangular carriers of the same frequency and phase for N submodules, with the amplitudes of these carriers arranged in equal intervals within the range [-N, N]. The control signal for each submodule is generated by logically ORing the comparison result of its corresponding carrier (including one positive carrier and one negative carrier) with the modulated wave output from the closed-loop controller. Using the PDLSPWM method increases the waveform quality of the open-loop output and creates a wider zero-level plateau near the zero-crossing point of the modulated wave, effectively extending the zero-level duration near the zero-crossing point and thus suppressing the switching losses of the H-bridge switches under closed-loop control.

[0021] For multi-bridge systems with M ≥ 2 bridge arms, an innovative AC-side phase control algorithm is employed. This algorithm divides the bridge arms into two groups: "leading bridge arms" and "lagging bridge arms." Based on the phase of the output fundamental frequency, it generates two complementary power frequency square wave control signals with a constant duty cycle of 0.5. The control signal of the leading bridge arm switches states when the fundamental frequency amplitude meets a specific threshold condition, while the control signal of the lagging bridge arm always maintains a complementary phase relationship with the leading bridge arm. The phases of the two sets of control signals are determined by the instantaneous value of the fundamental frequency and are independent of the high-frequency components of the modulation wave. Therefore, regardless of how the actual output waveform changes, the switching transistor of each H-bridge operates only twice within one fundamental frequency cycle, achieving strict power frequency switching.

[0022] The phase control algorithm includes a dynamic carrier reallocation strategy that triggers the carrier reallocation process when the fundamental phase reaches critical phase points of 90° and 270°. The redistribution rules require that carriers in specific amplitude ranges be fixedly allocated to specific groups of bridge arms in different phase intervals: taking the fundamental threshold as ±1, within the interval [-90°, 90°], carriers in the amplitude ranges [-4, -3], [-3, -2], [0, 1], and [1, 2] are allocated to the sub-modules corresponding to the leading bridge arm, and carriers in the ranges [-2, -1], [-1, 0], [2, 3], and [3, 4] are allocated to the sub-modules corresponding to the lagging bridge arm; within the interval [90°, 270°], carriers in the amplitude ranges [-2, -1], [-1, 0], [2, 3], and [3, 4] are allocated to the sub-modules corresponding to the leading bridge arm, and carriers in the ranges [-4, -3], [-3, -2], [0, 1], and [1, 2] are allocated to the sub-modules corresponding to the lagging bridge arm; carriers with an absolute amplitude value ≥ 4 are not restricted. The above allocation logic ensures that the output voltage polarities of the two equivalent bridge arms are opposite near the zero-crossing point of the fundamental wave, and synthesizes the high-frequency components of the modulated wave without changing the state of the H-bridge; at the same time, it ensures the correct synthesis of the multi-level output waveform and realizes zero-voltage switching of the H-bridge switching devices.

[0023] This invention employs a dual closed-loop control strategy of voltage and current for output closed-loop control. The outer loop is a voltage loop, which uses a first QPR controller to generate an inner loop reference signal by detecting the difference between the reference voltage and the output voltage. The inner loop is a current loop, which uses a second QPR controller to detect the difference between the inner loop reference and the filter capacitor current, and generate a modulated wave signal with the reference voltage as the fundamental frequency but containing high-frequency harmonic components.

[0024] This invention integrates an online battery energy balancing strategy based on SOC ranking, with a preset balancing time interval. Periodic execution. At the equalization trigger moment, by collecting the SOC parameters of each battery, and under the premise of satisfying the carrier allocation rules, the submodule containing the battery with higher SOC is preferentially allocated to the carrier with lower amplitude in the current output interval. This allocation method allows the high SOC battery to have a longer conduction time during discharge, thereby achieving online automatic battery energy equalization. Through the synergistic implementation of the above technical solutions, this invention can effectively solve the problem of excessively high H-bridge switching frequency in the cascaded half-bridge converter under closed-loop control, achieving high-efficiency and high-reliability energy conversion of the converter.

[0025] This embodiment uses a converter with two bridge arms, each containing four sub-modules, as an example to describe the specific implementation of the present invention in detail. Those skilled in the art can understand the present invention based on this example and apply it to other parameter configurations.

[0026] like Figure 2 As shown, the embodiment topology includes two battery packs, each powered by four half-bridge submodules connected in series. Each submodule contains a storage battery and a half-bridge consisting of two switching transistors. The AC output sides of the two H-bridges are connected in series and then connected to the load or grid after passing through an LC filter. The first battery pack is designated as the leading group, and the corresponding H-bridge is designated as the leading arm; the second battery pack is designated as the lagging group, and the corresponding H-bridge is designated as the lagging arm. This embodiment of the invention employs a dual closed-loop QPR control strategy for closed-loop control of the output. The controller samples the load voltage v. o The input signal to the voltage loop is obtained by subtracting the reference voltage from the input signal. After passing through the QPR controller of the voltage loop, the reference current signal of the current loop is output. Considering that filters often adopt an integrated design, capacitor current acquisition is relatively difficult. Therefore, the controller acquires the inductor current and the load current, and the difference between the two yields the capacitor current. The input signal to the current loop is obtained by subtracting the reference current from the capacitor current. After passing through the QPR controller of the current loop, the final closed-loop modulation wave original signal is obtained. The signal is then scaled to obtain the actual modulation wave signal PWM of the PWM module. ref The scaling factor is 8 / U. max (U) max (The amplitude is the reference voltage). Through the PDLSPWM process, 16 sets of PWM control signals are obtained. Among them, 8 sets are the comparison results of the modulated wave and the positive carrier wave, and 8 sets are the comparison results of the modulated wave and the load wave.

[0027] like Figure 3As shown, it is assumed that the DC-side half-bridge uses PDLSPWM modulation under closed-loop control, but the AC-side H-bridge still uses traditional zero-crossing modulation. When considering the harmonics contained in the modulation wave, the H-bridge will inevitably oscillate near the zero-crossing point of the fundamental wave. Since the phases of the positive load waves are all the same under PD modulation, the difference between the instantaneous values ​​of the upper and lower carrier waves is always 1. In addition, the carrier frequency is generally much greater than the fundamental frequency, which means that there must be a certain time interval between the output positive level and the output negative level of the converter: from Figure 3 In the middle, it is reflected in PWM. 1+ high level and PWM 1- There is a region where the H-bridge is simultaneously at a low level between the high and low levels. Oscillation of the H-bridge may occur during this region. Since the converter's output voltage is 0 during this time, even if the H-bridge oscillates, its switching can still be considered a zero-voltage switch, reducing the switching losses of the H-bridge. In contrast, in the traditional equivalent POD mode, because the carrier phases of amplitudes in the [-1,0] and [0,1] intervals are opposite, their instantaneous values ​​can both be 0, resulting in an extremely short switching time between the converter's positive and negative output levels. Since the converter inevitably undergoes an H-bridge state switching process between positive and negative output levels, the H-bridge exhibits significant switching losses. In summary, using PDLSPWM helps suppress the switching losses of the H-bridge.

[0028] like Figure 4 As shown, the proposed phase control algorithm is used to generate the H-bridge control signal, with an amplitude threshold of ±1. The input to the algorithm is a reference sine wave or the fundamental component v of the output waveform. ref After scaling factor 8 / U max After normalization, the reference signal H for the actual H-bridge phase control algorithm is obtained. ref And add a phase-locked loop to determine H. ref The phase θ. The bridge arms are divided into two groups: "leading arms" and "lagging arms". The leading arm is defined at H... ref The state transition occurs before the zero crossing from the negative half-cycle to the positive half-cycle, with the lagging bridge arm at H. ref The state transition occurs after the positive half-cycle crosses zero into the negative half-cycle. A high-level control signal indicates a non-negative voltage output from the bridge arm, and a low-level control signal indicates a non-positive voltage output from the bridge arm. This occurs when θ satisfies -90°≤θ<90° and H... ref >-1, or when 90°≤θ<270° and H ref When >1, the advance arm control signal H a It is in a high-level state at the beginning and in a low-level state at the end of the time; when bit θ satisfies 90°≤θ<270° and the fundamental instantaneous value V o >-1, or when -90°≤θ<90° and V o When >1, the lagging bridge arm control signal H lIt is in a high-level state; otherwise, it lags behind the bridge arm control signal H. l It is in a low-level state. Using the above algorithm, the control signals for the two bridge arms are two sets of complementary square waves, each with a duty cycle of 0.5. Therefore, for any switch in the H-bridge, it operates only twice within one fundamental cycle, and the conduction time of all H-bridge switches is equal.

[0029] The phase control algorithm requires a dynamic carrier reallocation strategy to generate correct multi-level output. This strategy triggers a carrier reallocation process when the fundamental phase reaches critical phase points of 90° and 270°, fixing the carrier in a specific amplitude range to specific groups of bridge arms in different phase intervals. (U...) n This represents the nth carrier wave with a positive amplitude (1≤n≤8), represented by D. n This represents the nth carrier group with a negative amplitude. From the perspective of the submodule, the amplitude distribution of the 16 carrier groups within one period is as follows: In the interval [-90°, 90°], carriers in the amplitude intervals [-4, -3], [-3, -2], [0, 1], and [1, 2] are assigned to the leading arm, and carriers in the intervals [-2, -1], [-1, 0], [2, 3], and [3, 4] are assigned to the lagging arm; In the interval [90°, 270°], carriers in the amplitude intervals [-2, -1], [-1, 0], [2, 3], and [3, 4] are assigned to the leading arm, and carriers in the intervals [-4, -3], [-3, -2], [0, 1], and [1, 2] are assigned to the lagging arm; Carriers with an absolute amplitude value ≥ 4 are not restricted. The above allocation logic ensures that the output voltage polarities of the two equivalent bridge arms are opposite near the zero-crossing point of the fundamental wave, and synthesizes the high-frequency components of the modulated wave without changing the state of the H-bridge; at the same time, it ensures the correct synthesis of the multi-level output waveform and realizes zero-voltage switching of the H-bridge switching devices.

[0030] like Figure 5 As shown, during converter operation, the system uses a preset equalization time interval. A periodic online energy balancing strategy is implemented. The SOC parameters of all energy storage batteries in the leading and lagging arms are collected and sorted. When the preset balancing time arrives, carriers with amplitudes in the range [-4, 4] are allocated to the four sub-modules with the lowest SOC values ​​in both arms (two in the leading arm and two in the lagging arm), based on the principle that sub-modules with higher SOC correspond to carriers with lower absolute amplitude values. For carriers with absolute amplitude values ​​greater than 4, carriers closer to the horizontal axis are allocated to the arm with higher SOC, and the remaining carriers are allocated to the arm with lower SOC. This balancing strategy achieves energy balancing for all energy storage batteries in the converter.

[0031] Based on the same inventive concept, this application provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the aforementioned H-bridge low-frequency switching control method for a cascaded half-bridge converter.

[0032] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the aforementioned H-bridge low-frequency switching control method for a cascaded half-bridge converter.

[0033] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0034] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0035] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0036] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0037] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A low-frequency switching control method for an H-bridge of a cascaded half-bridge converter, wherein the DC input side of the cascaded half-bridge converter is composed of M battery packs connected in series, each battery pack consisting of... The system consists of several half-bridge submodules connected in series. Each half-bridge module adopts a half-bridge structure containing an independent energy storage battery and two switching transistors. M and All values ​​are integers not less than 2; the AC output side consists of M H-bridge inverter units connected in series on the AC side, with the number of H-bridge inverter units matching the number of battery packs. The DC input terminal of each H-bridge inverter unit is directly connected to the output terminal of the corresponding battery pack, and each H-bridge inverter unit independently bears the DC voltage of the corresponding battery pack; the total output AC voltage of the cascaded half-bridge converter is the sum of the AC voltages of all H-bridge inverter units, and an LC low-pass filter is connected after the AC output side to filter the voltage waveform on the AC output side into the required load voltage waveform; its characteristic is that... The control method includes: The DC input side employs a co-phase carrier stacked modulation strategy to generate control signals for the half-bridge submodule, thereby suppressing switching losses in the H-bridge inverter unit. The AC output side uses a phase control algorithm, through bridge arm grouping, power frequency square wave signal generation, and dynamic carrier reallocation, to limit the switching frequency of the H-bridge inverter unit to the power frequency. Simultaneously, the AC output side employs a voltage and current dual closed-loop control strategy to achieve output closed-loop control. Furthermore, a battery online energy balancing strategy based on SOC sorting is adopted to achieve dynamic energy balancing of the energy storage battery.

2. The H-bridge low-frequency switching control method for a cascaded half-bridge converter according to claim 1, characterized in that, The specific voltage and current dual closed-loop control strategy is as follows: The voltage and current dual closed-loop control strategy includes outer loop voltage control and inner loop current control. The outer loop voltage control uses a first quasi-proportional resonant controller, whose resonant frequency is the fundamental frequency. At the current moment, the difference between the externally provided reference voltage and the load voltage is detected, and the difference is used by the first quasi-proportional resonant controller to generate the given signal for the inner loop current. The inner loop current control uses a second quasi-proportional resonant controller. The given signal for the inner loop current is added to the load current, and then the difference is calculated with the inductor current of the LC low-pass filter. The difference is used by the second quasi-proportional resonant controller to generate the modulated wave signal for the current moment.

3. The H-bridge low-frequency switching control method for a cascaded half-bridge converter according to claim 2, characterized in that, The specific in-phase carrier stacked modulation strategy is as follows: Let N be the number of all half-bridge submodules on the DC input side. Provide 2N triangular carriers with the same phase and frequency to each of the N half-bridge submodules. The amplitudes of these 2N triangular carriers are arranged in a continuous, equally spaced layer within the interval [-N, N]. Each half-bridge submodule is assigned one positive and one negative triangular carrier. Initially, the control signal for each half-bridge submodule is generated by logically ORing the comparison result of its corresponding triangular carrier and the externally provided reference voltage. At other times, the control signal for each half-bridge submodule is generated by logically ORing the comparison result of its corresponding triangular carrier and the modulation wave generated by the voltage-current dual-loop control strategy from the previous time step. When the externally provided reference voltage v ref Or the modulation wave v generated by the voltage and current dual closed-loop control strategy at the previous moment. ref When v is positive, the modulation logic is positive logic, that is, when v is positive. ref When the voltage is greater than a certain triangular carrier wave, a control signal of "1" is generated, the upper transistor of the half-bridge submodule corresponding to the triangular carrier wave is turned on and the lower transistor is turned off, and the energy storage battery voltage is output; when v ref When the voltage is less than a certain triangular carrier wave, a control signal of "0" is generated. The upper transistor of the half-bridge submodule corresponding to the triangular carrier wave is turned off and the lower transistor is turned on, the half-bridge submodule is short-circuited, and the output is 0; when v ref When v is negative, the modulation logic is negative logic, that is, when v ref When the value is greater than a certain triangular carrier wave, a control signal of "0" is generated. ref When the signal is less than a certain triangular carrier wave, a control signal of "1" is generated.

4. The H-bridge low-frequency switching control method for a cascaded half-bridge converter according to claim 3, characterized in that, The phase control algorithm is as follows: The fundamental threshold is set to ±1. Initially, the input to the phase control algorithm is the externally provided reference voltage. At other times, the input is the modulated wave generated by the voltage-current dual-loop control strategy from the previous time step. The input to the phase control algorithm is scaled by a factor of 8 / U. max After normalization, the actual reference signal H for the phase control algorithm is obtained. ref H is determined through a phase-locked loop. ref The phase θ, the initial time U max The amplitude of the externally provided reference voltage, U at other times max The amplitude of the modulation wave generated by the voltage and current dual closed-loop control strategy at the previous moment; In a network of M H-bridge inverter units, at least one H-bridge inverter unit is defined as a leading arm, and at least one H-bridge inverter unit is defined as a lagging arm. The leading arm is defined as... ref The state transition occurs before the zero crossing from the negative half-cycle to the positive half-cycle, with the lagging bridge arm at H. ref The state transition occurs after the fundamental wave crosses zero from the positive half-cycle to the negative half-cycle. The phase at the zero-crossing point when the fundamental wave crosses the negative half-axis to the positive half-axis is taken as 0°. When the fundamental wave phase is in the range [-90°, 90°], triangular carrier waves in the amplitude ranges [-4, -3], [-3, -2], [0, 1], and [1, 2] are allocated to two half-bridge sub-modules of the battery pack corresponding to the advanced bridge arm. Triangular carrier waves in the amplitude ranges [-2, -1], [-1, 0], [2, 3], and [3, 4] are allocated to… Two half-bridge submodules of the battery pack corresponding to the lagging arm; when the fundamental phase is in [90°, 270°], triangular carriers in the amplitude range of [-2, -1], [-1, 0], [2, 3], [3, 4] are allocated to two half-bridge submodules of the battery pack corresponding to the leading arm, and triangular carriers in the amplitude range of [-4, -3], [-3, -2], [0, 1], [1, 2] are allocated to two half-bridge submodules of the battery pack corresponding to the lagging arm; When the phase θ satisfies -90°≤θ<90° and H ref >-V th Or when 90°≤θ< 270° and H ref >V th At that time, the advance arm control signal is at a high level; at other times, the advance arm control signal is at a low level. -V th V th These are the preset negative and positive voltage thresholds, V. th Take a constant of 1; when the phase θ satisfies 90°≤θ<270° and H ref >-V th Or when -90°≤θ<90° and H ref >V th At the specified time, the lagging arm control signal is at a high level; at other times, the lagging arm control signal is at a low level.

5. The H-bridge low-frequency switching control method for a cascaded half-bridge converter according to claim 4, characterized in that, The specific online energy balancing strategy for batteries based on SOC ranking is as follows: When the cascaded half-bridge converter is working normally, a preset equalization time interval is used. A battery online energy balancing strategy based on SOC sorting is executed periodically. At the balancing trigger time, the SOC parameters of all energy storage batteries in the battery pack corresponding to the leading arm and the SOC parameters of all energy storage batteries in the battery pack corresponding to the lagging arm are obtained. When the cascaded half-bridge converter is operating in the discharge state, triangular carriers located in the amplitude range of [-4,-3], [-3,-2], [0,1], [1,2] are assigned to the two half-bridge sub-modules with the highest SOC in the battery pack corresponding to the leading arm, and triangular carriers located in the amplitude range of [-2,-1], [-1,0], [2,3], [3,4] are assigned to the two half-bridge sub-modules with the highest SOC in the battery pack corresponding to the lagging arm. The SOC parameters of the remaining N-4 half-bridge sub-modules are sorted from high to low, and the remaining carriers are sorted from closest to furthest. The remaining carriers are assigned one-to-one with the remaining N-4 half-bridge sub-modules. The carrier closest to the horizontal axis among the remaining carriers is assigned to the half-bridge sub-module with the highest SOC, and the carrier furthest from the horizontal axis is assigned to the half-bridge sub-module with the lowest SOC. When the cascaded half-bridge converter is operating in the charging state, triangular carriers located in the amplitude range of [-4,-3], [-3,-2], [0,1], [1,2] are assigned to the two half-bridge sub-modules with the lowest SOC in the battery pack corresponding to the leading arm, and triangular carriers located in the amplitude range of [-2,-1], [-1,0], [2,3], [3,4] are assigned to the two half-bridge sub-modules with the lowest SOC in the battery pack corresponding to the lagging arm. The SOC parameters of the remaining N-4 half-bridge sub-modules are sorted from low to high, and the remaining carriers are sorted from closest to furthest. The remaining carriers are assigned one-to-one with the remaining N-4 half-bridge sub-modules. The carrier closest to the horizontal axis among the remaining carriers is assigned to the half-bridge sub-module with the lowest SOC, and the carrier furthest from the horizontal axis is assigned to the half-bridge sub-module with the highest SOC.

6. A computer device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the H-bridge low-frequency switching control method for the cascaded half-bridge converter as described in any one of claims 1 to 5.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the H-bridge low-frequency switching control method for the cascaded half-bridge converter as described in any one of claims 1 to 5.

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