A low voltage sample-and-hold circuit, a control method thereof, and a converter

Abstract

The embodiment of the application discloses a low-voltage sampling and holding circuit, a control method thereof and a converter, relates to the technical field of integrated circuit design, and the low-voltage sampling and holding circuit comprises a sub-threshold leakage suppression module, a double-gate voltage bootstrap module, a dynamic substrate biasing module, a core sampling tube, a pseudo switch tube and a clock control unit. The sub-threshold leakage suppression module comprises a charge redistribution capacitor, and is used for generating a negative voltage in a holding stage. The double-gate voltage bootstrap module is used for lifting the gate voltage of the core sampling tube in a sampling stage. The dynamic substrate biasing module is used for dynamically switching the substrate potential of the core sampling tube and key devices. The core sampling tube comprises a first short channel MOS tube and a second short channel MOS tube connected in series. The clock control unit is used for outputting a first clock signal and a second clock signal, and controlling the modules to work in cooperation in the sampling stage and the holding stage. The high linearity sampling and low leakage holding in the low-voltage scene are synergistically optimized.

Description

A low-voltage sample-and-hold circuit, its control method and converter Technical Field

[0001] This invention relates to the field of technology, and more particularly to a low-voltage sample-and-hold circuit, its control method, and a converter. Background Technology

[0002] In low-voltage, low-power successive approximation analog-to-digital converters (SAR ADCs), the sample-and-hold circuit, as a core front-end module, directly determines the conversion accuracy and power consumption. Traditional sample-and-hold circuits often use a single bootstrap capacitor to raise the gate voltage. Under low voltage conditions, insufficient gate-source drive voltage leads to high on-resistance and poor linearity. At the same time, during the hold phase, the sampling transistor is turned off only through zero level. Under extreme conditions such as FF process corners and 125°C high temperatures, the subthreshold leakage current is significant, and the leakage current suppression capability of a single long-channel sampling transistor is limited. In addition, charge injection and clock feedthrough effects when the sampling switch is turned off can easily introduce signal distortion. The lack of dynamic substrate bias can also exacerbate the substrate bias effect and parasitic leakage current, making it difficult to meet the application requirements of high accuracy, low leakage current, and wide operating conditions. Summary of the Invention

[0003] The technical problem to be solved by the embodiments of the present invention is the technical problem of insufficient gate voltage drive under low voltage and large subthreshold leakage current under extreme operating conditions in traditional low voltage sample-and-hold circuits.

[0004] To address the aforementioned problems, this invention discloses a low-voltage sample-and-hold circuit. This achieves coordinated optimization of high linearity sampling and low leakage current holding in low-voltage scenarios.

[0005] This invention provides a low-voltage sample-and-hold circuit, which includes a subthreshold leakage suppression module, including a charge redistribution capacitor C3, for generating a negative voltage during the hold phase;

[0006] A double gate voltage bootstrap module is used to boost the gate voltage of the core sampling transistor during the sampling phase; it includes a first bootstrap capacitor C1 and a second bootstrap capacitor C2, the lower plate of the first bootstrap capacitor C1 is connected to the input voltage, and the lower plate of the second bootstrap capacitor C2 is grounded.

[0007] The dynamic substrate bias module is used to dynamically switch the substrate potential of the core sampling tube and key devices.

[0008] The core sampling transistor includes a first short-channel MOSFET Ms1 and a second short-channel MOSFET Ms2 connected in series.

[0009] A pseudo-switching transistor is used to reverse the charge injection and clock feedthrough effects when the core sampling transistor is disconnected.

[0010] The clock control unit is used to output complementary first and second clock signals to control the modules to work together during the sampling and holding phases.

[0011] A further technical solution is that the switching timing of the pseudo-switching transistor is reversed and synchronized with that of the core sampling transistor.

[0012] A further technical solution is that the double gate voltage bootstrap module also includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6;

[0013] The source of the first MOS transistor M1 is connected to the power supply voltage, the drain is connected to the upper plate of the second bootstrap capacitor C2, and the gate is connected to the second clock signal.

[0014] The source of the second MOS transistor M2 is connected to the upper plate of the second bootstrap capacitor C2, the drain is grounded, and the gate is connected to the first clock signal.

[0015] The source of the third MOS transistor M3 is connected to the power supply voltage, the drain is connected to the upper plate of the first bootstrap capacitor C1, and the gate is connected to the second clock signal.

[0016] The source of the fourth MOS transistor M4 is connected to the upper plate of the first bootstrap capacitor C1, the drain is grounded, and the gate is connected to the first clock signal.

[0017] The source of the fifth MOS transistor M5 is connected to the lower plate of the second bootstrap capacitor C2, the drain is connected to the upper plate of the first bootstrap capacitor C1, and the gate is connected to the first clock signal.

[0018] The source of the sixth MOS transistor M6 is connected to the upper plate of the first bootstrap capacitor C1, and the drain is connected to the gate of the core sampling transistor. The gate is connected to the first clock signal.

[0019] A further technical solution is that the subthreshold leakage suppression module also includes an eighth MOS transistor M8, a ninth MOS transistor M9, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16;

[0020] The source of the eighth MOS transistor M8 is connected to the lower plate of the charge redistribution capacitor C3, the drain is grounded, and the gate is connected to the first clock signal.

[0021] The source of the ninth MOS transistor M9 is connected to the lower plate of the charge redistribution capacitor C3, and the drain is connected to the gate of the core sampling transistor. The gate is connected to the second clock signal.

[0022] The upper plate of the charge redistribution capacitor C3 is connected to the second clock signal CLKB;

[0023] The source of the fifteenth MOS transistor M15 is grounded, the drain is connected to the substrate of the core sampling transistor, and the gate is connected to the second clock signal.

[0024] The source of the sixteenth MOS transistor M16 is connected to the source of the first short-channel MOS transistor Ms1, the drain is connected to the substrate of the core sampling transistor, and the gate is connected to the first clock signal.

[0025] A further technical solution includes a gate drive buffer M10, the input terminal of which is connected to the drain of the sixth MOS transistor M6 and the drain of the ninth MOS transistor M9, and the output terminal is connected to the gate of the core sampling transistor.

[0026] A further technical solution is that the first short-channel MOS transistor Ms1 and the second short-channel MOS transistor Ms2 are high-voltage NMOS transistors fabricated using a 130nm CMOS process.

[0027] This invention also provides a control method for the low-voltage sample-and-hold circuit described in any of the embodiments, comprising the following steps:

[0028] The system receives a first clock signal and a second clock signal output by the clock control unit. The first clock signal and the second clock signal are complementary clock signals. When the first clock signal is high and the second clock signal is low, it is determined to be in the sampling phase. When the first clock signal is low and the second clock signal is high, it is determined to be in the holding phase.

[0029] When entering the sampling stage, the double gate voltage bootstrap module establishes a voltage difference between the power supply voltage and stores energy through the synergistic effect of the first bootstrap capacitor and the second bootstrap capacitor, raising the gate voltage of the core sampling tube to the sum of the input voltage and twice the power supply voltage, and the dynamic substrate bias module is shorted to the source.

[0030] During the holding phase, the double gate voltage bootstrap module resets the first bootstrap capacitor and the second bootstrap capacitor, maintaining the voltage difference between the two capacitor plates; the subthreshold leakage suppression module, based on the principle of charge conservation, generates a negative voltage through the charge redistribution capacitor and applies it to the gate of the core sampling tube, forcing the core sampling tube to be deeply turned off; and the dynamic substrate bias module is grounded.

[0031] This invention also provides a successive approximation analog-to-digital converter including a low-voltage sample-and-hold circuit as described in any of the above embodiments.

[0032] Compared with the prior art, the technical effects achieved by the embodiments of the present invention include:

[0033] The sampling tube gate voltage is raised to the sum of the input voltage and twice the supply voltage by a double gate voltage bootstrap module, improving low-voltage conduction linearity. Negative voltage turn-off combined with dual short-channel sampling tubes in series significantly suppresses leakage current under extreme conditions of FF process and 125℃. Signal distortion is reduced by reverse compensation charge injection and clock feedthrough through pseudo-switching tubes. The dynamic substrate bias module switches the substrate potential in stages to eliminate substrate bias effect and block parasitic leakage paths, ultimately adapting the circuit to low-voltage, low-power SAR ADC, maintaining high accuracy and low leakage characteristics over a wide process angle and temperature range. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 is a schematic diagram of a low-voltage sample-and-hold circuit provided in an embodiment of the present invention;

[0036] Figure 2 is a flowchart of a control method for a low-voltage sample-and-hold circuit provided in an embodiment of the present invention;

[0037] Figure 3 is a state diagram of the sampling stage of a low-voltage sample-and-hold circuit provided in an embodiment of the present invention;

[0038] Figure 4 is a state diagram of the holding stage of a low-voltage sample-and-hold circuit provided in an embodiment of the present invention;

[0039] Figure 5 is a schematic diagram of a successive approximation analog-to-digital converter structure provided in an embodiment of the present invention. Detailed Implementation

[0040] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Similar component reference numerals in the drawings represent similar components. Obviously, the embodiments described below are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0041] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0042] It should also be understood that the terminology used in this specification of embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of the invention. As used in this specification of embodiments of the invention and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0043] Referring to Figure 1, this embodiment of the invention provides a low-voltage sample-and-hold circuit. This low-voltage sample-and-hold circuit includes a subthreshold leakage suppression module, comprising a charge redistribution capacitor C3 for generating a negative voltage during the hold phase; a double gate voltage bootstrap module for raising the gate voltage of the core sampling transistor during the sampling phase; a first bootstrap capacitor C1 and a second bootstrap capacitor C2, with the lower plate of the first bootstrap capacitor C1 connected to the input voltage and the lower plate of the second bootstrap capacitor C2 grounded; a dynamic substrate bias module for dynamically switching the substrate potential of the core sampling transistor and key devices; a core sampling transistor, comprising a first short-channel MOSFET Ms1 and a second short-channel MOSFET Ms2 connected in series; a pseudo-switching transistor for reverse compensation of charge injection and clock feedthrough effects when the core sampling transistor is disconnected; and a clock control unit for outputting complementary first and second clock signals to control the coordinated operation of each module during the sampling and hold phases. Specific descriptions of each component are as follows:

[0044] In this embodiment, the subthreshold leakage suppression module is a circuit module that generates a negative voltage based on the principle of charge conservation to deeply turn off the sampling transistor and suppress the leakage current in the subthreshold region of the MOS transistor; the double gate voltage bootstrap module is a bootstrap boost module that uses cascaded dual bootstrap capacitors to store energy and raise the gate voltage of the sampling transistor to the sum of the input voltage and twice the power supply voltage; the dynamic substrate bias module is a module that dynamically switches the substrate potential of the MOS transistor according to the sampling / holding phase to eliminate the substrate bias effect and suppress parasitic leakage current; the core sampling transistor is composed of two short-channel MOS transistors connected in series and is a switching device that performs signal sampling and holding switching; the pseudo-switching transistor is synchronized with the core sampling transistor in reverse timing and is used as an auxiliary switching device to compensate for the non-ideal effects of charge injection and clock feedthrough.

[0045] In this embodiment, the low-voltage sample-and-hold circuit integrates three major functional modules: subthreshold leakage suppression, double gate voltage bootstrapping, and dynamic substrate biasing, and is equipped with a dual short-channel core sampling transistor and a pseudo-switching transistor. The lower plate of the first bootstrapping capacitor C1 is connected to the input voltage, the lower plate of the second bootstrapping capacitor C2 is grounded, and the clock control unit outputs a complementary clock signal to coordinate the working state of each module during the sampling and holding phases. Each module forms a closed-loop collaborative path with the clock control through potential connection.

[0046] Referring again to Figure 1, in this embodiment, the switching timing of the pseudo-switch transistor is reversed and synchronized with that of the core sampling transistor.

[0047] Specifically, the on / off state of the dummy switch is completely opposite to that of the core sampling transistor. When the core sampling transistor is on, the dummy switch is off, and when the core sampling transistor is off, the dummy switch is on. The gate of the dummy switch is controlled by a clock signal complementary to that of the core sampling transistor. During the sampling phase, the core sampling transistor is on and the dummy switch is off, without interfering with signal transmission. During the hold phase, the core sampling transistor is off and the dummy switch is on, generating reverse charge to cancel out the charge injection and clock feedthrough of the core sampling transistor.

[0048] Real-time reverse compensation for non-ideal effects can be achieved without additional control circuitry. Sampling distortion can be reduced and output signal accuracy improved simply through timing synchronization.

[0049] Furthermore, the double gate voltage bootstrap module also includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6; the source of the first MOSFET M1 is connected to the power supply voltage, the drain is connected to the upper plate of the second bootstrap capacitor C2, and the gate is connected to the second clock signal; the source of the second MOSFET M2 is connected to the upper plate of the second bootstrap capacitor C2, the drain is grounded, and the gate is connected to the first clock signal; the source of the third MOSFET M3 is connected to the power supply voltage, and the drain is... The source of the fourth MOS transistor M4 is connected to the upper plate of the first bootstrap capacitor C1, the drain is grounded, and the gate is connected to the first clock signal; the source of the fifth MOS transistor M5 is connected to the lower plate of the second bootstrap capacitor C2, the drain is connected to the upper plate of the first bootstrap capacitor C1, and the gate is connected to the first clock signal; the source of the sixth MOS transistor M6 is connected to the upper plate of the first bootstrap capacitor C1, the drain is connected to the gate of the core sampling transistor, and the gate is connected to the first clock signal.

[0050] Specifically, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 are bootstrap capacitor reset / charge control MOSFETs, which are controlled by complementary clock to realize capacitor plate potential switching; the fifth MOSFET M5 and the sixth MOSFET M6 are bootstrap capacitor cascade and gate voltage transfer MOSFETs, which establish a dual capacitor cascade path when turned on to transfer the boosted voltage to the gate of the core sampling transistor.

[0051] The gates of the first MOSFET M1 and the third MOSFET M3 are connected to the second clock signal, and the gates of the second MOSFET M2 and the fourth MOSFET M4 are connected to the first clock signal. During the sampling phase, the first MOSFET M1 and the third MOSFET M3 are turned on, and the second MOSFET M2 and the fourth MOSFET M4 are turned off, so as to charge the first bootstrap capacitor C1 and the second bootstrap capacitor C2 and establish the VDD voltage difference. During the holding phase, the first MOSFET M1 and the third MOSFET M3 are turned off, and the second MOSFET M2 and the fourth MOSFET M4 are turned on, so as to complete the capacitor reset.

[0052] The gates of the fifth MOSFET M5 and the sixth MOSFET M6 are connected to the first clock signal and are turned on during the sampling phase, realizing the cascaded potential coupling of the first bootstrap capacitor C1 and the second bootstrap capacitor C2, and transmitting double the bootstrap voltage to the gate of the core sampling transistor.

[0053] Furthermore, the subthreshold leakage suppression module also includes an eighth MOS transistor M8, a ninth MOS transistor M9, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16; the source of the eighth MOS transistor M8 is connected to the lower plate of the charge redistribution capacitor C3, the drain is grounded, and the gate is connected to the first clock signal; the source of the ninth MOS transistor M9 is connected to the lower plate of the charge redistribution capacitor C3, the drain is connected to the gate of the core sampling transistor, and the gate is connected to the second clock signal; the upper plate of the charge redistribution capacitor C3 is connected to the second clock signal CLKB; the source of the fifteenth MOS transistor M15 is grounded, the drain is connected to the substrate of the core sampling transistor, and the gate is connected to the second clock signal; the source of the sixteenth MOS transistor M16 is connected to the source of the first short-channel MOS transistor Ms1, the drain is connected to the substrate of the core sampling transistor, and the gate is connected to the first clock signal.

[0054] Specifically, the eighth MOSFET M8 and the ninth MOSFET M9 are the control switches for the charge redistribution capacitor C3, responsible for generating and transmitting negative voltage to the gate of the sampling transistor; the fifteenth MOSFET M15 and the sixteenth MOSFET M16 are the substrate potential switching switches, controlling the sampling transistor substrate to ground and substrate and source short-circuited states, respectively.

[0055] The gate of the eighth MOSFET M8 is connected to the first clock. During the sampling phase, it is turned on to ground the lower plate of the charge redistribution capacitor C3 to store energy. The gate of the ninth MOSFET M9 is connected to the second clock. During the hold phase, it is turned on to transfer the negative voltage generated by the charge redistribution capacitor C3 to the gate of the core sampling transistor. The upper plate of the charge redistribution capacitor C3 is connected to the second clock. When the clock changes, a negative voltage is generated through charge conservation.

[0056] The gate of the fifteenth MOSFET M15 is connected to the second clock, and the gate of the sixteenth MOSFET M16 is connected to the first clock. During the sampling phase, the sixteenth MOSFET M16 is turned on and the fifteenth MOSFET M15 is turned off, and the substrate is shorted to the source of the first short-channel MOSFET Ms1. During the holding phase, the fifteenth MOSFET M15 is turned on and the sixteenth MOSFET M16 is turned off, and the substrate is grounded.

[0057] Furthermore, it also includes a gate drive buffer M10, the input terminal of which is connected to the drain of the sixth MOS transistor M6 and the drain of the ninth MOS transistor M9, and the output terminal is connected to the gate of the core sampling transistor.

[0058] Specifically, the gate drive buffer M10 is a buffer device used to enhance the gate voltage drive capability and reduce signal attenuation and timing delay.

[0059] The input terminal of the gate drive buffer M10 is connected to the drain of the sixth MOS transistor M6 and the drain of the ninth MOS transistor M9 to receive the bootstrap high voltage and negative voltage. The output terminal is directly connected to the gate of the core sampling transistor to amplify the gate voltage signal and shape the waveform.

[0060] Improve the gate voltage response speed, avoid gate voltage attenuation caused by long traces or parasitic capacitance, and ensure the timeliness and stability of the sampling tube's on / off state.

[0061] Furthermore, the first short-channel MOS transistor Ms1 and the second short-channel MOS transistor Ms2 are high-voltage NMOS transistors fabricated using a 130nm CMOS process.

[0062] Specifically, based on 130nm CMOS process, the N-type metal-oxide-semiconductor field-effect transistor has a gate oxide layer and drain-source terminals that can withstand voltage stresses higher than those of conventional devices.

[0063] Both the first short-channel MOSFET Ms1 and the second short-channel MOSFET Ms2 are NMOS transistors manufactured using this process. They can withstand the gate voltage of Vin+2VDD during the sampling phase and the negative voltage of -VDD during the holding phase, thus meeting the voltage stress requirements of double bootstrapping and negative voltage turn-off.

[0064] Referring to Figure 2, this embodiment of the invention also provides a control method applied to the low-voltage sample-and-hold circuit described in any of the embodiments, including steps S101-S103:

[0065] S101, receive the first clock signal and the second clock signal output by the clock control unit. The first clock signal and the second clock signal are complementary clock signals. When the first clock signal is high and the second clock signal is low, it is determined to be the sampling stage; when the first clock signal is low and the second clock signal is high, it is determined to be the holding stage.

[0066] S102, when entering the sampling stage, the double gate voltage bootstrap module establishes a voltage difference between the power supply voltage and stores energy through the synergistic effect of the first bootstrap capacitor and the second bootstrap capacitor, raising the gate voltage of the core sampling tube to the sum of the input voltage and twice the power supply voltage, and the dynamic substrate bias module is shorted to the source.

[0067] S103, when entering the holding phase, the double gate voltage bootstrap module resets the first bootstrap capacitor and the second bootstrap capacitor, and maintains the voltage difference of the power supply voltage between the two capacitor plates; the subthreshold leakage suppression module generates a negative voltage through the charge redistribution capacitor based on the principle of charge conservation and applies it to the gate of the core sampling tube, forcing the core sampling tube to be deeply turned off, and the dynamic substrate bias module is grounded.

[0068] Specifically, the circuit receives first and second clock signals. A high-level first clock plus a low-level second clock constitutes the sampling phase, while a low-level first clock plus a high-level second clock constitutes the hold phase. During the sampling phase, dual capacitors store energy to raise the gate voltage, and the substrate and source are shorted. During the hold phase, the capacitors are reset, a negative voltage turns off the sampling transistor, and the substrate is grounded. Complementary clocks enable full module coordination, eliminating the need for complex timing control and reducing circuit power consumption and design complexity.

[0069] Furthermore, in step S103, the process of generating the negative voltage is as follows:

[0070] The upper plate of the charge redistribution capacitor goes low with the second clock signal. Based on the principle of charge conservation, the voltage of the lower plate of the charge redistribution capacitor drops synchronously from ground potential by a power supply voltage to obtain the negative voltage.

[0071] Specifically, during the second phase, when the clock goes low, the potential of the upper plate of C3 drops sharply. Due to charge conservation, the potential of the lower plate synchronously drops from ground potential by one power supply voltage, generating a negative voltage -VDD. The negative voltage generation mechanism is purely passive and low-power, requiring no external auxiliary power supply. The negative voltage output is stable under extreme process angles and temperature ranges, and the leakage current suppression effect is reliable.

[0072] Furthermore, the operating logic of the dynamic substrate bias module is as follows:

[0073] Sampling phase: The sixteenth MOS transistor M16 is turned on, the fifteenth MOS transistor M15 is turned off, and the substrate of the core sampling transistor is shorted to the source of the first short-channel MOS transistor Ms1.

[0074] Hold phase: The fifteenth MOS transistor M15 is turned on, the sixteenth MOS transistor M16 is turned off, and the substrate of the core sampling transistor is grounded.

[0075] Specifically, during the sampling phase, the sixteenth MOSFET M16 is turned on and the fifteenth MOSFET M15 is turned off. The substrate of the core sampling transistor is at the same potential as the source of the first short-channel MOSFET Ms1, eliminating the threshold voltage drift caused by substrate bias. During the holding phase, the fifteenth MOSFET M15 is turned on and the sixteenth MOSFET M16 is turned off. The substrate is grounded, blocking the parasitic PN junction reverse bias leakage path.

[0076] The solution addresses the bias effect and parasitic leakage in stages, while balancing sampling linearity with low leakage characteristics during the hold phase.

[0077] Referring to Figure 3, Figure 3 is a state diagram of the sampling stage of a low-voltage sample-and-hold circuit provided in an embodiment of the present invention. During the sampling stage, CLKS is at a high level and CLKB is at a low level. At this time, the first MOSFET M1 to the fourth MOSFET M4 are turned off, and the power supply voltage VDD charges the first bootstrap capacitor C1 and the second bootstrap capacitor C2 through the internal branch, so that a voltage difference of VDD is established between the plates of the first bootstrap capacitor C1 and the second bootstrap capacitor C2. At the same time, the fifth MOSFET M5 and the sixth MOSFET M6 are turned on, and the initial value of the gate voltage Vgate of the first short-channel MOSFET Ms1 and the second short-channel MOSFET Ms2 reaches 2VDD, driving the seventh MOSFET M7 to turn on. Subsequently, the input signal Vin is applied to the first bootstrap capacitor through the turned-on seventh MOSFET M7. According to the principle of charge conservation, the upper plate potential of the first bootstrap capacitor C1 changes synchronously with Vin, causing the gate voltage Vgate of the first short-channel MOSFETs Ms1 and Ms2 to be further raised to Vin + 2VDD. At this time, the gate-source voltage VGS of the core sampling transistor is Vin + 2VDD - Vin = 2VDD, achieving double gate voltage bootstrapping, which greatly improves the conduction linearity of the core sampling transistor and enhances the tolerance to the setup error of the DAC capacitor array. During this stage, the eighth MOSFET M8 is turned on, pulling the lower plate of the charge redistribution capacitor C3 down to ground potential VSS, preparing for the generation of the negative voltage during the stage.

[0078] Referring to Figure 4, Figure 4 is a state diagram of the holding stage of a low-voltage sample-and-hold circuit provided in an embodiment of the present invention. During the hold phase, the clock control unit outputs CLKS as low and CLKB as high. The upper plate of the charge redistribution capacitor C3 becomes low along with CLKB. Based on the principle of charge conservation, the charge on the plate of the charge redistribution capacitor C3 remains unchanged, and the voltage of the lower plate synchronously drops by one power supply voltage VDD, from ground potential VSS to -VDD. At this time, the ninth MOSFET M9 is turned on, transmitting the -VDD negative voltage to the gate of the core sampling transistor, forcing the core sampling transistor to be deeply turned off, effectively suppressing subthreshold leakage. At the same time, the reset switches of the first MOSFET M1 to the fourth MOSFET M4 are turned on, charging the upper plates of the first bootstrap capacitor C1 and the second bootstrap capacitor C2 to VDD, and pulling down the lower plates of the first bootstrap capacitor C1 and the second bootstrap capacitor C2 to ground potential VSS, so that the voltage difference between the plates of the first bootstrap capacitor C1 and the second bootstrap capacitor C2 is maintained at VDD, preparing for the next sampling phase.

[0079] Referring to Figure 5, an embodiment of the present invention also provides a successive approximation analog-to-digital converter including a low-voltage sample-and-hold circuit as described in any of the above embodiments.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0081] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0082] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0083] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0084] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0085] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0086] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0087] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A low-voltage sample-and-hold circuit, characterized in that, include: The subthreshold leakage suppression module includes a charge redistribution capacitor C3 for generating a negative voltage during the holding phase; A double gate voltage bootstrap module is used to boost the gate voltage of the core sampling transistor during the sampling phase; it includes a first bootstrap capacitor C1 and a second bootstrap capacitor C2, the lower plate of the first bootstrap capacitor C1 is connected to the input voltage, and the lower plate of the second bootstrap capacitor C2 is grounded; a dynamic substrate bias module is used to dynamically switch the substrate potential of the core sampling transistor and key devices. The core sampling transistor includes a first short-channel MOSFET Ms1 and a second short-channel MOSFET Ms2 connected in series; a pseudo-switching transistor is used to reverse compensate for the charge injection and clock feedthrough effects when the core sampling transistor is disconnected; a clock control unit is used to output complementary first and second clock signals to control the coordinated operation of each module during the sampling and holding phases; the double gate voltage bootstrap module also includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, and a sixth MOSFET M6; the first MOSFET... The source of MOSFET M1 is connected to the power supply voltage, the drain is connected to the upper plate of the second bootstrap capacitor C2, and the gate is connected to the second clock signal; the source of the second MOSFET M2 is connected to the upper plate of the second bootstrap capacitor C2, the drain is grounded, and the gate is connected to the first clock signal; the source of the third MOSFET M3 is connected to the power supply voltage, the drain is connected to the upper plate of the first bootstrap capacitor C1, and the gate is connected to the second clock signal; the source of the fourth MOSFET M4 is connected to the upper plate of the first bootstrap capacitor C1, the drain is grounded, and the gate is connected to the first clock signal; the source of the fifth MOSFET M5... The lower plate of the second bootstrap capacitor C2 is connected to the second bootstrap capacitor C2, the drain is connected to the upper plate of the first bootstrap capacitor C1, and the gate is connected to the first clock signal; the source of the sixth MOS transistor M6 is connected to the upper plate of the first bootstrap capacitor C1, the drain is connected to the gate of the core sampling transistor, and the gate is connected to the first clock signal; the subthreshold leakage suppression module also includes an eighth MOS transistor M8, a ninth MOS transistor M9, a fifteenth MOS transistor M15, and a sixteenth MOS transistor M16; the source of the eighth MOS transistor M8 is connected to the lower plate of the charge redistribution capacitor C3, the drain is grounded, and the gate is connected to the upper plate of the first bootstrap capacitor C1. A clock signal is provided; the source of the ninth MOS transistor M9 is connected to the lower plate of the charge redistribution capacitor C3, the drain is connected to the gate of the core sampling transistor, and the gate is connected to the second clock signal; the upper plate of the charge redistribution capacitor C3 is connected to the second clock signal CLKB; the source of the fifteenth MOS transistor M15 is grounded, the drain is connected to the substrate of the core sampling transistor, and the gate is connected to the second clock signal; the source of the sixteenth MOS transistor M16 is connected to the source of the first short-channel MOS transistor Ms1, the drain is connected to the substrate of the core sampling transistor, and the gate is connected to the first clock signal.

2. The low-voltage sample-and-hold circuit according to claim 1, characterized in that, The switching timing of the pseudo-switching transistor is reversed and synchronized with that of the core sampling transistor.

3. The low-voltage sample-and-hold circuit according to claim 1, characterized in that, It also includes a gate drive buffer M10, the input terminal of which is connected to the drain of the sixth MOS transistor M6 and the drain of the ninth MOS transistor M9, and the output terminal is connected to the gate of the core sampling transistor.

4. The low-voltage sample-and-hold circuit according to claim 1, characterized in that, The first short-channel MOS transistor Ms1 and the second short-channel MOS transistor Ms2 are high-voltage NMOS transistors fabricated using a 130nm CMOS process.

5. A control method applied to the low-voltage sample-and-hold circuit according to any one of claims 1-4, characterized in that, The method includes: receiving a first clock signal and a second clock signal output by a clock control unit, wherein the first clock signal and the second clock signal are complementary clock signals; when the first clock signal is high and the second clock signal is low, it is determined to be a sampling phase; when the first clock signal is low and the second clock signal is high, it is determined to be a holding phase; when entering the sampling phase, the double gate voltage bootstrap module establishes a voltage difference between the power supply voltage and stores energy between the two capacitor plates through the synergistic effect of the first bootstrap capacitor and the second bootstrap capacitor, raising the gate voltage of the core sampling tube to the sum of the input voltage and twice the power supply voltage, and the dynamic substrate bias module is short-circuited with the source; when entering the holding phase, the double gate voltage bootstrap module resets the first bootstrap capacitor and the second bootstrap capacitor, and maintains the voltage difference between the two capacitor plates; the subthreshold leakage suppression module generates a negative voltage through the charge redistribution capacitor based on the principle of charge conservation and applies it to the gate of the core sampling tube, forcing the core sampling tube to be deeply turned off, and the dynamic substrate bias module is grounded.

6. The control method for the low-voltage sample-and-hold circuit according to claim 5, characterized in that, During the holding phase, the negative voltage is generated as follows: the upper plate of the charge redistribution capacitor goes low with the second clock signal, and based on the principle of charge conservation, the voltage of the lower plate of the charge redistribution capacitor drops synchronously from the ground potential by a power supply voltage to obtain the negative voltage.

7. The control method for the low-voltage sample-and-hold circuit according to claim 5, characterized in that, The working logic of the dynamic substrate bias module is as follows: Sampling stage: the sixteenth MOS transistor M16 is turned on and the fifteenth MOS transistor M15 is turned off, and the substrate of the core sampling transistor is shorted to the source of the first short-channel MOS transistor Ms1; Hold stage: the fifteenth MOS transistor M15 is turned on and the sixteenth MOS transistor M16 is turned off, and the substrate of the core sampling transistor is grounded.

8. A successive approximation analog-to-digital converter, characterized in that, Includes the low-voltage sample-and-hold circuit as described in any one of claims 1-4.

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