Heterogeneous memory stack
By employing a hierarchical memory stacking scheme, which combines multi-layer memory dies with single-layer surface bonding, the issue of TSV area occupancy is resolved, thereby improving memory density and connectivity, making it suitable for high-bandwidth computing systems.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-04-07
AI Technical Summary
In existing memory stacking architectures, the TSV region occupies memory cell area, resulting in wasted die space and affecting area utilization and connectivity.
A hierarchical memory stacking scheme is adopted, which combines multi-layer memory dies with single-layer memory dies and achieves vertical interconnection through through-silicon vias and surface bonding, thereby expanding memory capacity and increasing connection density.
It maximizes memory density and reduces signal transmission latency, making it suitable for high-bandwidth computing applications, especially artificial intelligence accelerators and high-performance computing platforms.
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Figure CN121815658A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to semiconductor memory, and more particularly to a three-dimensional heterogeneous stacking scheme for stacking multi-layer memory dies on top of single-layer memory dies. BACKGROUND
[0002] Modern computing systems require increasingly more powerful memory architectures to keep pace with the rapid development of processor speeds and data-intensive applications. Technologies such as high-bandwidth memory (HBM) and 3D-stacked dynamic random access memory (DRAM) utilize vertical integration techniques to increase memory bandwidth and capacity, making them a good solution. These architectures utilize through-silicon via (TSV) to enable inter-die connections, thereby reducing data transfer bottlenecks.
[0003] However, memory stacking architectures based on TSV technology require a TSV area within each memory die to ensure space for vertical interconnects. This TSV area is necessary to accommodate the through-silicon vias for inter-layer connections, but its presence introduces significant design constraints that affect die area utilization. Specifically, the TSV area occupies area that could otherwise be used for layout of memory cells, resulting in wasted die space.
[0004] Accordingly, there is a need in the art for an improved stacked memory device architecture that maximizes memory density while enhancing inter-die connectivity. SUMMARY
[0005] Accordingly, it is an object of the present invention to provide a hierarchical memory stacking scheme that utilizes multi-layer memory dies to expand capacity while reserving a single-layer memory die for high-density surface bonding, thereby enabling good performance in high-bandwidth computing applications.
[0006] Embodiments of the present invention provide a stacked memory device including a first memory die and a second memory die. The first memory die has a multi-layer structure, each layer including at least a memory cell region and a through-silicon via region, wherein the first memory die is electrically connected to an integrated circuit device through a plurality of vertical interconnects in the through-silicon via regions. The second memory die is disposed between the first memory die and the integrated circuit device, has a single-layer structure, and includes at least a memory cell region and a through-silicon via region, wherein the second memory die is electrically connected to the integrated circuit device through a surface bond. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 A cross-sectional view of a stacked memory device of an embodiment of the present invention is shown.
[0008] Figure 2 A plan layout of one of the layers of the first memory die in a stacked memory device of an embodiment of the present invention is shown.
[0009] Figure 3 A plan layout of the second memory die in a stacked memory device of an embodiment of the present invention is shown.
[0010] REFERENCE NUMERALS
[0011] 10 stacked memory device
[0012] 110 first memory die
[0013] 111, 121 memory cell region
[0014] 112, 122 TSV region
[0015] 113, 123 first circuit region
[0016] 114, 124 second circuit region
[0017] 115 TSV interconnect
[0018] 120 second memory die
[0019] 125 surface bond
[0020] 130 integrated circuit device
[0021] 140 substrate
[0022] LS1-LS4 layer DETAILED DESCRIPTION
[0023] Numerous specific details are described below to provide the reader with a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate how the invention can be implemented in the absence of one or more specific details, or by utilizing other methods, elements, or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the core concepts of the invention.
[0024] The phrase "in one embodiment" in this specification means that a particular feature, structure, or characteristic described in that embodiment may be included in at least one embodiment of the invention. Therefore, the phrase "in one embodiment" appearing throughout this specification does not necessarily mean the same embodiment. Furthermore, the aforementioned particular features, structures, or characteristics may be combined in any suitable form in one or more embodiments.
[0025] Please see Figure 1 The figure illustrates a cross-sectional view of a stacked memory device according to an embodiment of the present invention. In various embodiments of the present invention, the stacked memory device can be implemented in different memory architectures, including but not limited to high-bandwidth memory (HBM) architectures. As shown, the stacked memory device 10 is vertically stacked on top of the integrated circuit device 130 and provides vertical interconnects through through-silicon via (TSV) structures and surface bonding.
[0026] In some embodiments, the integrated circuit device 130 can be implemented as a logic die, including but not limited to a central processing unit (CPU) for general computing applications, a graphics processing unit (GPU) for high performance computing and / or AI applications, a neural processing unit (NPU) for AI inference or training purposes, a field-programmable gate array (FPGA), or a special application integrated circuit (ASIC). In other embodiments, the integrated circuit device 130 can be a memory-related controller, a physical layer (PHY) control unit, or a HBM logic die. Furthermore, the integrated circuit device 130 can be a high-speed interface controller, or a part of a heterogeneous multi-chip module (MCM) or a three-dimensional integrated circuit architecture. Still further, the integrated circuit device 130 can be implemented as a system on chip (SoC) that is electrically connected to the substrate 140 through solder bumps.
[0027] The stacked memory device 10 includes a first memory die 110 and a second memory die 120, each of which can be a semiconductor chip (cut from a wafer). The first memory die 110 has a multi-layer structure including a plurality of layers LS1-LS4 stacked on the second memory die 120. Note that although four layers LS1-LS4 of the first memory die 110 are illustrated in the embodiment, this is not a limitation of the present application. In various embodiments of the present application, fewer or more layers can be included in the multi-layer structure of the first memory die 110, depending on design requirements. Figure 1
[0028] Each of the layers LSI-LS4 is electrically connected to the integrated circuit device 130 through a plurality of vertical interconnects 115 within the TSV region. As used herein, the term "vertical interconnect" refers to an electrically conductive path extending through a semiconductor die, including a TSV formed of a conductive fill material. The vertical interconnects 115 extend through the layers LSI-LS4 of the first memory die 110, providing signal transmission paths between different layers and the integrated circuit device 130. Each of the layers LSI-LS4 of the first memory die 110 can include circuitry electrically connected to the vertical interconnects 115. In some embodiments, the vertical interconnects 115 can not penetrate the TSV region of the topmost layer (e.g., layer LSI) of the first memory die 110.
[0029] Referring to FIG. 1, a three-dimensional memory device 100 includes a first memory die 110 and a second memory die 120. The first memory die 110 includes a plurality of layers LSI-LS4 of memory cells, and the second memory die 120 includes a plurality of layers LSI'-LS4' of memory cells. The first memory die 110 is electrically connected to the second memory die 120 through a plurality of vertical interconnects 115 within a TSV region of the first memory die 110. The vertical interconnects 115 extend through the layers LSI-LS4 of the first memory die 110, providing signal transmission paths between different layers and the second memory die 120. Figure 2 Figure 1 Figure 2 A floorplan diagram of a portion of the layers LSI-LS4 of the first memory die 110 is shown. As shown, each layer of the first memory die 110 includes a memory cell region 111 and a TSV region 112. The memory cell region 111 includes an array of memory cells, and the TSV region 112 has a hole filled with a conductive material extending therethrough, forming a vertical interconnect 115 between different layers and the integrated circuit device 130. Each layer of the first memory die 110 further includes a first circuit region 113 and a second circuit region 114. The first circuit region 113 can include peripheral circuitry for input / output operations, as well as management of control / data signals. The second circuit region 114 can include decoder circuitry for addressing and accessing memory cells within the memory cell region 111. In some embodiments, the peripheral circuitry of the first circuit region 113 of each layer LSI-LS4 can be electrically connected directly to the integrated circuit device 130, or to the peripheral circuitry of the first circuit region 113 of one of the other layers LSI-LS4, enabling signal transmission between different layers before the signals reach the integrated circuit device 130.
[0030] The second memory die 120 has a single layer structure and is electrically connected to the integrated circuit device 130 by surface bonding 125, which can enable direct electrical interconnection across the entire active area of the second memory die 120. As used herein, the term "surface bonding" refers to a bonding technique that enables direct electrical interconnection between semiconductor dies without the use of solder balls. Surface bonding techniques can include hybrid bonding, oxide bonding, and direct metal bonding, such as Cu-Cu bonding.
[0031] Please also refer to Figure 3 and Figure 1 . Figure 3 A plan view of the second memory die 120 is shown. As shown, the second memory die 120 includes a memory cell region 121 and a TSV region 122. The memory cell region 121 includes an array of memory cells. The TSV region 122 includes vertical interconnects 115 that are vertically aligned with the TSV region 112 of the first memory die 110, thereby enabling signal routing between different layers and the integrated circuit device 130. Further, a first circuit region 123 of the second memory die 120 can include peripheral circuitry for input / output operations, as well as control / data signal management. A second circuit region 124 can include decoder circuitry for addressing and accessing memory cells within the memory cell region 121.
[0032] Although Figures 1 to 3 While the first memory die 110 and the second memory die 120 are shown to have the same die size, in other embodiments of the present application, the die sizes of the first memory die 110 and the second memory die 120 can be different. Further, while the TSV regions 112 of each layer LSI-LS4 in the first memory die 110 are vertically aligned with the TSV region 122 of the second memory die 120 to ensure electrical connection through the vertical interconnects 115 that extend to the integrated circuit device 130, the exact size of the TSV regions 112 in each layer LSI-LS4 need not match (may be larger or smaller) the size of the TSV region 122 in the second memory die 120. Further, the TSV regions 112 in different layers LSI-LS4 of the first memory die 110 can also differ in size.
[0033] As Figure 1 and Figure 3As shown, the entire active area of the second memory die 120 is used to implement surface bonding, which can provide a larger interconnect area compared to the TSV region 112 of the first memory die 110 (and the TSV region 122 of the second memory die 120). This enables a higher density of control and data signal paths between the second memory die 120 and the integrated circuit device 130.
[0034] In some embodiments, one or more vertical interconnects 115 from the first memory die 110 can form an intermediate branching structure to electrically connect to the second memory die 120, thereby enabling a selective communication path between the first memory die 110 and the second memory die 120. Further, control circuitry or buffer circuitry within one or more layers of the first memory die 110 can selectively interface with corresponding control or buffer circuitry in the second memory die 120.
[0035] In summary, the stacked memory device of the present application implements a hierarchical architecture that utilizes multiple layers of memory dies to scale memory capacity while reserving a single layer of memory die for surface bonding to enable high-density interconnects for control and data signal paths to improve memory bandwidth. By utilizing a first memory die with multiple stacked layers (e.g., LSI-LS4), the stacked memory device maximizes storage density. By surface bonding a second memory die, significantly larger interconnect areas can be provided compared to conventional TSV-based vertical interconnects. This architecture not only increases the number of available signal paths, but also mitigates signal transmission delays by reducing reliance on TSVs. Overall, the stacked memory device architecture of the present application significantly improves memory scalability, bandwidth efficiency, and interconnect density, making it well-suited for next-generation computing systems that require ultra-high memory throughput and low-latency data access, such as artificial intelligence accelerators, high-performance computing platforms, and advanced system-on-chip designs.
[0036] The above descriptions are only the preferred embodiment of the application, and all equivalent changes and modifications made within the scope of the application should be covered by the present application.
Claims
1. A stacked memory device, characterized in that, include: A first memory die has a multilayer structure, each layer including at least one memory cell region and a through-silicon via region, wherein the first memory die is electrically connected to an integrated circuit device through a plurality of vertical interconnects within the through-silicon via region; as well as A second memory die is disposed between the first memory die and the integrated circuit device, and has a single-layer structure. The second memory die includes at least one memory cell region and one through-silicon via region, wherein the second memory die is electrically connected to the integrated circuit device through surface bonding.
2. The stacked memory device as claimed in claim 1, characterized in that, Each layer of the first memory die further includes a first circuit region and a second circuit region; the memory cell region includes a memory cell array, the first circuit region of each layer of the first memory die includes peripheral circuits, and the second circuit region of each layer of the first memory die includes decoder circuits.
3. The stacked memory device as claimed in claim 1, characterized in that, The second memory die further includes a first circuit region and a second circuit region; the memory cell region includes a memory cell array, the first circuit region of the second memory die includes peripheral circuits, and the second circuit region of the second memory die includes decoder circuits.
4. The stacked memory device as claimed in claim 1, characterized in that, The number of signal paths between the first memory die and the integrated circuit device provided by the plurality of vertical interconnects is less than the number of signal paths between the second memory die and the integrated circuit device provided by the surface bonding.
5. The stacked memory device as claimed in claim 1, characterized in that, The size of the through-silicon via (TSV) region of the second memory die is larger than the TSV regions of each layer of the first memory die.
6. The stacked memory device as claimed in claim 1, characterized in that, The size of the through-silicon via (TSV) region of the second memory die is smaller than the TSV regions of each layer of the first memory die.
7. The stacked memory device as claimed in claim 1, characterized in that, The surface bonding includes at least one of hybrid bonding, oxide bonding, and direct metal bonding.
8. The stacked memory device as claimed in claim 1, characterized in that, The plurality of vertical interconnects penetrate the through-silicon via regions of the second memory die.
9. The stacked memory device as claimed in claim 1, characterized in that, One or more vertical interconnects originating from the first memory die form an intermediate branch structure to electrically connect to the second memory die.