Structure and method for integrating planarization process and resistor in semiconductor device
By dividing the device area on the semiconductor substrate and performing global planarization etching and dielectric layer processing, a multi-layer dielectric structure is formed, which solves the surface roughness problem caused by planarization etching, realizes effective planarization and resistor integration, meets the requirements of laser trimming, and improves product yield and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-06
- Publication Date
- 2026-04-07
AI Technical Summary
Existing planarization etching processes achieve macroscopic planarization but also increase surface roughness at the microscopic level, affecting subsequent processes such as laser trimming of CrSi resistors, leading to unstable laser absorption, decreased ablation accuracy, and trimming failure.
By dividing the device area on the semiconductor substrate, performing global planarization etching while retaining the thickness, removing part of the dielectric layer, forming a multilayer dielectric structure, exposing the metal layer and thin film resistor surface, and forming a second metal layer on the dielectric layer, effective planarization is achieved while avoiding surface roughness.
Without increasing the complexity of the process, planarization and resistor integration were achieved, significantly improving surface roughness, meeting the stringent requirements of laser trimming, and improving product yield and reliability.
Smart Images
Figure CN121815668A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to the structure and method of planarization process and resistor integration in semiconductor devices. Background Technology
[0002] Integrated circuit manufacturing processes typically involve multiple thin-film deposition and patterning steps, resulting in surface topography variations on the wafer. To facilitate subsequent fine photolithography and thin-film deposition on these uneven surfaces, planarization etching becomes a critical process step. This process typically employs methods such as plasma bombardment to perform overall, non-selective etching on the wafer surface to smooth out surface protrusions and achieve global or local planarization.
[0003] However, this commonly used planarization etching process has an inherent and easily overlooked technical drawback: while plasma bombardment of the material surface achieves macroscopic planarization, it often disrupts the surface's lattice structure or chemical bonds at the microscopic level, leading to a significant increase in surface roughness. This deterioration of microscopic roughness manifests as more nanoscale depressions, scratches, or a more "rough" surface. This surface unevenness introduced by the planarization process itself can have a serious negative impact on subsequent processes, especially for devices highly sensitive to surface conditions. A typical application is the laser trimming process for CrSi (chromium silicon) thin-film resistors.
[0004] In semiconductor device manufacturing, to obtain precise resistance values, laser beams are typically used to precisely ablate CrSi resistive materials to adjust their resistance to a target range. This process requires excellent surface finish and uniformity of the resistive material to ensure stable and controllable laser beam energy absorption and ablation effects. Excessive surface roughness after planarization etching can directly lead to the following problems:
[0005] Unstable laser absorption rate: Rough surfaces cause diffuse reflection of the laser beam, resulting in uneven distribution of laser energy acting on the CrSi material, which is difficult to predict and control.
[0006] Decreased ablation precision: Microscopic unevenness on the surface can interfere with the depth and shape of laser ablation, causing the adjustment amount to deviate from the expected value, and even causing damage to the resistive body or forming microcracks.
[0007] Adjustment failure: In the worst case, excessive surface roughness will make it impossible for the laser adjustment process to stably and accurately adjust the resistance value of the CrSi resistor to the preset target value range, resulting in a decrease in product yield.
[0008] In summary, while existing planarization etching processes address macroscopic planarity issues, they introduce new problems related to microscopic roughness deterioration. This contradiction severely impacts the performance and manufacturability of precision components such as CrSi resistors, hindering improvements in product yield and reliability. Therefore, there is an urgent need in the field for a new technical solution that can achieve effective planarization while avoiding or significantly improving surface roughness to meet the stringent requirements of subsequent high-performance devices, especially laser trimming processes. Summary of the Invention
[0009] The purpose of this invention is to provide a method for planarization process and resistor integration in semiconductor devices, comprising the following steps:
[0010] S1) Provides a semiconductor substrate, on which at least one first device region and at least one second device region are defined.
[0011] An independent first metal layer structure, an inter-metal first dielectric layer, and an inter-metal second dielectric layer are formed in the first device region, and an inter-metal first dielectric layer and an inter-metal second dielectric layer are formed in the second device region.
[0012] S2) Perform global planarization etching on the second dielectric layer between the metal layers and retain the thickness h to form the etched and retained second dielectric layer between the metal layers.
[0013] S3) Remove the second dielectric layer between metal layers etched and retained in the second device region, and globally grow to form a third dielectric layer between metal layers.
[0014] S4) A thin film resistor is formed in the second device region, and a fourth dielectric layer between metal layers is globally grown.
[0015] S5) Partial removal of the first dielectric layer, the third dielectric layer, and the fourth dielectric layer between the metal layers is performed to expose part of the surface of the first metal layer and the thin film resistor.
[0016] S6) A second metal layer is formed on the fourth dielectric layer between the metal layers, so that the second metal layer is in contact with the first metal layer and the thin film resistor respectively.
[0017] Furthermore, the semiconductor substrate is one of silicon and germanium silicon, or a combination thereof.
[0018] The first dielectric layer between the metal layers is either silicon oxide or silicon nitride.
[0019] The second dielectric layer between the metal layers is either silicon oxide or silicon nitride.
[0020] The fourth dielectric layer between the metal layers is either silicon oxide or silicon nitride.
[0021] The third dielectric layer between the metal layers is either silicon oxide or silicon nitride.
[0022] Furthermore, in step S2, the thickness of the second intermetallic dielectric layer removed by the planarization etching process is determined by the thickness of the second intermetallic dielectric layer to be retained on the first metal layer structure.
[0023] Furthermore, in step S3, the second dielectric layer between metal layers retained by the etching is removed by dry etching or wet etching, and the third dielectric layer between metal layers is formed in the first device region and the second device region by deposition.
[0024] Furthermore, the thin-film resistor is a CrSi resistor.
[0025] Furthermore, in step S4, the step of forming a thin film resistor in the second device region is as follows: depositing a thin film resistor in the second device region, etching excess thin film resistor, and forming the fourth dielectric layer between the metal layers in the first device region and the second device region by deposition.
[0026] Furthermore, in step S5, the first dielectric layer, the third dielectric layer, and the fourth dielectric layer between metal layers above the first metal layer in the first device region are partially etched, so that the surface of the first metal layer is partially exposed.
[0027] The first, third, and fourth intermetallic dielectric layers above the edge of the thin-film resistor in the second device region are partially etched, thereby exposing part of the surface of the thin-film resistor.
[0028] Furthermore, Ti / TIN / W material is deposited before the second metal layer is deposited.
[0029] Further, in step S6, the step of forming a second metal layer on the fourth dielectric layer between the metal layers is as follows: depositing a second metal layer on the fourth dielectric layer between the metal layers, so that the second metal layer is in contact with the first metal layer and the thin film resistor respectively, etching excess metal, and forming a metal lead-out terminal.
[0030] The planarization process and resistor integration structure in the semiconductor device are prepared by the method described above.
[0031] The technical effects of this invention are undeniable. This invention can achieve a planarization process and resistor integration structure without significantly increasing the difficulty and complexity of the process, thereby achieving effective planarization while avoiding or significantly improving surface roughness, and ultimately meeting the stringent requirements of processes such as laser trimming. Attached Figure Description
[0032] Figure 1This is a flowchart illustrating an embodiment of the planarization process and resistor integration in the semiconductor device of the present invention.
[0033] Figures 2-10 This is a schematic diagram of the semiconductor structure in each step of the embodiments of the present invention.
[0034] Explanation of reference numerals in the attached figures:
[0035] 100 - Semiconductor substrate; 101 - First dielectric layer between metal layers; 102 - Second dielectric layer between metal layers; 102' - Second dielectric layer between metal layers with large surface roughness retained after planarization etching; 103 - First metal layer; 104 - Third dielectric layer between metal layers; 105 - Thin film resistor; 106 - Fourth dielectric layer between metal layers; 107 - Second metal layer. Detailed Implementation
[0036] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.
[0037] Example 1:
[0038] A method for planarization processes and resistor integration in semiconductor devices includes the following steps:
[0039] S1 provides a semiconductor substrate 100, on which at least one first device region and at least one second device region are defined.
[0040] An independent first metal layer 103 structure, an inter-metal first dielectric layer 101, and an inter-metal second dielectric layer 102 are formed in the first device region, and an inter-metal first dielectric layer 101 and an inter-metal second dielectric layer 102 are formed in the second device region.
[0041] S2 performs global planarization etching on the second dielectric layer 102 between metal layers and retains the thickness h to form an etched and retained second dielectric layer 102' between metal layers.
[0042] S3 removes the second dielectric layer 102' between metal layers etched and retained in the second device region, and globally grows to form the third dielectric layer 104 between metal layers.
[0043] S4 forms a thin film resistor 105 in the second device region and globally grows a fourth dielectric layer 106 between metal layers.
[0044] S5 partially removes the first intermetallic dielectric layer 101, the third intermetallic dielectric layer 104, and the fourth intermetallic dielectric layer 106, thereby exposing part of the surface of the first metal layer 103 and the thin film resistor 105.
[0045] S6 forms a second metal layer 107 on the fourth dielectric layer 106 between the metal layers, so that the second metal layer 107 contacts the first metal layer 103 and the thin film resistor 105 respectively.
[0046] Example 2:
[0047] The method for planarization process and resistor integration in semiconductor devices is the same as in Example 1. Further, the semiconductor substrate 100 is one or a combination of silicon and germanium silicon.
[0048] The first dielectric layer 101 between the metal layers is either silicon oxide or silicon nitride.
[0049] The second dielectric layer 102 between the metal layers is one of silicon oxide and silicon nitride.
[0050] The fourth dielectric layer 106 between the metal layers is one of silicon oxide and silicon nitride.
[0051] The third dielectric layer 104 between the metal layers is either silicon oxide or silicon nitride.
[0052] Example 3:
[0053] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Embodiments 1-2. Further, in step S2, the thickness of the second dielectric layer 102 between metal layers removed by the planarization etching process is determined by the thickness of the second dielectric layer 102 between metal layers that needs to be retained on the structure of the first metal layer 103.
[0054] Example 4:
[0055] The method for planarization process and resistor integration in semiconductor devices is the same as any one of embodiments 1-3. Further, in step S3, the second dielectric layer 102' between metal layers is removed by dry etching or wet etching, and the third dielectric layer 104 between metal layers is formed in the first device region and the second device region by deposition.
[0056] Example 5:
[0057] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-4. Further, the thin film resistor 105 is a CrSi resistor.
[0058] Example 6:
[0059] The method for planarization process and resistor integration in semiconductor devices is the same as any one of embodiments 1-5. Further, in step S4, the step of forming a thin film resistor 105 in the second device region is as follows: depositing a thin film resistor 105 in the second device region, etching excess thin film resistor 105, and forming the fourth dielectric layer 106 between the metal layers in the first device region and the second device region by deposition.
[0060] Example 7:
[0061] The method for planarization process and resistor integration in semiconductor devices is the same as any one of embodiments 1-6. Further, in step S5, the first intermetallic dielectric layer 101, the third intermetallic dielectric layer 104, and the fourth intermetallic dielectric layer 106 above the first metal layer 103 in the first device region are partially etched, so that the surface of the first metal layer 103 is partially exposed.
[0062] The first intermetallic dielectric layer 101, the third intermetallic dielectric layer 104, and the fourth intermetallic dielectric layer 106 above the edge of the thin film resistor 105 in the second device region are partially etched, so that the surface of the thin film resistor 105 is partially exposed.
[0063] Example 8:
[0064] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-7. Furthermore, before the second metal layer 107 is deposited, Ti / TIN / W material is also deposited.
[0065] Example 9:
[0066] The method for planarization process and resistor integration in semiconductor devices is the same as any one of embodiments 1-8. Further, in step S6, the step of forming a second metal layer 107 on the fourth dielectric layer 106 between the metal layers is as follows: depositing a second metal layer 107 on the fourth dielectric layer 106 between the metal layers, so that the second metal layer 107 contacts the first metal layer 103 and the thin film resistor 105 respectively, etching excess metal to form a metal lead-out terminal.
[0067] Example 10:
[0068] The planarization process and resistor integration structure in the semiconductor device are prepared by the method described in any one of Examples 1-9.
[0069] Example 11:
[0070] Methods for planarization processes and resistor integration in semiconductor devices include:
[0071] S1: A semiconductor substrate is provided, on which at least one first device region and at least one second device region are defined, and an independent first metal layer structure, a first inter-metal dielectric layer and a second inter-metal dielectric layer are formed in the first device region, and an inter-metal first dielectric layer and an inter-metal second dielectric layer are formed in the second device region.
[0072] S2: Perform global planarization etching on the second dielectric layer between the metal layers while retaining a certain thickness;
[0073] S3: Remove the second intermetallic dielectric layer retained after etching the second device region and globally grow to form a third intermetallic dielectric layer;
[0074] S4: A thin film resistor is formed in the second device region and a fourth dielectric layer between metal layers is grown globally;
[0075] S5: Remove a portion of the intermetallic dielectric layer to the surface of the first metal layer and the surface of the thin film resistor, respectively;
[0076] S6: A second metal layer is formed on the fourth dielectric layer between the metal layers, so that the second metal layer is in contact with the first metal layer and the thin film resistor respectively.
[0077] Example 12:
[0078] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-11. Further, the semiconductor substrate is one or a combination of silicon and germanium silicon.
[0079] Example 13:
[0080] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-12, and further, the first dielectric layer between the metal layers is one of silicon oxide and silicon nitride.
[0081] Example 14:
[0082] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-13, further wherein the second dielectric layer between the metal layers is one of silicon oxide and silicon nitride.
[0083] Example 15:
[0084] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Embodiments 1-14. Further, in step S2, the thickness of the second dielectric layer between the metal layers removed by the planarization etching process is determined by the thickness of the second dielectric layer between the metal layers to be retained on the first metal layer structure.
[0085] Example 16:
[0086] The method for planarization process and resistor integration in semiconductor devices is the same as any one of embodiments 1-15. Further, in step S3, the second dielectric layer between metal layers retained after etching the second device region is removed by dry etching or wet etching, and the third dielectric layer between metal layers is formed in the first device region and the second device region by deposition.
[0087] Example 17:
[0088] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-16. Further, the third dielectric layer between the metal layers is one of silicon oxide and silicon nitride.
[0089] Example 18:
[0090] The method for planarization process and resistor integration in semiconductor devices is the same as any one of embodiments 1-17. Further, in step S4, the step of forming a thin film resistor in the second device region is as follows: depositing a thin film resistor in the second device region, etching excess thin film resistor, and forming the fourth dielectric layer between the metal layers in the first device region and the second device region by deposition.
[0091] Example 19:
[0092] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-18, and further, the thin film resistor is a CrSi resistor.
[0093] Example 20:
[0094] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-19. Further, the fourth dielectric layer between the metal layers is one of silicon oxide and silicon nitride.
[0095] Example 21:
[0096] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Embodiments 1-20. Further, in step S5, the inter-metal dielectric layer above the first metal layer in the first device region is etched to the surface of the first metal layer, and the inter-metal dielectric layer above the edge of the thin film resistor in the second device region is etched to the surface of the thin film resistor.
[0097] Example 22:
[0098] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-21. Furthermore, before the deposition of the second metal layer, it also includes the deposition of Ti / TIN / W material.
[0099] Example 23:
[0100] The method for planarization process and resistor integration in semiconductor devices is the same as any one of Examples 1-22. Further, in step S6, the step of forming a second metal layer on the fourth dielectric layer between the metal layers is as follows: depositing a second metal layer on the fourth dielectric layer between the metal layers, so that the second metal layer is in contact with the first metal layer and the thin film resistor respectively, etching excess metal, and forming a metal lead-out terminal.
[0101] Example 24:
[0102] Please see Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the planarization process and resistor integration structure and method in the semiconductor device of the present invention. The fabrication method of this embodiment includes:
[0103] S1: A semiconductor substrate 100 is provided, on which at least one first device region and at least one second device region are defined, and an independent first metal layer structure 103, a first intermetallic dielectric layer 101 and a second intermetallic dielectric layer 102 are formed in the first device region, and the first intermetallic dielectric layer 101 and the second intermetallic dielectric layer 102 are formed in the second device region.
[0104] S2: Perform global planarization etching on the second dielectric layer 102 between the metal layers and retain a certain thickness;
[0105] S3: Remove the second intermetallic dielectric layer 102' retained after etching the second device region and globally grow to form the third intermetallic dielectric layer 104;
[0106] S4: A thin film resistor 105 is formed in the second device region and a fourth dielectric layer 106 is globally grown between metal layers;
[0107] S5: Remove the fourth dielectric layer 106, the third dielectric layer 104, the second dielectric layer 102' with large surface roughness after planarization etching, the surfaces of the first dielectric layer 101 to the first metal layer 103, and the fourth dielectric layer 106 to the thin film resistor 105 in the first device region, respectively.
[0108] S6: A second metal layer 107 is formed on the fourth dielectric layer 106 between the metal layers, so that the second metal layer 107 is in contact with the first metal layer 103 and the thin film resistor 105 respectively.
[0109] Example 25:
[0110] The following is in conjunction with the appendix Figures 2-10 The following describes in detail the structure and method of planarization process and resistor integration in the semiconductor device:
[0111] S1: Please refer to Figure 2 A semiconductor substrate 100 is provided, on which at least one first device region and at least one second device region are defined, and an independent first metal layer structure 103, a first intermetallic dielectric layer 101 and a second intermetallic dielectric layer 102 are formed in the first device region, and the first intermetallic dielectric layer 101 and the second intermetallic dielectric layer 102 are formed in the second device region.
[0112] Please refer to Figure 2 The semiconductor substrate 100 is one of silicon and germanium-silicon or a combination thereof, or other substrate materials known to those skilled in the art. The first intermetallic dielectric layer 101 is one of silicon oxide and silicon nitride. The second intermetallic dielectric layer 102 is one of silicon oxide and silicon nitride.
[0113] S2: Please refer to Figure 3 and Figure 4 The second dielectric layer 102 between the metal layers is subjected to global planarization etching while retaining a certain thickness. The thickness of the second dielectric layer 102 removed by the planarization etching is determined by the required thickness of the second dielectric layer 102 between the metal layers to be retained in the structure of the first metal layer 103.
[0114] S3: Please refer to Figure 5 and Figure 6 After removing the second device region by etching, the second intermetallic dielectric layer 102' is retained and a third intermetallic dielectric layer 104 is globally grown.
[0115] Please see Figure 5 and Figure 6 In step S3, the second dielectric layer 102' retained after etching the second device region is removed by dry etching or wet etching, and the third dielectric layer 104 is formed in the first device region and the second device region by deposition. The third dielectric layer 104 is one of silicon oxide and silicon nitride.
[0116] S4: Please refer to Figure 7 and Figure 8 A thin film resistor 105 is formed in the second device region and a fourth dielectric layer 106 is grown globally between metal layers.
[0117] Please see Figure 7 and Figure 8The step of forming the thin-film resistor 105 in the second device region is as follows: depositing the thin-film resistor 105 in the second device region, etching the excess thin-film resistor 105, and forming the fourth dielectric layer 106 between the first device region and the second device region by deposition. The thin-film resistor 105 is a CrSi resistor. The fourth dielectric layer 106 between the metal layers is one of silicon oxide and silicon nitride.
[0118] S5: Please refer to Figure 9 The fourth dielectric layer 106, the third dielectric layer 104, the second dielectric layer 102' with a large surface roughness after planarization etching, the surfaces of the first dielectric layer 101 to the first metal layer 103, and the fourth dielectric layer 106 to the thin film resistor 105 in the first device region are removed respectively.
[0119] Please see Figure 9 The fourth intermetallic dielectric layer 106, the third intermetallic dielectric layer 104, the second intermetallic dielectric layer 102' with a large surface roughness after planarization etching, and the first intermetallic dielectric layer 101 to the surface of the first metal layer 103 above the first metal layer 103 in the first device region are etched. The fourth intermetallic dielectric layer 106 to the surface of the thin film resistor 105 above the edge of the thin film resistor 105 in the second device region are etched.
[0120] S6: Please refer to Figure 10 A second metal layer 107 is formed on the fourth dielectric layer 106 between the metal layers, so that the second metal layer 107 is in contact with the first metal layer 103 and the thin film resistor 105 respectively.
[0121] Please see Figure 10 Prior to the deposition of the second metal layer 107, the deposition of Ti / TIN / W material is also included.
[0122] Please see Figure 10 The step of forming a second metal layer 107 on the fourth dielectric layer 106 between the metal layers is as follows: the second metal layer 107 is deposited on the fourth dielectric layer 106 between the metal layers, and the second metal layer 107 is in contact with the first metal layer 103 and the thin film resistor 105 respectively. Excess metal is etched to form metal leads, and finally a structure integrating planarization process and resistor is obtained, thereby achieving effective planarization while avoiding or significantly improving surface roughness.
[0123] In summary, this embodiment proposes a structure and method for integrating planarization process with resistors in semiconductor devices. This structure can achieve planarization process integration with resistors without significantly increasing the difficulty and complexity of the process. This achieves effective planarization while avoiding or significantly improving surface roughness, ultimately meeting the stringent requirements of processes such as laser trimming.
Claims
1. A method for planarization process and resistor integration in semiconductor devices, characterized in that, Includes the following steps: S1) A semiconductor substrate (100) is provided, wherein at least one first device region and at least one second device region are defined on the semiconductor substrate (100); An independent first metal layer (103) structure, an inter-metal first dielectric layer (101) and an inter-metal second dielectric layer (102) are formed in the first device region, and an inter-metal first dielectric layer (101) and an inter-metal second dielectric layer (102) are formed in the second device region. S2) Perform global planarization etching on the second dielectric layer (102) between metal layers and retain the thickness h to form an etch-retained second dielectric layer (102') between metal layers. S3) Remove the second dielectric layer (102') between metal layers etched and retained in the second device region, and globally grow to form a third dielectric layer (104) between metal layers. S4) A thin film resistor (105) is formed in the second device region, and a fourth dielectric layer (106) is globally grown between metal layers. S5) Partial removal of the first dielectric layer (101), the third dielectric layer (104), and the fourth dielectric layer (106) between the metal layers is performed to expose part of the surface of the first metal layer (103) and the thin film resistor (105); S6) A second metal layer (107) is formed on the fourth dielectric layer (106) between the metal layers, so that the second metal layer (107) is in contact with the first metal layer (103) and the thin film resistor (105) respectively.
2. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: The semiconductor substrate (100) is one or a combination of silicon and germanium silicon; The first dielectric layer (101) between the metal layers is one of silicon oxide and silicon nitride; The second dielectric layer (102) between the metal layers is one of silicon oxide and silicon nitride; The fourth dielectric layer (106) between the metal layers is one of silicon oxide and silicon nitride; The third dielectric layer (104) between the metal layers is either silicon oxide or silicon nitride.
3. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: In step S2, the thickness of the second intermetallic dielectric layer (102) removed by the planarization etching process is determined by the thickness of the second intermetallic dielectric layer (102) that needs to be retained in the structure of the first metal layer (103).
4. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: In step S3, the second dielectric layer (102') between metal layers is removed by dry etching or wet etching, and the third dielectric layer (104) between metal layers is formed in the first device region and the second device region by deposition.
5. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: The thin-film resistor (105) is a CrSi resistor.
6. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: In step S4, the step of forming a thin film resistor (105) in the second device region is as follows: depositing a thin film resistor (105) in the second device region, etching excess thin film resistors (105), and forming the fourth dielectric layer (106) between the metal layers in the first device region and the second device region by deposition.
7. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: In step S5, the first intermetallic dielectric layer (101), the third intermetallic dielectric layer (104), and the fourth intermetallic dielectric layer (106) above the first metal layer (103) in the first device region are partially etched, so that the surface of the first metal layer (103) is partially exposed. The first intermetallic dielectric layer (101), the third intermetallic dielectric layer (104), and the fourth intermetallic dielectric layer (106) above the edge of the thin film resistor (105) in the second device region are partially etched, so that the surface of the thin film resistor (105) is partially exposed.
8. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: Before the second metal layer (107) is deposited, Ti / TIN / W material is also deposited.
9. The method for planarization process and resistor integration in a semiconductor device according to claim 1, characterized in that: In step S6, the step of forming a second metal layer (107) on the fourth dielectric layer (106) between the metal layers is as follows: depositing a second metal layer (107) on the fourth dielectric layer (106) between the metal layers, so that the second metal layer (107) contacts the first metal layer (103) and the thin film resistor (105) respectively, etching excess metal, and forming metal leads.
10. A planarization process and resistor integration structure in a semiconductor device, characterized in that: It is prepared by the method described in any one of claims 1-9.