Grid electrode manufacturing method for preventing light resistance from warping
By employing multilayer photoresist and overlay processes in gallium arsenide device manufacturing, photoresist warping is prevented, thus solving the problem of gate size runaway caused by photoresist warping and improving device performance and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-07
AI Technical Summary
During the manufacturing process of gallium arsenide devices, photoresist is prone to warping during the etching process of GaAs substrate, which leads to loss of control of critical gate dimensions and affects device performance and yield.
A multilayer photoresist is coated on the source and drain metals using an overlay process. The etch width of the cap layer is defined by wet etching and baking steps. The GaAs cap layer is etched first using i-line photoresist to avoid photoresist warping and improve linewidth accuracy and metal vapor deposition stability.
It effectively prevents photoresist warping, improves gate linewidth accuracy and device yield, simplifies the process flow, and improves device performance and process yield.
Smart Images
Figure CN121815729A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of gate metal technology, and in particular to a gate manufacturing method for preventing photoresist warping. Background Technology
[0002] In current gallium arsenide (GaAs) device manufacturing processes, gate patterning is typically achieved using i-line or electron beam lithography. However, during subsequent GaAs substrate etching, photoresist is prone to localized lifting or peeling. This can lead to uncontrolled and deviated gate critical dimensions (Gate CD). As the etching mask, the lifting of the photoresist alters the intended pattern morphology, causing the etched gate line width to deviate significantly from the design value. This typically manifests as an abnormally large gate CD, directly resulting in deviations from the device's electrical performance (such as saturation current and threshold voltage) and causing product performance inconsistencies. Furthermore, it can lead to photoresist structure instability during subsequent gate metal deposition processes, causing defects such as metal layer cracks, severely impacting device performance and process yield. Summary of the Invention
[0003] The purpose of this invention is to provide a gate manufacturing method to prevent photoresist warping, which can avoid the cracks in the metal vapor deposition caused by the photoresist warping after etching, improve photoresist warping, improve linewidth accuracy, and improve quality yield.
[0004] To achieve the above objectives, the present invention provides the following technical solution: a method for manufacturing a gate to prevent photoresist warping, the method comprising the following steps:
[0005] Step S1: Coat the first photoresist layer on both the source and drain metals, define the cap layer etching width using an overlay process, and etch the channel into the substrate using a wet etching process.
[0006] Step S2: Remove the first photoresist layer, coat the second photoresist layer, and develop.
[0007] Step S3: Pattern the second photoresist layer to form the bottom of the Y gate;
[0008] Step S4: Coat the third photoresist layer on the second photoresist layer and develop it. The third photoresist layer is a negative photoresist.
[0009] Step S5: Perform gate metal evaporation;
[0010] Step S6: Remove the third photoresist layer and excess metal using NMP solution;
[0011] Furthermore, the thickness of the second photoresist layer coating is...
[0012] Furthermore, the linewidth of the patterned second photoresist layer is between 0.08 and 0.6 μm.
[0013] Furthermore, the thickness of the third photoresist layer coating is... The linewidth after development is between 0.55 and 1.0 μm.
[0014] Furthermore, the thickness of the metal is in between.
[0015] Furthermore, after defining the cap layer etching width using the overlay process in step S1, the process also includes a baking step, wherein the baking temperature is 120-140°C.
[0016] The beneficial effects of this invention are:
[0017] 1. The cap layer of GaAs is etched away in advance using i-line photoresist (first photoresist), which avoids cracks in the metal vapor deposition caused by the photoresist lifting after etching.
[0018] 2. Improved photoresist warping, resulting in increased linewidth accuracy and higher quality yield;
[0019] 3. The breakdown voltage of the device is proportional to the etching; the width of the cap layer etching is defined in the first photoresist layer, which means that the definition of the breakdown voltage is extracted from the original gate etching process, simplifying the process; and it avoids the possibility of increasing the etching time in order to meet the required value of the gate breakdown voltage, which would exacerbate the photoresist warping and increase the possibility of metal cracks, and also increase the possibility of linewidth defocusing. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the photoresist patterning in this invention;
[0021] Figure 2 This is a schematic diagram of wet etching after photoresist patterning in this invention;
[0022] Figure 3 This is a schematic diagram illustrating the direct baking process after photoresist patterning;
[0023] Figure 4 This is a schematic diagram of wet etching performed on a pre-baked image.
[0024] Figure 5 Schematic diagram of the second photoresist layer being coated.
[0025] Figure 6 Schematic diagram of etching the second photoresist layer
[0026] Figure 7 This is a schematic diagram of the process of applying the third photoresist layer;
[0027] Figure 8 This is a schematic diagram of vapor-deposited metal;
[0028] Figure 9 A schematic diagram showing the removal of the third photoresist layer and excess metal.
[0029] Wherein, 1, substrate, 2, first photoresist layer, 3, channel, 4, second photoresist layer, 5, third photoresist layer, and 6, metal. Detailed Implementation
[0030] The invention will now be further described with reference to the accompanying drawings.
[0031] Please see Figures 1 to 9 The present invention provides an embodiment: a method for manufacturing a gate to prevent photoresist warping, the method comprising the following steps:
[0032] Step S1: Coat the first photoresist layer 2 on both the source and drain metals, define the cap layer etching width using an overlay process, and etch the channel 3 into the substrate 1 using a wet etching process.
[0033] Step S2: Remove the first photoresist layer 2, coat the second photoresist layer 4, and develop.
[0034] Step S3: Pattern the second photoresist layer 4 to form the bottom of the Y gate;
[0035] Step S4: Coat the third photoresist layer 5 on the second photoresist layer 4 and develop it. The third photoresist layer 5 is a negative photoresist.
[0036] Step S5: Evaporate the gate metal 6.
[0037] Step S6: Remove the third photoresist layer 5 and excess metal 6 with NMP solution;
[0038] Please continue reading. Figure 5 As shown, in one embodiment of the present invention, the thickness of the second photoresist layer 4 is [missing information].
[0039] Please continue reading. Figure 5 As shown, in one embodiment of the present invention, the linewidth of the patterned second photoresist layer 4 is between 0.08 and 0.6 μm.
[0040] Please continue reading. Figure 6 As shown, in one embodiment of the present invention, the thickness of the third photoresist layer 5 is [missing information]. The linewidth after development is between 0.55 and 1.0 μm. The preferred thickness of the third photoresist layer 5 is...
[0041] Please continue reading. Figure 7 As shown, in one embodiment of the present invention, the thickness of the metal 6 is... between.
[0042] Please continue reading. Figures 3 to 4 As shown, in one embodiment of the present invention, after defining the etch width of the cap layer using the overlay process in step S1, a baking step is further included, wherein the baking temperature is 120-140°C. The preferred baking temperature is 135°C. Specific Implementation Example 1:
[0044] 1. A first photoresist layer 2 with a thickness of [thickness value missing] is coated on the source and drain metals.
[0045] Then, two scenarios are considered to adapt to different gate etching widths. The main difference lies in the fact that different patterning linewidths determine different etching widths for GaAs substrate 1 materials. After photoresist development, channel 3 etching is performed, at which point the photoresist patterning linewidth is 0.4 μm, such as... Figure 1 As shown, taking succinic acid etching for 18 seconds as an example, the etching width will be 0.6 μm, as... Figure 2 As shown;
[0046] exist Figure 1 Based on the existing conditions, baking is performed at a temperature of 135℃ to achieve a linewidth of 0.4μm. Figure 3 As shown, the linewidth after etching is 0.6 μm, as... Figure 4 As shown;
[0047] 2. Remove the first photoresist layer 2 and coat the second photoresist layer 4, as follows: Figure 5 As shown; thickness is between;
[0048] 3. After patterning the second photoresist, expose the patterned area and then develop it. The photoresist in the exposed area will be revealed by the developer. Then bake it at 120℃ for 60 seconds to form the bottom of the Y-gate. Figure 6 As shown, the linewidth is between 0.08 and 0.6 μm.
[0049] 4. Apply the third photoresist layer 5, with a thickness of [missing information]. It is a negative photoresist; the linewidth after development is 0.55–1.0 μm, such as Figure 7
[0050] 5. Apply gate metal 6 by vapor deposition, such as Figure 8 As shown; the thickness of metal 6 is...
[0051] 6. After removing the photoresist with NMP solution, as follows: Figure 9 As shown.
[0052] The present invention operates on the following principle: Photoresist warping can cause cracks in the metal 6 deposition process, and warping also alters the linewidth, affecting yield. The present invention uses an i-line photoresist (first photoresist) to pre-etch away the GaAs cap layer, avoiding the cracks in the metal 6 deposition caused by photoresist warping after etching; it improves photoresist warping; enhances linewidth accuracy; and increases quality and yield. The device's breakdown voltage is proportional to the etching width. The cap layer etching width is defined in the first photoresist layer 2, thus removing the breakdown voltage definition from the original gate etching process, simplifying the process. Furthermore, it avoids the previous practice of increasing etching time to meet the required gate breakdown voltage, which exacerbated photoresist warping, increased the likelihood of metal 6 cracks, and increased the possibility of linewidth defocusing.
[0053] The above description is only a preferred embodiment of the present invention and should not be construed as a limitation of this application. All equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should be covered by the present invention.
Claims
1. A method for manufacturing a gate to prevent photoresist warping, characterized in that: The manufacturing method includes the following steps: Step S1: Coat the first photoresist layer on both the source and drain metals, define the cap layer etching width using an overlay process, and etch the channel into the substrate using a wet etching process. Step S2: Remove the first photoresist layer, coat the second photoresist layer, and develop. Step S3: Pattern the second photoresist layer to form the bottom of the Y gate; Step S4: Coat the third photoresist layer on the second photoresist layer and develop it. The third photoresist layer is a negative photoresist. Step S5: Perform gate metal evaporation; Step S6: Remove the third photoresist layer and excess metal using NMP solution.
2. The method for manufacturing a gate to prevent photoresist warping according to claim 1, characterized in that: The thickness of the second photoresist layer coating is 3. The method for manufacturing a gate to prevent photoresist warping according to claim 1, characterized in that: The linewidth of the patterned second photoresist layer is between 0.08 and 0.6 μm.
4. The method for manufacturing a gate to prevent photoresist warping according to claim 1, characterized in that: The thickness of the third photoresist layer coating is The linewidth after development is between 0.55 and 1.0 μm.
5. The method for manufacturing a gate to prevent photoresist warping according to claim 1, characterized in that: The metal thickness is between.
6. The method for manufacturing a gate to prevent photoresist warping according to claim 1, characterized in that: After defining the cap layer etching width using the overlay process in step S1, the process also includes a baking step, wherein the baking temperature is 120-140℃.