SiC-based integrated circuit and semiconductor device

Abstract

The embodiment of the invention provides a SiC-based integrated circuit and a semiconductor device. The SiC-based integrated circuit comprises a SiC-based complementary metal oxide semiconductor transistor, the gate length of the complementary metal oxide semiconductor transistor is larger than the preset reference length, and the preset reference length is the initial gate length meeting the circuit speed-area compromise. According to the invention, the threshold voltage drift amount of the device in a high-temperature environment is reduced by increasing the gate length of the PMOSFET and the NMOSFET, keeping the gate width unchanged or performing proper adjustment, so that the size of the device in the SiC-based CMOS integrated circuit is optimized, and the high-temperature long-term reliability of the SiC-based CMOS integrated circuit is also remarkably improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor integrated circuits, and in particular to a SiC-based integrated circuit and a semiconductor device. BACKGROUND

[0002] In the fields of aerospace, drilling exploration and chemical metallurgy, chips often work in high-temperature environments above 400℃. Limited by the physical properties of materials, the integrated circuits based on semiconductor silicon (Si) material are increasingly weak in high-temperature applications, and the maximum operating temperature of Si-based integrated circuits is only about 300℃. As the temperature rises, the intrinsic carrier concentration in the semiconductor will increase sharply, causing the device to turn off and leading to functional failure of the integrated circuit. Compared with Si material, silicon carbide (SiC) material as the third generation semiconductor material has unique advantages in terms of band gap, heat conduction capacity and other characteristics, so it can work at higher operating temperatures, and the theoretical limit operating temperature of SiC-based semiconductor devices can reach 1000℃. Therefore, the current SiC replaces Si material to make integrated circuits applied to high-temperature extreme environments has been widely favored.

[0003] Due to the advantages of low power consumption, high integration, strong anti-interference and compatible SiC power metal-oxide-semiconductor field effect transistor (MOSFET) device preparation process, SiC-based complementary metal-oxide-semiconductor transistor (CMOS) integrated circuit technology has become the most concerned research hotspot at present.

[0004] However, the higher the operating temperature, the more serious the high-temperature reliability of the integrated circuit composed of the gate oxide layer structure of the SiC-based CMOS device, especially the PMOSFET (P-channel metal-oxide-semiconductor field effect transistor) circuit. SUMMARY

[0005] The embodiments of the present disclosure provide a SiC-based integrated circuit and a semiconductor device, which improve the reliability of CMOS devices by optimizing the size of CMOS devices in a SiC-based CMOS integrated circuit, thereby improving the reliability of the SiC-based CMOS integrated circuit.

[0006] As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a SiC-based integrated circuit, which comprises a complementary metal-oxide-semiconductor transistor, and a gate length of the complementary metal-oxide-semiconductor transistor is greater than a preset reference length, and the preset reference length is an initial gate length meeting a circuit speed-area trade-off.

[0007] In some optional embodiments, the complementary metal-oxide-semiconductor transistor comprises a P-channel metal-oxide-semiconductor field effect transistor and / or an N-channel metal-oxide-semiconductor field effect transistor, and the gate length of the P-channel metal-oxide-semiconductor field effect transistor is greater than the gate length of the N-channel metal-oxide-semiconductor field effect transistor.

[0008] In some optional embodiments, the gate length is in a range of 1 ≤ L ≤ 5 .

[0009] In some optional embodiments, the gate width of the complementary metal-oxide-semiconductor transistor is in a range of 20 ≤ W ≤ 80 .

[0010] In some optional embodiments, a plurality of the complementary metal-oxide-semiconductor transistors share a source / drain region, a folded gate structure, or adopt a multi-finger gate structure.

[0011] In some optional embodiments, any one or more of an inverter, a NAND gate, a NOR gate, a latch, a register, an amplifier, or an analog-to-digital converter is further included.

[0012] In some optional embodiments, the rise time of the inverter is determined based on a PMOSFET, and the fall time is determined based on an NMOSFET (N-channel metal-oxide-semiconductor field effect transistor).

[0013] In some optional embodiments, the inverter comprises a complementary metal-oxide-semiconductor transistor with a gate width to length ratio of 80:5.

[0014] In some optional embodiments, the inverter comprises a complementary metal-oxide-semiconductor transistor with a gate width to length ratio of 20:2.

[0015] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a semiconductor device comprising the SiC-based integrated circuit of the first aspect.

[0016] The technical solutions of the embodiments of the present disclosure utilize the size-dependent law of SiC-based CMOS device reliability, optimize the size of CMOS devices in the SiC-based CMOS integrated circuit, i.e., increase the gate length of the PMOSFET and the NMOSFET, keep the gate width unchanged or adjust it appropriately during the circuit design stage, to reduce the threshold voltage drift of the device in a 400 °C high-temperature environment, thereby optimizing the size of the SiC-based CMOS integrated circuit device and significantly improving the high-temperature long-term reliability of the SiC-based CMOS integrated circuit.

[0017] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0018] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0019] Figure 1 A schematic diagram of the BTI characteristics of the same size SiC-based CMOS device provided in this application at 400°C; Figure 2a This is a schematic diagram illustrating the size dependence of the threshold voltage drift of the SiC-based CMOS device (NMOSFET) provided in this application after 3000 seconds of stress. Figure 2b This is a schematic diagram illustrating the size dependence of the threshold voltage drift of the SiC-based CMOS device (PMOSFET) provided in this application after 3000 seconds of stress. Figure 3 This is a schematic diagram showing the performance degradation of the SiC-based CMOS inverter circuit provided in this application after 60 minutes of continuous operation. Figure 4a The inverter provided in this application has a gate width-to-length ratio of 80. / 5 A schematic diagram of a circuit board constructed using SiC-based CMOS devices; Figure 4b The inverter provided in this application has a gate width-to-length ratio of 20. / 2 A schematic diagram of a circuit board constructed using SiC-based CMOS devices. Detailed Implementation

[0020] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0021] In the related art, the higher the working temperature, the more serious the high-temperature reliability of the integrated circuit composed of the gate oxide layer structure of the SiC-based CMOS device. In addition, since the gate oxide layer formation condition of the SiC-based MOSFET device is currently optimized only for NMOSFET, the quality of the gate oxide layer of PMOSFET is poorer than that of NMOSFET, that is, the high-temperature reliability problem of SiC-based PMOSFET is more serious.

[0022] To solve some problems in the related art, the embodiments of the present disclosure provide a SiC-based integrated circuit, which will be described in detail below through specific embodiments.

[0023] In view of the high-temperature reliability problem caused by the poor quality of the gate oxide layer of the SiC-based CMOS device, according to the size-dependent relationship of the reliability of the SiC-based CMOS device, the device size is adjusted in the design stage of the SiC-based CMOS integrated circuit to achieve reliability reinforcement. Based on this idea, the present application carries out a bias temperature instability (BTI) experiment on the SiC-based CMOS device under high-temperature environment to obtain the change relationship between the threshold voltage drift and the gate length and the gate width. First, according to the change relationship between the threshold voltage drift and the gate length and the gate width, the size-dependent law that the threshold voltage drift increases significantly with the shortening of the gate length and remains basically unchanged with the change of the gate width is determined. Then, according to the size-dependent law obtained by the experiment, in the layout design stage of the SiC-based CMOS integrated circuit, the gate length of the PMOSFET or NMOSFET constituting the integrated circuit is set to be greater than the reference length, and the reference length is the initial gate length that meets the circuit speed-area compromise; the gate width is kept or adjusted appropriately to meet the circuit performance requirements, thereby reducing the threshold voltage drift and improving the high-temperature long-term reliability of the SiC-based CMOS integrated circuit on the premise of sacrificing part of the layout area.

[0024] Specifically, taking the bias temperature instability (BTI) experiment of the CMOS device as an example, Figure 1 It is shown that the threshold voltage drift of the SiC-based PMOSFET is much larger than that of the NMOSFET. The test conditions of the above BTI experiment are: temperature 400℃, stress voltage ±30 V, stress time 3000 s, wherein +30 V is applied to the NMOSFET and -30 V is applied to the PMOSFET.

[0025] According to the results shown in Figure 1 It can be seen from the results that the threshold voltage of the SiC-based CMOS device will drift under the action of high-temperature long-time stress voltage, and the threshold voltage drift of the PMOSFET is much larger than that of the NMOSFET.

[0026] ReferenceFigure 2a and Figure 2b Fig. 6 shows the size dependence of threshold voltage shift amount of SiC-based CMOS devices (NMOSFET) and SiC-based CMOS devices (PMOSFET) after 3000 seconds of stress, respectively, as shown in the figure, wherein the test conditions are: temperature 400℃, stress voltage ±30 V, +30 V applied to NMOSFET and -30 V applied to PMOSFET. According to the size dependence of threshold voltage shift amount obtained by experiment, it can be determined that after the same stress time, the threshold voltage shift amount of the device does not change with the gate width, but significantly increases with the shortening of the gate length, and this effect is more significant in SiC-based PMOSFET devices.

[0027] Based on the above ideas and experimental results, the embodiment provides a SiC-based integrated circuit, which comprises one or more complementary metal oxide semiconductor transistors, the gate length of the complementary metal oxide semiconductor transistor is greater than a preset reference length, and the preset reference length is an initial gate length that meets the circuit speed-area trade-off.

[0028] The SiC-based integrated circuit provided by the embodiment utilizes the size dependence of SiC-based CMOS device reliability, increases the gate length of PMOSFET and NMOSFET, keeps the gate width unchanged or adjusts it appropriately during the circuit design stage, so as to reduce the threshold voltage shift amount of the device under the high temperature environment of 400 °C, thereby optimizing the size of the device in the SiC-based CMOS integrated circuit and significantly improving the high temperature long-term reliability of the SiC-based CMOS integrated circuit.

[0029] The SiC-based integrated circuit provided by the embodiment can be but not limited to applied to SiC-based CMOS integrated circuit design under high temperature extreme environment such as aerospace, drilling exploration and chemical metallurgy.

[0030] In some optional schemes, the complementary metal oxide semiconductor transistor comprises a P-channel metal oxide semiconductor field effect transistor and / or an N-channel metal oxide semiconductor field effect transistor, and the gate length in the case of the P-channel metal oxide semiconductor field effect transistor is greater than the gate length in the case of the N-channel metal oxide semiconductor field effect transistor.

[0031] Based on the above experiment, in the size-dependent relationship, the threshold voltage drift of PMOSFET is greater than that of NMOSFET, that is, the gate length of PMOSFET is greater than that of NMOSFET, so the gate length of N-channel metal-oxide-semiconductor field-effect transistor can be appropriately reduced to reduce the layout area sacrifice.

[0032] In other optional schemes, the test of the present embodiment shows that the threshold voltage drift of complementary metal-oxide-semiconductor transistor increases sharply with the shortening of the gate length, and is basically independent of the gate width. Therefore, the gate length of the complementary metal-oxide-semiconductor transistor can be set to a range of 1 ≤L≤5 , and the gate width of the complementary metal-oxide-semiconductor transistor can be set to a range of 20 ≤W≤80 , so as to better meet the circuit performance requirements and reduce the layout sacrifice.

[0033] In other optional schemes, the SiC-based integrated circuit further includes any one or more of inverters, NAND gates, NOR gates, latches, registers, amplifiers or analog-to-digital converters, so as to realize more functions and improve the diversity of the SiC-based integrated circuit.

[0034] Reference Figure 3 is a performance degradation of a SiC-based CMOS inverter circuit working for 60 minutes. The test conditions are: temperature 400℃, power supply voltage 30V, and input voltage is a square wave signal with frequency 20kHz, high and low voltage 30V / 0V.

[0035] As shown in Figure 3 , it can be seen that the inverter composed of devices with longer gate length degrades more slowly, especially the rise time degradation determined by the characteristics of PMOSFET. Based on this characteristic, the SiC-based integrated circuit provided by the present embodiment determines the rise time of the inverter based on PMOSFET and determines the fall time based on NMOSFET.

[0036] Specifically, the inverter can include complementary metal-oxide-semiconductor transistors with a gate width to length ratio of 80:5. Experiments show that the inverter composed of PMOSFET with a gate length of 5 and a gate width of 80 has a rise time drift much smaller than that of the inverter composed of devices with a gate length of 2 .

[0037] Further, the above inverter can further include a complementary metal-oxide-semiconductor transistor with a gate width-length ratio of 20:2 to reduce the layout area as much as possible on the basis of ensuring circuit reliability.

[0038] Reference is made to Figure 4a and Figure 4b , which are respectively a schematic diagram of a circuit layout built by inverters constructed by SiC-based CMOS devices with a gate width-length ratio of 80 / 5 , and a schematic diagram of a circuit layout built by inverters constructed by SiC-based CMOS devices with a gate width-length ratio of 20 / 2 . In combination with Figure 4a and Figure 4b , it can be determined that improving circuit reliability increases the layout area consumption, and the area overhead increased due to the increased gate length can be partially offset by sharing source / drain regions, folding gate structures, or using multi-finger gate structures.

[0039] In some other optional solutions, the SiC-based integrated circuit can include a plurality of the complementary metal-oxide-semiconductor transistors, and the plurality of the complementary metal-oxide-semiconductor transistors share source / drain regions, have folding gate structures, or use multi-finger gate structures to partially offset the area overhead increased due to the increased gate length.

[0040] The embodiments of the present application further provide a semiconductor device, which includes the SiC-based integrated circuit in any of the above embodiments.

[0041] It should be noted that the semiconductor device provided by the embodiments has the same inventive concept as the SiC-based integrated circuit provided by the embodiments of the present application, and any of the above embodiments of the SiC-based integrated circuit is also applicable to the semiconductor device and has the same beneficial effects, which will not be described herein again.

[0042] In the description of the present specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0043] In addition, the terms "first", "second", etc. are used only to describe different instances, and cannot be construed to indicate or imply relative importance or imply the number of indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0044] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected, or it can be communicated; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0045] In the present disclosure, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "above" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is higher than the second feature in horizontal height. The first feature "below", "below" and "below" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is lower than the second feature in horizontal height.

[0046] The above disclosure provides many different implementations or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0047] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any skilled person in the art can easily think of various changes or replacements within the technical scope disclosed by the present disclosure, and different parts in different embodiments can be combined with each other without conflict, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A SiC-based integrated circuit, characterized in that, The invention includes a SiC-based complementary metal-oxide-semiconductor transistor (CMOS transistor) with a gate length greater than a preset reference length, the preset reference length being an initial gate length that satisfies the circuit speed-area tradeoff.

2. The SiC-based integrated circuit according to claim 1, characterized in that, The complementary metal-oxide-semiconductor transistor includes a P-channel metal-oxide-semiconductor field-effect transistor and / or an N-channel metal-oxide-semiconductor field-effect transistor, and the gate length of the P-channel metal-oxide-semiconductor field-effect transistor is greater than the gate length of the N-channel metal-oxide-semiconductor field-effect transistor.

3. The SiC-based integrated circuit according to claim 1, characterized in that, The value range of the gate length is 1. ≤L≤5 .

4. The SiC-based integrated circuit according to claim 1, characterized in that, The gate width of the complementary metal-oxide-semiconductor transistor is in the range of 20. ≤W≤80 .

5. The SiC-based integrated circuit according to any one of claims 1-4, characterized in that, Multiple complementary metal-oxide-semiconductor transistors share a source / drain region, a folded gate structure, or a multi-finger gate structure.

6. The SiC-based integrated circuit according to any one of claims 1-4, characterized in that, It also includes any one or more of the following: inverter, NAND gate, NOR gate, latch, register, amplifier, or analog-to-digital converter.

7. The SiC-based integrated circuit according to any one of claims 1-4, characterized in that, The rise time of the inverter is determined based on the PMOSFET, and the fall time is determined based on the NMOSFET.

8. The SiC-based integrated circuit according to claim 7, characterized in that, The inverter includes a complementary metal-oxide-semiconductor transistor with a gate width-to-length ratio of 80:

5.

9. The SiC-based integrated circuit according to claim 7, characterized in that, The inverter includes a complementary metal-oxide-semiconductor transistor with a gate width-to-length ratio of 20:

2.

10. A semiconductor device, characterized in that, Including any one of claims 1-9, the SiC-based integrated circuit.

Images