Back contact solar cell and photovoltaic module

Abstract

The invention provides a back contact solar cell and a photovoltaic module, the back contact solar cell comprises a silicon substrate, the back surface of the silicon substrate comprises first areas and second areas which are alternately arranged, and the conduction types of the first areas and the second areas are different; a first suede area is arranged at the junction of the back surface and the side surface of the silicon substrate; a second suede area is arranged at the junction of the front surface and the side surface of the silicon substrate; the inner expansion layer, the first interface passivation layer, the doped polycrystalline silicon layer, the second interface passivation layer and the doped hydrogenated amorphous silicon layer are sequentially arranged in the side plane area of the silicon substrate, a good passivation effect can be achieved on the side edge, the filling factor of the back contact solar cell is improved, and the hidden crack and fragment risk of a cell piece is reduced.

Description

Technical Field

[0001] This application relates to the field of solar cells, and more particularly to a back-contact solar cell and photovoltaic module. Background Technology

[0002] HTBC (Heterojunction Tunnel Oxide Back Contact) solar cell technology is a high-efficiency crystalline silicon solar cell technology that combines the technical features of TBC (Tunnel Oxide Back Contact) cells and heterojunction cells. It is a highly promising high-performance crystalline silicon solar cell.

[0003] Although HTBC cells, as highly efficient crystalline silicon-based single-junction solar cells, have broad market application prospects, their structure still needs continuous improvement in order to further enhance their performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this application discloses a back-contact solar cell and photovoltaic module to optimize the structure of HTBC cells and improve their performance.

[0005] In a first aspect, this application provides a back-contact solar cell, comprising: A silicon substrate, wherein the back side of the silicon substrate includes an alternately arranged first region and a second region, the first region and the second region having different conductivity types; The silicon substrate has a first textured area at the junction of the back side and the side side; The silicon substrate has a second textured area at the junction of the front and side surfaces; The side planar region of the silicon substrate is sequentially provided with an inner expansion layer, a first interface passivation layer, a doped polycrystalline silicon layer, a second interface passivation layer, and a doped hydrogenated amorphous silicon layer.

[0006] In some embodiments of this application, a first step structure is provided at the junction of the back side and the side side of the silicon substrate.

[0007] In some embodiments of this application, the first step structure includes a first step and a second step, the first step includes an intersecting first sub-surface and a second sub-surface, the second step includes an intersecting third sub-surface and a fourth sub-surface, and the second sub-surface intersects with the third sub-surface.

[0008] In some embodiments of this application, the distance between the first sub-surface and the third sub-surface is D1, where 0 μm < D1 ≤ 30 μm.

[0009] In some embodiments of this application, the distance between the second sub-surface and the fourth sub-surface is H1, where 0 μm < H1 ≤ 100 μm.

[0010] In some embodiments of this application, a second step structure is provided at the junction of the front and side surfaces of the silicon substrate.

[0011] In some embodiments of this application, the second step structure includes a third step and a fourth step, the third step including intersecting fifth and sixth sub-surfaces, the fourth step including intersecting seventh and eighth sub-surfaces, and the sixth sub-surface intersecting the seventh sub-surface.

[0012] In some embodiments of this application, the distance between the fifth sub-surface and the seventh sub-surface is D2, where 0 μm < D2 ≤ 30 μm.

[0013] In some embodiments of this application, the distance between the sixth sub-surface and the eighth sub-surface is H2, where 0 μm < H2 ≤ 100 μm.

[0014] In some embodiments of this application, the surfaces of the first velvet region and the second velvet region have a pyramidal velvet structure.

[0015] In some embodiments of this application, a transparent conductive oxide layer is further disposed on the surface of the doped hydrogenated amorphous silicon layer located on the side of the silicon substrate.

[0016] Secondly, this application provides a photovoltaic module, which includes a back-contact solar cell as described in the first aspect.

[0017] Compared with the prior art, this application has at least the following beneficial effects: This application provides a back-contact solar cell and photovoltaic module. The back-contact solar cell includes a silicon substrate. A first textured region is located at the junction of the back and side surfaces of the silicon substrate, and a second textured region is located at the junction of the front and side surfaces. An inner extension layer, a first interface passivation layer, a doped polycrystalline silicon layer, a second interface passivation layer, and a doped hydrogen-coated amorphous silicon layer are sequentially disposed on the side planar region of the silicon substrate. The back-contact solar cell of this application retains the first interface passivation layer and the doped polycrystalline silicon layer in the side planar region, thereby forming a passivation structure composed of the first interface passivation layer and the doped polycrystalline silicon layer. This provides good passivation for the side edges, improving the parallel resistance and fill factor of the back-contact solar cell. Furthermore, the first and second textured regions are etched regions with a textured structure; that is, the first and second textured regions are formed by etching and modifying the original defects at the edges, providing a good amorphous silicon passivation substrate and reducing the edge defect state density. Under the combined effect of the above structures, the structure of the back-contact solar cell is optimized, and its performance is improved. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a back-contact solar cell in one embodiment of this application; Figure 2 This is a schematic diagram of the back-contact solar cell in another embodiment of this application; Figure 3 This is a schematic diagram of the back step structure in one embodiment of this application; Figure 4 This is a structural diagram of the front step structure in one embodiment of this application; Figure 5 This is a scanning electron microscope (SEM) image of a stepped structure in one embodiment of this application; Figure 6 This is a schematic diagram of a silicon substrate in one embodiment of this application; Figure 7 This is a schematic diagram of the formation of a functional film layer and a texturing mask layer in one embodiment of this application; Figure 8 This is a schematic diagram illustrating the patterning of the texturing mask layer in one embodiment of this application; Figure 9 This is a top view of a texturing mask layer in one embodiment of this application; Figure 10 This is a schematic diagram illustrating the penetration of the fabrication solution in one embodiment of this application; Figure 11 This is a schematic diagram of the structure of the battery cell after texturing in one embodiment of this application; Figure 12 This is a schematic diagram of the alumina layer and the antireflection layer in one embodiment of this application; Figure 13 This is a schematic diagram illustrating the removal of the first alumina layer in one embodiment of this application; Figure 14 This is a schematic diagram of the formation of a second interface passivation layer and a doped hydrogenated amorphous silicon layer in one embodiment of this application; Figure 15 This is a schematic diagram illustrating the patterning of the second interface passivation layer and the hydrogen-doped amorphous silicon layer in one embodiment of this application. Figure 16 This is a schematic diagram of the deposition of a transparent conductive oxide layer in one embodiment of this application; Figure 17 This is a schematic diagram of an isolation structure formed in one embodiment of this application.

[0020] Figure reference numerals: Silicon substrate-1, Second step structure-2, First step structure-3, Inner expansion layer-4, First interface passivation layer-5, Doped polycrystalline silicon layer-6, Second interface passivation layer-7, Doped hydrogenated amorphous silicon layer-8, Transparent conductive oxide layer-9, Back electrode-10, First region-11, Second region-12, First textured region-13, Second textured region-14, Front passivation layer-15, Anti-reflection layer-16, Isolation structure-17, Side planar region-20, Third step-21, Fourth step-22, First step-31, Second step-32, Textured mask layer-102, First alumina layer-103, Fifth sub-surface-211, Sixth sub-surface-212, Seventh sub-surface-221, Eighth sub-surface-222, First sub-surface-311, Second sub-surface-312, Third sub-surface-321, Fourth sub-surface-322. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0023] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0024] Furthermore, the terms "installation," "setup," "equipped with," "connection," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0025] Furthermore, the terms "first," "second," etc., are primarily used to distinguish different devices, components, or parts (which may be the same or different in specific type and construction), and are not intended to indicate or imply the relative importance or quantity of the indicated devices, components, or parts. Unless otherwise stated, "a plurality of" means two or more.

[0026] The technical solution of this application will be further described below with reference to the embodiments and accompanying drawings.

[0027] Firstly, this application provides a back-contact solar cell, with reference to... Figure 1The back-contact solar cell includes a silicon substrate 1. The back side of the silicon substrate 1 includes alternating first regions 11 and second regions 12, which have different conductivity types. In one example, the first region 11 is an N-type region, and the second region 12 is a P-type region. A first textured region 13 is present at the junction of the back side and the side surface of the silicon substrate 1; a second textured region 14 is present at the junction of the front side and the side surface of the silicon substrate 1. The side planar region 20 of the silicon substrate 1 is sequentially provided with an inner expansion layer 4, a first interface passivation layer 5, a doped polycrystalline silicon layer 6, a second interface passivation layer 7, and a doped hydrogenated amorphous silicon layer 8. The back-contact solar cell of this application retains a first interface passivation layer and a doped polycrystalline silicon layer in the side planar region, thereby forming a passivation structure composed of the first interface passivation layer and the doped polycrystalline silicon layer. This provides excellent passivation for the side edges, improving the parallel resistance and fill factor of the back-contact solar cell. Furthermore, the first textured region and the second textured region are regions with textured structures formed by etching. That is, the first textured region and the second textured region are formed after etching and modifying the original defects at the edges, utilizing the excellent passivation effect of amorphous silicon to reduce the defect state density at the front and back edges of the back-contact solar cell. Under the combined effect of the above structures, the structure of the back-contact solar cell is optimized, and its performance is improved.

[0028] In one alternative implementation, refer to Figure 2 , Figure 2 This is a schematic diagram of a back-contact solar cell in another embodiment of this application, specifically a schematic diagram of a back-contact solar cell placed with its back side facing up and its front side facing down. A first step structure 3 is provided at the junction of the back side and the side of the silicon substrate, and a first textured area 13 is located within the first step structure 3. Because the solar cell of this application has step structures formed on both the front and back sides, it provides more force points for clamping the silicon substrate, thereby dispersing the force exerted on the silicon substrate during clamping and reducing the risk of microcracks and fragmentation caused by forces from both sides of the clamp when the edge of the solar cell contacts the clamp.

[0029] In one alternative implementation, refer to Figure 3 The first step structure 3 includes a first step 31 and a second step 32. The first step 31 includes an intersecting first sub-surface 311 and a second sub-surface 312, and the second step 32 includes an intersecting third sub-surface 321 and a fourth sub-surface 322. The second sub-surface 312 intersects with the third sub-surface 321. Compared with the zero-edge structure of traditional solar cell edges, the first and second steps on the back edge of the solar cell in this application provide more force points for clamping the silicon substrate due to the step structure formed on the front and back sides. This disperses the force on the silicon substrate during clamping and reduces the risk of microcracks and fragments caused by the forces from both sides of the clamp when the edge of the solar cell contacts the clamp.

[0030] It should be noted that, Figure 3 The first and second steps shown are for illustrative purposes only. The textured surface is a microstructure; in reality, both the first and second sub-surfaces can have a textured surface. Furthermore... Figure 3 The filled area shown (i.e., the side planar area 20) is used to indicate the area where the back contact battery is located and does not represent the actual film structure.

[0031] In one alternative implementation, refer to Figure 3 The distance between the first sub-surface 311 and the third sub-surface 321 is D1, where 0 μm < D1 ≤ 30 μm. For example, D1 can be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, or 30 μm. Within the above range, D1 can maximize the passivation area of ​​the side surface while reducing the occurrence of edge chipping of the solar cell.

[0032] In one alternative implementation, refer to Figure 3 The distance between the second sub-surface 312 and the fourth sub-surface 322 is H1, where 0 μm < H1 ≤ 100 μm. For example, H1 can be 10 μm, 20 μm, 30 μm, 50 μm, 80 μm, or 1000 μm. Within the above range, H1 can maximize the passivation area of ​​the side surface while reducing the occurrence of edge chipping of the solar cell.

[0033] In this application, references Figure 3 D1 refers to the distance between the lowest point of the first sub-surface 311 and the third sub-surface 321; H1 refers to the distance between the highest point of the second sub-surface 312 and the fourth sub-surface 322.

[0034] In one alternative implementation, refer to Figure 2 A second step structure 2 is provided at the junction of the front and side surfaces of the silicon substrate 1, and the second textured area 14 is located within the second step structure 2. Because the solar cell of this application has step structures formed on the front and back surfaces, it provides more force points for clamping the silicon substrate, thereby dispersing the force exerted on the silicon substrate during clamping. This further reduces the risk of microcracks and fragments caused by forces from both sides of the clamp when the edge of the solar cell contacts the clamp.

[0035] In one alternative implementation, refer to Figure 4The second step structure 2 includes a third step 21 and a fourth step 22. The third step 21 includes intersecting fifth sub-surfaces 211 and 212, and the fourth step 22 includes intersecting seventh sub-surfaces 221 and 222. The sixth sub-surface 212 intersects with the seventh sub-surface 221. Compared with the traditional single-angled edge structure of solar cells, the third and fourth steps of the front edge of the solar cell in this application provide more force points for clamping the silicon substrate due to the stepped structure formed on the front and back sides. This disperses the force on the silicon substrate during clamping and further reduces the risk of microcracks and fragments caused by the forces from both sides of the clamp when the edge of the solar cell contacts the clamp.

[0036] It should be noted that, Figure 4 The third and fourth steps shown are for illustrative purposes only. The velvety structure is a microstructure; in reality, the fifth and sixth sub-surfaces can also have a velvety structure. Furthermore... Figure 4 The filled area shown (i.e., the side planar area 20) is used to indicate the area where the back contact battery is located and does not represent the actual film structure.

[0037] In one alternative implementation, refer to Figure 4 The distance between the fifth sub-surface 211 and the seventh sub-surface 221 is D2, where 0 μm < D2 ≤ 30 μm. For example, D2 can be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, or 30 μm. Within the above range, D2 can maximize the passivation area of ​​the side surface while reducing the occurrence of edge chipping of the solar cell.

[0038] In one alternative implementation, refer to Figure 4 The distance between the sixth sub-surface 212 and the eighth sub-surface 222 is H2, where 0 μm < H2 ≤ 100 μm. For example, H2 can be 10 μm, 20 μm, 30 μm, 50 μm, 80 μm, or 100 μm. Within the above range, H2 can maximize the passivation area of ​​the side surface while reducing the occurrence of edge chipping of the solar cell.

[0039] In this application, references Figure 4 D2 refers to the distance between the lowest point of the fifth sub-surface 211 and the seventh sub-surface 221; H2 refers to the distance between the highest point of the sixth sub-surface 212 and the eighth sub-surface 222.

[0040] Figure 5 This is a SEM image of the step structure in one embodiment of this application, from... Figure 5 It can be seen that the junction between the back side and the side side of the silicon substrate has a stepped structure, specifically the first stepped structure 3.

[0041] In one alternative implementation, refer to Figure 1 A transparent conductive oxide layer 9 is also provided on the surface of the hydrogen-doped amorphous silicon layer 8 located on the side of the silicon substrate 1, which can physically protect the passivation layer on the side, thereby isolating moisture and other substances from eroding the solar cell; in another optional embodiment, the transparent conductive oxide layer may not be provided on the surface of the hydrogen-doped amorphous silicon layer 8 located on the side of the silicon substrate 1.

[0042] In one alternative implementation, refer to Figure 1 The surfaces of the first velvet region 13 and the second velvet region 14 have a pyramid velvet structure, which can be formed as a result of velveting after laser film opening.

[0043] In one alternative implementation, refer to Figure 1 The front side of the silicon substrate 1 is provided with a front passivation layer 15 and an anti-reflection layer 16, and the front side of the silicon substrate 1 has a front textured structure.

[0044] The material of the first interface passivation layer in this application can include a variety of dielectric materials, such as at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide, or titanium oxide. Specifically, the first interface passivation layer can be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent interface passivation performance, which can minimize the recombination loss of minority carriers on the semiconductor substrate surface, and is a thin film with excellent reliability and durability for subsequent high-temperature processes. To better provide interface passivation for the substrate, the thickness of the first interface passivation layer can be 0.8 nm to 5 nm. For example, the thickness of the first interface passivation layer can be 0.8 nm, 1.0 nm, 1.2 nm, 1.5 nm, 2 nm, 3 nm, 4 nm, 5 nm, etc. However, this application is not limited to these values, and the thickness of the first interface passivation layer can have various values. The first interface passivation layer can also have a pinhole channel function, allowing carriers in the crystalline silicon solar cell to move freely. The selective passage of majority carriers is generated by heavily doped polycrystalline silicon, which helps to reduce the recombination loss of minority carriers. In addition, the first interface passivation layer can be used as a diffusion barrier layer to prevent the dopant in the doped polysilicon layer from diffusing into the semiconductor substrate.

[0045] The thickness of the doped polycrystalline silicon layer is 30nm~500nm, and the doping concentration is 1×10⁻⁶. 19 atoms / cm 3 ~9.9×10 20 atoms / cm 3 It can be doped with phosphorus; The thickness of the second interface passivation layer is 0.1 nm to 30 nm, and the microstructure factor R is 0.01 to 0.99. The thickness of the hydrogenated amorphous silicon layer ranges from 5 nm to 100 nm, and the doping concentration is 1 × 10⁻⁶. 17 atoms / cm 3 ~9.9×10 19 atoms / cm 3 It can be doped with boron; The transparent conductive oxide layer is made of indium tin oxide (ITO), with a thickness of 20 nm to 150 nm, a sheet resistance of 10 Ω / sq to 90 Ω / sq, and a carrier mobility of 10 cm² / V·s to 120 cm² / V·s. The materials for the back electrode include silver; The material of the front passivation layer includes aluminum oxide, with a thickness of 0.1 nm to 100 nm; The materials of the antireflective layer include, but are not limited to, silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 30 nm to 180 nm.

[0046] This application does not impose any particular limitation on the preparation method of back-contact solar cells. Exemplarily, it may include the following steps: Step A, Reference Figure 6 A silicon substrate 1 is provided, and the thickness of the silicon substrate is not particularly limited, for example, it can be 100μm~220μm; Step B: A first interface passivation layer 5 and an intrinsic polycrystalline silicon layer are deposited on the back and side of the silicon substrate 1. The intrinsic polycrystalline silicon layer is subjected to phosphorus doping and high-temperature annealing crystallization treatment to form a doped polycrystalline silicon layer 6. Phosphorus atoms diffuse towards the silicon substrate 1 during the high-temperature annealing process, forming an inner diffusion layer 4 between the silicon substrate 1 and the first interface passivation layer 5. At the same time, a phosphosilicate glass (PSG) layer is formed on the back of the doped polycrystalline silicon layer 6. The PSG layer is removed, and a silicon nitride layer is deposited on the back of the doped polycrystalline silicon layer 6 as a texturing mask layer 102 with a thickness of 20nm~120nm to obtain... Figure 7 The structure shown; Step C: Use a localized patterning laser to remove the texturing mask layer 102 on a portion of the back side and the texturing mask layer 102 on the front side of the battery to form... Figure 8 and Figure 9 The structure is shown. The laser can be at least one of nanosecond, picosecond, or femtosecond lasers, and the wavelength can be any of infrared, visible, or ultraviolet lasers; the laser spot size is 20μm×20μm to 400μm×400μm.

[0047] Step D, see Figure 10 The texturing solution is injected into the semi-finished solar cell in the direction indicated by the arrow, forming a texturized structure on the front, back, and side opening areas of the silicon substrate 1. Then, it is sequentially washed with an alkaline solution, followed by water washing, and then acid washing with an HF-containing acid solution. After further washing and drying, the desired result is obtained. Figure 11 The structure shown.

[0048] Step E: Using ALD process, a first aluminum oxide layer 103 is formed on the back and sides of the semi-finished solar cell. Simultaneously, a front passivation layer 15 is formed on the front side of the silicon substrate 1, with a deposition temperature of 210℃~290℃. Then, using PECVD process, an anti-reflection layer 16 is deposited on the surface of the front passivation layer 15 to obtain... Figure 12 The structure shown; Step F: Using a chain wet cleaning machine, remove the first alumina layer 103 on the back and sides, and the anti-reflective coating around the edges of the back / sides. The cleaning solution is a mixed solution of HCl and HF, wherein the concentration of HCl ranges from 0.2wt% to 10wt%, and the concentration of HF ranges from 0.2wt% to 30wt%, resulting in... Figure 13 The structure shown; Step G: Using PECVD technology, a second interface passivation layer 7 and a doped hydrogenated amorphous silicon layer 8 are sequentially deposited on the back and side of the semi-finished solar cell. The deposition temperature is 160℃~240℃. The doping type of the doped hydrogenated amorphous silicon layer 8 is opposite to that of the doped polycrystalline silicon layer 6. The thickness of the doped hydrogenated amorphous silicon layer 8 is 5nm~100nm, and the effective doping concentration is 1×10⁻⁶. 17 / cm 3 ~9.9×10 19 / cm 3 ,get Figure 14 The structure shown; Step H: Pattern the second interface passivation layer 7 and the hydrogen-doped amorphous silicon layer 8 in the first region 11 to obtain... Figure 15 The structure shown; Step 1: Deposit a transparent conductive oxide layer 9 on the back of the solar cell. The transparent conductive oxide layer 9 can be formed using a plate-type physical vapor deposition (PVD) apparatus. In one example, the transparent conductive oxide layer 9 can be an indium tin oxide film (where In₂O₃:SnO₂ = 80~90:10~20, by mass ratio), resulting in... Figure 16 The structure shown; Step J: Perform isolation trenching on the transparent conductive oxide layer 9. The treatment area for isolation trenching is located in the first region 11, thereby forming at least one isolation structure 17 in each first region 11, resulting in... Figure 17 The structure shown; Step K: Metallization is performed on the back side of the solar cell to form the back electrode 10, resulting in... Figure 1 The back-contact solar cell shown.

[0049] In step H, the patterning process can be performed using a laser, specifically a green picosecond laser with a wavelength of 532 nm and an energy density of 10 mJ / cm².2 ~1000 mJ / cm 2 After graphical processing, a chain wet cleaning machine or a tank wet cleaning machine can be used to clean the semi-finished solar cells.

[0050] In step J, the isolation trenching can be performed using laser etching or wet etching processes. For example, an acidic etching paste can be used for screen printing, followed by drying and cleaning to selectively etch away a portion of the transparent conductive oxide layer 9 in the first region 11, forming a patterned isolation structure 17 with a width of 10 μm to 200 μm. This application does not have any particular limitation on the acidic etching paste, as long as it can etch the transparent conductive oxide layer.

[0051] In step K, during the metallization process, an electrode paste can be applied to the surface of the transparent conductive oxide layer 9 in the first region 11 and the second region 12, and after curing and photoinjection, a back electrode 10 is formed. The electrode paste can be a silver-coated copper paste (silver content of 10 wt%~90 wt%, balance copper). The equipment for curing and photoinjection can be a chain furnace or a cassette furnace.

[0052] This application provides a photovoltaic module, which includes a back-contact solar cell as described in the first aspect.

[0053] This application also provides a photovoltaic module for converting received light energy into electrical energy and transmitting it to an external load. The photovoltaic module includes: at least one cell string, which is composed of multiple solar cells connected together; an encapsulating film for covering the surface of the cell string; and a cover plate for covering the surface of the encapsulating film facing away from the cell string.

[0054] The foregoing has provided a detailed description of a back-contact solar cell and photovoltaic module disclosed in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core inventive points of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon substrate, wherein the back side of the silicon substrate includes an alternately arranged first region and a second region, the first region and the second region having different conductivity types; The silicon substrate has a first textured area at the junction of the back side and the side side; The silicon substrate has a second textured area at the junction of the front and side surfaces; The side planar region of the silicon substrate is sequentially provided with an inner expansion layer, a first interface passivation layer, a doped polycrystalline silicon layer, a second interface passivation layer, and a doped hydrogenated amorphous silicon layer.

2. The back-contact solar cell according to claim 1, characterized in that, A first step structure is provided at the junction of the back side and the side side of the silicon substrate.

3. The back-contact solar cell according to claim 2, characterized in that, The first step structure includes a first step and a second step. The first step includes an intersecting first sub-surface and a second sub-surface. The second step includes an intersecting third sub-surface and a fourth sub-surface. The second sub-surface intersects with the third sub-surface.

4. The back-contact solar cell according to claim 3, characterized in that, The distance between the first sub-surface and the third sub-surface is D1, where 0 μm < D1 ≤ 30 μm.

5. The back-contact solar cell according to claim 3, characterized in that, The distance between the second sub-surface and the fourth sub-surface is H1, where 0 μm < H1 ≤ 100 μm.

6. The back-contact solar cell according to claim 1, characterized in that, A second step structure is provided at the junction of the front and side surfaces of the silicon substrate.

7. The back-contact solar cell according to claim 6, characterized in that, The second step structure includes a third step and a fourth step. The third step includes an intersecting fifth sub-surface and a sixth sub-surface. The fourth step includes an intersecting seventh sub-surface and an eighth sub-surface. The sixth sub-surface intersects with the seventh sub-surface.

8. The back-contact solar cell according to claim 7, characterized in that, The distance between the fifth sub-surface and the seventh sub-surface is D2, where 0 μm < D2 ≤ 30 μm.

9. The back-contact solar cell according to claim 7, characterized in that, The distance between the sixth sub-surface and the eighth sub-surface is H2, where 0 μm < H2 ≤ 100 μm.

10. The back-contact solar cell according to claim 1, characterized in that, The surfaces of the first and second velvet regions have a pyramidal velvet structure.

11. The back-contact solar cell according to claim 1, characterized in that, A transparent conductive oxide layer is also disposed on the surface of the hydrogenated amorphous silicon layer located on the side of the silicon substrate.

12. A photovoltaic module, characterized in that, The photovoltaic module includes the back-contact solar cell as described in any one of claims 1 to 11.

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