Contact hole etching method and insulated gate bipolar transistor

Abstract

The invention provides a contact hole etching method and an insulated gate bipolar transistor. The method comprises the following steps: carrying out first etching on a dielectric layer by adopting first etching gas until a polycrystalline silicon layer is exposed; the first etching gas comprises fluorocarbon gas, O2 and Ar; performing second etching on the polycrystalline silicon layer by adopting second etching gas; the second etching gas comprises CF4, O2, HBr and Cl2; the first etching mode and the second etching mode are both inductively coupled plasma etching. According to the invention, through combined control of the etching gas type and bias voltage of inductively coupled plasma etching, only flexible and accurate control of different process steps in the same reaction chamber is needed, namely, the contact hole with a smooth side wall and without concave-convex is obtained through efficient etching, so that the production efficiency, the yield and the flexibility are improved, and the production cost is reduced. Meanwhile, pollution and interface damage risks caused by exposure of the substrate in the environment are avoided, the probability of contact resistance and device failure is reduced, and the stability of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for etching contact holes and an insulated gate bipolar transistor. Background Technology

[0002] As a core device in modern power electronic systems, the precision and reliability of the contact etching process for Insulated Gate Bipolar Transistors (IGBTs) directly determine the device's conduction characteristics, switching losses, and long-term stability. In the manufacturing process of IGBTs, contact etching is a crucial step in determining the device's electrical performance and reliability. Contact etching requires precisely opening holes in the dielectric layer (typically silicon dioxide, SiO2) to expose the underlying polysilicon (Poly-Si) gate, simultaneously achieving high-precision pattern transfer between the silicon dioxide dielectric layer and the underlying polysilicon gate, while ensuring interface integrity and low contact resistance. However, the Si-O bond energy in silicon dioxide is as high as 799 kJ / mol, while the Si-Si bond energy in polysilicon is only 326 kJ / mol. The fundamental differences in their chemical activity, bond strength, and physical properties make it difficult for a single etching process to simultaneously meet the processing requirements of both materials.

[0003] CN111653476A discloses a method for etching contact holes, comprising: forming an interlayer film mainly composed of silicon dioxide on a semiconductor substrate; defining the formation areas of contact holes on a polysilicon gate and on an active region using photolithography; performing a first etching of the interlayer film using a silicon dioxide etching process with high etch selectivity to polysilicon until the top surface of the polysilicon gate is exposed; performing a second etching of the polysilicon gate using a polysilicon etching process with high etch selectivity to silicon dioxide to etch to a set depth; and performing a third etching of the interlayer film using a silicon dioxide etching process with high etch selectivity to polysilicon until the top surface of the active region is exposed. This invention also discloses a contact hole etching structure. This invention increases the etching amount of polysilicon, thereby increasing the contact area between the contact hole and the polysilicon, significantly reducing the contact resistance between the contact hole and the polysilicon gate, and ensuring the resistance of the polysilicon gate and the performance of the entire circuit.

[0004] CN10305043A discloses a method for etching contact holes, comprising the following steps: depositing an interlayer dielectric on a wafer; planarizing the interlayer dielectric; performing contact hole photolithography; performing wet etching of the contact holes to remove 30% to 70% of the thickness of the interlayer dielectric; and performing dry etching of the contact holes. This invention employs a two-step etching process. The first step uses wet etching, utilizing the isotropic nature of etching to create a bowl-shaped morphology for the steps of the interlayer dielectric at the contact holes. The second step uses dry etching, utilizing the anisotropic nature of dry etching to make the step morphology nearly right-angled. This combination of wet and dry etching results in smoother steps at the contact holes, without large sharp corners, preventing voids in the metal layer at the sharp corners of the contact holes, while ensuring sufficient thickness of the interlayer dielectric at the steps of the polysilicon gate.

[0005] CN102456567A discloses a plasma dry etching method for contact holes. First, a photolithographic pattern of the contact hole is formed on the dielectric layer of the wafer. Then, plasma dry etching is performed on the dielectric layer according to the photolithographic pattern of the contact hole. During the etching process, the distance between the upper electrode plate and the lower electrode plate is not fixed but is in a dynamic process. When etching begins, the physical bombardment effect of the plasma is relatively weak to avoid the photolithographic pattern from peeling off. As etching progresses, the physical bombardment effect of the plasma is gradually strengthened to prevent contact holes with large aspect ratios from being blocked, thereby improving the etching accuracy of the contact holes.

[0006] Therefore, it is of great significance to provide a simple method that can achieve high-quality contact hole etching. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the present invention aims to provide a method for etching contact holes and an insulated gate bipolar transistor. This invention employs inductively coupled plasma etching, a method that, within the same reaction chamber, precisely controls the type of etching gas and the bias voltage to approximate or achieve the etching conditions required by each of the two materials, thereby achieving efficient etching of contact holes and smoothing of the contact hole sidewalls.

[0008] To achieve this objective, the present invention adopts the following technical solution:

[0009] In a first aspect, the present invention provides a method for etching contact holes, the method comprising:

[0010] (1) A polysilicon layer and a dielectric layer are sequentially formed on the surface of a substrate, and then a patterned photoresist layer is formed on the surface of the dielectric layer to expose the contact hole formation area and place it in an inductively coupled plasma reaction chamber.

[0011] (2) The dielectric layer of the contact hole formation area is etched by a first etching gas until the polysilicon layer is exposed; the first etching gas includes fluorine gas, O2 and Ar; the source power and bias power of the first etching are each 400W~600W independently.

[0012] (3) O2 and N2 are introduced to clean the reaction chamber;

[0013] (4) The polysilicon layer in the contact hole formation area is etched a second time using a second etching gas; the second etching gas includes CF4, O2, HBr and Cl2; the source power of the second etching is 1000W~1500W and the bias power is 400W~600W.

[0014] This invention employs inductively coupled plasma etching, a method that precisely controls the type of etching gas and the bias voltage to approximate or achieve the etching conditions required by each of the two materials. The dielectric layer is etched using a physical etching method with high bias voltage and fluorocarbon gas, while the polysilicon layer is etched using a chemical etching method with low bias voltage and bromine-based gas. This allows for flexible and precise control of different process steps within the same reaction chamber, achieving highly efficient etching of contact holes. Furthermore, the control of chamber contamination and gas residue between the two steps improves etching quality and ensures smooth contact hole sidewalls.

[0015] The etching method provided by this invention eliminates the need to transfer the substrate between different chambers to switch etching modes, thereby improving production efficiency, yield, and flexibility. It also avoids the risk of contamination and interface damage caused by substrate exposure to the environment, reduces contact resistance and the probability of device failure, improves device stability, reduces the number of devices, and lowers costs.

[0016] Preferably, in step (2), the first etching gas includes any one or a combination of at least two of C4F6, C4F8, or C3F6.

[0017] Preferably, in step (2), the flow rate ratio of fluorocarbon gas, O2 and Ar in the first etching gas is 1:(0.5~1):(8~12).

[0018] Preferably, in step (2), during the first etching process, the flow rate of the fluorocarbon gas is 5 sccm to 50 sccm.

[0019] Preferably, in step (2), during the first etching process, the flow rate of O2 is 5 sccm to 50 sccm.

[0020] Preferably, in step (2) during the first etching process, the flow rate of Ar is 50 sccm to 500 sccm.

[0021] Preferably, in step (2), during the first etching process, the pressure in the reaction chamber is 1 mTorr ~ 20 mTorr.

[0022] Preferably, in step (3), the flow rate ratio of N2 to O2 is (2~5):1, and the flow rate of O2 is 4 sccm~5 sccm.

[0023] Preferably, during the cleaning process described in step (3), the pressure inside the reaction chamber is 5 mTorr to 15 mTorr.

[0024] Preferably, the cleaning temperature in step (3) is 30°C to 50°C.

[0025] Preferably, in step (4), the flow rate ratio of CF4, O2, HBr and Cl2 in the second etching gas is 1:(0.5~2):(8~13):(8~13).

[0026] Preferably, in step (4), the flow rate of CF4 in the second etching gas is 5 sccm to 50 sccm.

[0027] Preferably, in step (4), the flow rate of O2 in the second etching gas is 2 sccm to 50 sccm.

[0028] Preferably, in step (4), the flow rate of HBr in the second etching gas is 40 sccm to 500 sccm.

[0029] Preferably, in step (4), the flow rate of Cl2 in the second etching gas is 40 sccm to 500 sccm.

[0030] Preferably, in step (4) during the second etching process, the pressure in the reaction chamber is 1 mTorr ~ 20 mTorr.

[0031] Preferably, in step (2), the source power of the first etching is the same as the bias power.

[0032] Preferably, the temperatures of the first etching in step (2) and the second etching in step (4) are each independently 30°C to 40°C.

[0033] Preferably, the etching method further includes using a third etching gas to remove the patterned photoresist layer through the third etching; the third etching gas includes O2 and He.

[0034] Preferably, during the third etching process, the pressure inside the reaction chamber is 1 mTorr to 20 mTorr.

[0035] Preferably, during the third etching process, the source power is 1000W~1500W.

[0036] Preferably, the flow rate of the O2 is 150 sccm to 300 sccm.

[0037] Preferably, the flow rate of He is 0~100 sccm.

[0038] In a second aspect, the present invention provides an insulated gate bipolar transistor, wherein the contact holes of the insulated gate bipolar transistor are prepared using the etching method described in the first aspect.

[0039] In this invention, the terms "first aspect," "second aspect," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features. Moreover, "first," "second," etc., serve only as a non-exhaustive enumeration and should be understood not to constitute a closed limitation on quantity.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] (1) The present invention adopts inductively coupled plasma etching as an etching method. By precisely controlling the type of etching gas and the bias voltage, the etching conditions required by the two materials can be approximated or achieved. Only different process steps in the same reaction chamber need to be flexibly and precisely controlled, thus achieving efficient etching of the contact hole. The sidewall of the etched contact hole is smooth, and there are no bumps at the interface between the dielectric layer and the polysilicon layer.

[0042] (2) The etching method provided by the present invention improves the etching quality by coordinating the control of chamber contamination and gas residue between the two etching steps.

[0043] (3) The etching method provided by the present invention does not require the substrate to be transferred between different chambers to switch etching modes, which improves production efficiency, yield and flexibility, and can also avoid the risk of pollution and interface damage caused by substrate exposure in the environment, reduce contact resistance and device failure probability, and improve device stability. Attached Figure Description

[0044] Figure 1 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 1 of this application.

[0045] Figure 2 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 2 of this application.

[0046] Figure 3 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 3 of this application.

[0047] Figure 4This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 4 of this application.

[0048] Figure 5 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 5 of this application.

[0049] Figure 6 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 6 of this application.

[0050] Figure 7 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 7 of this application.

[0051] Figure 8 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 8 of this application.

[0052] Figure 9 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Embodiment 9 of this application.

[0053] Figure 10 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Comparative Example 1 of this application.

[0054] Figure 11 This is a SEM image of the longitudinal cross-section of the contact hole obtained by etching in Comparative Example 2 of this application. Detailed Implementation

[0055] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. In this invention, "a combination of at least two" means, unless otherwise specified, a quantity greater than or equal to two. For example, "any combination of one or at least two" means one or more of two. It is understood that when referring to "a combination of at least two," it means any suitable combination of multiple items, i.e., a combination of "at least two" items carried out in a manner that does not conflict with and allows for the implementation of the invention.

[0057] In the description of this invention, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this invention, "a plurality of" means two or more, unless otherwise explicitly defined.

[0058] The "range" disclosed in this invention can be defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of the specific range. This type of range definition can include or exclude endpoints; any endpoint can be independently included or excluded, and they can be arbitrarily combined, meaning any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60~120 and 80~110 are listed for specific parameters, it is understood that ranges of 60~110 and 80~120 are also expected. Furthermore, if minimum range values ​​1 and 2 are listed, and maximum range values ​​3, 4, and 5 are also listed, then the following ranges are all expected: 1~3, 1~4, 1~5, 2~3, 2~4, and 2~5. In this invention, unless otherwise stated, the numerical range "a~b" represents a shortened representation of any combination of real numbers between a and b, where a and b are real numbers. For example, the numerical range "0~5" indicates that all real numbers between "0" and "5" have been listed in this article; "0~5" is simply a shortened representation of these numerical combinations. Furthermore, when a parameter is described as an integer ≥2, it is equivalent to listing integers such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc. For instance, when a parameter is described as an integer selected from "2~10", it is equivalent to listing the integers 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0059] Unless otherwise specified, all embodiments and optional embodiments of the present invention can be combined with each other to form new technical solutions.

[0060] In one specific embodiment, the present invention provides an etching method for contact holes, the method comprising:

[0061] (1) A polysilicon layer and a dielectric layer are sequentially formed on the surface of a substrate, and then a patterned photoresist layer is formed on the surface of the dielectric layer to expose the contact hole formation area and place it in an inductively coupled plasma reaction chamber.

[0062] (2) The dielectric layer of the contact hole formation region is etched using a first etching gas until the polysilicon layer is exposed; the first etching gas includes fluorocarbon gas, O2 and Ar; the source power and bias power of the first etching are each independently 400W~600W, for example, 400W, 420W, 440W, 460W, 480W, 500W, 520W, 540W, 560W, 580W or 600W;

[0063] (3) O2 and N2 are introduced to clean the reaction chamber;

[0064] (4) The polysilicon layer in the contact hole formation region is etched a second time using a second etching gas; the second etching gas includes CF4, O2, HBr and Cl2; the source power of the second etching is 1000W~1500W, for example, it can be 1000W, 1050W, 1100W, 1150W, 1200W, 1250W, 1300W, 1350W, 1400W, 1450W or 1500W; the bias power is 400W~600W, for example, it can be 400W, 420W, 440W, 460W, 480W, 500W, 520W, 540W, 560W, 580W or 600W.

[0065] In this invention, the dielectric layer is made of silicon dioxide or silicon nitride.

[0066] This invention employs inductively coupled plasma etching, a method that precisely controls the type of etching gas and the bias voltage to approximate or achieve the etching conditions required by each of the two materials. The invention utilizes a physical etching method with high bias voltage and fluorine gas to etch dielectric layers with higher bond energy and greater thickness, and a chemical etching method with low bias voltage and bromine-based gas to etch polysilicon layers. By flexibly and precisely controlling different process steps within the same reaction chamber, efficient etching of contact holes can be achieved.

[0067] The etching method provided by this invention not only allows for flexible and precise control of the etching gas and bias power, but also effectively controls chamber contamination and residue. By introducing N2 and O2 into the chamber, byproducts are removed, preventing the chamber walls, electrodes, spray heads, and other surfaces from adsorbing fluoropolymers and byproducts from the first etching gas after etching the dielectric layer. When the second etching gas is used to etch polysilicon subsequently, the fluoropolymers and byproducts desorb and participate in the reaction, severely disrupting the selectivity of the underlying thin gate oxide layer during polysilicon etching, thereby reducing defects and eliminating the step between the etched polysilicon layer and the dielectric layer, resulting in smoother contact hole sidewalls.

[0068] The etching method provided by this invention eliminates the need to transfer the substrate between different chambers to switch etching modes, thereby improving production efficiency, yield, and flexibility. It also avoids the risk of contamination and interface damage caused by substrate exposure to the environment, reduces contact resistance and the probability of device failure, and improves device stability.

[0069] In some embodiments, in step (2), the first etching gas includes any one or a combination of at least two of C4F6, C4F8 or C3F6. Typical but non-limiting combinations include combinations of C4F6 and C4F8, combinations of C3F6 and C4F6, or combinations of C4F8 and C3F6.

[0070] This invention uses a fluorine-based first etching gas to perform the first etching of the dielectric layer. In the first etching gas, maintaining a suitable flow ratio between fluorine-carbon gas, O2, and Ar is beneficial to the simultaneous improvement of etching rate and etching quality. When the proportion of fluorine-carbon gas increases, the etching rate increases, but it will reduce the polysilicon to silicon dioxide selectivity ratio, resulting in over-etching of silicon dioxide, thinning of the gate oxide layer, and increasing the risk of device short circuit or leakage. When the proportion of O2 is appropriately increased, it can increase the polysilicon to silicon dioxide selectivity ratio, but it will reduce the etching quality and result in poor contact hole smoothness.

[0071] In some embodiments, in step (2), the flow rate ratio of fluorocarbon gas, O2 and Ar in the first etching gas is 1:(0.5~1):(8~12), for example, it can be 1:0.5:8, 1:0.6:8.5, 1:0.7:9, 1:0.8:10, 1:0.9:11 or 1:1:12.

[0072] In some embodiments, during the first etching process in step (2), the flow rate of the fluorocarbon gas is 0 sccm to 50 sccm, for example, it can be 5 sccm, 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm or 50 sccm.

[0073] In some implementations, during the first etching process in step (2), the flow rate of O2 is 0 sccm to 50 sccm, for example, it can be 5 sccm, 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm or 50 sccm.

[0074] In some implementations, during the first etching process in step (2), the flow rate of Ar is 50 sccm to 500 sccm, for example, it can be 50 sccm, 100 sccm, 200 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm or 500 sccm.

[0075] In some embodiments, during the first etching process in step (2), the pressure in the reaction chamber is 1 mTorr to 20 mTorr, for example, it can be 1 mTorr, 2 mTorr, 4 mTorr, 6 mTorr, 8 mTorr, 10 mTorr, 12 mTorr, 14 mTorr, 16 mTorr, 18 mTorr or 20 mTorr.

[0076] In some implementations, the flow rate ratio of N2 and O2 introduced in step (3) is (2~5):1, for example, it can be 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1 or 5:1, and the flow rate of O2 introduced is 4sccm~5sccm, for example, it can be 4sccm, 4.2sccm, 4.4sccm, 4.6sccm, 4.8sccm or 5sccm.

[0077] In some embodiments, during the cleaning process described in step (3), the pressure in the reaction chamber is 5mTorr to 15mTorr, for example, it can be 5mTorr, 7mTorr, 9mTorr, 11mTorr, 13mTorr or 15mTorr.

[0078] In some embodiments, the cleaning temperature in step (3) is 30°C to 50°C, for example, it can be 30°C, 35°C, 40°C, 45°C or 50°C.

[0079] This invention uses a bromine-based gas including HBr to perform a second etching on a polycrystalline silicon layer. In the second etching gas, the etching rate increases when the CF4 / Cl2 ratio increases; and the etching angle decreases and the slope of the contact hole sidewall increases when the O2 or HBr ratio increases.

[0080] In some embodiments, in step (4), the flow rate ratio of CF4, O2, HBr and Cl2 in the second etching gas is 1:(0.5~2):(8~13):(8~13), for example, it can be 1:0.5:8:8, 1:0.7:8.5:8, 1:0.9:9:9.5, 1:1:9.5:10, 1:1.2:10:10.5, 1.4:10.5:11, 1:1.6:11:11.5, 1:1.8:12:12 or 1:2:13:13.

[0081] In some embodiments, in step (4), the flow rate of CF4 in the second etching gas is 5 sccm to 50 sccm, for example, it can be 5 sccm, 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm or 50 sccm.

[0082] In some embodiments, in step (4), the flow rate of O2 in the second etching gas is 2 sccm to 50 sccm, for example, it can be 2 sccm, 5 sccm, 10 sccm, 15 sccm, 20 sccm, 25 sccm, 30 sccm, 35 sccm, 40 sccm, 45 sccm or 50 sccm.

[0083] In some embodiments, in step (4), the flow rate of HBr in the second etching gas is 40 sccm to 500 sccm, for example, it can be 40 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm or 500 sccm.

[0084] In some embodiments, in step (4), the flow rate of Cl2 in the second etching gas is 40 sccm to 500 sccm, for example, it can be 40 sccm, 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm or 500 sccm.

[0085] In some embodiments, during the second etching process in step (4), the pressure in the reaction chamber is 1 mTorr to 20 mTorr, for example, it can be 1 mTorr, 2 mTorr, 4 mTorr, 6 mTorr, 8 mTorr, 10 mTorr, 12 mTorr, 14 mTorr, 16 mTorr, 18 mTorr or 20 mTorr.

[0086] In some implementations, the source power of the first etching in step (2) is the same as the bias power.

[0087] In some embodiments, the temperatures of the first etching in step (2) and the second etching in step (4) are each independently 30°C to 40°C, for example, 30°C, 32°C, 34°C, 36°C, 38°C, or 40°C. In this invention, only a low temperature of 30°C to 40°C is required to achieve efficient etching of the contact hole, which is less likely to cause photoresist mask flow, avoids pattern transmission errors, and is more conducive to improving the etching accuracy of the contact hole.

[0088] In some embodiments, the etching method further includes using a third etching gas to remove the patterned photoresist layer by third etching; the third etching gas includes O2 and He.

[0089] In some embodiments, the third etching includes inductively coupled plasma etching. In this invention, the photoresist removal step is also performed in an inductively coupled plasma reaction chamber, further improving production efficiency while avoiding the need to switch devices between different reaction chambers.

[0090] In some embodiments, during the third etching process, the pressure in the reaction chamber is 1 mTorr to 20 mTorr, for example, it can be 1 mTorr, 2 mTorr, 4 mTorr, 6 mTorr, 8 mTorr, 10 mTorr, 12 mTorr, 14 mTorr, 16 mTorr, 18 mTorr or 20 mTorr.

[0091] In some embodiments, during the third etching process, the source power is 1000W to 1500W, for example, it can be 1000W, 1050W, 1100W, 1150W, 1200W, 1250W, 1300W, 1350W, 1400W, 1450W or 1500W.

[0092] In some implementations, the flow rate of O2 is 150 sccm to 300 sccm, for example, it can be 150 sccm, 175 sccm, 200 sccm, 225 sccm, 250 sccm, 275 sccm or 300 sccm.

[0093] In some implementations, the flow rate of He is 0~100 sccm, for example, it can be 5 sccm, 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm or 100 sccm.

[0094] In another specific embodiment, the present invention provides an insulated gate bipolar transistor, wherein the contact hole of the insulated gate bipolar transistor is prepared by the etching method described in one of the preceding specific embodiments.

[0095] The numerical range described in this invention includes not only the point values ​​listed above, but also any point values ​​within the numerical ranges not listed above. Due to space limitations and for the sake of brevity, this invention will not exhaustively list all the specific point values ​​included in the range.

[0096] Example 1

[0097] This embodiment provides a method for etching contact holes, the method comprising:

[0098] (1) A polysilicon layer and a dielectric layer are sequentially formed on the surface of a substrate; a patterned photoresist layer is formed on the surface of the dielectric layer to expose the contact hole formation area;

[0099] (2) C4F6, O2 and Ar with a flow ratio of 1:0.7:8 are used as the first etching gas, wherein the flow rate of C4F6 is 40 sccm, the flow rate of O2 is 28 sccm and the flow rate of Ar is 320 sccm. The temperature in the reaction chamber is set to 35°C, the pressure is 10 mTorr, and the source power and bias power are both 500W. Inductively coupled plasma etching is performed on the dielectric layer of the contact hole formation area until the polysilicon layer is exposed.

[0100] (3) Introduce N2 and O2 into the reaction chamber at a flow rate ratio of 3:1. The flow rate of O2 is 4 sccm and the flow rate of N2 is 12 sccm. The pressure in the reaction chamber is 10 mTorr.

[0101] (4) CF4, O2, HBr and Cl2 with a flow ratio of 1:0.5:9:9 are used as the second etching gas, wherein the flow rate of CF4 is 30 sccm, the flow rate of O2 is 15 sccm, the flow rate of HBr is 270 sccm and the flow rate of Cl2 is 270 sccm. The temperature in the reaction chamber is set to 36°C, the pressure is 12 mTorr, the source power is 1200 W and the bias power is 480 W. Inductively coupled plasma etching is performed on the polysilicon layer in the contact hole formation area.

[0102] (5) Using 200 sccm of O2 and 50 sccm of He as the third etching gas, the pressure in the reaction chamber is set to 6 mTorr and the source power is 1200 W to perform inductively coupled plasma etching on the patterned photoresist layer.

[0103] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 1 As shown, the etched contact hole morphology in this embodiment is precise, with a small difference between the bottom (polysilicon layer) and the top (dielectric layer) of the contact hole, which can effectively avoid insufficient coverage of the hole bottom during subsequent thin film deposition. The contact hole interface is clean, with no etching residue on the sidewalls and bottom, avoiding affecting the adhesion of the subsequent thin film. Furthermore, the contact hole is free from etching damage, with smooth sidewalls and no protrusions or grooves at the contact between the polysilicon layer and the dielectric layer, avoiding affecting the coverage of the contact hole sidewalls and bottom in the subsequent thin film deposition process.

[0104] Example 2

[0105] This embodiment provides a method for etching contact holes, the method comprising:

[0106] (1) A polysilicon layer and a silicon dioxide dielectric layer are sequentially formed on the substrate surface; a patterned photoresist layer is formed on the surface of the silicon dioxide dielectric layer to expose the contact hole formation area;

[0107] (2) C4F8, O2 and Ar with a flow ratio of 1:0.5:9 are used as the first etching gas, wherein the flow rate of C4F8 is 10 sccm, the flow rate of O2 is 5 sccm and the flow rate of Ar is 90 sccm. The temperature in the reaction chamber is set to 30°C, the pressure is 1 mTorr, and the source power and bias power are both 420W. Inductively coupled plasma etching is performed on the silicon dioxide dielectric layer in the contact hole formation area until the polysilicon layer is exposed.

[0108] (3) Introduce N2 and O2 into the reaction chamber at a flow rate ratio of 2:1. The flow rate of O2 is 5 sccm and the flow rate of N2 is 10 sccm. The pressure in the reaction chamber is 7.5 mTorr.

[0109] (4) CF4, O2, HBr and Cl2 with a flow ratio of 1:0.9:10:9 are used as the second etching gas, wherein the flow rate of CF4 is 5 sccm, the flow rate of O2 is 4.5 sccm, the flow rate of HBr is 50 sccm and the flow rate of Cl2 is 45 sccm. The temperature in the reaction chamber is set to 30°C, the pressure is 3 mTorr, the source power is 1000W and the bias power is 400W. Inductively coupled plasma etching is performed on the polysilicon layer in the contact hole formation area.

[0110] (5) Using 150 sccm of O2 and 10 sccm of He as the third etching gas, the pressure in the reaction chamber is set to 1 mTorr and the source power is 1000 W to perform inductively coupled plasma etching on the patterned photoresist layer.

[0111] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 2 As shown, the contact hole etched in this embodiment has a precise morphology, a clean contact hole interface, no etch damage, smooth sidewalls, and no protrusions or grooves at the contact between the polysilicon layer and the dielectric layer.

[0112] Example 3

[0113] This embodiment provides a method for etching contact holes, the method comprising:

[0114] (1) A polysilicon layer and a silicon dioxide dielectric layer are sequentially formed on the substrate surface; a patterned photoresist layer is formed on the surface of the silicon dioxide dielectric layer to expose the contact hole formation area;

[0115] (2) C3F6, O2 and Ar with a flow ratio of 1:0.6:10 are used as the first etching gas, wherein the flow rate of C3F6 is 50 sccm, the flow rate of O2 is 30 sccm and the flow rate of Ar is 500 sccm. The temperature in the reaction chamber is set to 40°C, the pressure is 18 mTorr, and the source power and bias power are both 600W. Inductively coupled plasma etching is performed on the silicon dioxide dielectric layer in the contact hole formation area until the polysilicon layer is exposed.

[0116] (3) Introduce N2 and O2 into the reaction chamber at a flow rate ratio of 5:1. The flow rate of O2 is 5 sccm and the flow rate of N2 is 25 sccm. The pressure in the reaction chamber is 15 mTorr.

[0117] (4) CF4, O2, HBr and Cl2 with a flow ratio of 1:0.8:9:12 are used as the second etching gas, wherein the flow rate of CF4 is 40 sccm, the flow rate of O2 is 32 sccm, the flow rate of HBr is 360 sccm and the flow rate of Cl2 is 480 sccm. The temperature in the reaction chamber is set to 40℃, the pressure is 20 mTorr, the source power is 1500W and the bias power is 600W. Inductively coupled plasma etching is performed on the polysilicon layer in the contact hole formation area.

[0118] (5) Using 300 sccm of O2 and 100 sccm of He as the third etching gas, the pressure in the reaction chamber is set to 20 mTorr and the source power is 1500 W to perform inductively coupled plasma etching on the patterned photoresist layer.

[0119] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 3 As shown, the contact hole etched in this embodiment has a precise morphology, no etching damage on the contact hole sidewall, and a smooth contact hole sidewall. There are no protrusions or grooves at the contact between the polysilicon layer and the dielectric layer, which does not affect the coverage of the contact hole sidewall and bottom in the subsequent thin film deposition process.

[0120] Example 4

[0121] This embodiment provides an etching method for contact holes. Except for the flow ratio of C4F6, O2 and Ar being 1:0.2:5, the method is the same as in Embodiment 1.

[0122] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 4 As shown, the contact hole etched in this embodiment has a precise morphology, a clean interface, and smooth sidewalls. However, at the contact point between the polysilicon layer and the dielectric layer, the dielectric layer has a small-radius protrusion and minor etching damage, which will affect the coverage of the contact hole sidewalls and bottom in subsequent thin film deposition processes.

[0123] Example 5

[0124] This embodiment provides an etching method for contact holes. Except for the flow ratio of C4F6, O2 and Ar being 1:2:15, the method is the same as in Embodiment 1.

[0125] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 5 As shown, in this embodiment, the bottom (polysilicon layer) of the etched contact hole has a large difference from the top (dielectric layer) of the top contact hole, which may affect the hole bottom coverage during subsequent thin film deposition. The sidewall of the contact hole is smooth, but at the contact point between the polysilicon layer and the dielectric layer, the dielectric layer has a small-radius protrusion, which affects the coverage of the sidewall and bottom of the contact hole in the subsequent thin film deposition process.

[0126] Example 6

[0127] This embodiment provides an etching method for contact holes. Except for the flow rate ratio of CF4, O2, HBr and Cl2 being 1:0.4:7:7.5, the method is the same as in Embodiment 1.

[0128] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 6 As shown, the etched morphology of the contact holes obtained in this embodiment is inaccurate. There is a significant offset between the bottom (polysilicon layer) and the top (dielectric layer) of the contact holes, which will result in insufficient coverage of the bottom of the holes in subsequent thin film deposition processes. There are residues at the interface and obvious etching residues on the sidewalls, which affect the adhesion of the subsequently deposited thin films. The etching damage is obvious. At the contact between the polysilicon layer and the dielectric layer, there are obvious protrusions in the dielectric layer and obvious grooves in the polysilicon layer, which affect the coverage of the sidewalls and bottom of the contact holes in subsequent thin film deposition processes.

[0129] Example 7

[0130] This embodiment provides an etching method for contact holes. Except for the flow ratio of CF4, O2, HBr and Cl2 being 1:2.5:15:15, the method is the same as in Embodiment 1.

[0131] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 7 As shown, the etched morphology of the contact holes obtained in this embodiment is inaccurate. There is a significant offset between the bottom (polysilicon layer) and the top (dielectric layer) of the contact holes, which may result in insufficient coverage of the bottom of the holes in subsequent thin film deposition processes. There are residues at the interface, with obvious etching residues on the sidewalls of the contact holes, affecting the adhesion of the subsequently deposited thin films. The etching damage is obvious, with obvious protrusions in the dielectric layer and obvious grooves in the polysilicon layer at the contact point between the polysilicon layer and the dielectric layer, affecting the coverage of the sidewalls and bottom of the contact holes in subsequent thin film deposition processes.

[0132] Example 8

[0133] This embodiment provides a method for etching contact holes. Except for step (2) where the bias power is 350W, the method is the same as in embodiment 1.

[0134] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 8 As shown, the contact hole etched in this embodiment has a precise morphology, a clean interface, and smooth sidewalls. There are no protrusions or grooves at the contact between the polysilicon layer and the dielectric layer, but there is minor etching damage. This has little impact on the coverage of the contact hole sidewalls and bottom in the subsequent thin film deposition process.

[0135] Example 9

[0136] This embodiment provides a method for etching contact holes. Except for step (3) where the bias power is 650W, the method is the same as in embodiment 1.

[0137] The longitudinal cross-sectional SEM image of the contact hole obtained by etching in this embodiment is shown below. Figure 9 As shown, the contact hole etched in this embodiment has a precise morphology, a clean interface, controllable etching damage, and smooth sidewalls. However, there is an obvious arc transition at the contact between the polysilicon layer and the dielectric layer, which affects the coverage of the contact hole sidewalls and bottom in the subsequent thin film deposition process.

[0138] Comparative Example 1:

[0139] (1) A polysilicon layer and a silicon dioxide dielectric layer are sequentially formed on the substrate surface; a patterned photoresist layer is formed on the surface of the silicon dioxide dielectric layer to expose the contact hole formation area;

[0140] (2) The patterned wafer is placed in a capacitively coupled plasma etching (CCP) apparatus. C4F8, O2 and Ar with a flow ratio of 1:0.5:9 are used as the first etching gas, wherein the flow rate of C4F8 is 20 sccm, the flow rate of O2 is 10 sccm and the flow rate of Ar is 180 sccm. The pressure in the reaction chamber is set to 10 mTorr, the source power is 420 W and the bias power is 1000 W. The silicon dioxide dielectric layer in the contact hole formation area is plasma etched until the polysilicon layer is exposed. The wafer is then removed from the CCP etching apparatus and placed in an inductively coupled plasma etching apparatus.

[0141] (3) CF4, O2, HBr and Cl2 with a flow ratio of 1:0.9:10:9 are used as the second etching gas, wherein the flow rate of CF4 is 18 sccm, the flow rate of O2 is 14.4 sccm, the flow rate of HBr is 180 sccm and the flow rate of Cl2 is 144 sccm. The pressure in the reaction chamber is set to 30 mTorr, and the source power and bias power are both 400 W. Inductively coupled plasma etching is performed on the polysilicon layer in the contact hole formation area.

[0142] (4) Using 150 sccm of O2 and 10 sccm of He as the third etching gas, the pressure in the reaction chamber is set to 1 mTorr and the source power is 1000 W to perform inductively coupled plasma etching on the patterned photoresist layer.

[0143] The longitudinal cross-sectional SEM image of the contact hole obtained by this comparative etching is shown below. Figure 10 As shown, the etched morphology of the contact hole obtained in this embodiment is not accurate. There is a significant offset between the bottom (polysilicon layer) and the top (dielectric layer) of the contact hole, which may cause insufficient coverage of the bottom of the hole in the subsequent thin film deposition process. Although the interface is clean, the etching damage is obvious. At the contact between the polysilicon layer and the dielectric layer, there is a significant difference in the etching width between the dielectric layer and the polysilicon layer, forming a step structure, which affects the coverage of the sidewall and bottom of the contact hole in the subsequent thin film deposition process.

[0144] Comparative Example 2:

[0145] This comparative example provides a method for etching contact holes. Except for step (2) where the source power is 550W and the pressure in the reaction chamber is 10mTorr, and step (3) where the pressure in the reaction chamber is 50mTorr, the method is the same as that of the comparative example 1.

[0146] The longitudinal cross-sectional SEM image of the contact hole obtained by this comparative etching is shown below. Figure 11 As shown, the etched morphology of the contact hole obtained in this embodiment is not accurate: there is a significant offset between the bottom (polysilicon layer) and the top (dielectric layer) of the contact hole, which may result in insufficient coverage of the bottom of the hole in the subsequent thin film deposition process; the interface is clean, but the etching damage is obvious. At the contact between the polysilicon layer and the dielectric layer, there is a significant difference in the etching width between the dielectric layer and the polysilicon layer, forming a multi-level step structure, which affects the coverage of the sidewall and bottom of the contact hole in the subsequent thin film deposition process.

[0147] The applicant declares that the above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention fall within the protection and disclosure scope of the present invention.

Claims

1. A method for etching contact holes, characterized in that, The method includes: (1) A polysilicon layer and a dielectric layer are sequentially formed on the surface of a substrate, and then a patterned photoresist layer is formed on the surface of the dielectric layer to expose the contact hole formation area and place it in an inductively coupled plasma reaction chamber. (2) The dielectric layer of the contact hole formation area is etched by a first etching gas until the polysilicon layer is exposed; the first etching gas includes fluorine gas, O2 and Ar; the source power and bias power of the first etching are each 400W~600W independently. (3) O2 and N2 are introduced to clean the reaction chamber; (4) The polysilicon layer in the contact hole formation area is etched a second time using a second etching gas; the second etching gas includes CF4, O2, HBr and Cl2; the source power of the second etching is 1000W~1500W and the bias power is 400W~600W.

2. The etching method as described in claim 1, characterized in that, Step (2) The first etching gas includes any one or a combination of at least two of C4F6, C4F8 or C3F6; And / or, in step (2), the flow rate ratio of fluorocarbon gas, O2 and Ar in the first etching gas is 1:(0.5~1):(8~12); And / or, in step (2) during the first etching process, the pressure in the reaction chamber is 1 mTorr ~ 20 mTorr.

3. The etching method as described in claim 1, characterized in that, In step (3), the flow rate ratio of N2 to O2 is (2~5):1, and the flow rate of O2 is 4 sccm~5 sccm; And / or, during the cleaning process described in step (3), the pressure in the reaction chamber is 5 mTorr ~ 15 mTorr.

4. The etching method as described in claim 1, characterized in that, The cleaning temperature in step (3) is 30℃~50℃.

5. The etching method as described in claim 1, characterized in that, In step (4), the flow rate ratio of CF4, O2, HBr and Cl2 in the second etching gas is 1:(0.5~2):(8~13):(8~13); And / or, in step (4) during the second etching process, the pressure in the reaction chamber is 1 mTorr ~ 20 mTorr.

6. The etching method as described in claim 1, characterized in that, In step (2), the source power of the first etching is the same as the bias power.

7. The etching method as described in claim 1, characterized in that, The temperatures for the first etching in step (2) and the second etching in step (4) are each 30°C to 40°C.

8. The etching method as described in claim 1, characterized in that, The etching method further includes using a third etching gas to remove the patterned photoresist layer through third etching; the third etching gas includes O2 and He.

9. The etching method as described in claim 8, characterized in that, During the third etching process, the pressure in the reaction chamber is 1 mTorr ~ 20 mTorr; And / or, during the third etching process, the source power is 1000W~1500W.

10. An insulated-gate bipolar transistor, characterized in that, The contact holes of the insulated gate bipolar transistor are prepared using the etching method described in any one of claims 1 to 9.

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