Scribing process of semiconductor chip
By cutting the silicon wafer and ceramic wafer after bonding and curing to form wiring channels and stress relief grooves, and then gradually removing them using cutting blades of different specifications, the chip displacement problem was solved, achieving high-precision and high-efficiency chip processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-06
- Publication Date
- 2026-04-07
AI Technical Summary
In existing technologies, the process of cutting and then bonding chips and ceramic sheets can easily lead to chip displacement, which cannot meet the requirements of complex and high-precision structures, resulting in low product processing success rate and poor efficiency.
The process involves first bonding and curing the silicon wafer and ceramic wafer together, then cutting them with a dicing blade to form wiring channels and dicing channels, and processing stress relief grooves on both sides. Different sizes of dicing blades are used to gradually remove the silicon wafer and ceramic wafer to form a chip unit.
It enables efficient processing of complex and high-precision structures, avoids deviations caused by colloidal interference and changes in colloidal flow when chip spacing is low, and improves production efficiency.
Smart Images
Figure CN121815973A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a dicing process of a semiconductor chip. BACKGROUND
[0002] In order to improve the use strength of the chip or meet the spacing requirements of the chip, the chip is usually bonded to the ceramic sheet in the chip packaging process. The common method is to cut the chip and the ceramic sheet into the required size respectively and then bond them, and the position accuracy is controlled by a chip mounter. Since the glue has fluidity, if the spacing size of the chips is close, the glue between the chips will interfere with each other; and the flow, volume change and bubble volatilization in the curing process of the glue are easy to cause the displacement of the chips. Therefore, this method cannot meet the requirements when facing some complex and high-precision structures, resulting in low processing success rate and poor efficiency. SUMMARY
[0003] The present application provides a dicing process of a semiconductor chip to solve the technical problem that the process mode of cutting the chip and the ceramic sheet first and then bonding them is easy to cause the displacement of the chip and cannot meet the requirements of complex and high-precision structures.
[0004] The present application provides a dicing process of a semiconductor chip, which comprises the following steps: bonding and curing a silicon sheet and a ceramic sheet to form a bonding layer between the silicon sheet and the ceramic sheet; cutting the surface of the silicon sheet by using a dicing knife to form a wiring channel and a dicing channel on the surface of the silicon sheet; cutting the two sides of the dicing channel by using the dicing knife to form a stress release groove penetrating through the silicon sheet and the bonding layer in the thickness direction of the silicon sheet; cutting off the silicon sheet and the bonding layer at the dicing channel by using a first cutting knife; cutting off the ceramic sheet at the dicing channel by using a second cutting knife to form a plurality of chip units.
[0005] In an embodiment of the present application, in the step of bonding and curing the silicon sheet and the ceramic sheet, the silicon sheet and the ceramic sheet are bonded by using a bonding glue, and the bonding glue comprises conductive glue, epoxy glue or resin glue.
[0006] In an embodiment of the present application, the thickness of the bonding layer is 10-100 microns.
[0007] In an embodiment of the present application, in the step of bonding and curing the silicon sheet and the ceramic sheet, the total thickness of the bonded silicon sheet and the ceramic sheet is less than or equal to 2 mm.
[0008] In an embodiment of the present application, the surface of the silicon wafer is cut by a scribe blade, and in the step of forming wiring channels and scribe channels on the surface of the silicon wafer, the scribe blade is a diamond scribe blade, and the thickness of the diamond scribe blade is 25-50 microns.
[0009] In an embodiment of the present application, the surface of the silicon wafer is cut by a scribe blade, and in the step of forming wiring channels and scribe channels on the surface of the silicon wafer, the width of the scribe channel is greater than or equal to 50 microns, and the scribe channels are arranged in an array on the silicon wafer.
[0010] In an embodiment of the present application, the surface of the silicon wafer is cut by a scribe blade, and in the step of forming wiring channels and scribe channels on the surface of the silicon wafer, the width of the scribe channel is greater than or equal to 50 microns, and the scribe channels are arranged in an array on the silicon wafer.
[0011] In an embodiment of the present application, the surface of the silicon wafer is cut by a scribe blade, and in the step of forming wiring channels and scribe channels on the surface of the silicon wafer, the width of the scribe channel is greater than or equal to 50 microns, and the scribe channels are arranged in an array on the silicon wafer.
[0012] In an embodiment of the present application, the surface of the silicon wafer is cut by a scribe blade, and in the step of forming wiring channels and scribe channels on the surface of the silicon wafer, the width of the scribe channel is greater than or equal to 50 microns, and the scribe channels are arranged in an array on the silicon wafer.
[0013] In an embodiment of the present application, the width of the first cutting blade is W1, the width of the second cutting blade is W2, and W1-W2 is greater than or equal to 50 microns.
[0014] The scribe process for semiconductor chips provided by the present application first cures the silicon wafer and the ceramic wafer, then cuts the scribe channels by a scribe blade, processes stress release grooves on both sides of the scribe channels, removes the upper silicon wafer at the scribe channels by a first cutting blade, removes the lower ceramic wafer at the scribe channels by a second cutting blade, switches the cutting blades of different specifications to process complex required structures and divide them, and all structures are formed at one time, which meets the spacing requirements at one time, produces multiple devices at one time, avoids the interference of the gel when the chip spacing is low and the deviation caused by the flow and volume change of the gel, realizes high-precision processing, and improves the production efficiency. BRIEF DESCRIPTION OF DRAWINGS
[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0016] In the attached diagram: Figure 1 This is a schematic diagram of a semiconductor chip dicing process provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the dicing process for a semiconductor chip provided in one embodiment of the present invention. Figure One ; Figure 3 This is a schematic diagram of the dicing process for a semiconductor chip provided in one embodiment of the present invention. Figure Two ; Figure 4 This is a schematic diagram of the dicing process for a semiconductor chip provided in one embodiment of the present invention. Figure Three ; Figure 5 This is a schematic diagram of the dicing process for a semiconductor chip provided in one embodiment of the present invention. Figure Four ; Figure 6 This is a schematic diagram of the dicing process for a semiconductor chip provided in one embodiment of the present invention. Figure Five ; Figure 7 This is a schematic diagram of the dicing process for a semiconductor chip provided in one embodiment of the present invention. Figure Six .
[0017] The attached figures are labeled as follows: 10 - Silicon wafer; 20 - Ceramic wafer; 30 - Adhesive layer; 40 - Die-cut groove; 50 - Stress relief groove; 110 - Slicing blade; 120 - First cutting blade; 130 - Second cutting blade; 200-Chip Unit. Detailed Implementation
[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.
[0021] For example, a 3×3 silicon wafer array is bonded to a ceramic wafer with a gap of only 50μm between adjacent silicon wafers. If the silicon wafers and ceramic wafers are cut separately and then bonded with conductive adhesive, the placement accuracy is extremely high, and the flow and overflow of the adhesive can easily lead to contact and short circuit between the chips.
[0022] Based on this, one embodiment of the present invention provides a dicing process for a semiconductor chip, such as... Figure 1 As shown, the dicing process for semiconductor chips includes the following steps: S1: The silicon wafer 10 is bonded to the ceramic sheet 20 and cured to form an adhesive layer 30 between the silicon wafer 10 and the ceramic sheet 20. S2: The surface of the silicon wafer 10 is cut using a dicing blade 110 to form wiring channels and dicing channels 40 on the surface of the silicon wafer 10; S3: The dicing blade 110 is used to cut both sides of the dicing channel 40 to form a stress relief groove 50 that penetrates the silicon wafer 10 and the adhesive layer 30 in the thickness direction of the silicon wafer 10. S4: Use the first cutting blade 120 to remove the silicon wafer 10 and the adhesive layer 30 at the dicing channel 40; S5: The ceramic sheet 20 at the dicing channel 40 is removed by the second cutting blade 130 to form multiple chip units 200.
[0023] Specifically, the silicon wafer 10 and ceramic wafer 20 are first bonded and cured. Then, a dicing blade 110 is used to cut the upper silicon wafer dicing channel 40 using a grinding wheel cutting process. A first cutting blade 120 is then used to remove the upper silicon wafer 10 and the bonding layer 30 at the dicing channel 40, and a second cutting blade 130 is used to remove the lower ceramic wafer 20 at the dicing channel 40, thus dividing the wafer into multiple chip units 200. By switching between various blade specifications, complex required structures can be processed and divided. All structures are formed in one step, meeting the spacing requirements at once. Multiple devices can be produced simultaneously, avoiding interference from the colloid when the chip spacing is low, as well as deviations caused by the flow and volume changes of the colloid. This achieves high-precision processing and improves production efficiency.
[0024] See Figure 2 In some embodiments, in step S1, the step of bonding and curing the silicon wafer 10 and the ceramic sheet 20 is performed by using an adhesive to bond the silicon wafer 10 and the ceramic sheet 20. The adhesive may include conductive adhesive, epoxy adhesive or resin adhesive.
[0025] Specifically, the adhesive first bonds the silicon wafer 10 to the ceramic wafer 20, fixing their positions. The adhesive layer 30 then tightly bonds the silicon wafer 10 and the ceramic wafer 20, significantly improving the stability of the entire packaging structure.
[0026] After curing, conductive adhesive can form an adhesive layer with a certain strength and flexibility, while meeting electrical performance requirements; epoxy adhesive has high adhesive strength after curing, and can maintain its insulation properties and electrical stability, and is resistant to chemical corrosion and has good thermal stability; resin adhesive has good thermal insulation properties, good flexibility and impact resistance, good flowability and plasticity, and can fully fill the gap between silicon wafer 10 and ceramic wafer 20 during the bonding process to form a uniform adhesive layer 30.
[0027] In step S1, the thickness of the adhesive layer 30 is 10μm to 100μm. Adhesive layers within this thickness range can alleviate stress through their own elastic deformation, reducing stress damage to the chip. Furthermore, while ensuring a tight bond between the silicon wafer 10 and the ceramic wafer 20, it minimizes the impact on the overall chip thickness. The adhesive layer 30 can withstand a certain degree of mechanical vibration and impact, and is beneficial for achieving a thinner and lighter chip.
[0028] Furthermore, in step S1, during the step of bonding and curing the silicon wafer 10 and the ceramic sheet 20, the total thickness of the bonded silicon wafer 10 and ceramic sheet 20 is less than or equal to 2 mm.
[0029] In some embodiments, in step S2, the dicing blade 110 is used to cut the surface of the silicon wafer 10 to form wiring channels and dicing channels 40 on the surface of the silicon wafer 10. In this step, the dicing blade 110 is a diamond dicing blade 110 and the thickness of the diamond dicing blade 110 is 25μm~50μm.
[0030] Specifically, the wiring channels provide precise pathways for the internal circuit connections of the chip, enabling reliable electrical connections between various electronic components according to design requirements. The dicing channels 40 clearly define the positions and boundaries for subsequent chip dicing. The dicing blade 110 is made of diamond, offering excellent edge smoothness. Diamond itself possesses extremely high hardness and wear resistance, and combined with an appropriate thickness, it maintains good stability during the cutting process, resulting in smoother and more even cut edges. The relatively thin 25μm-50μm diamond dicing blade 110 allows for the formation of narrower kerfs when cutting the silicon wafer 10. The narrower kerf results in smaller wiring channels and dicing channels 40 on the surface of the silicon wafer 10, which is beneficial for improving chip integration. Furthermore, the thinner dicing blade 110 generates relatively less cutting stress when cutting the silicon wafer 10, minimizing damage to the internal crystal structure of the silicon wafer 10.
[0031] See Figure 3 In step S2, the surface of the silicon wafer 10 is cut using a dicing blade 110 to form wiring channels and dicing channels 40 on the surface of the silicon wafer 10. The width of the dicing channel 40 is greater than or equal to 50 μm, and the dicing channels 40 are arranged in an array on the silicon wafer 10.
[0032] Specifically, the dicing track 40 is used to define the position and boundary for subsequent chip dicing. The width of the dicing track 40 is greater than or equal to 50μm, which can provide a clear boundary for chip dicing, facilitate chip dicing, and better disperse cutting stress, making the stress distribution more uniform, reducing stress concentration, and thus reducing the generation of microcracks.
[0033] See Figure 4 In step S3, the dicing blade 110 is used to cut both sides of the dicing channel 40 to form a stress relief groove 50 that penetrates the silicon wafer 10 and the adhesive layer 30 in the thickness direction of the silicon wafer 10. In this step, the dicing blade 110 is a diamond dicing blade 110, the stress relief grooves 50 on both sides of the dicing channel 40 have the same width, and the stress relief grooves 50 are exposed on the surface of the corresponding ceramic sheet 20.
[0034] Specifically, during the cutting process, stress concentration will occur inside the silicon wafer 10. The stress relief groove 50 can provide a stress relief channel for the stress generated during the subsequent cutting of the silicon wafer 10, and disperse the stress to the surrounding area, thereby avoiding defects such as cracks and breakage of the silicon wafer 10 caused by stress concentration. It can prevent edge chipping caused by subsequent cutting of the silicon wafer 10 and improve the chip processing yield.
[0035] Since the stress relief groove 50 penetrates the silicon wafer 10 and the adhesive layer 30, the stress generated inside the silicon wafer 10 due to processing, thermal expansion and contraction can be released. Compared with the traditional method of only surface treatment or partial cutting, this through-cutting can more thoroughly release the stress deep inside the silicon wafer 10 and reduce the accumulation of stress inside the silicon wafer 10.
[0036] The stress relief grooves 50 on both sides of the dicing channel 40 have the same width, which ensures more uniform stress release on both sides. During the stress release process, the stress is released simultaneously on both sides to the same degree, so that the silicon wafer 10 maintains good flatness after stress release.
[0037] See Figure 5 In step S4, the first cutting blade 120 is used to cut off the silicon wafer 10 and the adhesive layer 30 at the dicing channel 40. The first cutting blade 120 is a resin blade, and the width of the first cutting blade 120 is 100μm~300μm.
[0038] Specifically, the first cutting blade 120 uses a resin blade to cut the silicon wafer 10 and the adhesive layer 30, achieving high-precision cutting and ensuring that the edges of the cut silicon wafer 10 are smooth, reducing the generation of burrs and microcracks, and preventing damage to the internal structure of the chip. The resin blade has good guidance and stability during the cutting process, effectively reducing cutting deviation. Compared with some tools that are too hard or have overly aggressive cutting methods, the resin blade causes less damage to the silicon wafer 10 and the adhesive layer 30 during cutting; the stress generated during the resin blade cutting process is relatively small, and its impact on the internal stress of the silicon wafer 10 is also smaller. Combined with the stress relief groove 50, it can release cutting stress, thereby reducing the risk of edge chipping.
[0039] When cutting the adhesive layer 30, the resin blade can completely and evenly remove the adhesive layer 30 during the cutting process, without leaving any residue or uneven removal, and can effectively prevent the material of the adhesive layer 30 from contaminating the chip surface.
[0040] The first cutting blade 120 extends to the surface of the ceramic wafer 20, that is, after removing the silicon wafer 10 and the adhesive layer 30 at the dicing channel 40, the surface of the corresponding ceramic wafer 20 is exposed. Using a relatively wide first cutting blade 120 (the width of the first cutting blade 120 is 100μm~300μm) to cut the silicon wafer 10 can avoid blade wobbling during subsequent ceramic cutting.
[0041] See Figure 6 In step S5, the ceramic piece 20 at the slicing channel 40 is removed using the second cutting blade 130. The second cutting blade 130 is a resin blade, and the width of the second cutting blade 130 is smaller than the width of the first cutting blade 120.
[0042] Specifically, the second cutting blade 130 uses a resin blade to cut the ceramic sheet 20, which can accurately divide the ceramic sheet 20 into parts corresponding to the silicon wafer 10, and finally form a complete chip unit 200, ensuring that the structure of each chip unit 200 is complete and the size meets the design requirements.
[0043] Using a narrower second cutting blade 130 to cut the ceramic sheet 20 minimizes the dimensional difference between the ceramic sheet 20 and the silicon wafer 10. The narrower resin blade ensures that the width of the removed portion is highly consistent with the design dimensions, keeping the error within a minimal range and meeting the requirements of high-precision manufacturing. The narrower resin blade also exerts less impact on the ceramic sheet 20 during cutting, better dispersing cutting stress and reducing stress concentration at the edges, thereby lowering the risk of edge chipping.
[0044] In the above embodiment, the width of the first cutting blade 120 is W1, the width of the second cutting blade 130 is W2, and W1-W2≥50μm.
[0045] After the semiconductor chip is fabricated using the aforementioned dicing process, multiple chip units 200 can be formed at once, such as... Figure 7 As shown.
[0046] In summary, the semiconductor chip dicing process proposed in this invention involves first bonding and curing a silicon wafer 10 and a ceramic wafer 20, then using a dicing blade 110 to cut dicing channels 40, and processing stress relief grooves 50 on both sides of the dicing channels 40. A first cutting blade 120 removes the upper layer of silicon wafer 10 from the dicing channels 40, and a second cutting blade 130 removes the lower layer of ceramic wafer 20 from the dicing channels 40. By switching between various blade specifications, complex desired structures are processed and divided to form multiple chip units 200. All structures are formed in one step, meeting the spacing requirements at once. Multiple devices can be produced simultaneously, avoiding interference from the colloid when the chip spacing is low, and deviations caused by the flow and volume changes of the colloid. This achieves high-precision processing and improves production efficiency.
[0047] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A dicing process for a semiconductor chip, characterized in that, include: The silicon wafer is bonded to the ceramic sheet and cured to form an adhesive layer between the silicon wafer and the ceramic sheet; The surface of the silicon wafer is cut using a dicing blade to form wiring channels and dicing channels on the surface of the silicon wafer; The dicing blade is used to cut both sides of the dicing channel to form a stress relief groove that penetrates the silicon wafer and the adhesive layer in the thickness direction of the silicon wafer; The silicon wafer and the adhesive layer at the dicing groove are removed using a first cutting blade; The ceramic sheet at the dicing channel is removed using a second cutting blade to form multiple chip units.
2. The semiconductor chip dicing process according to claim 1, characterized in that, In the step of bonding and curing the silicon wafer and the ceramic sheet, an adhesive is used to bond the silicon wafer and the ceramic sheet. The adhesive includes conductive adhesive, epoxy adhesive or resin adhesive.
3. The dicing process for a semiconductor chip according to claim 1 or 2, characterized in that, The thickness of the adhesive layer is 10μm to 100μm.
4. The semiconductor chip dicing process according to claim 1, characterized in that, In the step of bonding and curing the silicon wafer and the ceramic sheet, the total thickness of the bonded silicon wafer and the ceramic sheet is less than or equal to 2 mm.
5. The semiconductor chip dicing process according to claim 1, characterized in that, In the step of cutting the surface of a silicon wafer with a dicing blade to form wiring channels and dicing channels on the surface of the silicon wafer, the dicing blade is a diamond dicing blade with a thickness of 25μm~50μm.
6. The dicing process for a semiconductor chip according to claim 1 or 5, characterized in that, In the step of cutting the surface of a silicon wafer with a dicing blade to form wiring channels and dicing channels on the surface of the silicon wafer, the width of the dicing channel is greater than or equal to 50 μm, and the dicing channel array is arranged on the silicon wafer.
7. The semiconductor chip dicing process according to claim 1, characterized in that, In the step of cutting both sides of the dicing channel with the dicing blade to form stress relief grooves penetrating the silicon wafer and the adhesive layer in the thickness direction of the silicon wafer, the dicing blade is a diamond dicing blade, the stress relief grooves on both sides of the dicing channel have the same width, and the stress relief grooves are exposed on the surface of the corresponding ceramic wafer.
8. The semiconductor chip dicing process according to claim 1, characterized in that, In the step of removing the silicon wafer and the adhesive layer at the dicing channel using a first cutting blade, the first cutting blade is a resin blade, and the width of the first cutting blade is 100μm~300μm.
9. The semiconductor chip dicing process according to claim 8, characterized in that, In the step of using a second cutting blade to remove the ceramic piece at the scribbling path, the second cutting blade is a resin blade, and the width of the second cutting blade is smaller than the width of the first cutting blade.
10. The semiconductor chip dicing process according to claim 9, characterized in that, The width of the first cutting blade is W1, the width of the second cutting blade is W2, and W1-W2≥50μm.