Method and apparatus for controlling battery storage mode

Abstract

A method of exiting a first battery from a battery storage mode is provided. The method may include receiving a wake-up signal indicative of a power-on event when the first battery is in the battery storage mode; generating an exit signal in response to the wake-up signal to cause the first battery to supply power to a first processing circuit; waiting for a predetermined period of time after a predetermined edge of the exit signal; determining whether the first battery is supplying power to the first processing circuit after expiration of the predetermined time period; and generate a second exit signal in response to determining that the first battery is not supplying power to the first processing circuit. In the battery storage mode, a second battery provides power to a second processing circuit to perform the method of exiting the first battery from the battery storage mode.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. non-provisional patent application No. 18 / 416,274, filed January 18, 2024, entitled "Method and Apparatus for Controlling Battery Storage Mode," and Indian provisional patent application No. 202341061894, filed September 14, 2023, entitled "Method and Apparatus for Controlling Battery Storage Mode," the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates generally to saving battery power in electronic devices, and more specifically, to a method and apparatus for discharging battery storage modes in electronic devices. Summary of the Invention

[0003] According to one aspect of various examples, a method is provided for exiting a battery storage mode for a first battery. The method may include: receiving a wake-up signal indicating a power-on event while the first battery is in battery storage mode; generating an exit signal in response to the wake-up signal to cause the first battery to supply power to a first processing circuit; waiting for a predetermined time period after a predetermined edge of the exit signal; determining, after the predetermined time period has expired, whether the first battery is supplying power to the first processing circuit; and generating a second exit signal in response to determining that the first battery is not supplying power to the first processing circuit. In battery storage mode, a second battery may supply power to a second processing circuit to perform the method of exiting the battery storage mode for the first battery. The first battery and the second battery may be respective portions of a single rechargeable battery. The exit signal may be a pulse signal having a predetermined pulse width.

[0004] The method may include entering an idle state in response to determining that a first battery is supplying power to a first processing circuit. In response to determining that the first battery is not supplying power to the device, the method may include determining whether a maximum number of retries has been reached. In response to determining that the maximum number of retries has not been reached, the method may include generating a second exit signal to cause the first battery to supply power to the device. In response to determining that the maximum number of retries has been reached, the method may include causing the device to enter an idle state in which the device waits to receive a second wake-up signal.

[0005] According to one aspect of various examples, a controller is provided for exiting a battery storage mode to provide power to a first processing circuit. The controller may include: a second processing circuit, the second processing circuit being configured to at least: receive a wake-up signal indicating a power-on event while the first battery is in battery storage mode; generate an exit signal in response to the wake-up signal to cause the first battery to supply power to the first processing circuit; wait for a predetermined time period after a predetermined edge of the exit signal; determine whether the first battery is supplying power to the first processing circuit after the predetermined time period has expired; and generate a second exit signal in response to determining that the first battery is not supplying power to the first processing circuit. In battery storage mode, the second battery provides power to the second processing circuit. The exit signal may be a pulse signal having a predetermined pulse width.

[0006] The second processing circuit can enter an idle state in response to determining that the first battery is supplying power to the first processing circuit. The second processing circuit can also, in response to determining that the first battery is not supplying power to the first processing circuit, determine whether the maximum number of retries has been reached, and in response to determining that the maximum number of retries has not been reached, generate a second exit signal to cause the first battery to supply power to the first processing circuit. The second processing circuit can also, in response to determining that the maximum number of retries has been reached, cause the device to enter an idle state, in which the device waits to receive a second wake-up signal. The first battery and the second battery can be corresponding portions of a single rechargeable battery. The first processing circuit can initiate a startup sequence after the first battery begins supplying power to the first processing circuit.

[0007] According to one aspect of various examples, a controller is provided for exiting a battery storage mode for a first battery. The controller may include: a first processing circuit powered by an output of the first battery; and a second processing circuit powered by an output of a second battery, the second processing circuit being configured to at least: receive a wake-up signal indicating a power-on event when the first battery is in battery storage mode; generate an exit signal in response to the wake-up signal to cause the first battery to supply power to the first processing circuit; wait for a predetermined time period after a predetermined edge of the exit signal; determine whether the first battery is supplying power to the first processing circuit; and generate a second exit signal in response to determining that the first battery is not supplying power to the first processing circuit. In battery storage mode, the first battery may not supply power to the first processing circuit. The first processing circuit may initiate a startup sequence after the first battery begins supplying power to the first processing circuit. The exit signal may be a pulse signal having a predetermined pulse width.

[0008] The second processing circuit may enter an idle state in response to determining that the first battery is supplying power to the first processing circuit. The second processing circuit may also, in response to determining that the first battery is not supplying power to the first processing circuit, determine whether the maximum number of retries has been reached, and in response to determining that the maximum number of retries has not been reached, generate a second exit signal to cause the first battery to supply power to the first processing circuit. The second processing circuit may also, in response to determining that the maximum number of retries has been reached, enter an idle state in which it waits to receive a second wake-up signal. The first battery and the second battery may be corresponding portions of a single rechargeable battery. Attached Figure Description

[0009] Figure 1 A block diagram of a controller for battery storage modes for battery withdrawal, based on various examples, is shown.

[0010] Figure 2 Examples are shown Figure 1 Block diagram of the second processing circuit.

[0011] Figure 3 The change detection circuits are shown according to various examples.

[0012] Figure 4 A flowchart illustrating a method for exiting battery storage mode using state machines based on various examples is shown.

[0013] Figure 5 Timing diagrams illustrating various signals associated with methods for exiting battery storage mode, based on various examples, are shown. Detailed Implementation

[0014] Reference will now be made to the various examples shown in the accompanying drawings, in which the same reference numerals always denote the same elements. These examples may be presented in various forms, and are not limited to those described herein.

[0015] Portable electronic devices (such as, but not limited to, laptops, tablets, and mobile phones) include one or more batteries that provide power to circuitry contained within these devices. These batteries are typically charged when they are inserted into the portable electronic device during the manufacturing process, enabling them to power the device and allowing customers to use the device immediately upon purchase without first charging the batteries. However, after the charged batteries are inserted into the device during the manufacturing process, they may experience leakage, reducing their charge level. As the amount of time between the completion of the manufacturing process and the customer's purchase of the device increases, less charge may remain in the main battery, potentially leaving insufficient charge to power on the device without prior charging. Therefore, an apparatus and method may be needed to limit battery leakage and extend the amount of time between manufacturing and purchase during which the battery retains sufficient charge to power the device.

[0016] After the manufacturing process is complete, the main battery can be placed in battery storage mode to reduce leakage. In battery storage mode, the main battery does not supply power to the device, thereby conserving the energy stored in the main battery. Therefore, there is a need for a process and apparatus to remove the main battery from battery storage mode during the first startup or any subsequent startup when the battery is in storage mode.

[0017] Figure 1 A block diagram of a controller 100 for discharging a battery storage mode, according to various examples, is shown. The controller 100, according to various examples, may be an embedded controller for controlling the startup process of a portable electronic device, such as, but not limited to, a laptop computer, tablet computer, or mobile phone. The portable electronic device may include one or more batteries for providing power to various circuits contained within the device. For example, the portable electronic device may include a battery that may be divided into a primary section for providing main power to the device and a second or backup section for providing power to certain components of the device. For example, the second or backup section may supply power to a real-time clock rail for providing power to a real-time clock (RTC) that operates with very low power even when the rest of the device is not powered. According to various examples, the portable electronic device may include a separate battery, a primary battery for providing main power to the device, and a separate backup battery for providing power to certain components of the device, such as the RTC rail. For example, the backup battery may be in the form of a coin cell battery.

[0018] like Figure 1As shown, the controller 100 may include a first processing circuit 110 powered by the output of a first battery 102 (which may be a main battery) and a second processing circuit 120 powered by the output of a second battery 103 (e.g., a second or backup portion or a coin cell battery). According to various examples, the first battery 102 and the second battery 103 may be respective portions of a single rechargeable battery 101. The second processing circuit 120 may receive power from the second battery 103 via an RTC rail. The first processing circuit 110, powered by the first battery 102, may receive a battery output 115 from the first battery 102, and the second processing circuit 120 may receive an output 121 from the second battery 103. When the first processing circuit 110 receives the battery output 115 from the first battery 102, that power may supply power to the second processing circuit 120, thereby conserving power stored in the second battery 103 for use only when the battery output 115 from the first battery 102 is not supplied. The second processing circuit 120 may also receive a battery output digital indicator signal (BPLUS) 122 indicating whether the first battery 102 is supplying power to the first processing circuit 110. The second processing circuit 120 may also receive a wake-up signal 123 indicating that a power-on or wake-up event has occurred. For example, a wake-up signal indicating a power-on event may indicate that the power button of a portable electronic device has been pressed, or that a laptop computer has been turned on. Circuitry (not shown) for providing the wake-up signal 123 may be part of the second processing circuit 120. The second processing circuit 120 may output a voltage control interface output (VCI_OUT) signal 124 based on the wake-up signal 123 to enable power from the first battery 102 to be supplied to the first processing circuit 110, and an exit signal 125 to cause the first battery 102 to exit battery storage mode and supply power to the first processing circuit 110, as explained in more detail below. For example, the exit signal can trigger the battery management unit to drive the first field-effect transistor (FET), which allows power from the first battery 102 to be supplied to the first processing circuit 110, and the VCI_OUT signal 124 can be used to enable the voltage regulator, which supplies power from the first battery 102 to the first processing circuit 110 at the required voltage.

[0019] Figure 2 Examples are shown Figure 1A block diagram of the second processing circuit 120 is provided. The second processing circuit 120 may include a finite state machine (FSM) 200 for controlling the process of exiting the battery storage mode of the first battery 102. The second processing circuit 120 may include a storage mode register 210 for storing multiple bits used by the FSM 200 to control the process of exiting the battery storage mode, as explained in more detail below. For example, the storage mode register 210 may store an exit storage mode enable bit to enable the process of exiting the battery storage mode of the first battery 102. The storage mode register 210 may include three maximum retry count bits for setting the maximum number of attempts that the FSM 200 can make to exit the battery storage mode of the first battery 102. Although Figure 2 The storage mode register 210 uses three maximum retry count bits, but a different number of bits can be used. Storage mode register 210 may also include an exit storage count mode bit to indicate the counting mode used to exit battery storage mode for the first battery 102. For example, the storage count mode bit may indicate whether the controller is operating in a fixed count mode or an increment count mode, as explained in more detail below.

[0020] The second processing circuit 120 may further include a change detection circuit 220 for detecting changes that cause the first battery 102 to exit battery storage mode. For example, a change may be pressing a power button on an electronic device or opening the lid of a laptop computer. The change detection circuit 220 may receive a voltage control interface output (VCI_OUT) signal 124 from the FSM 200 and may output a VCI_OUT_CHANGE signal 203 to the FSM 200 to indicate when the VCI_OUT signal has changed from one logic state to another, as explained in more detail below. The change detection circuit 220 may also receive a next state signal (Next_State) 204 from the FSM 200, as explained further below.

[0021] The second processing circuit 120 may further include a decrement counter 230 coupled to the FSM 200, wherein the decrement counter 230 is used to decrement the count from a count value (CNT_VAL) provided by the FSM 200. Although Figure 2 The example shows a decrement counter 230 that counts down from a count value, but an increment counter can also be used to increment the count value. The FSM 200 can send a load count signal (LOAD_CNT) to load a count value (CNT_VAL) onto the decrement counter, from which the decrement counter 230 will count down. The decrement counter 230 can output a count signal (CNT) to the FSM 200 to facilitate exiting battery storage mode, as explained further below.

[0022] The second processing circuit 120 may further include a retry counter 240 coupled to the FSM 200 and used to store a count of the number of retry attempts (RETRY_CNT) that the FSM 200 has performed to exit the battery storage mode for the first battery 102. The retry counter 240 provides the retry count (RETRY_CNT) to the FSM 200, and the FSM 200 may increment the retry count by sending a retry increment signal (RETRY_CNT++) to the retry counter 240 as additional retry attempts are performed. The FSM 200 may also reset the retry count by sending a retry count reset signal (RST_RETRY_CNT) to the retry counter 240.

[0023] The second processing circuit 120 can receive a clock signal (CLK_32KHz) 201 to coordinate the operation of the FSM 200. Figure 2 The clock signal (CLK_32KHz) 201 is shown as a 32KHz clock signal, but other frequencies can be used. The second processing circuit 120 can also receive a second battery reset signal (VBAT_RST) 202 to reset the change detection circuit 220, as explained further below.

[0024] Figure 3 Examples are shown Figure 2 220. Change detection circuit. Figure 3 The change detection circuit 220 can receive a VCI_OUT signal 124, which can be generated in response to a wake-up signal 123, a clock signal (CLK_32KHz) 201, a Next_State signal 204 from the FSM 200, and a second battery reset signal (VBAT_RST) 202. The change detection circuit can also output a VCI_OUT_CHANGE signal 203 to indicate when the VCI_OUT signal 124 has changed from one logic state to another. The wake-up signal 123 can be an OR of multiple wake-up conditions, including pressing the power button, lifting the laptop lid, or attaching the laptop to a power line, and the VCI_OUT signal 124 can be asserted in response to the wake-up signal 123. The change detection circuit 220 may include an OR gate 300, an integrated clock gate 301, an AND gate 302, and flip-flops or latches (such as...). Figure 3The example implementation shows a D flip-flop 304. When the portable electronic device is in battery storage mode, the VCI_OUT_CHANGE signal 203 is logic low because the VCI_OUT signal 124 received at the first input of the AND gate 302 has not yet changed from its initial default state of logic low. A logic high signal is output from the inverted output of the D flip-flop 304 to one input of the AND gate 302, such that when the VCI_OUT signal 124 becomes logic high (i.e., becomes active), the AND gate 302 outputs a logic high signal to the D input of the D flip-flop 304. On a predetermined edge of the clock signal CLK, the Q output of the D flip-flop 304 (i.e., the VCI_OUT_CHANGE signal 203) becomes logic high to indicate that the logic level of the VCI_OUT signal 124 has changed from invalid low to active high. A second battery reset signal (VBAT_RST) 202 can be used to clear the D flip-flop 304 to reset the Q output of the D flip-flop 302 to logic low.

[0025] like Figure 3 As shown in the example implementation, the clock signal CLK can be gated to save power. More specifically, the change detection circuit 220 may include an OR gate 300 having a first input for receiving the next state signal (Next_State) 204 from the FSM 200. When the next state is not an idle state, the next state signal (Next_State) 204 is logic high (see [link to example implementation]). Figure 4The OR gate 300 may include a second input for receiving the output of the AND gate 302 and an output terminal for outputting an enable signal EN to the integrated clock gate (ICG) 301. The OR gate 300 outputs a valid (e.g., logic high) enable signal EN to the ICG 301 when the Next_State signal 204 indicates that the next state is not an idle state (as described below) or when the output of the AND gate 302 is logic high. The ICG 301 also receives a clock signal (CLK_32kHz) 201, which is output to the CLK pin of the D flip-flop 304 based on the enable signal EN. Specifically, when the output of the OR gate 300 is logic high, the ICG 301 outputs the clock signal CLK_32kHz 201 to the CLK pin of the D flip-flop 304. When the output of OR gate 300 is logic low, the CLK pin of D flip-flop 304 remains logic low; that is, the clock signal CLK_32KHz 201 is not passed to the CLK pin of D flip-flop 304. Since the inverted output of D flip-flop 304 is fed back to the second input of AND gate 302, when VCI_OUT goes high, the Q output of D flip-flop 304 will change high in response to the next clock cycle of clock signal CLK_32KHz 201 as it passes through integrated clock gate 301. The inverted output of D flip-flop 304 will then change low, which will consequently change the D input of D flip-flop 304 low. Assuming NEXT_State signal 204 is high, the output of D flip-flop 304, i.e., signal VCI_OUT_CHANGE 203, will fall back low on the next clock cycle of CLK_32KHz 201. Therefore, when the NEXT_State signal is high, in response to VCI_OUT going high, the VCI_OUT_CHANGE 203 signal will generate a pulse of equal width in response to the frequency of CLK_32KHz 201. When the NEXT_State signal is low, the VCI_OUT_CHANGE 203 signal will generate a logic high signal until it is reset by the VBAT_RST 202 signal or the NEXT_State signal going high, allowing CLK_32KHz 201 to pass.

[0026] Figure 4 Flowcharts illustrating methods for exiting battery storage mode for FSM 200 based on various examples are shown, and Figure 5 Timing diagrams illustrating various signals associated with methods for exiting battery storage mode, based on various examples, are shown. (Reference) Figure 4 and Figure 5An example method for exiting battery storage mode begins in idle state 401, in which the first battery 102 is in storage mode. In idle state 401, the retry count (RETRY_CNT) stored in retry counter 240 is set to zero by a retry count reset signal RST_RETRY_CNT output by FSM 200. When a power-on event occurs (such as a user pressing the power button of a portable electronic device or turning on a laptop computer), a signal indicating the power-on event is generated and received by the controller. Figure 5 In an example implementation, the wake-up signal 123 changes from a logic high level to a logic low level and then back to a logic high level to indicate a power-on event. In response to the wake-up signal 123 indicating a power-on event, specifically the rising edge of the wake-up signal 123, the VCI_OUT signal 124 generated by the second processing circuitry 120 (e.g., by FSM 200) can change from a logic low level to a logic high level. As described above... Figure 3 As explained, the change detection circuit 220 of the second processing circuit 120 receives the VCI_OUT signal 124 and outputs a VCI_OUT_CHANGE signal 203 at a logic high level (shown as a positive pulse of equal width in response to the frequency of CLK_32KHz 201) to indicate that the VCI_OUT signal 124 has changed the logic state from low to high.

[0027] When the VCI_OUT_CHANGE signal 203 goes high, if the exit memory mode enable bit (SM_EN) stored in the memory mode register 210 is enabled ( Figure 4 The value in the battery output is set to zero), and the battery output digital indicator signal BPLUS122 indicates that the first battery 102 is not supplying power. Figure 4 If the logic value in the output signal is low, the state machine enters the LOAD_500MS_CNT state 402. In this state, the exit signal SYS_PRES# 125 becomes logic high, such as... Figure 5 As shown, the counter is set to determine the predetermined time for the width of the exit signal. Figure 4 and Figure 5 In the example implementation, the predetermined width of the exit signal is 500ms, but other widths can be used. In LOAD_500MS_CNT state 402, FSM 200 outputs a load count signal LOAD_CNT and a count value CNT_VAL to the decrement counter 230, causing the decrement counter 230 to set the count CNT to be equal to the count value CNT_VAL. Figure 4 and Figure 5 In the example, the count value CNT_VAL can be equal to 500ms.

[0028] FSM 200 then transitions to the DOWN_CNT1 state 403, in which the decrement counter 230 counts down from the count value CNT_VAL until the decrement counter 230 reaches zero. During the DOWN_CNT1 state 403, the exit signal SYS_PRES# 125 remains logic high.

[0029] When the decrement counter 230 reaches zero, it outputs a count signal CNT==0 to the FSM 200 indicating that the decrement counter 230 has reached zero. In response to receiving the count signal CNT==0, the FSM 200 enters the LOAD_WAIT_CNT state 404. In this state, the FSM 200 sets the exit signal 125 back to logic low and outputs a load count signal LOAD_CNT and a count value CNT_VAL to the decrement counter 230 to set a predetermined time period to wait after a predetermined edge (e.g., a falling edge) of the exit signal 125, after which it determines whether the first battery 102 is supplying power to the first processing circuit 110.

[0030] For example, if the exit storage count mode bit stored in storage mode register 210 is set to indicate a fixed count mode, the count value CNT_VAL can be one second. If the exit storage count mode bit is set to indicate an increment count mode, i.e., where the delay time for waiting for the main battery to exit battery storage mode in the first instance can be different from the delay mode provided for subsequent instances, the count value CNT_VAL can be set to a maximum of five seconds. Decrement counter 230 sets the count CNT to be equal to the count value CNT_VAL.

[0031] After setting the count CNT, the FSM enters the DOWN_CNT2 state 405. In this DOWN_CNT2 state, the decrement counter 230 counts down from the predetermined amount of time set in the LOAD_WAIT_CNT state 404 to wait after the falling edge of the exit signal 125. The FSM then determines whether the first battery 102 is supplying power to the first processing circuit 110. During the DOWN_CNT2 state 405, the exit signal 125 remains logic low. When the decrement counter 230 reaches zero, it outputs a count value CNT==0 to the FSM 200, causing the FSM 200 to enter the CHECK_BPLUS state 406. Alternatively, even if the count value CNT is not zero, if the battery output digital indicator signal BPLUS 122 is logic high, indicating that power is being provided by the first battery 102, and the retry count RETRY_CNT stored in the retry counter 240 is not equal to zero, then the FSM 200 will enter the CHECK_BPLUS state 406. In the CHECK_BPLUS state 406, the FSM 200 increments the retry count RETRY_CNT stored in the retry counter 240 and provided to the FSM 200 by sending a retry increment signal RETRY_CNT++ to the retry counter 240, indicating that an attempt to exit battery storage mode has occurred. In the CHECK_BPLUS state 406, the FSM 200 determines whether the battery output digital indicator signal BPLUS 122 is logic high or logic low. If the battery output digital indicator signal BPLUS 122 is logic low and the retry count RETRY_CNT is less than the maximum allowed number of retries, as indicated by the maximum retry count bit stored in the storage mode register 210, then the FSM 200 returns to the LOAD_500MS_CNT state 402 to generate a second exit signal by setting the exit signal SYS_PRES# 125 to logic high, thereby attempting to exit the battery storage mode of the first battery 102 again. Alternatively, if the battery output digital indicator signal BPLUS 122 is logic high or the number of retries equals the maximum allowed number of retries, then the FSM 200 returns to the idle state 401. The battery output digital indicator signal BPLUS 122 in the logic high state indicates that the first battery output 115 has begun supplying power to the first processing circuit 110, thus allowing a full startup process to occur. Figure 4 As shown, any other state of FSM 200 ( Figure 4 The "Other" option in the text will default to idle state 401, such as any unused state. By placing the device in battery storage mode during manufacturing and exiting battery storage mode as explained herein, the initial charge of the first battery 102 can be sustained for a longer period of time.

[0032] Various examples have been disclosed herein in conjunction with the foregoing description and accompanying drawings. It should be understood that describing and illustrating each combination and sub-combination of these examples literally would be an undue repetition. Therefore, all examples can be combined in any manner and / or combination, and this specification (including the accompanying drawings) should be construed as constituting a complete written description of all combinations and sub-combinations of the examples described herein, as well as the ways and processes of preparing and using them, and should support any claims to any such combinations or sub-combinations.

[0033] Those skilled in the art will understand that the examples described herein are not limited to those specifically shown and described above. Furthermore, unless the contrary is mentioned above, it should be noted that all figures are not drawn to scale. Various modifications and variations are possible in accordance with the above teachings.

Claims

1. A method for exiting a battery storage mode, the method comprising: Receive a wake-up signal indicating a power-on event when the first battery is in the battery storage mode; In response to the wake-up signal, an exit signal is generated to cause the first battery to supply power to the first processing circuit. Wait for a predetermined time period after the predetermined edge of the exit signal; After the predetermined time period expires, determine whether the first battery is supplying power to the first processing circuit. as well as A second exit signal is generated in response to determining that the first battery is not supplying power to the first processing circuit; In the battery storage mode, the second battery supplies power to the second processing circuit to execute the method of causing the first battery to exit the battery storage mode.

2. The method of claim 1, wherein the first battery and the second battery are respective portions of a single rechargeable battery.

3. The method according to claim 1, wherein the exit signal is a pulse signal having a predetermined pulse width.

4. The method of claim 1, wherein the method includes entering an idle state in response to determining that the first battery is supplying power to the first processing circuit.

5. The method according to claim 1, wherein the method comprises: In response to determining that the first battery is not supplying power to the first processing circuit, determine whether the maximum number of retries has been reached; as well as In response to determining that the maximum number of retries has not been reached, a second exit signal is generated to enable the first battery to supply power to the first processing circuit.

6. The method according to claim 5, wherein the method comprises: In response to determining that the maximum number of retries has been reached, the second processing circuit enters an idle state, in which the second processing circuit waits to receive a second wake-up signal.

7. A controller for exiting a first battery storage mode to provide power to a first processing circuit, the controller comprising: A second processing circuit, the second processing circuit being used for at least: Receive a wake-up signal indicating a power-on event when the first battery is in the battery storage mode; In response to the wake-up signal, an exit signal is generated to cause the first battery to supply power to the first processing circuit; Wait for a predetermined time period after the predetermined edge of the exit signal; After the predetermined time period expires, determine whether the first battery is supplying power to the first processing circuit. as well as A second exit signal is generated in response to determining that the first battery is not supplying power to the first processing circuit; In the battery storage mode, the second battery provides power to the second processing circuit.

8. The controller according to claim 7, wherein the exit signal is a pulse signal having a predetermined pulse width.

9. The controller of claim 7, wherein the second processing circuitry is configured to enter an idle state in response to determining that the first battery is supplying power to the first processing circuitry.

10. The controller of claim 7, wherein the second processing circuit is used for: In response to determining that the first battery is not supplying power to the first processing circuit, it is determined whether the maximum number of retries has been reached; and In response to determining that the maximum number of retries has not been reached, a second exit signal is generated to enable the first battery to supply power to the first processing circuit.

11. The controller of claim 10, wherein the second processing circuit is configured to enter the idle state in response to determining that the maximum number of retries has been reached, wherein in the idle state the second processing circuit waits to receive a second wake-up signal.

12. The controller of claim 7, wherein the first battery and the second battery are respective portions of a single rechargeable battery.

13. The controller of claim 8, wherein the first processing circuit is configured to initiate a startup sequence after the first battery begins supplying power to the first processing circuit.

14. A controller for exiting a battery storage mode for a first battery, the controller comprising: A first processing circuit, which is powered by the output of the first battery; as well as A second processing circuit, powered by the output of a second battery, is used for at least: Receive a wake-up signal indicating a power-on event when the first battery is in the battery storage mode; In response to the wake-up signal, an exit signal is generated to cause the first battery to supply power to the first processing circuit; Wait for a predetermined time period after the predetermined edge of the exit signal; Determine whether the first battery is supplying power to the first processing circuit; as well as A second exit signal is generated in response to determining that the first battery is not supplying power to the first processing circuit; In the battery storage mode, the first battery does not provide power to the first processing circuit; and The first processing circuit is used to initiate a startup sequence after the first battery begins supplying power to the first processing circuit.

15. The controller of claim 14, wherein the exit signal is a pulse signal having a predetermined pulse width.

16. The controller of claim 14, wherein the second processing circuitry is configured to enter an idle state in response to determining that the first battery is supplying power to the first processing circuitry.

17. The controller of claim 14, wherein the second processing circuitry is configured to: In response to determining that the first battery is not supplying power to the first processing circuit, it is determined whether the maximum number of retries has been reached; and In response to determining that the maximum number of retries has not been reached, a second exit signal is generated to enable the first battery to supply power to the first processing circuit.

18. The controller of claim 17, wherein the second processing circuit is configured to enter the idle state in response to determining that the maximum number of retries has been reached, wherein in the idle state the second processing circuit waits to receive a second wake-up signal.

19. The controller of claim 14, wherein the first battery and the second battery are respective portions of a single rechargeable battery.

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