Semiconductor chip and electronic device

Abstract

Provided is a semiconductor chip capable of suppressing a region in which a product circuit is disposed from being squeezed by a TEG. The semiconductor chip includes: a first semiconductor substrate on which a first circuit is disposed; a second semiconductor substrate on which a second circuit is disposed and which overlaps and is bonded to the first surface of the first semiconductor substrate; the test element group comprises a device to be tested and a test circuit used for testing the device to be tested and is configured on the first semiconductor substrate and the second semiconductor substrate, only the device to be tested and the device to be tested in the test circuit are configured on the second semiconductor substrate, and the test element group is configured on the first semiconductor substrate and the second semiconductor substrate. The test circuit is disposed on the first semiconductor substrate.

Description

Technical Field

[0001] This technology (based on the technology disclosed herein) relates to semiconductor chips and electronic devices, and in particular to semiconductor chips and electronic devices having a TEG (test element group). Background Technology

[0002] Patent Document 1 discloses a test structure for process monitoring of CoW (Chip-on-Wafer) and WoW (Wafer-on-Wafer). In Patent Document 1, the test circuit and the DUT (Device Under Test) are arranged in the same plane. List of cited references Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-46569 Summary of the Invention The technical problem that the invention aims to solve

[0004] In Patent Document 1, since the test circuit and the DUT are set in the same plane, there is a possibility that the area where the product circuit is configured may be squeezed by the TEG.

[0005] The purpose of this technology is to provide semiconductor chips and electronic devices that can suppress the compression of product circuitry areas by TEG. Technical solutions to solve technical problems

[0006] A semiconductor chip according to one aspect of the present technology includes: a first semiconductor substrate on which a first circuit is disposed; a second semiconductor substrate on which a second circuit is disposed, and which overlaps and is bonded to a first surface of the first semiconductor substrate; and a test element group including a device under test (DUT) and a test circuit for testing the DUT, and disposed on the first semiconductor substrate and the second semiconductor substrate, wherein only the DUT and the DUT in the test circuit are disposed on the second semiconductor substrate, and the test circuit is disposed on the first semiconductor substrate.

[0007] An electronic device according to one aspect of the present technology includes a semiconductor chip and an optical system, the optical system forming an image of image light from a subject on the semiconductor chip. Attached Figure Description

[0008] Figure 1 This is a chip layout diagram illustrating an example configuration of a semiconductor chip according to a first embodiment of the present technology. Figure 2 This is a longitudinal cross-sectional view showing the cross-sectional configuration of a semiconductor chip according to a first embodiment of the present technology. Figure 3This is a block diagram illustrating the configuration of an OCMT according to a first embodiment of the present technology. Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor chip according to a first embodiment of the present technology. Figure 5 This is a plan view showing a first semiconductor wafer according to a first embodiment of the present technology. Figure 6 It is shown in an enlarged manner Figure 5 A magnified view of a portion of the area. Figure 7 This is a plan view showing a second semiconductor substrate obtained by monolithizing a second semiconductor wafer according to a first embodiment of the present technology. Figure 8 This is a longitudinal cross-sectional view showing the cross-sectional configuration of a semiconductor chip according to a comparative example. Figure 9 This is a longitudinal cross-sectional view showing the cross-sectional configuration of a semiconductor chip according to a modified example 1 of the first embodiment of the present technology. Figure 10 It is shown Figure 9 The diagram illustrates the state of a semiconductor chip mounted on an interposer. Figure 11 This is a longitudinal cross-sectional view showing the cross-sectional configuration of a semiconductor chip according to a modified example 2 of the first embodiment of the present technology. Figure 12 This is a longitudinal cross-sectional view showing the cross-sectional configuration of a semiconductor chip according to a modified example 3 of the first embodiment of the present technology. Figure 13 This is a longitudinal cross-sectional view showing the cross-sectional configuration of a semiconductor chip according to a modified example 4 of the first embodiment of the present technology. Figure 14 This is a flowchart illustrating a method for manufacturing a semiconductor chip according to a variation 5 of the first embodiment of the present technology. Figure 15 This is a chip layout diagram illustrating an example configuration of a semiconductor chip according to a second embodiment of the present technology. Figure 16 This is a block diagram illustrating an example configuration of a semiconductor chip according to a second embodiment of the present technology. Figure 17 This is an equivalent circuit diagram of a pixel of a semiconductor chip according to the second embodiment of the present technology. Figure 18 This is an explanatory diagram showing the stacked structure of a semiconductor chip according to a second embodiment of the present technology. Figure 19 This is a longitudinal cross-sectional view showing a portion of a semiconductor chip according to a second embodiment of the present technology. Figure 20 This is a longitudinal cross-sectional view showing a portion of a semiconductor chip according to a second embodiment of the present technology, modified 1. Figure 21 This is a longitudinal cross-sectional view showing a portion of a semiconductor chip according to a second embodiment of the present technology, modified 1. Figure 22 This is a longitudinal cross-sectional view showing the cross-sectional configuration of a semiconductor chip according to a modified example 2 of the second embodiment of the present technology. Figure 23 This is a block diagram illustrating an example of a schematic configuration of an electronic device. Detailed Implementation

[0009] In the following description, preferred embodiments for implementing the present technology will be described with reference to the accompanying drawings. Note that the following embodiments are intended to illustrate examples of representative embodiments of the present technology, and the scope of the present technology should not be narrowly interpreted in light of these embodiments.

[0010] In the following figures, identical or similar parts are indicated by identical or similar reference numerals. It should be noted that the figures are schematic, and the relationships between thicknesses and planar dimensions, the thickness ratios between layers, etc., differ from actual conditions. Therefore, the following description should be considered to determine specific thicknesses and dimensions. Furthermore, it goes without saying that dimensional relationships and scales will differ partially between the figures. Additionally, due to the use of figures suitable for describing this technology, the configuration of the figures may vary.

[0011] Furthermore, the following embodiments illustrate apparatus and methods for embodying the technical concept of this technology, and the technical concept of this technology is not intended to limit the materials, shapes, structures, layouts, etc., of the components to those described below. Various modifications can be made to the technical concept of this technology within the scope of the claims.

[0012] Furthermore, the definitions of directions such as up and down in the following description are merely for ease of description and are not intended to limit the technical ideas of this disclosure. For example, it is unmistakable that when an object is viewed by rotating it 90°, up and down are converted and read as left and right, while when an object is viewed by rotating it 180°, up and down are reversed and read.

[0013] The descriptions will be presented in the following order. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment Application examples of electronic devices

[0014] [First Embodiment] In this embodiment, an example of applying the technology to a semiconductor chip having a structure in which multiple semiconductor substrates are stacked via chip-on-wafer (CoW).

[0015] <<On-Chip Monitor TEG>> As a method for manufacturing semiconductor chips with a stacked structure of multiple semiconductor substrates, there are technologies called wafer-on-wafer (WoW) for bonding semiconductor wafers to each other, and technologies called chip-on-wafer (CoW) for bonding monolithic semiconductor chips to semiconductor wafers. Furthermore, test patterns called test element groups (TEGs) are typically set in semiconductor chips to evaluate and manage circuit characteristics.

[0016] In semiconductor chip manufacturing processes using monolayer semiconductor chips or WoW (Work of Work), a TEG (Divider TEG) is typically set up in a dicing area, and testing is performed using the dicing TEG. In the dicing area, dicing pads are set for each device to be inspected. Testing is performed by bringing the probes of the inspection device into contact with the dicing pads of each device to be inspected. Then, after testing using the dicing TEG, a dicing process is performed to obtain a monolithic semiconductor chip. The dicing TEG is destroyed by the dicing process and becomes unusable thereafter.

[0017] In the case of semiconductor chip manufacturing via CoW (Co-Wave), the semiconductor chip to be bonded to the semiconductor wafer has already been monolithized, and the dicing area has been lost. Therefore, in CoW, it is necessary to place a TEG (Technical On-Glass Regulator) in the area where the product circuitry is located, not in the dicing area. This TEG is called an on-chip monitor TEG (hereinafter referred to as OCMT). Since the OCMT is not destroyed during monolithization, it can be used for testing even after monolithization. Therefore, the circuit characteristics of the semiconductor chip can be continuously monitored. Figure 8 This is a diagram showing a longitudinal cross-sectional configuration of a semiconductor chip 2X according to a comparative example. The semiconductor chip 2X has a stacked structure of a first semiconductor substrate A and a second semiconductor substrate B. In the semiconductor chip 2X, in addition to the product circuit Ba, an OCMT 9X including a test circuit X and a device under test (DUT) Y is also disposed. Since both the test circuit X and the DUT Y are disposed on the second semiconductor substrate B, the OCMT 9X may compress the area in the second semiconductor substrate B where the product circuit Ba is disposed.

[0018] <<Overall Configuration of Semiconductor Devices>> First, the overall configuration of semiconductor device 1 will be described. For example... Figure 1As shown, the semiconductor device 1 according to the first embodiment of the present technology mainly includes a semiconductor chip 2, which has a square two-dimensional planar shape in a plan view. That is, the semiconductor device 1 is mounted on the semiconductor chip 2. A plurality of bonding pads 14 are provided at the edges of the semiconductor chip 2. The plurality of bonding pads 14 are arranged, for example, along the four sides of the two-dimensional plane of the semiconductor chip 2. The plurality of bonding pads 14 are for electrically connecting the semiconductor chip 2 to the input / output terminals of an external device. The semiconductor device 1 includes an OCMT 9 as an on-chip monitor (TEG). The OCMT 9 is a test element group.

[0019] like Figure 2 As shown, the semiconductor chip 2 has a stacked structure of multiple semiconductor substrates. For example, the semiconductor chip 2 has a stacked structure of a first semiconductor substrate A and a second semiconductor substrate B. One surface of the second semiconductor substrate B overlaps and bonds with the first surface S1 of the first semiconductor substrate A. The first semiconductor substrate A is an example of a first semiconductor substrate, and the second semiconductor substrate B is an example of a second semiconductor substrate. In this embodiment, it is assumed that the first semiconductor substrate A is a substrate manufactured in-house, and the second semiconductor substrate B is a substrate purchased from another company. Although not shown, each of the first semiconductor substrate A and the second semiconductor substrate B has a stacked structure of semiconductor layers and multiple wiring layers. Furthermore, the semiconductor device 1 includes a product circuit Aa and a product circuit Ba electrically connected to each other as product circuits. Product circuit Aa is an example of a first circuit, and product circuit Ba is an example of a second circuit. Product circuit Aa is disposed on the first semiconductor substrate A, and product circuit Ba is disposed on the second semiconductor substrate B. Product circuit Aa can be a circuit of the same type as product circuit Ba, or it can be a circuit of a different type. While not limited to these, product circuit Aa is, for example, a logic circuit, and product circuit Ba is a storage circuit such as Dynamic Random Access Memory (DRAM), or a system-on-chip (SoC) circuit such as artificial intelligence (AI) or a CPU. The semiconductor chip 2 has wiring L that forms connection lines for various circuits. For example, a portion of wiring L is used to connect product circuit Aa and product circuit Ba.

[0020] The OCMT 9 is configured across a first semiconductor substrate A and a second semiconductor substrate B. The OCMT 9 includes a test circuit X, a device under test (DUT) Y electrically connected to the test circuit X, and measurement pads 14A electrically connected to the test circuit X. On the second semiconductor substrate B, only the DUT Y and the DUT Y from the test circuit X are configured. The test circuit X is configured on the first semiconductor substrate A. More specifically, only the DUT Y and the test circuit X from the test circuit X are configured on the first semiconductor substrate A. The OCMT 9 is a stacked test element group, wherein the test circuit X and the DUT Y are configured on different semiconductor substrates. Furthermore, the OCMT 9 is electrically isolated from the product circuits (product circuits Aa, Ba, etc.) configured in the semiconductor chip 2.

[0021] The OCMT 9 includes wiring L1 for the electrical connection test circuit X and measurement pad 14A, and wiring L2 for the electrical connection test circuit X and device under test (DUT) Y. Wiring L2 spans a first semiconductor substrate A and a second semiconductor substrate B. Wiring L1 and wiring L2 are other parts of wiring L. Without distinguishing between wiring L1, wiring L2, and other wiring L, they are simply referred to as wiring L. Wiring L includes conductors. Examples of materials constituting wiring L include metallic materials.

[0022] First, the test circuit X and the device under test (DUT) Y will be described. The DUT Y is a device that is separately configured as part of a product circuit for testing. Although not shown, multiple DUTs Y are disposed on the second semiconductor substrate B, and each of the multiple DUTs Y is connected to the test circuit X via wiring L2. The DUT Y can be a single element such as a transistor or a resistor, or it can be a circuit combining multiple elements. Furthermore, the DUT Y can be a test pattern used to evaluate the manufacturing process of a specific element. In this embodiment, the case where the DUT Y is a single element will be described. The DUT Y is the element under test and is disposed on an element-by-element basis. The DUT Y is an element of the same type as the element to be tested among the elements included in the product circuit Baa. Furthermore, the DUT Y is, for example, an element with the same technology node as the elements included in the product circuit Baa. As an example, in the case where it is desired to test an n-type MOSFET among the elements included in the product circuit Baa, the n-type MOSFET is separately disposed as the DUT Y on the second semiconductor substrate B. The device under test (DUT) Y is separately mounted on the same semiconductor substrate as the semiconductor substrate on which the product circuit Ba is located. For example... Figure 3As shown, for example, the device under test (DUT) Y is a component such as transistor Y1, capacitor Y2, or resistor Y3. Various types of DUTs Y can be disposed on the second semiconductor substrate B. Furthermore, to verify reproducibility, multiple components of the same type can be disposed on the second semiconductor substrate B as DUTs Y. For example, multiple transistors Y1, multiple capacitors Y2, and multiple resistors Y3 can be disposed, or multiple p-type MOSFETs as transistors Y1 can be disposed.

[0023] Test circuit X is a circuit that performs tests on the device under test (Y). For example... Figure 3 As shown, the test circuit X includes, for example, a selection circuit X1, a switch X2, and an oscillation circuit X3. The selection circuit X1 has the function of selecting a portion of a plurality of devices under test (DUTs) Y disposed on the second semiconductor substrate B. The switch X2 also has a switching function for switching the DUTs Y. The test circuit X tests the selected or switched DUTs Y. Hereinafter, the selection circuit X1 will be described as an example. When a signal is input to the selection circuit X1 via the measurement pad 14A, the selection circuit selects one or more of the plurality of DUTs Y according to the input signal. Then, the test circuit X has the function of testing the selected DUT Y based on the signal input to the selection circuit X1 from the outside via the measurement pad 14A. For example, if the selected element is a transistor Y1, the test circuit X tests the operation of the transistor Y1. Furthermore, for example, if the selected element is a capacitor Y2, the test circuit X tests the capacitance of the capacitor Y2 via the oscillation circuit X3. Furthermore, for example, if the selected element is a resistor Y3, the test circuit X tests the resistor Y3. Then, the test circuit X outputs the test results to the outside via the measurement pad 14A. Note that the test circuit X and the device under test Y can be as follows: Figure 2 The figures shown can overlap in the thickness direction, or they can not overlap in the thickness direction.

[0024] Measurement pads 14A, electrically connected to the test circuit X, are disposed on the semiconductor chip 2, such that one surface of the chip is exposed to the outside. In this embodiment, measurement pads 14A are disposed on the first semiconductor substrate A. Measurement pads 14A are specifically assigned to OCMT 9. Figure 1 This is a portion of the bonding pad 14 shown. Without distinguishing between the measurement pad 14A and other bonding pads 14, they are simply referred to as bonding pads 14. The measurement pad 14A includes conductors such as metals. Examples of materials constituting the measurement pad 14A include metals such as copper (Cu) and aluminum (Al).

[0025] <<Semiconductor Chip Manufacturing Methods>> In the following text, reference will be made to Figures 4 to 7A method for manufacturing semiconductor chip 2 is described. Note that in this embodiment, the CoW bonding will be described primarily, and descriptions of other parts may be omitted. The description will mainly follow... Figure 4 The flowchart shown is used for description.

[0026] First, prepare a first semiconductor wafer WA and a second semiconductor wafer WB (step S101), and then monolithize the second semiconductor wafer WB into a second semiconductor substrate B (step S102). Figure 5 The first semiconductor wafer WA is shown. Figure 6 It shows Figure 5 More specific configuration for region WA1. For example... Figure 6 As shown, in the first semiconductor wafer WA, substrate portions that become the first semiconductor substrate A in the case of monolithic fabrication have been formed along the row and column directions. A test circuit X is formed in each substrate portion that becomes the first semiconductor substrate A in the case of monolithic fabrication. Similarly, in the second semiconductor wafer WB, substrate portions that become the second semiconductor substrate B in the case of monolithic fabrication have also been formed along the row and column directions. Figure 7 A portion of a substrate portion of a second semiconductor substrate B, obtained by monolithizing a second semiconductor wafer WB, is shown. A device under test (DUT) Y is formed in each substrate portion of the monolithized second semiconductor substrate B.

[0027] Next, as Figure 4 As shown, the monolithically formed second semiconductor substrate B is bonded to the first semiconductor wafer WA (step S103). More specifically, only defect-free substrates (KGD: Known Good Die) that meet the criteria in the monolithically formed second semiconductor substrate B are selected and bonded to the first semiconductor wafer WA. By bonding the second semiconductor substrate B to the first semiconductor wafer WA, a stacked OCMT 9 is formed in the substrate portion of the semiconductor chip 2 in the monolithic case.

[0028] Subsequently, testing is performed using OCMT 9 (step S104). This testing is performed on each substrate portion that becomes a semiconductor chip 2 in the monolithic case by bringing the probes of the inspection device into contact with the measurement pads 14A. Since any device under test Y can be selected using at least one of the selection circuit X1 and the switch X2, multiple devices under test Y can be tested without moving the probes of the inspection device.

[0029] Then, for each substrate portion that becomes semiconductor chip 2 in the monolithic configuration, it is determined whether the test result of the device under test Y meets the reference value (step S105). For substrate portions determined to meet the reference value (step S105, Yes), sequential processing up to the final product is performed (step S106). For substrate portions determined not to meet the reference value (step S105, No), no processing up to the final product is performed. Note that test results in cases where the reference value is determined not to be met are fed back into the manufacturing process up to the present (step S107).

[0030] <<Main Effects of the First Embodiment>> The main effects of the first embodiment will be described below, preceded by a summary. Figure 8 In the semiconductor chip 2X shown according to the comparative example, since both the test circuit X and the device under test Y are disposed on the second semiconductor substrate B, the OCMT 9X may encroach upon the area in the second semiconductor substrate B where the product circuit Ba is disposed. Furthermore, when using a general-purpose product such as DRAM or SoC as the second semiconductor substrate B, for example, the production of the general-purpose product can be outsourced to other companies, and the manufactured wafers or chips can be purchased. Configuring a test circuit X, which has a design complexity comparable to that of an outsourced chip, is not easy. Moreover, by configuring the test circuit X on an outsourced chip, technology may be leaked to the outsourcing company.

[0031] On the other hand, the semiconductor chip 2 according to the first embodiment of the present invention includes an OCMT 9, which has a device under test (DUT) Y and a test circuit X for testing the DUT Y and is disposed on a first semiconductor substrate A and a second semiconductor substrate B. Only the DUT Y and the DUT X from the test circuit are disposed on the second semiconductor substrate B, while the test circuit X is disposed on the first semiconductor substrate A. The test circuit X and the DUT Y are disposed in a dispersed manner on different semiconductor substrates. Therefore, the area where product circuits Aa and Ba are disposed can be suppressed from being squeezed by the OCMT 9. Furthermore, since the OCMT 9 is disposed by utilizing blank areas in each of the first semiconductor substrate A and the second semiconductor substrate B where no circuits such as product circuits are formed, the OCMT 9 can be disposed while suppressing the squeezing of the area where product circuits Aa and Ba are disposed.

[0032] Furthermore, since the semiconductor chip 2 according to the first embodiment of this technology has the above-described configuration, compared to the case where both the test circuit X and the device under test Y are disposed on the second semiconductor substrate B, the area occupied by the OCMT 9 on the second semiconductor substrate B can be prevented from becoming too large. With this arrangement, the area of ​​the second semiconductor substrate B where the product circuit Ba is disposed can be prevented from being squeezed. More specifically, when the chip size is the same, the insufficiency of the area constituting the product circuit Ba in the second semiconductor substrate B can be prevented. Furthermore, while ensuring the area constituting the product circuit Ba, an increase in chip size can be prevented.

[0033] Furthermore, since the semiconductor chip 2 according to the first embodiment of this technology has the above-described configuration, a margin is generated in the region of the second semiconductor substrate B, and the number of devices under test (DUTs) Y can be increased. With this arrangement, various types of DUTs Y can be provided, and more types of measurement items can be employed. Moreover, with this arrangement, the number of DUTs Y of the same type can be increased, and the reliability of the test can be improved.

[0034] Furthermore, since the semiconductor chip 2 according to the first embodiment of the present technology has the above-described configuration, the design burden of the outsourcing company can be reduced, and the technology leakage to the outsourcing company can be suppressed.

[0035] Furthermore, in the semiconductor chip 2 according to the first embodiment of the present technology, the OCMT 9 includes a measurement pad 14A electrically connected to the test circuit X and configured to expose one surface of the measurement pad 14A. Therefore, when testing is performed, multiple devices under test Y can be tested without moving the probes of the inspection device.

[0036] Furthermore, in the semiconductor chip 2 according to the first embodiment of this technology, a plurality of devices under test (DUTs) Y are disposed on the second semiconductor substrate B, and the chip includes a selection circuit X1 for selecting a portion of the plurality of DUTs Y, a switch X2 for switching the DUTs Y, etc. Since the selection circuit X1 and the switch X2 can select any DUT Y, the plurality of DUTs Y can be tested without moving the probes of the inspection device.

[0037] Furthermore, in the semiconductor chip 2 according to the first embodiment of this technology, the second semiconductor substrate B on which the device under test (DUT) Y is disposed overlaps and is bonded to the first semiconductor substrate A on which the test circuit X is disposed. Therefore, compared with the case where the first semiconductor substrate A and the second semiconductor substrate B are arranged side by side, the length of the wiring L2 can be shortened. With this arrangement, the resistance between the test circuit X and the DUT Y can be reduced, and power consumption can be suppressed. In addition, by arranging the test circuit X and the DUT Y to overlap in the planar view, the area occupied by the OCMT 9 can be prevented from becoming too large in the planar view.

[0038] Furthermore, since the semiconductor chip 2 according to the first embodiment of this technology includes an OCMT 9 instead of a dicing TEG, testing can be performed even after monolithization. In a dicing TEG, there are cases where wiring extends from the dicing pads and connects to the test circuit, and the wiring needs to be arranged in a way that passes through a protective ring provided in the peripheral edge portion of the semiconductor chip 2 without damaging the protective ring. On the other hand, in the semiconductor chip 2 according to the first embodiment of this technology, since the OCMT 9 is not provided in the dicing lines and is completely contained within the chip, the protective ring is almost unaffected.

[0039] <<Modifications of the First Embodiment>> In the following text, variations of the first embodiment will be described.

[0040] <Variation Example 1> In the semiconductor chip 2 according to the first embodiment, such as Figure 2 As shown, the measuring pad 14A is disposed on the first semiconductor substrate A, but the technology is not limited thereto. Figure 9 In the semiconductor chip 2 shown in Modified Example 1 of the first embodiment, a measurement pad 14A is disposed on a second semiconductor substrate B. A wiring L1 is disposed across the first semiconductor substrate A and the second semiconductor substrate B. Figure 10 As shown, the semiconductor chip 2 according to this modification can be mounted on the inserter P and the device under test Y can be tested. The inserter P is a substrate with electrical wiring laid on it. When the semiconductor chip 2 is mounted on the inserter P, the measuring pad 14A contacts the upper surface terminal Pa of the inserter P.

[0041] Even in the semiconductor chip 2 of the modified example 1 according to the first embodiment, similar effects to those of the semiconductor chip 2 according to the first embodiment described above can be obtained.

[0042] Furthermore, in the semiconductor chip 2 of the modified example 1 according to the first embodiment, since the semiconductor chip 2 is mounted on the inserter P and the device under test Y is tested, the inspection becomes easier.

[0043] Note that in the above variation, the monolithized semiconductor chip 2 is mounted on the inserter P for testing the device under test Y. However, the unmonolithified wafer can also be mounted on the inserter P for testing the device under test Y.

[0044] <Variation Example 2> like Figure 2 As shown, the second semiconductor substrate B included in the semiconductor chip 2 according to the first embodiment is a single one, but the technology is not limited thereto. Figure 11The semiconductor chip 2 shown in Modification 2 of the first embodiment includes a plurality of second semiconductor substrates B. That is, in the plan view, the plurality of second semiconductor substrates B are bonded side by side to the first semiconductor substrate A.

[0045] Figure 11 An example is shown where the semiconductor chip 2 includes two second semiconductor substrates B1 and B2, but the semiconductor chip 2 may include more than three second semiconductor substrates. One surface of each of the second semiconductor substrates B1 and B2 overlaps and bonds to the first surface S1 of the first semiconductor substrate A. Without distinguishing between the second semiconductor substrates B1 and B2, they are simply referred to as the second semiconductor substrate B. The second semiconductor substrates B1 and B2 have a similar configuration to the second semiconductor substrate B.

[0046] A product circuit B1a is disposed on a second semiconductor substrate B1, and a product circuit B2a is disposed on a second semiconductor substrate B2. Product circuit B1a can be the same type as product circuit B2a, or it can be a different type of circuit. While not limited to this, for example, product circuit B1a could be a memory circuit such as DRAM, and product circuit B2a could be a SoC circuit such as artificial intelligence or a CPU. The semiconductor chip 2 has wiring L that forms the connection wiring for various circuits. Product circuit B1a and product circuit Aa are connected by wiring L, and product circuit B2a and product circuit Aa are connected by wiring L.

[0047] Multiple devices under test (DUTs) Y are disposed on each of the second semiconductor substrate B1 and the second semiconductor substrate B2. To distinguish the DUTs Y disposed on the second semiconductor substrate B1 from those disposed on the second semiconductor substrate B2, the DUTs Y disposed on the second semiconductor substrate B1 are referred to as DUTs Ya, and the DUTs Y disposed on the second semiconductor substrate B2 are referred to as DUTs Yb. When there is no need to distinguish between DUTs Ya and Yb, they are simply referred to as DUTs Y. OCMT 9 includes DUTs Ya and Yb. DUT Ya and test circuit X are connected via wiring L21, and DUTs Yb and test circuit X are connected via wiring L22. When there is no need to distinguish between wiring L21 and wiring L22, they are simply referred to as wiring L2. DUT Ya is a component of the same type as the component under test included in product circuit B1a. DUT Yb is a component of the same type as the component under test included in product circuit B2a.

[0048] The test circuit X has the function of selecting a device under test (DUT) Y disposed on any of the plurality of second semiconductor substrates B1 and B2 and testing the selected DUT Y. For example, the test circuit X selects one of a DUT Ya disposed on the second semiconductor substrate B1 and a DUT Yb disposed on the second semiconductor substrate B2. The test circuit X selects the DUT Y by using at least one of a selection circuit X1 and a switch X2.

[0049] Even in the semiconductor chip 2 of the modified example 2 according to the first embodiment, similar effects as those of the semiconductor chip 2 according to the first embodiment described above can be obtained.

[0050] Furthermore, according to Modification 2 of the first embodiment, the semiconductor chip 2 includes a plurality of second semiconductor substrates B, and the test circuit X has the function of selecting a device under test (DUT) Y disposed on any of the plurality of second semiconductor substrates B and testing the selected DUT Y. As described above, since the plurality of DUTs Y disposed on the plurality of second semiconductor substrates B share a single test circuit X, it is not necessary to provide multiple test circuits X for the first semiconductor substrate A, and the area of ​​the first semiconductor substrate A where the product circuit Aa is disposed can be suppressed.

[0051] <Variation Example 3> like Figure 2 As shown, the first semiconductor substrate A included in the semiconductor chip 2 according to the first embodiment is a single one, but the technology is not limited thereto. Figure 12 The semiconductor chip 2 shown in Modification 3 of the first embodiment includes a plurality of first semiconductor substrates A. That is, the plurality of first semiconductor substrates A are stacked and bonded in the thickness direction.

[0052] Figure 12 An example is shown where the semiconductor chip 2 includes two first semiconductor substrates A1 and A2, but the semiconductor chip 2 may include three or more first semiconductor substrates. The first semiconductor substrate A2 overlaps and is bonded to a second surface S2, which is the surface of the first semiconductor substrate A1 opposite to the first surface S1. Without distinguishing between the first semiconductor substrate A1 and the first semiconductor substrate A2, they are simply referred to as the first semiconductor substrate A.

[0053] A product circuit A1a is disposed on a first semiconductor substrate A1, and a product circuit A2a is disposed on a first semiconductor substrate A2. Product circuit A1a can be the same type of circuit as product circuit A2a, or it can be a different type of circuit. While not limited to this, for example, both product circuit A1a and product circuit A2a are logic circuits. The semiconductor chip 2 has wiring L that forms connection lines for various circuits. Product circuit Ba and product circuit A1a are connected by wiring L, and product circuit A1a and product circuit A2a are connected by wiring L.

[0054] Test circuit X is disposed on one of a plurality of first semiconductor substrates A. For example, test circuit X is disposed only on first semiconductor substrate A2 of first semiconductor substrates A1 and A2. For example, the location of test circuit X among the plurality of first semiconductor substrates A can be determined according to the technology node of the semiconductor substrates. For example, when the substrate with high performance is first semiconductor substrate A2, the area occupied by test circuit X can be saved by disposing of test circuit X on first semiconductor substrate A2. Wiring L2 is disposed from first semiconductor substrate A2 to second semiconductor substrate B and electrically connects test circuit X and device under test Y.

[0055] Even in the semiconductor chip 2 of the modified example 3 according to the first embodiment, similar effects as those of the semiconductor chip 2 according to the first embodiment described above can be obtained.

[0056] <Variation Example 4> In the semiconductor chip 2 according to the modified example 3 of the first embodiment, such as Figure 12 As shown, the test circuit X is configured on one of a plurality of first semiconductor substrates A, but the technology is not limited thereto. Figure 13 In the semiconductor chip 2 shown in Modified Example 4 of the first embodiment, the test circuit X is disposed on a plurality of first semiconductor substrates A in a distributed manner.

[0057] Figure 13An example is shown where the semiconductor chip 2 includes two first semiconductor substrates A1 and A2. For example, test circuit X is disposed on the first semiconductor substrates A1 and A2 in a distributed manner. The portion of test circuit X disposed on the first semiconductor substrate A1 is referred to as test circuit Xa, and the portion of test circuit X disposed on the first semiconductor substrate A2 is referred to as test circuit Xb, to distinguish them from each other. When it is not necessary to distinguish between test circuit Xa and test circuit Xb, they are simply referred to as test circuit X. Furthermore, test circuit Xa and test circuit Xb can be collectively referred to as test circuit X. The OCMT9 includes wiring L1 for electrically connecting test circuit Xb and measurement pad 14A, wiring L3 for electrically connecting test circuit Xb and test circuit Xa, and wiring L2 for electrically connecting test circuit Xa and device under test Y.

[0058] Even in the semiconductor chip 2 of Modified Example 4 according to the first embodiment, similar effects to those of the semiconductor chip 2 of Modified Example 3 according to the first embodiment can be obtained. Furthermore, in the semiconductor chip 2 of Modified Example 4 according to the first embodiment, since the test circuit X is disposed in a distributed manner on multiple first semiconductor substrates A, it is possible to prevent the area occupied by the test circuit X in each first semiconductor substrate A1 and A2 from becoming too large. With this arrangement, it is possible to further prevent the areas where product circuits A1a and A2a are disposed from being squeezed by the test circuit X.

[0059] <Variation Example 5> In the manufacturing method of semiconductor chip 2 according to the first embodiment, such as Figure 4 As shown, semiconductor chip 2 is formed by CoW, but this technology is not limited to this. Figure 14 In the method for manufacturing semiconductor chip 2 according to Modification 5 of the first embodiment, semiconductor chip 2 is formed by WoW.

[0060] First, a first semiconductor wafer WA and a second semiconductor wafer WB are prepared (step S201), and the second semiconductor wafer WB is bonded to the prepared first semiconductor wafer WA (step S202). Then, testing is performed using an OCMT 9 (step S203). Since the process in step S203 is similar to that in step S104 described above, its description will be omitted. Next, for each substrate portion that becomes a semiconductor chip 2 in the case of monolithic assembly, it is determined whether the test result of the device under test Y meets the reference value (step S204). For substrate portions determined to meet the reference value (step S204, yes), sequential processing up to the final product is performed (step S205). For substrate portions determined not to meet the reference value (step S204, no), no processing up to the final product is performed. Note that the test results in cases where the reference value is determined not to be met are fed back into the manufacturing process up to this point (step S206).

[0061] Even in the semiconductor chip 2 of the modified example 5 according to the first embodiment, similar effects as those of the semiconductor chip 2 according to the first embodiment described above can be obtained.

[0062] Furthermore, in the semiconductor chip 2 of the modified example 5 according to the first embodiment, since an OCMT is configured instead of a dicing TEG, even if the semiconductor chip 2 is formed by WoW, it can be tested using an OCMT 9 after monolithization.

[0063] [Second Embodiment] The following will describe Figures 15 to 19 The second embodiment of the present technology is shown. In this embodiment, an example of the present technology being applied to a light detection device as a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor will be described. That is, semiconductor device 1 is a light detection device.

[0064] <<Overall Configuration of Semiconductor Devices>> First, the overall configuration of the semiconductor device 1, which serves as a photodetector, will be described. For example... Figure 15 As shown, the semiconductor device 1 according to the first embodiment of this technology mainly includes a semiconductor chip 2, which has a square two-dimensional planar shape in the plan view. That is, the semiconductor device 1 is mounted on the semiconductor chip 2. Figure 23 As shown, the semiconductor device 1 captures image light (incident light 106) from the subject through an optical system (optical lens) 102, converts the amount of light of the incident light 106 that forms an image on the imaging surface into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal.

[0065] like Figure 15 As shown, in a two-dimensional plane including the intersecting X and Y directions, a semiconductor chip 2 on which a semiconductor device 1 is mounted includes a square pixel region 2A disposed in the central part and a peripheral region 2B disposed outside the pixel region 2A in a manner that surrounds the pixel region 2A.

[0066] Pixel region 2A, for example, is received by Figure 23 The optical system 102 shown has a light-receiving surface that converges light. Then, in pixel region 2A, a plurality of pixels 3 are arranged in a matrix within a two-dimensional plane including the X and Y directions. In other words, pixels 3 are repeatedly arranged in each of the intersecting X and Y directions within the two-dimensional plane. Note that in this embodiment, for example, the X and Y directions are orthogonal to each other. Furthermore, the direction orthogonal to both the X and Y directions is the Z direction (thickness direction, stacking direction). Additionally, the direction perpendicular to the Z direction is the horizontal direction.

[0067] like Figure 15 As shown, a plurality of bonding pads 14 are arranged in the peripheral region 2B. For example, each of the plurality of bonding pads 14 is arranged along each of the four sides of the semiconductor chip 2 in a two-dimensional plane. Each of the plurality of bonding pads 14 is used for electrically connecting the semiconductor chip 2 to an input / output terminal of an external device.

[0068] <Logic Circuits> like Figure 16 As shown, semiconductor chip 2 includes logic circuit 13. Logic circuit 13 includes vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, output circuit 7, control circuit 8, etc. Logic circuit 13 includes complementary MOS (CMOS) circuitry, which includes, for example, an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a p-channel MOSFET as field-effect transistors.

[0069] The vertical driving circuit 4 includes, for example, a shift register. The vertical driving circuit 4 sequentially selects the desired pixel driving lines 10 and supplies pulses for driving the pixels 3 to the selected pixel driving lines 10 to drive each pixel 3 row by row. That is, the vertical driving circuit 4 sequentially selects and scans each pixel 3 in the pixel region 2A row by row in the vertical direction, and supplies a pixel signal from each pixel 3, based on the signal charge generated by the photoelectric conversion element of the pixel 3 according to the received light quantity, to the column signal processing circuit 5 via the vertical signal line 11.

[0070] The column signal processing circuit 5 is arranged for each column of pixels 3, and for each column of pixels, it performs signal processing such as noise removal on the signal output from a row of pixels 3. For example, the column signal processing circuit 5 performs signal processing such as correlated double sampling (CDS) and analog-to-digital (AD) conversion to remove pixel-specific fixed-pattern noise. A horizontal selection switch (not shown) is provided in the output stage of the column signal processing circuit 5, and the horizontal selection switch is connected to the horizontal signal line 12.

[0071] The horizontal drive circuit 6 includes, for example, a shift register. The horizontal drive circuit 6 sequentially selects each column signal processing circuit 5 by sequentially outputting horizontal scan pulses to the column signal processing circuit 5, and causes each column signal processing circuit 5 to output the processed pixel signal to the horizontal signal line 12.

[0072] The output circuit 7 performs signal processing on the pixel signals sequentially supplied from each column signal processing circuit 5 via the horizontal signal line 12, and outputs the processed signal. For example, buffering, black level adjustment, column change correction, and various digital signal processing techniques can be used for signal processing.

[0073] The control circuit 8 generates clock and control signals based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, which serve as the operating references for the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0074] <pixel> Figure 17 This is an equivalent circuit diagram showing an example configuration of pixel 3. Pixel 3 includes a photoelectric conversion element PD, a charge accumulation region (floating diffusion section) FD that accumulates (holds) the signal charge converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charge converted by the photoelectric conversion element PD to the charge accumulation region FD. In addition, pixel 3 also includes a readout circuit 15 electrically connected to the charge accumulation region FD.

[0075] The photoelectric conversion element PD generates a signal charge corresponding to the amount of light received. Furthermore, the photoelectric conversion element PD temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transmission transistor TR, and the anode side is electrically connected to a reference potential line (e.g., ground). For example, a photodiode can be used as the photoelectric conversion element PD.

[0076] The drain region of the transfer transistor TR is electrically connected to the charge accumulation region FD. The gate electrode of the transfer transistor TR is electrically connected to the pixel drive line 10 (see reference). Figure 16 The transmission transistor drive line in ).

[0077] The charge accumulation region FD temporarily accumulates and retains the signal charge transmitted from the photoelectric conversion element PD via the transmission transistor TR.

[0078] The readout circuit 15 reads the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. For example, the readout circuit 15 includes, but is not limited to, an amplifying transistor AMP, a selecting transistor SEL, and a reset transistor RST, which are pixel transistors. Each of these transistors (AMP, SEL, and RST) includes a MOSFET, which comprises a gate insulating film formed of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions serving as source and drain regions. Furthermore, these transistors can be metal-insulator-semiconductor FETs (MISFETs), where the gate insulating film includes a silicon nitride (Si3N4, SiN) film, or a stacked film of silicon nitride and silicon oxide films, etc. Additionally, the readout circuit 15 can be configured for each photoelectric conversion element PD, or one readout circuit 15 can be shared by multiple photoelectric conversion elements PD. Similarly, the charge accumulation region FD can be configured for each photoelectric conversion element PD, or one charge accumulation region FD can be shared by multiple photoelectric conversion elements PD.

[0079] The source region of the amplifying transistor AMP is electrically connected to the drain region of the select transistor SEL, and the drain region of the amplifying transistor AMP is electrically connected to the power supply line Vdd and the drain region of the reset transistor. Then, the gate electrode of the amplifying transistor AMP is electrically connected to the charge accumulation region FD and the source region of the reset transistor RST.

[0080] The source region of the selector transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region of the selector transistor SEL is electrically connected to the source region of the amplifying transistor AMP. Then, the gate electrode of the selector transistor SEL is electrically connected to the pixel drive line 10 (see reference). Figure 16 The selection transistor drive line in ).

[0081] The source region of the reset transistor RST is electrically connected to the charge accumulation region FD and the gate electrode of the amplification transistor AMP, and the drain region of the reset transistor RST is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the pixel drive line 10 (see reference). Figure 16 The reset transistor drive line in ).

[0082] <<Specific Configuration of Semiconductor Chips>> Next, we will refer to Figure 18 and Figure 19 Describe the specific configuration of the semiconductor chip 2 on which the semiconductor device 1 is mounted.

[0083] <Stacked Structure of Semiconductor Chips> like Figure 18 As shown, the semiconductor chip 2 includes a first semiconductor substrate A, a third semiconductor substrate C bonded to the second surface S2 side of the first semiconductor substrate A, and two second semiconductor substrates B1 and B2. The first surface S1 and the second surface S2 are one surface and the other surface of the first semiconductor substrate A. Figure 19 A portion of pixel region 2A and a peripheral region 2B are shown in a longitudinal cross-sectional configuration. For example, a color filter Ft and a microlens (on-chip lens) Lz are disposed on one side of the third semiconductor substrate C. The color filter Ft separates the colors of light incident on the semiconductor chip 2. Examples of color filters Ft include filters for different colors, such as filters for red light, filters for green light, and filters for blue light. The microlens Lz focuses the light incident on the semiconductor chip 2 onto pixel 3. The color filter Ft and the microlens Lz are made of, for example, a resin material.

[0084] <Third Semiconductor Substrate> The third semiconductor substrate C is an example of a third semiconductor substrate. The third semiconductor substrate C includes a semiconductor layer 20C and a multilayer wiring layer 30C stacked on the other side of the semiconductor layer 20C. A product circuit Ca is disposed in the portion of the third semiconductor substrate C corresponding to the pixel region 2A. The product circuit Ca is an example of a third product circuit, including... Figure 17 The photoelectric conversion element PD is shown. The product circuit Ca includes, in the portion of the third semiconductor substrate C corresponding to the pixel region 2A. Figure 17 The transmission transistor TR, charge accumulation region FD, readout circuit 15, etc. are shown.

[0085] Semiconductor layer 20C includes a semiconductor substrate. Semiconductor layer 20C is not limited to this, but may include, for example, a silicon (Si) substrate. In the portion of semiconductor layer 20C corresponding to pixel region 2A, a plurality of pixels 3 are arranged in a matrix along the row direction (X direction) and column direction (Y direction) in a planar view. In semiconductor layer 20C, for example, semiconductor regions of a first conductivity type (e.g., p-type) and semiconductor regions of a second conductivity type (e.g., n-type) are configured. A photoelectric conversion element PD is configured, for example, for each pixel 3, in semiconductor layer 20C. The photoelectric conversion element PD then performs photoelectric conversion and generates a signal charge corresponding to the amount of light received. No test circuit X is configured in the third semiconductor substrate C.

[0086] The multilayer wiring layer 30C is not limited to this, but may include, for example, an insulating film and wiring L disposed within the insulating film. The insulating film has a configuration of multiple known insulating films such as silicon oxide (SiO2, SiO) films, silicon nitride (Si3N4, SiN) films, and silicon oxynitride (SiON) films stacked together. The wiring L is a known conductive material, such as a metallic material like copper (Cu), tungsten (W), or aluminum (Al), etc. This configuration is similar for the multilayer wiring layers 30A1, 30A2, and 30B described below.

[0087] <First Semiconductor Substrate> The first semiconductor substrate A includes a semiconductor layer 20A, a multilayer wiring layer 30A1 stacked on one side of the semiconductor layer 20A and overlapping and bonded to the multilayer wiring layer 30C, and a multilayer wiring layer 30A2 stacked on the other side of the semiconductor layer 20A. Wiring L is provided in each of the multilayer wiring layers 30A1 and 30A2. A product circuit Aa is disposed in the portion of the first semiconductor substrate A corresponding to the pixel region 2A. The product circuit Aa includes, for example, logic circuit 13. The semiconductor layer 20A includes a semiconductor substrate. The semiconductor layer 20A is not limited thereto, but may include, for example, a silicon (Si) substrate.

[0088] <Second Semiconductor Substrate> Semiconductor chip 2 includes multiple second semiconductor substrates B, namely second semiconductor substrates B1 and B2. Without distinguishing between them, second semiconductor substrates B1 and B2 are simply referred to as second semiconductor substrates B. Each second semiconductor substrate B includes a semiconductor layer 20B and a multilayer wiring layer 30B stacked on one side of the semiconductor layer 20B and overlapping and bonded to a multilayer wiring layer 30A2. Wiring L is provided in the multilayer wiring layer 30B. A product circuit B1a is disposed on second semiconductor substrate B1, and a product circuit B2a is disposed on second semiconductor substrate B2. Product circuit B1a includes memory circuitry such as DRAM, and product circuit B2a includes circuitry such as SoC (System-on-a-Chip) circuitry such as artificial intelligence or a CPU. Semiconductor layer 20B is not limited to this, but may include, for example, a silicon (Si) substrate.

[0089] <Through Conductor> Semiconductor chip 2 includes a through conductor TSV that penetrates through semiconductor layer 20A along its thickness direction. The through conductor TSV is also part of wiring L. The through conductor TSV electrically connects wiring L disposed in multilayer wiring layer 30A1 and wiring L disposed in multilayer wiring layer 30A2. The through conductor TSV is also part of wiring L. Semiconductor chip 2 may include a through conductor TSV that penetrates through semiconductor layer 20B or semiconductor layer 20C along its thickness direction.

[0090] <Connecting pads> Semiconductor chip 2 includes multiple pairs of connection pads CCa and CCb. Connection pads CCa and CCb are also part of wiring L. In some pairs, each of the connection pads CCa and CCb contacts each other, sandwiching the bonding surface between the first semiconductor substrate A and the second semiconductor substrate B, and is electrically connected to wiring L disposed in multilayer wiring layer 30A2 and wiring L disposed in multilayer wiring layer 30B. In other pairs, each of the connection pads CCa and CCb contacts each other, sandwiching the bonding surface between the first semiconductor substrate A and the third semiconductor substrate C, and is electrically connected to wiring L disposed in multilayer wiring layer 30A1 and wiring L disposed in multilayer wiring layer 30C.

[0091] <ocmt> The test circuit X and measurement pad 14A of the OCMT 9 are disposed on a first semiconductor substrate A, and the device under test (DUT) Y is disposed on a second semiconductor substrate B. The wiring L2 connecting the test circuit X and the DUT Y includes a through conductor TSV and paired connection pads CCa and CCb. The test circuit X and the DUT Y are electrically connected via the through conductor TSV and the paired connection pads CCa and CCb.

[0092] <<Main Effects of the Second Embodiment>> Even in the semiconductor chip 2 according to the second embodiment, similar effects to those of the semiconductor chip 2 according to the first embodiment can be obtained.

[0093] Note that although the third semiconductor substrate C includes only one semiconductor layer 20C, it may also include two semiconductor layers. In this case, the photoelectric conversion element PD and the readout circuit 15 may be formed separately for one and the other of the two semiconductor layers.

[0094] <<Modifications of the Second Embodiment>> In the following text, variations of the second embodiment will be described.

[0095] <Variation Example 1> In the semiconductor chip 2 according to the second embodiment, such as Figure 19 As shown, the measurement pad 14A is disposed on the first semiconductor substrate A, but the technology is not limited thereto. In the semiconductor chip 2 of the modified example 1 according to the second embodiment, the measurement pad 14A may be disposed on the second semiconductor substrate B or the third semiconductor substrate C.

[0096] exist Figure 20 In the semiconductor chip 2 shown, measurement pad 14A is disposed on a third semiconductor substrate C. Wiring L1 is disposed across the first semiconductor substrate A and the third semiconductor substrate C. Wiring L1 includes a through conductor TSV (not shown) and a pair of connection pads CCa and CCb. Test circuit X and measurement pad 14A are electrically connected via the through conductor TSV and the pair of connection pads CCa and CCb.

[0097] exist Figure 21 In the semiconductor chip 2 shown, measurement pad 14A is disposed on the second semiconductor substrate B. Wiring L2 is disposed across the first semiconductor substrate A and the second semiconductor substrate B. Wiring L1 includes a through conductor TSV (not shown) and a pair of connection pads CCa and CCb. Test circuit X and measurement pad 14A are electrically connected via the through conductor TSV and the pair of connection pads CCa and CCb.

[0098] Even in the semiconductor chip 2 of the modified example 1 according to the second embodiment, similar effects to those of the semiconductor chip 2 according to the second embodiment described above can be obtained.

[0099] <Variation Example 2> exist Figure 22 In the semiconductor chip 2 shown in Modified Example 2 of the second embodiment, with Figure 11 Similar to Variation 2 of the first embodiment shown, a test circuit X is shared by multiple devices under test Y disposed on multiple second semiconductor substrates B.

[0100] Even in the semiconductor chip 2 of the modified example 2 according to the second embodiment, similar effects as those of the semiconductor chip 2 according to the second embodiment described above can be obtained.

[0101] <Variation Example 3> In the semiconductor chip 2 of the modified example 3 according to the second embodiment, although not shown, the test circuit X can be configured on the third semiconductor substrate C.

[0102] Even in the semiconductor chip 2 of the modified example 3 according to the second embodiment, similar effects as those of the semiconductor chip 2 according to the second embodiment described above can be obtained.

[0103] [Third Embodiment] The third embodiment of this technology will now be described. In this embodiment, the semiconductor chip 2 according to the first embodiment is equipped with a light detection device as a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor. More specifically, in the first semiconductor substrate A described in the first embodiment and its variations 1 and 2, the photoelectric conversion element PD is configured similarly to that of the third semiconductor substrate C. That is, the product circuit Aa has a configuration similar to that of the product circuit Ca. Furthermore, in the first semiconductor substrate A2 described in variations 3 and 4 of the first embodiment, the photoelectric conversion element PD is configured similarly to that of the third semiconductor substrate C. That is, the product circuit A2a has a configuration similar to that of the product circuit Ca.

[0104] Even in the semiconductor chip 2 according to the third embodiment, similar effects to those of the semiconductor chip 2 according to the first embodiment can be obtained.

[0105] [Fourth Embodiment] <1. Examples of applications of electronic devices> Next, we will describe Figure 23 The electronic device 100 shown is based on a fourth embodiment of the present technology. The electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. For example, the electronic device 100 is an electronic device such as a camera, but is not limited thereto. Furthermore, the electronic device 100 includes a semiconductor chip 2 on which the aforementioned light detection device is mounted as the solid-state imaging device 101.

[0106] An optical lens (optical system) 102 forms an image of the image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. Through this arrangement, signal charge accumulates in the solid-state imaging device 101 over a certain period of time. A shutter device 103 controls the illumination period and the blocking period of the solid-state imaging device 101. A drive circuit 104 supplies drive signals for controlling the transmission operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. Based on the drive signals (timing signals) supplied from the drive circuit 104, the solid-state imaging device 101 performs signal transmission. A signal processing circuit 105 performs various signal processing operations on the signals (pixel signals) output from the solid-state imaging device 101. The processed video signal is stored in a storage medium such as a memory or output to a monitor.

[0107] Note that electronic device 100 is not limited to a camera, but can be any other electronic device. For example, an electronic device can be an imaging device, such as a camera module for mobile devices such as mobile phones.

[0108] Furthermore, the electronic device 100 may include a light detection device according to any one of the second to third embodiments and variations thereof, or a combination of at least two of the second to third embodiments and variations thereof, as a solid-state imaging device 101.

[0109] [Other Embodiments] As described above, the present technology has been described through the first to fourth embodiments, but it should not be construed as limiting the present technology by the description and drawings that constitute a part of this disclosure. It will be apparent to those skilled in the art that various alternative embodiments, examples, and operational techniques are available based on this disclosure.

[0110] For example, the technical ideas described in the first to fourth embodiments can be combined with each other. For example, variations 3 and 4 of the first embodiment related to a plurality of first semiconductor substrates A and variation 2 of the first embodiment related to a plurality of second semiconductor substrates B can be combined. As described above, various combinations based on the various technical ideas are possible.

[0111] Furthermore, this technology is applicable to any light detection device, including not only the aforementioned solid-state imaging devices as image sensors, but also distance measurement sensors, also known as time-of-flight (ToF) sensors, which measure distance. A distance measurement sensor is a sensor that emits illumination light toward an object, detects the reflected light as illumination light reflected from the object's surface, and calculates the distance to the object based on the time of flight from emitting the illumination light to receiving the reflected light. The above structure can be used as the structure of a distance measurement sensor.

[0112] In addition, the materials constituting the above components may include, for example, additives and impurities.

[0113] As stated above, it goes without saying that this technology includes various embodiments not described herein. Therefore, the scope of this technology is limited only by the matters specified in the claims, which are reasonably derived from the foregoing description.

[0114] Furthermore, the effects described in this article are merely examples and are not intended to be limiting; other effects can also be achieved.

[0115] Note that this technology can have the following configurations. (1) A semiconductor chip comprising: A first semiconductor substrate on which a first circuit is disposed; A second semiconductor substrate, on which a second circuit is disposed, overlaps and is bonded to a first surface of the first semiconductor substrate; and A test element assembly, comprising a device under test (DUT) and test circuitry for testing the DUT, is disposed on a first semiconductor substrate and a second semiconductor substrate, wherein... On the second semiconductor substrate, only the device under test (DUT) and the DUT in the test circuit are disposed, and The test circuit is disposed on the first semiconductor substrate. (2) The semiconductor chip according to (1), wherein The devices under test are set up in units of components. (3) The semiconductor chip according to (1) or (2), wherein The test element group includes measurement pads electrically connected to the test circuit and configured to expose one surface of the measurement pads. (4) The semiconductor chip according to (3), wherein The measuring pad is disposed on the first semiconductor substrate or the second semiconductor substrate. (5) The semiconductor chip according to any one of (1) to (4), wherein A plurality of the devices under test are disposed on the second semiconductor substrate, and The test circuit includes a selection circuit for selecting a portion of the plurality of devices under test (DUTs) and has the function of testing the selected DUTs. (6) The semiconductor chip according to any one of (1) to (4), wherein A plurality of the devices under test are disposed on the second semiconductor substrate, and The test circuit includes a switch for switching the device under test (DUT) and has the function of testing the DUT after switching. (7) The semiconductor chip according to any one of (1) to (6), wherein The device under test is a capacitor, and The test circuit includes an oscillating circuit for testing the capacitance of the capacitor. (8) The semiconductor chip according to any one of (1) to (6), wherein The device under test is a transistor or a resistor. (9) The semiconductor chip according to any one of (1) to (8), wherein Multiple second semiconductor substrates are provided. (10) The semiconductor chip according to (9), wherein The test circuit has the following functions: selecting the device under test (DUT) disposed on any of the multiple second semiconductor substrates, and testing the selected DUT. (11) The semiconductor chip according to (9) or (10), wherein The second circuit configured in each of the plurality of second semiconductor substrates is a different type of circuit. (12) The semiconductor chip according to any one of (1) to (11), wherein Multiple first semiconductor substrates are provided. Multiple first semiconductor substrates overlap and bond with each other, and The test circuit is configured on at least one of the plurality of the first semiconductor substrates. (13) The semiconductor chip according to any one of (1) to (12), wherein The first circuit and the second circuit are different types of circuits. (14) The semiconductor chip according to any one of (1) to (13) further comprises: A third semiconductor substrate is disposed thereon, and is bonded to a surface of the first semiconductor substrate opposite to the first surface. (15) The semiconductor chip according to (14) further includes: Through conductor; and Connect the pad pairs, where The through conductor extends in the thickness direction through any semiconductor layer included in the first semiconductor substrate to the third semiconductor substrate. The pads in the connection pad pair are in contact with each other, sandwiching the bonding surface between the first semiconductor substrate and the second semiconductor substrate or the bonding surface between the first semiconductor substrate and the third semiconductor substrate, and The test circuit and the device under test are electrically connected via at least one of the through conductor and the connection pad pair. (16) The semiconductor chip according to (14) or (15) further includes: The measuring pads, electrically connected to the test circuit, are configured to expose one surface, wherein... The measurement pads are disposed on the first semiconductor substrate, the second semiconductor substrate, or the third semiconductor substrate. (17) An electronic device comprising a semiconductor chip and an optical system, wherein the optical system forms an image of image light from a subject on the semiconductor chip, wherein The semiconductor chip includes: A first semiconductor substrate on which a first circuit is disposed; A second semiconductor substrate, on which a second circuit is disposed, overlaps and is bonded to a first surface of the first semiconductor substrate; and A test element assembly, comprising a device under test (DUT) and test circuitry for testing the DUT, is disposed on a first semiconductor substrate and a second semiconductor substrate. On the second semiconductor substrate, only the device under test (DUT) and the DUT in the test circuit are disposed, and The test circuit is disposed on the first semiconductor substrate.

[0116] The scope of this technology is not limited to the exemplary embodiments shown and described, but also includes all embodiments that produce effects equivalent to those intended by this technology. Furthermore, the scope of this technology is not limited to the combination of features of the invention as defined by the claims, but can be defined by any desired combination of specific features from all disclosed features. List of reference numerals

[0117] 2 Semiconductor chips 14A Measurement Pads 20A, 20B, 20C Semiconductor Layers 100 Electronic devices 102 Optical System A, A1, A2 First semiconductor substrate AMP transistor B, B1, B2 Second semiconductor substrates C Third semiconductor substrate CCa, CCb connection pads PD photoelectric conversion element S1 First Surface TSV through conductor X, Xa, Xb test circuit X1 Selection Circuit X2 switch X3 Oscillator Circuit Y, Ya, Yb Device under Test Y1 transistor Y2 capacitor Y3 Resistor Element< / ocmt>

Claims

1. A semiconductor chip, comprising: A first semiconductor substrate on which a first circuit is disposed; A second semiconductor substrate on which a second circuit is disposed, and which overlaps and is bonded to a first surface of the first semiconductor substrate; and A test element assembly, comprising a device under test (DUT) and test circuitry for testing the DUT, is disposed on a first semiconductor substrate and a second semiconductor substrate, wherein... On the second semiconductor substrate, only the device under test (DUT) and the DUT in the test circuit are disposed, and The test circuit is disposed on the first semiconductor substrate.

2. The semiconductor chip according to claim 1, wherein The devices under test are set up in units of components.

3. The semiconductor chip according to claim 1, wherein... The test element group includes measurement pads electrically connected to the test circuit and configured to expose one surface of the measurement pads.

4. The semiconductor chip according to claim 3, wherein The measuring pad is disposed on the first semiconductor substrate or the second semiconductor substrate.

5. The semiconductor chip according to claim 1, wherein... A plurality of the devices under test are disposed on the second semiconductor substrate, and The test circuit includes a selection circuit for selecting a portion of the plurality of devices under test (DUTs) and has the function of testing the selected DUTs.

6. The semiconductor chip according to claim 1, wherein... A plurality of the devices under test are disposed on the second semiconductor substrate, and The test circuit includes a switch for switching the device under test (DUT) and has the function of testing the DUT after switching.

7. The semiconductor chip according to claim 1, wherein... The device under test is a capacitor, and The test circuit includes an oscillating circuit for testing the capacitance of the capacitor.

8. The semiconductor chip according to claim 1, wherein The device under test is a transistor or a resistor.

9. The semiconductor chip according to claim 1, wherein Multiple second semiconductor substrates are provided.

10. The semiconductor chip according to claim 9, wherein The test circuit has the following functions: selecting the device under test (DUT) disposed on any of the plurality of second semiconductor substrates, and testing the selected DUT.

11. The semiconductor chip according to claim 9, wherein The second circuit configured in each of the plurality of second semiconductor substrates is a different type of circuit.

12. The semiconductor chip according to claim 1, wherein Multiple first semiconductor substrates are provided. Multiple first semiconductor substrates overlap and bond with each other, and The test circuit is configured on at least one of the plurality of the first semiconductor substrates.

13. The semiconductor chip according to claim 1, wherein The first circuit and the second circuit are different types of circuits.

14. The semiconductor chip according to claim 1, further comprising: A third semiconductor substrate is disposed thereon, and is bonded to a surface of the first semiconductor substrate opposite to the first surface.

15. The semiconductor chip according to claim 14, further comprising: Through conductor; and Connect the pad pairs, among which The through conductor extends in the thickness direction through any semiconductor layer included in the first semiconductor substrate to the third semiconductor substrate. The pads in the connection pad pair are in contact with each other, sandwiching the bonding surface between the first semiconductor substrate and the second semiconductor substrate or the bonding surface between the first semiconductor substrate and the third semiconductor substrate, and The test circuit and the device under test are electrically connected via at least one of the through conductor and the connection pad pair.

16. The semiconductor chip according to claim 14, further comprising: The measuring pads, electrically connected to the test circuit, are configured to expose one surface, wherein... The measurement pads are disposed on the first semiconductor substrate, the second semiconductor substrate, or the third semiconductor substrate.

17. An electronic device comprising a semiconductor chip and an optical system, the optical system forming an image of image light from a subject on the semiconductor chip, wherein... The semiconductor chip includes: A first semiconductor substrate on which a first circuit is disposed; A second semiconductor substrate on which a second circuit is disposed, and which overlaps and is bonded to a first surface of the first semiconductor substrate; and A test element assembly, comprising a device under test (DUT) and test circuitry for testing the DUT, is disposed on a first semiconductor substrate and a second semiconductor substrate. On the second semiconductor substrate, only the device under test (DUT) and the DUT in the test circuit are disposed, and The test circuit is disposed on the first semiconductor substrate.

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