Thread bundle exiting method and device, equipment, storage medium and program product

Abstract

The invention provides a thread bundle exiting method and device, equipment, a storage medium and a program product. The method is applied to the technical field of graphics processing units. The method comprises the steps of performing second processing on a synchronization identifier corresponding to a target thread bundle under the condition of obtaining a feedback signal of a target instruction sequence; the feedback signal represents that an instruction in the target instruction sequence is executed completely; the second processing represents that the target thread bundle is executed; the synchronization identifiers corresponding to the first processing and the second processing are different; and under the condition that all instructions in the target instruction sequence are executed by the target assembly line, executing an exit operation of the target thread bundle. The problem that the thread beam exits before instruction execution can be avoided, and then the result of polluting a subsequent new thread beam register is avoided.

Description

Technical Field

[0001] This application relates to graphics processing unit technology, and more particularly to a thread bundle exit method, apparatus, device, storage medium, and program product. Background Technology

[0002] To improve the parallelism of Graphics Processing Units (GPUs) and General-Purpose computing on Graphics Processing Units (GPGPUs), instruction sequences are typically executed using either a Single Instruction, Multiple Data with 32 data elements (SIMD32) architecture or a Single Instruction, Multiple Threads with 32 threads per warp (SIMT32) architecture.

[0003] Related technologies employ a multi-pipeline architecture to execute instruction sequences, that is, issuing instructions in the instruction sequence to the corresponding pipelines for execution. However, using a multi-pipeline architecture can lead to the problem of thread bundles exiting before instructions are executed, which can pollute the register results of subsequent new thread bundles. Summary of the Invention

[0004] This application provides a thread bundle exit method, apparatus, device, storage medium, and program product that can avoid the problem of thread bundles exiting before instructions are executed, thereby avoiding contamination of the results of subsequent new thread bundle registers.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a thread termination method, the method including: When the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline, the synchronization flag corresponding to the target thread bundle is processed first; the first processing indicates that the target thread bundle has started execution. Upon receiving a feedback signal for the target instruction sequence, a second processing is performed on the synchronization flag corresponding to the target thread bundle; the feedback signal indicates that an instruction in the target instruction sequence has been executed; the second processing indicates that the target thread bundle has been executed; the synchronization flags corresponding to the first and second processing are different. After the target pipeline has executed all instructions in the target instruction sequence, the target thread bundle exit operation is performed.

[0006] This application provides a thread termination device, the device comprising: The first processing unit is used to perform first processing on the synchronization flag corresponding to the target thread bundle when the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline; the first processing indicates that the target thread bundle has started execution; The second processing unit is used to perform a second processing on the synchronization flag corresponding to the target thread bundle when a feedback signal of the target instruction sequence is obtained; the feedback signal indicates that an instruction in the target instruction sequence has been executed; the second processing indicates that the target thread bundle has been executed; the synchronization flags corresponding to the first processing and the second processing are different; The first execution unit is used to perform the exit operation of the target thread bundle after all instructions in the target instruction sequence have been executed in the target pipeline.

[0007] This application provides a computer device, which includes: a memory for storing computer-executable instructions or computer programs; and a processor for executing the computer-executable instructions or computer programs stored in the memory to implement the thread bundle exit method provided in this application.

[0008] This application provides a computer-readable storage medium storing a computer program or computer-executable instructions for implementing the thread bundle exit method provided in this application when executed by a processor.

[0009] This application provides a computer program product, including a computer program or computer executable instructions. When the computer program or computer executable instructions are executed by a processor, they implement the thread bundle exit method provided in this application.

[0010] The embodiments of this application have the following beneficial effects: When the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline, the synchronization flag corresponding to the target thread bundle undergoes first processing. This first-processed synchronization flag clearly indicates that the target thread bundle has started execution or entered the started state. Upon receiving feedback signals from the target instruction sequence, the synchronization flag corresponding to the target thread bundle undergoes second processing. The second-processed synchronization flag differs from the first-processed one, clearly indicating that the target thread bundle has completed execution. After the target pipeline has executed all target instructions in the target instruction sequence, the target thread bundle enters the completed state. By performing first processing on the synchronization flag when the target thread bundle starts execution and second processing when it completes, the lifecycle of the target thread bundle—not executed, started, and completed—is clearly defined. The execution progress of the target thread bundle can be intuitively determined by reading the synchronization flag, ensuring that the target thread bundle exits only after the target pipeline has executed all target instructions in the target instruction sequence. This avoids the problem of the target thread bundle exiting before the instructions are executed, precisely controlling the exit timing of the target thread bundle. In addition, by simply setting a synchronization flag, the execution status of the target thread bundle can be recorded at all times. This ensures that the issued instruction sequence can be executed normally before the thread bundle resources are released without occupying a large amount of the SIMT32 pipeline. This also ensures that when multiple stream processors issue instructions to enter multiple parallel pipelines for execution at the same time, the thread bundle can exit safely, avoiding contamination of the register results of subsequent new thread bundles. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating a thread bundle exit method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the first structure of a thread bundle exit system provided in an embodiment of this application; Figure 3 This is a schematic diagram of the second structure of a thread bundle exit system provided in an embodiment of this application; Figure 4 This is a schematic diagram of a third structure of a thread bundle exit system provided in an embodiment of this application; Figure 5 This is a schematic diagram of an instruction sequence provided in an embodiment of this application; Figure 6 This is a schematic diagram of the fourth structure of a thread bundle exit system provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a thread bundle exit device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0014] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0016] Figure 1 This is a flowchart illustrating a thread bundle exit method provided in an embodiment of this application. The following will be combined with... Figure 1 The steps shown are explained as follows: Figure 1 As shown, the method includes the following steps S101 to S103: Step S101: When the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline, perform the first processing on the synchronization flag corresponding to the target thread bundle.

[0017] A target thread bundle is the basic execution unit of parallel computing. In some implementations, the target thread bundle can be any thread bundle within a thread workgroup. In other implementations, the target thread bundle can be any actively running thread bundle within a thread workgroup. The target instruction sequence is the complete set of instructions to be executed by the target thread bundle, which are processed in the pipeline in logical order.

[0018] A target pipeline is used to execute instructions in a target instruction sequence. In some implementations, the target pipeline may include: a vector processing pipeline, a matrix-related instruction pipeline, a scalar processing pipeline, etc. Specifically, the vector processing pipeline handles vector operations, the matrix-related instruction pipeline handles matrix operations, and the scalar processing pipeline handles scalar operations.

[0019] Synchronization flags are used to mark the execution state of a target thread bundle and are the core basis for tracking the lifecycle of a thread bundle. In some implementations, synchronization flags can be numerical values. In other implementations, synchronization flags can be signals.

[0020] The first processing indicates that the target thread bundle has begun execution. Specifically, the first processing is the operation performed on the synchronization flag when the target instruction sequence enters the target pipeline and begins execution.

[0021] In some implementations, a mathematical operation is performed on the synchronization flag when an instruction in the target instruction sequence enters the target pipeline and begins execution. In other implementations, a dedicated execution status register is allocated to each thread bundle, and when an instruction in the target instruction sequence enters the target pipeline and begins execution, the execution status register is set to a fixed value, for example, 1. Of course, it can also be set to other values, and this application does not limit this.

[0022] Step S102: Upon receiving a feedback signal for the target instruction sequence, perform a second processing on the synchronization flag corresponding to the target thread bundle.

[0023] Feedback signals are status signals returned by the pipeline during execution, used to indicate that some instructions in the target instruction sequence have been completed.

[0024] The second process, indicating that the target thread bundle has completed execution, involves operations on the synchronization flag after receiving a feedback signal. In some implementations, the second process has the reverse processing logic of the first process; that is, the synchronization flags corresponding to the first and second processes are different.

[0025] In some implementations, after receiving the feedback signal, a mathematical operation is performed on the synchronization flag, the reverse of the mathematical operation performed in the first process. In other implementations, a dedicated execution status register is allocated to each thread bundle, and after receiving the feedback signal, the execution status register is set to a fixed value, for example, 0. Of course, it can also be set to other values, which are not limited in this application, but it needs to be different from the value set in the execution status register when an instruction in the target instruction sequence enters the target pipeline and begins execution.

[0026] Step S103: After the target pipeline has executed all instructions in the target instruction sequence, execute the exit operation of the target thread bundle.

[0027] The exit operation of a target thread bundle is a closing action triggered after the execution of all target instructions in the target instruction sequence. In some implementations, the exit operation of a target thread bundle includes releasing the target thread bundle number and releasing the occupied shared memory resources.

[0028] In some implementations, the hardware directly triggers an exit operation after the target pipeline has executed all instructions in the target instruction sequence. For example, this involves releasing the target thread bundle number and releasing occupied shared memory resources. In other implementations, the software first performs verification, such as checking for abnormal resource usage. Once confirmed to be problem-free, the software sends a thread bundle exit command to the instruction controller via a dedicated API. Upon receiving the thread bundle exit command from the software, the instruction controller executes the exit operation step by step: first releasing the occupied shared memory resources, then clearing the thread bundle number, and finally performing the exit operation.

[0029] When the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline, the synchronization flag corresponding to the target thread bundle undergoes first processing. This first-processed synchronization flag clearly indicates that the target thread bundle has started execution or entered the started state. Upon receiving feedback signals from the target instruction sequence, the synchronization flag corresponding to the target thread bundle undergoes second processing. The second-processed synchronization flag differs from the first-processed one, clearly indicating that the target thread bundle has completed execution. After the target pipeline has executed all target instructions in the target instruction sequence, the target thread bundle enters the completed state. By performing first processing on the synchronization flag when the target thread bundle starts execution and second processing when it completes, the lifecycle of the target thread bundle—not executed, started, and completed—is clearly defined. The execution progress of the target thread bundle can be intuitively determined by reading the synchronization flag, ensuring that the target thread bundle exits only after the target pipeline has executed all target instructions in the target instruction sequence. This avoids the problem of the target thread bundle exiting before the instructions are executed, precisely controlling the exit timing of the target thread bundle. In addition, by simply setting a synchronization flag, the execution status of the target thread bundle can be recorded at all times. This ensures that the issued instruction sequence can be executed normally before the thread bundle resources are released without occupying a large amount of the SIMT32 pipeline. This also ensures that when multiple stream processors issue instructions to enter multiple parallel pipelines for execution at the same time, the thread bundle can exit safely, avoiding contamination of the register results of subsequent new thread bundles.

[0030] In some embodiments, the thread bundle exit method provided in this application further includes step A1: Step A1: Obtain the processing signals for each of the multiple thread bundles.

[0031] In some scenarios, the instruction controller fetches instructions from the instruction cache based on the program counter address, decodes them, and distributes them to the matching pipeline, while simultaneously issuing processing signals. The pipeline executes the instructions and generates feedback signals, which are sent back to the instruction controller. Upon receiving the feedback signals, the instruction controller performs the corresponding control operations. For example, if an instruction executes normally to the write-back stage, the pipeline sends back an instruction completion signal. Upon receiving the completion signal, the instruction controller marks the instruction as completed. If all instructions in the target thread bundle have completed, resource release is triggered, and the target thread bundle status is updated to completed.

[0032] The processing signal is used to reflect the adjustment mechanism of the synchronization flag of the corresponding thread bundle. That is, the processing signal is used to adjust the synchronization flag. In some implementations, the processor may include: counters, signal feedback, dependency addition, or strong feedback behaviors. Signal feedback refers to the pipeline sending a completion signal to the instruction controller after executing the corresponding instruction. Strong feedback behavior refers to forcing the pipeline to send feedback to the instruction controller after executing the corresponding instruction.

[0033] In some implementations, a processing signal corresponding to the thread bundle is added to the transmitting end of the instruction transmitter, so that when an instruction in the instruction sequence enters the corresponding pipeline, the corresponding processing signal is emitted.

[0034] In other implementations, when the first instruction in the instruction sequence enters the pipeline through the instruction transmitter, the instruction activation detector located in the pipeline captures the first instruction and generates a processing signal.

[0035] In some other implementations, a start instruction is inserted at the beginning of the instruction sequence, and a processing signal is generated when the start instruction is decoded and executed.

[0036] After step A1, the "first processing of the synchronization flag corresponding to the target thread bundle" in step S101 above can be implemented through the following step A11: Step A11: Perform first processing on the synchronization flag corresponding to the target thread bundle according to the first processing signal in the target processing signal corresponding to the target thread bundle.

[0037] When the target processing signal includes a counter, the synchronization identifier can be the counter's count value.

[0038] In some implementations, mathematical operations can be performed on the synchronization flag corresponding to the target thread bundle based on the first processing signal. Furthermore, mathematical operations can be performed on the count value.

[0039] After step A1, the "second processing of the synchronization flag corresponding to the target thread bundle" in step S102 above can be implemented through the following step A12: Step A12: Perform second processing on the synchronization flag corresponding to the target thread bundle according to the second processing signal in the target processing signal corresponding to the target thread bundle.

[0040] In some implementations, the mathematical operation described above can be performed on the synchronization flag corresponding to the target thread bundle based on the second processing signal. Furthermore, the mathematical operation described above can be performed on the count value.

[0041] Based on the above technical solution, by setting processing signals and processing the synchronization flag through these signals, the adjustment of the synchronization flag can be completed by responding to only explicit signals, which can reduce the complexity of hardware control and improve the efficiency of instruction execution.

[0042] In some embodiments, the step A11 above, "performing first processing on the synchronization identifier corresponding to the target thread bundle according to the first processing signal in the target processing signal corresponding to the target thread bundle", can be implemented by the following step A111: Step A111: Increment the current count value of the counter to obtain the first count value.

[0043] In some implementations, the addition process involves summing the current count value with a first value. The first value can be any value, such as 1, and is not limited thereto. For example, if the current count value is 0 and the first value is 1, the current count value of 0 indicates that the target thread bundle has not yet started execution. When the thread bundle starts execution, a corresponding signal is added to increment the current count value from 0 to obtain a first count value of 1, indicating that the thread bundle has started execution.

[0044] In some embodiments, the step A12 above, "performing second processing on the synchronization identifier corresponding to the target thread bundle according to the second processing signal in the target processing signal corresponding to the target thread bundle", can be implemented by the following step A121: Step A121: Decrement the current count value of the counter to obtain the second count value.

[0045] In some implementations, the decrementing process involves subtracting the current count value from the first value. For example, if the current count value is 1 and the first value is 1, the current count value of 1 indicates that the target thread bundle has not yet finished executing. After the target thread bundle finishes executing, the current count value of 1 is decremented by 1 to obtain the second count value of 0, indicating that the target thread bundle has finished executing.

[0046] In some embodiments, the step A11 above, "performing first processing on the synchronization identifier corresponding to the target thread bundle according to the first processing signal in the target processing signal corresponding to the target thread bundle", can also be implemented by the following step A112: Step A112: Decrement the current count value of the counter to obtain the third count value.

[0047] In some implementations, taking a current count value of 0 and a first value of 1 as an example, a current count value of 0 indicates that the target thread bundle has not yet started execution. When the thread bundle starts execution, a corresponding signal processing is added to decrement the current count value by 1, resulting in a third count value of -1, indicating that the thread bundle has started execution.

[0048] In some embodiments, the step A12 above, "performing second processing on the synchronization identifier corresponding to the target thread bundle according to the second processing signal in the target processing signal corresponding to the target thread bundle", can be implemented by the following step A122: Step A122: Increment the current count value of the counter to obtain the fourth count value.

[0049] In some implementations, taking a current count value of -1 and a first value of 1 as an example, a current count value of -1 indicates that the target thread bundle has not yet finished executing. After the target thread bundle finishes executing, the current count value of -1 is incremented by 1 to obtain a fourth count value of 0, indicating that the target thread bundle has finished executing.

[0050] Based on the above scheme of performing first and second processing on the synchronization flag corresponding to the target thread bundle according to the processing signal, in some embodiments, when the target thread bundle has started execution, the current count value of the counter is incremented to obtain a first count value, and when the target thread bundle has finished execution, the current count value of the counter is decremented to obtain a second count value. In other embodiments, when the target thread bundle has started execution, the current count value of the counter is decremented to obtain a third count value, and when the target thread bundle has finished execution, the current count value of the counter is incremented to obtain a fourth count value. By using the count value as the synchronization flag, unnecessary hardware overhead can be reduced.

[0051] In some embodiments, the step S103 above, "execute the exit operation of the target thread bundle after the target pipeline has executed all instructions in the target instruction sequence", can be implemented by the following steps S111 to S113: Step S111: Clear the synchronization flag when the synchronization flag indicates that the target pipeline has executed all instructions in the target instruction sequence.

[0052] Taking the synchronization flag as the counter value as an example, the synchronization flag indicates that the target pipeline has completed the execution of the target instruction sequence, and the synchronization flag can be the initial counter value. In some implementations, the initial counter value can be 0.

[0053] Clearing the synchronization flag restores the synchronization flag to its initial state and releases the flag resource. In some implementations, when the synchronization flag is the count value of a counter, restoring the synchronization flag to its initial state may mean restoring the counter's count value to its initial value.

[0054] Step S112: After the synchronization flag is cleared, check the status information of the target thread bundle and the status information of the target instruction sequence.

[0055] The state information of the target thread bundle and the state information of the target instruction sequence are used to characterize the execution state of the target thread bundle. In some implementations, the state information of the target thread bundle and the state information of the target instruction sequence may include: the resource occupancy status of the target thread bundle, the execution status of the instructions, and the release status of the target thread bundle number, etc. The resource occupancy status of the target thread bundle may include: the occupancy status of shared memory, the occupancy status of the instruction cache, etc. If the target thread bundle is in the started state, it will occupy shared memory in a preset address range (e.g., binding the 0x2000-0x2FFF address range), and the shared memory occupancy status is marked as allocated or in read / write; if the target thread bundle is in the completed state, the shared memory occupancy status will be updated to released, and the address range can be allocated to other thread bundles; if the target thread bundle triggers an exception (execution exception state), the shared memory will be marked as occupancy exception and cannot be released normally, causing subsequent thread bundles to be unable to request the resource.

[0056] In addition, when the target thread bundle is in the pending execution state, its target instruction sequence has been preloaded into the instruction cache. The instruction cache occupancy status is either cache hit or loaded, which is a prerequisite for triggering the instruction fetch operation. If the target thread bundle has exited but the instructions have not been executed, the instruction cache will still retain the instruction data of the target thread bundle. The occupancy status is residual occupancy, which will squeeze the cache space of the new thread bundle, causing the cache to be missing when the new thread bundle fetches instructions, thus prolonging the execution time of its started state.

[0057] If the target thread bundle is in the started state, its bound instruction sequence is in the fetch completed, decoded, or executed state, and at least one instruction has not been written back; if the entire instruction sequence enters the executed state, the target thread bundle will trigger a completion event and synchronously switch to the completed state, and the hardware will allow it to release the registers, shared memory, and other resources it occupies; if an abnormal state such as division by zero or address out of bounds is triggered during instruction execution, the target thread bundle will be marked as an execution abnormal state, the instruction execution flow will be immediately interrupted, and it will be unable to switch to the completed state.

[0058] If the target thread bundle is in a pending, started, or execution abnormal state, its target thread bundle number will be continuously occupied by the hardware, and the unfinished instructions will still carry this number. If the target thread bundle enters the completed state, the hardware will trigger the number release process, clear the target thread bundle number associated with the instructions, and the target thread bundle number can be reassigned to a newly created thread bundle. If the target thread bundle has exited but the instructions have not been completed, the target thread bundle number will not be released normally, and the residual instructions will still carry the target thread bundle number, which will cause number conflicts when the new thread bundle is executed, resulting in resource pollution anomalies.

[0059] In some implementations, the status information of the target thread bundle can be obtained through the thread bundle status register. In other implementations, the status information of the target thread bundle can be obtained by reading the thread bundle scheduler log through a hardware interface.

[0060] In some implementations, instruction status information can be obtained through a pipeline status register, thereby obtaining the status information of the target instruction sequence based on the status information of each instruction. In other implementations, instruction status information can be obtained through a feedback signal register, thereby obtaining the status information of the target instruction sequence based on the status information of each instruction.

[0061] Step S113: If the status information meets the exit conditions, execute the exit operation of the target thread bundle.

[0062] The exit condition is a preset criterion for determining when a target thread bundle exits. Meeting this condition indicates that the thread bundle can exit safely. In some implementations, the status information meeting the exit condition includes at least one of the following: the current count value of the counter is the initial count value; the processes of both the target thread bundle and the target instruction sequence have ended; and the resources of both the target thread bundle and the target instruction sequence have been released.

[0063] In some implementations, the current count value of the counter is the initial count value, indicating that the counter has returned to its initial state and all instructions issued by the instruction controller have been executed. After the last instruction is executed and written back to the register, the target pipeline returns a feedback signal to the instruction controller indicating that all instructions have been executed. When no instructions are in execution or not started, the instruction sequence corresponding to the target thread bundle has been fully processed, and there are no unexecuted instruction processes. At this point, both the target thread bundle and the target instruction sequence have ended. The release of resources for the target thread bundle and the target instruction sequence can include: the release of register resources, the release of resources stored in shared memory, etc. It can also include: the release of pipeline and issue port resources. The release of pipeline and issue port resources can be understood as the binding relationship between the thread bundle and the target pipeline being severed, the issue port no longer reserving a channel for the thread bundle, and the instruction buffer and data register inside the pipeline being cleared and restored to an idle state.

[0064] The exit operation is when a thread bundle releases all the hardware resources it occupies, such as registers, shared memory, pipelined bindings, etc., so that the instruction controller can reclaim the resources and allocate them to a new thread bundle.

[0065] In some implementations, after all issued instructions have been executed, the end instruction has been executed, the resources of the vector calculator and scalar calculator have been released, the instruction buffer has been cleared, the thread bundle has exited normally, the thread bundle number has been released, all thread bundles have been executed, the shared memory has been released, and then the thread workgroup number has been released for use by a new thread workgroup. After all of the above have been achieved, the target thread bundle exits.

[0066] Based on the above technical solution, the synchronization flag is cleared only after all instructions have been executed. The subsequent process only proceeds after confirming that the target pipeline has processed all instructions of the thread bundle, ensuring the complete execution of the instruction sequence and preventing data loss or calculation errors. Furthermore, the status information check verifies the resource usage of the thread bundle and instructions, and only performs an exit operation when all resources have been released. This prevents long-term resource occupation and avoids contaminating the results of subsequent new thread bundle registers, ensuring the safety of hardware resource recycling.

[0067] In some embodiments, the thread bundle exit method provided in this application further includes the following steps S121 to S123: Step S121: For any target instruction in the target instruction sequence, based on the instruction type corresponding to the target instruction and the correspondence between the instruction type and the transmission port, determine the target transmission port that matches the instruction type corresponding to the target instruction from multiple transmission ports.

[0068] Each transmit port transmits instructions of the corresponding instruction type. In some implementations, the transmit port may include: an Arithmetic and Logic Unit (ALU) transmit port, a vector transmit port, a matrix instruction transmit port, and a scalar instruction transmit port, etc. Specifically, the ALU transmit port transmits floating-point or integer type instructions, the vector transmit port transmits vector type instructions, the matrix instruction transmit port transmits matrix type instructions, and the scalar instruction transmit port transmits scalar type instructions.

[0069] The correspondence between instruction types and transmit ports can be a preset correspondence. For example, floating-point or integer type instructions correspond to ALU transmit ports, vector type instructions correspond to vector transmit ports, matrix type instructions correspond to matrix instruction transmit ports, and scalar type instructions correspond to scalar instruction transmit ports.

[0070] In some implementations, multiple instruction types and the corresponding transmission port for each instruction type can be predetermined; the multiple instruction types are used as key information items, the corresponding transmission port for each instruction type is used as value information items, and the resulting key-value pairs are used as the correspondence between instruction types and transmission ports.

[0071] It should be noted that the correspondence between instruction type and transmission port can be represented in the form of key-value pairs, mapping table, or logical relationship diagram. This application embodiment does not limit this.

[0072] Taking a key-value pair implementation as an example, after obtaining the instruction type corresponding to the target instruction, the key information item with the same instruction type (matching basis) as the target instruction can be found in the correspondence between instruction type and emitter port. The emitter port in the value information item corresponding to that key information item is then used as the target emitter port. For example, if the instruction type corresponding to the target instruction is floating-point, the matched target emitter port is the ALU emitter port. It should be noted that the method for determining the target emitter port of target instructions of other instruction types is the same as that for floating-point instructions, and will not be elaborated further here.

[0073] Taking a mapping table as an example, after obtaining the instruction type corresponding to the target instruction, the corresponding instruction type can be used as the matching basis. The index entry matching the instruction type (matching basis) can be found in the correspondence between instruction types and transmit ports. The transmit port in the value information item corresponding to that index entry is then used as the target transmit port. For example, if the instruction type corresponding to the target instruction is floating-point, the matched target transmit port is the ALU transmit port. It should be noted that the method for determining the target transmit port of target instructions of other instruction types is the same as that for floating-point instructions, and will not be elaborated upon here.

[0074] Step S122: Based on the instruction type corresponding to the target instruction and the correspondence between the instruction type and the pipeline, determine the target pipeline that matches the instruction type corresponding to the target instruction from multiple pipelines at the target transmit port.

[0075] The correspondence between instruction types and pipelines can be a predefined one. For example, vector-type instructions correspond to vector processing pipelines, matrix-type instructions correspond to matrix-related instruction pipelines, and scalar-type instructions correspond to scalar processing pipelines. The scalar processing pipeline includes control instruction pipelines and scalar processing instruction pipelines.

[0076] In some implementations, multiple instruction types and the pipeline corresponding to each instruction type can be predetermined; the multiple instruction types are used as key information items, the pipeline corresponding to each instruction type is used as value information items, and the resulting key-value pairs are used as the correspondence between instruction types and pipelines.

[0077] It should be noted that the correspondence between instruction types and pipelines can be represented in the form of key-value pairs, mapping tables, or logical relationship diagrams. This application does not limit this aspect.

[0078] Taking a key-value pair implementation as an example, after obtaining the instruction type corresponding to the target instruction, the key information item with the same instruction type (matching basis) as the target instruction can be found in the correspondence between instruction type and pipeline. The pipeline in the value information item corresponding to that key information item is then used as the target pipeline. For example, if the instruction type corresponding to the target instruction is a vector type, the matched target pipeline is the vector processing pipeline. It should be noted that the method for determining the target pipeline for other instruction types is the same as that for vector type instructions, and will not be elaborated further here.

[0079] Taking a mapping table as an example, after obtaining the instruction type corresponding to the target instruction, the corresponding instruction type can be used as the matching basis. The index item matching the instruction type (matching basis) can be found in the correspondence between instruction types and pipelines. The pipeline in the value information item corresponding to that index item is then used as the target pipeline. For example, if the instruction type corresponding to the target instruction is a vector type, the matched target pipeline is the vector processing pipeline. It should be noted that the method for determining the target pipeline for other instruction types is the same as that for vector type instructions, and will not be elaborated further here.

[0080] Step S123: The target command is transmitted to the target pipeline through the target transmission port.

[0081] After determining the target transmission port, the target command is transmitted to the target pipeline through the target transmission port so that the target pipeline executes the target command.

[0082] In some implementations, vector-type instructions are sent to the vector processing pipeline via a vector send port.

[0083] In other implementations, matrix-type instructions are sent to the matrix-related instruction pipeline via a matrix instruction send port.

[0084] In some other implementations, scalar type instructions are sent to the scalar processing pipeline via a scalar instruction sending port.

[0085] Based on the above technical solution, the correspondence between instruction type, transmission port, and pipeline ensures that specific types of instructions are assigned to dedicated pipelines, which can reduce the delay of instructions in the pipeline and improve the execution efficiency of a single instruction.

[0086] In some embodiments, the thread bundle exit method provided in this application further includes the following steps S131 to S134: Step S131: Based on the judgment conditions, determine the branch corresponding to each thread in the target thread bundle.

[0087] The conditional statement is used to determine the branch corresponding to each thread in the target thread bundle. In some implementations, the conditional statement may include an if-else statement. Specifically, if a thread satisfies the if statement, the branch corresponding to the if statement is determined as the branch corresponding to that thread. If a thread satisfies the else statement, the branch corresponding to the else statement is determined as the branch corresponding to that thread.

[0088] The branch corresponding to a thread is the execution path selected by a single thread within a thread bundle based on the judgment condition. Threads within the same thread bundle may choose different branches due to different judgment condition results.

[0089] Step S132: Determine the mask corresponding to each thread based on the branch corresponding to each thread.

[0090] The mask corresponding to a thread is used to indicate whether the thread participates in the execution of the current instruction. In some implementations, the mask corresponding to a thread can use binary bits to represent the identifier of a single thread branch state; for example, 1 bit corresponds to 1 thread. Specifically, 1 indicates that the thread has selected the target branch and needs to execute the corresponding instruction, while 0 indicates that it has not been selected and will not be executed for the time being.

[0091] In some embodiments, if a thread enters an if statement, the corresponding mask is 1. If a thread enters an else statement, the corresponding mask is 0. In other embodiments, if a thread enters an if statement, the corresponding mask is 0. If a thread enters an else statement, the corresponding mask is 1. The specific implementation depends on the context.

[0092] Step S133: Determine the mask of the target thread bundle based on the masks corresponding to all threads.

[0093] The mask of the target thread bundle is used to characterize the branch distribution state of the entire thread bundle.

[0094] In some implementations, the masks corresponding to all threads constitute the mask for the target thread bundle. Specifically, the masks corresponding to all threads are combined to obtain the mask for the target thread bundle. Specifically, a 32-thread bundle corresponds to a 32-bit mask.

[0095] Step S134: If the mask representation of the target thread bundle is valid, perform an instruction fetch operation from the target instruction sequence.

[0096] A target thread bundle is considered valid if its mask satisfies the condition that at least one thread has selected the target branch (i.e., the mask is not all zeros). This indicates that the thread bundle still has instructions to execute and is capable of continuing instruction fetching and execution. In some embodiments, the target thread bundle is considered valid if at least one mask is valid. In the SIMT32 thread bundle execution scenario, mask validity primarily refers to the mask value representing the availability of threads within the target thread bundle meeting a preset validity condition (usually a non-zero mask value). For the thread bundle as a whole, a valid mask indicates that the thread bundle is qualified to execute instructions (not masked, terminated, or marked as abnormal), which is a prerequisite for triggering instruction fetching and execution operations. For a single thread within the thread bundle, each bit of the mask corresponds to a thread. A single bit being 1 indicates that the thread is valid (needs to participate in instruction execution), multiple bits being 1 indicate that some or all threads within the thread bundle are valid, and a mask of all 1s indicates that all 32 threads within the thread bundle are valid. In short, mask validity is the core basis for hardware to determine whether a thread bundle or thread can execute instructions; invalid masks skip instruction operations to avoid resource waste.

[0097] The instruction fetch operation reads the next instruction to be executed from the target instruction sequence. When the target thread bundle is active, it schedules the target thread bundle to perform the instruction fetch operation from the target instruction sequence, checks for any data dependencies between instructions, and if there are no data dependencies, directly issues the current instruction.

[0098] Each bit of the thread bundle mask corresponds to one thread within the SIMT32 thread bundle (32 bits in total). The activity level of the thread bundle is determined by the percentage of valid bits (values ​​of 1) in the mask. A higher percentage of valid bits indicates higher thread bundle activity; a percentage of 0 valid bits (all 0 bits in the mask) indicates a completely inactive thread bundle; a percentage of 100% valid bits (all 1 bits in the mask) indicates the thread bundle is in its most active state. For example, if a thread bundle mask is all 1s (all 32 bits are 1), it means all 32 threads are active and need to participate in instruction execution, indicating 100% thread bundle activity. The hardware will allocate full pipeline, register, and other resources to it. If only 16 bits of the thread bundle mask are 1s and the remaining 16 bits are 0s, it means only half of the threads are active, indicating 50% activity. The hardware allocates resources as needed (e.g., reserving arithmetic units only for active threads). If only one bit of the thread bundle mask is 1 (activity level 3.125%), or all 0 bits (activity level 0), the hardware will reduce or stop allocating resources to it, or even skip the instruction execution flow of that thread bundle.

[0099] Based on the above technical solution, the thread bundle mask can dynamically reflect the branch execution status. The instruction controller can determine the activity level of the thread bundle based on the mask, prioritize scheduling the thread bundle with a high proportion of active threads, avoid a large number of idle threads occupying the pipeline, and improve the overall parallel utilization of the GPU.

[0100] In some embodiments, the thread bundle exit method provided in this application further includes the following steps S141 to S143: Step S141: Determine the start time and response time of the target thread bundle.

[0101] The start time is the point in time when the target thread bundle execution begins. The start time is either the time when the target instruction sequence is acquired, or the time when the target instruction is first emitted into the target pipeline.

[0102] Response time is the time taken to execute the target instruction sequence.

[0103] In some implementations, the time recorded in the timestamp register when the first instruction in the target instruction sequence enters the target pipeline is used as the start time. In other implementations, the time recorded in the timestamp register when the target instruction sequence is fetched is used as the start time.

[0104] In some implementations, the time recorded in the timestamp register after all instructions in the target instruction sequence have been executed is used as the response time. In other implementations, the time when the target thread bundle exits, recorded in the timestamp register, is used as the response time.

[0105] Step S142: Determine the test time period of the target pipeline based on the start time and response time.

[0106] The time period to be tested is the time range within which the expected instruction sequence should be completed.

[0107] In some implementations, the response time and start time are subtracted to obtain the test time period; that is, the time period between the start time and the response time is determined as the test time period of the target pipeline.

[0108] S143, if the test time period for reaching the target pipeline is greater than or equal to the preset first time period and the synchronization flag has not been cleared, report the first anomaly.

[0109] The first time period is a preset time threshold used to determine whether the test time period has been completed.

[0110] If the time interval before reaching the target pipeline is greater than or equal to the preset first time interval, it indicates that within the preset first time interval, there are still instructions in the target instruction sequence that have not been executed, the target thread bundle has failed to exit normally, and an anomaly has occurred.

[0111] If the synchronization flag is not completely cleared, it can be understood that the target thread bundle is still in the execution state, indicating that the target instruction sequence has not been completed.

[0112] The first anomaly is an anomaly signal reported when the test period exceeds the preset first time period and the synchronization flag is not cleared, indicating that the execution of the instruction sequence has timed out or stalled.

[0113] Based on the above technical solution, determining the test period based on the start time and response time essentially sets an expected completion window for the execution of the instruction sequence. If the synchronization flag is not cleared after the window ends, it indicates that there may be problems such as pipeline blockage, resource deadlock, or instruction errors. The reporting of the first anomaly can trigger timely investigation and prevent the fault from spreading.

[0114] In some embodiments, the thread bundle exit method provided in this application further includes: reporting a second exception if any thread in the target thread bundle fails to exit within a preset second time period.

[0115] The preset second time period is a pre-defined time window used to determine whether all threads within the thread bundle have exited within a reasonable time. This time period is typically determined based on the task complexity and hardware latency characteristics of the thread bundle, and must cover the maximum time required for all threads in the thread bundle to exit under normal circumstances.

[0116] If any thread fails to exit, it can be understood as at least one thread within the thread bundle not having completed execution. The second exception is an exception signal reported when there are still threads within the thread bundle that have not exited at the end of the second time period.

[0117] The existence of any thread in the target thread bundle that has not exited within the preset second time period is declared from the perspective of the thread bundle. In some embodiments, it is declared from the perspective of the thread workgroup. If any thread bundle in the thread workgroup fails to exit within the preset second time period, a second exception will also be reported.

[0118] Based on the above technical solution, the second anomaly mechanism can detect problems early by monitoring the exit status of all threads, trigger timely investigations, and prevent the spread of faults.

[0119] In some embodiments, the thread bundle exit method provided in this application further includes the following steps S151 to S153: Step S151: If the target thread bundle encounters an abnormality and cannot exit, a clear signal is sent to the target pipeline within a preset third time period to enable the target pipeline to perform a clearing operation.

[0120] In some implementations, anomalies in the target thread bundle may include: instructions that have not been fully executed still carrying the target thread bundle number after the target thread bundle has exited; division by zero occurring during instruction execution; and out-of-bounds access. The core reason why instructions that have not been fully executed after the target thread bundle has exited still carrying the target thread bundle number is that the thread bundle exit mechanism is not bound to the instruction lifecycle. The hardware only marks the thread bundle as exited and releases surface resources, but does not clean up the thread bundle number identifiers of instructions waiting to be executed in the pipeline, causing the instructions to still be associated with the number of the exited thread bundle. The core reason for division by zero during instruction execution is that the division circuit of the hardware arithmetic logic unit cannot handle illegal operations with division by zero. The core reason for out-of-bounds access is that the address accessed by the instruction (instruction address, data address, register address, etc.) exceeds the hardware's preset legal range.

[0121] The phrase "instructions that still carry the target thread bundle number after the target thread bundle exits" means that if 10 instructions are executed, and the target thread bundle exits, and no new thread bundle is scheduled in when the 11th instruction finishes execution, then the target thread bundle ID corresponding to the 11th instruction is the one that was just released. If the target thread bundle ID cannot be found when the result of the 11th instruction returns, an exception occurs. Out-of-bounds access behaviors during the process can include instruction address out-of-bounds, data address out-of-bounds, and register access out-of-bounds. Instruction address out-of-bounds occurs when the target thread bundle performs an instruction fetch operation, and the program counter points to an instruction address that exceeds the chip's preset instruction storage range (e.g., the instruction storage range is 0x0000-0xFFFF, but the program counter points to 0x10001), triggering an address out-of-bounds error during the instruction fetch phase and terminating the instruction fetch operation. Data address out-of-bounds occurs when the target instruction sequence of a target thread bundle attempts to read or write memory beyond its allocated address space (e.g., the target thread bundle is allocated a shared memory range of 0x2000-0x2FFF, but attempts to access address 0x3000). This triggers out-of-bounds detection in the memory access pipeline, interrupts instruction execution, and marks the target thread bundle as an execution exception. Register access out-of-bounds occurs when a thread attempts to read or write register number 32 out of the 32 standard general-purpose registers (numbered 0-31) of a SIMT32 thread bundle. This triggers register access out-of-bounds, and the hardware immediately terminates the execution of the target thread bundle's instruction sequence.

[0122] The preset third time period is the pre-defined duration of the transmission clear signal.

[0123] The clear signal is a control signal sent by the instruction controller to the target pipeline, causing the instruction pipeline to immediately terminate the execution of all currently incomplete instructions and discard intermediate results. In some implementations, the clear signal may be the killkernel signal.

[0124] A clear operation is an action performed by the target pipeline in response to a clear signal, restoring the pipeline to an idle state. In some implementations, a clear operation may include terminating currently executing instructions, releasing instruction buffers, etc.

[0125] In some implementations, if the target thread bundle encounters an anomaly and cannot exit, the kill enable signal can be continuously raised during a third time period to cause the target pipeline to perform a cleanup operation.

[0126] Step S152: Upon receiving a cleanup completion signal from the target pipeline in response to the cleanup signal, determine that the cleanup operation of the target pipeline has been completed.

[0127] The cleanup completion signal is an acknowledgment signal returned by the target pipeline to the instruction controller after completing the cleanup operation, indicating that the pipeline has released all resources associated with the abnormal thread bundle. In some implementations, the cleanup completion signal may be the pipeline kill done signal.

[0128] In some implementations, the cleanup operation of the target pipeline is determined to be complete after receiving the pipeline kill done signal returned by the target pipeline.

[0129] Step S153: Reset the synchronization flag.

[0130] Resetting the synchronization flag restores the synchronization flag corresponding to the abnormal thread bundle to its initial state, eliminating the status flag in execution and paving the way for the scheduling of a new thread bundle. In some implementations, this can be done by restoring the synchronization flag to its default value. For example, the binary flag of a dedicated execution status register can be set from 1 to 0. Another example is setting the counter value from n to 0.

[0131] Based on the above technical solutions, if a thread bundle fails to exit due to an anomaly, it will continuously occupy core resources such as pipelines and registers, preventing subsequent thread bundles from being scheduled. Clearing signals and performing a clear operation can forcibly release these resources, preventing the anomaly of a single thread bundle from spreading to block the entire computing core and ensuring continuous hardware operation. Furthermore, the clear operation quickly returns the pipeline occupied by the anomaly to an idle state. Combined with resetting the synchronization flag, the instruction controller can immediately allocate new tasks to that pipeline, reducing resource idle time. Especially in scenarios with intensive multi-threaded bundle scheduling, this significantly reduces the impact of anomalies on overall throughput.

[0132] The thread bundle exit method provided in this application embodiment will be described in detail below with reference to specific application scenarios.

[0133] For GPUs or GPGPUs, to improve parallelism, SIMD32 or SIMT32 architectures are typically used for processing; these are commonly referred to as thread bundles. GPUs employ a large number of thread bundles for scheduling to hide execution latency.

[0134] However, in design, a multi-pipeline architecture is typically used to execute as many dependency-free instructions as possible in parallel. Multiple pipelines operate in parallel; once data dependencies are resolved at the data emitter port, data is directly sent to the corresponding pipeline. If data dependencies exist, they are resolved according to the de-dependency method. (See reference...) Figure 2 , Figure 2The schematic diagram of a first structure of a thread bundle exit system shown includes: register 201, instruction issuing unit 202, fixed-delay pipeline 203, and non-fixed-delay pipeline 204. The interaction process between register 201, instruction issuing unit 202, fixed-delay pipeline 203, and non-fixed-delay pipeline 204 is as follows: Step S211, resolve data dependencies. The instruction issuing unit 202 determines whether there is a data dependency between instructions. If there is a data dependency, the instruction issuing unit 202 resolves the data dependency by decomposing the instructions into fixed-delay pipelined instructions and non-fixed-delay pipelined instructions.

[0135] Step S212: Fixed-delay pipeline instruction data preparation. For a fixed-delay pipeline instruction, the instruction issuer 202 reads the instruction data corresponding to the fixed-delay pipeline instruction from register 201, and then issues the fixed-delay pipeline instruction and its corresponding instruction data to the fixed-delay pipeline 203 for execution. After the fixed-delay pipeline instruction is executed, the execution result is stored in register 201.

[0136] Step S213: Preparation of non-fixed delay pipelined instruction data. For non-fixed delay pipelined instructions, the instruction issuer 202 obtains the instruction data corresponding to the non-fixed delay pipelined instruction from register 201.

[0137] Step S214: Receiving non-fixed-delay pipelined instructions and data. Register 201 returns the instruction data corresponding to the non-fixed-delay pipelined instruction to instruction issue unit 202. Then, instruction issue unit 202 issues the non-fixed-delay pipelined instruction and its corresponding instruction data to non-fixed-delay pipeline 204 for execution. After the non-fixed-delay pipelined instruction is executed, the execution result is stored in register 201.

[0138] However, in a parallel execution structure, instructions without data dependencies will not respond. Then, at the end of instruction execution, the JUMP0 or END instruction is executed directly to exit and release all resources, resulting in the thread bundle exiting before the instruction execution.

[0139] These unfinished instructions or requests in the pipeline, without any operations blocking the execution of dependent JUMP0 or END termination instructions, and releasing all resources, can result in the pipeline still executing instructions, even though the thread bundle has already exited. These instructions may, on the one hand, pollute the register results of newly restarted thread bundles; on the other hand, they often cause the compiler to overlook certain dependencies, leading to thread bundle termination and resource release, resulting in a deadlock.

[0140] This application implements a thread bundle safe execution exit mechanism for multi-parallel pipelines. Without occupying a large amount of the SIMT32 wave pipeline, it can ensure that all pipeline instructions issued can be executed normally before releasing thread bundle resources, thus ensuring that the thread bundle can exit safely when multiple stream processors issue instructions to the multi-parallel pipeline for execution at the same time.

[0141] This application designs a safe exit mechanism in a kernel architecture that executes multiple parallel pipeline thread bundles in parallel, ensuring that each pipeline can exit safely. Multiple stream processors can simultaneously issue instructions into multiple different parallel pipelines. The instruction issuance mechanisms of these stream processors are independent of each other, and multiple thread bundles are issued and executed simultaneously within each stream processor. (Refer to...) Figure 3 The stream processor 301 includes stream processors 0 to m, and the pipeline 302 includes pipelines a to n. Taking pipeline 0 as an example, pipeline 0 can simultaneously issue instructions into pipelines a to n, and can simultaneously issue and execute multiple thread bundles.

[0142] Reference Figure 4 , Figure 4 The schematic diagram of a third structure of a thread bundle exit system shown includes: an instruction controller 401, a vector processing register 402, a scalar processing register 403, a floating-point and fixed-point ALU processing unit 404, and a pipeline 405. The pipeline 405 includes a merged processing pipeline a, a processing pipeline b, and a processing pipeline N. The specific steps for interaction between them may include: Step S411, thread bundle scheduling execution. The instruction controller 401 schedules the active thread bundles to perform instruction fetching operations and issue instructions.

[0143] Step S412, Inter-instruction data dependency check. The instruction controller 401 performs an inter-instruction data dependency check to see if there is any inter-instruction data dependency. If there is no data dependency, the current instruction is issued directly.

[0144] Step S413: Operand prefetching processing logic. For example, the instruction controller 401 can prefetch operands from the vector processing register 402, the scalar processing register 403, and the floating-point and fixed-point ALU processing units 404. Then, the current instruction and the prefetched operands are issued to the corresponding processing pipeline in the pipeline 405 for processing.

[0145] Add processing signals when transmitting instructions and data with the same thread bundle and thread group at the transmitting end. When a valid instruction is transmitted into the pipeline below, add relevant processing signals. When the pipeline finishes executing an instruction, the above processing signal is cleared; At this point, when the execution of the instruction ends and the exit instruction is executed, all status information of the instructions within the thread bundle and thread group is checked. Only when all information of the thread bundle and thread group is completed can the relevant thread bundle and thread group exit operation be executed, thereby achieving a two-way check between instruction issuance and execution completion.

[0146] If the waiting time exceeds the specified period and the relevant processing signal is not cleared, an abnormality will be reported.

[0147] When this exception occurs and exit is not possible, the relevant cleanup operations are triggered to complete the reset behavior. At the same time, the kill kernel is triggered to ensure a safe execution environment when a new kernel is scheduled in for execution.

[0148] Figure 5 This is a schematic diagram of an instruction sequence provided in an embodiment of this application, referred to... Figure 5 The instruction sequence includes instructions PC0-PCn, with the last instruction being JUMP0 / END.

[0149] Reference Figure 6 , Figure 6 The fourth structural diagram of a thread bundle exit system shown includes: a thread control and instruction transmitter 601, an instruction transmitter port 602, and a pipeline 603. The thread control and instruction transmitter 601 controls thread scheduling and instruction issuance. The instruction transmitter port 602 includes: an ALU instruction transmitter port, a vector instruction transmitter port, a matrix instruction transmitter port, and a scalar instruction transmitter port. The pipeline 603 includes: a floating-point / integer ALU, a vector processing pipeline, a matrix-related instruction pipeline, a control instruction pipeline, and a scalar processing instruction pipeline. The control instruction and scalar processing instruction pipelines constitute the scalar processing pipeline, where the control instructions are used to execute control operation-related behaviors. The thread control and instruction transmitter, instruction controller, and instruction issuing unit can be different terms with the same meaning.

[0150] Specific signal processing includes, but is not limited to, counters, signal feedback, adding dependencies, or strong feedback behaviors. Different pipelines can count according to the pipeline itself, or they can operate according to different specific bars or fences.

[0151] Taking a counter as an example, when an instruction pipeline c of thread bundle b in thread workgroup a is issued, the counter for the relevant operation in pipeline c (initialized to 0) is incremented by 1; when pipeline c completes the relevant operation of thread bundle b in thread workgroup a, it is decremented by 1. When a JUMP0 / END instruction is issued, the thread bundle enters a waiting state for thread bundle exit. At this time, it checks that the counter values ​​of all pipelines in the thread bundle are cleared to 0. A timer is then started to wait. If a timeout occurs and more than 2ms have passed, and the thread bundle still cannot wait for all pipeline counter values ​​to be cleared to 0, an exception is reported.

[0152] At the same time, when the thread workgroup exits, it checks all thread bundles in the thread workgroup to enter the exit state. If any thread bundle fails to complete the clearing operation in the timeout state, it reports an exception.

[0153] When a kill kernel occurs, the kill_enable signal is continuously pulled high. When all pipeline killdone signals are detected, the pipeline kill is waited for to complete, and then the counter is cleared to 0 in the safe exit mechanism processing embodiment.

[0154] By adding safety mechanisms for handling pipelined instructions and cleaning up pipelined processes upon completion, the system can safely execute in parallel and complete safe exit operations in a multi-pipeline parallel execution system, thus improving the robustness of program execution.

[0155] Based on the above embodiments, this application also provides a thread bundle exit device. Figure 7 This is a schematic diagram of the structure of the thread bundle exit device 70 provided in the embodiments of this application, as shown below. Figure 7 As shown, the thread bundle exit device 70 includes: The first processing unit 701 is used to perform first processing on the synchronization flag corresponding to the target thread bundle when the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline; the first processing indicates that the target thread bundle has started execution. The second processing unit 702 is used to perform a second processing on the synchronization flag corresponding to the target thread bundle when a feedback signal of the target instruction sequence is obtained; the feedback signal indicates that an instruction in the target instruction sequence has been executed; the second processing indicates that the target thread bundle has been executed; the synchronization flags corresponding to the first processing and the second processing are different; The first execution unit 703 is used to execute the exit operation of the target thread bundle after all instructions in the target instruction sequence have been executed in the target pipeline.

[0156] In some embodiments, the thread bundle exit device further includes: an acquisition unit, configured to acquire processing signals for each of the multiple thread bundles; the processing signals are used to reflect the adjustment mechanism of the synchronization flag of the corresponding thread bundle; the first processing unit is further configured to perform a first processing on the synchronization flag corresponding to the target thread bundle according to the first processing signal in the target processing signal corresponding to the target thread bundle; the second processing unit is further configured to perform a second processing on the synchronization flag corresponding to the target thread bundle according to the second processing signal in the target processing signal corresponding to the target thread bundle.

[0157] In some embodiments, when the target processing signal includes a counter, the count value of the counter is used as a synchronization identifier; the first processing unit is further configured to increment the current count value of the counter to obtain a first count value; the second processing unit is further configured to decrement the current count value of the counter to obtain a second count value.

[0158] In some embodiments, when the processing signal includes a counter, the count value of the counter is used as a synchronization identifier; the first processing unit is further configured to decrement the current count value of the counter to obtain a third count value; the second processing unit is further configured to increment the current count value of the counter to obtain a fourth count value.

[0159] In some embodiments, the first execution unit is further configured to clear the synchronization flag when the synchronization flag indicates that the target pipeline has executed all instructions in the target instruction sequence; after the synchronization flag is cleared, check the status information of the target thread bundle and the status information of the target instruction sequence; and if the status information meets the exit conditions, perform the exit operation of the target thread bundle.

[0160] In some embodiments, when the target processing signal includes a counter, the counter's count value is used as a synchronization identifier; the status information satisfies the exit condition, including at least one of the following: the current count value of the counter is the initial count value; the current count value of the counter being the initial count value indicates that the execution of both the target thread bundle and the target instruction sequence has ended; the processes of both the target thread bundle and the target instruction sequence have ended; and the resources of both the target thread bundle and the target instruction sequence have been released.

[0161] In some embodiments, the thread bundle exit device further includes: a first determining unit, configured to, for any target instruction in the target instruction sequence, determine a target issuing port from a plurality of issuing ports that matches the instruction type corresponding to the target instruction based on the instruction type corresponding to the target instruction and the correspondence between the instruction type and the issuing port; each issuing port issues an instruction of the corresponding instruction type; a second determining unit, configured to, based on the instruction type corresponding to the target instruction and the correspondence between the instruction type and the pipeline, determine a target pipeline from a plurality of pipelines of the target issuing port that matches the instruction type corresponding to the target instruction; and a first issuing unit, configured to issue the target instruction to the target pipeline through the target issuing port.

[0162] In some embodiments, the thread bundle exit device further includes: a third determining unit, configured to determine the branch corresponding to each thread in the target thread bundle based on a judgment condition; a fourth determining unit, configured to determine the mask corresponding to each thread based on the branch corresponding to each thread; a fifth determining unit, configured to determine the mask of the target thread bundle based on the masks corresponding to all threads; and a second execution unit, configured to perform an instruction fetch operation from the target instruction sequence when the mask of the target thread bundle indicates that the target thread bundle is valid.

[0163] In some embodiments, the thread bundle exit device further includes: a sixth determining unit, configured to determine the start time and response time of the target thread bundle; the start time is the time when the target instruction sequence is acquired, or the time when the target instruction is first emitted into the target pipeline; a seventh determining unit, configured to determine the test time period of the target pipeline based on the start time and response time; and a first reporting unit, configured to report a first exception if the test time period of the target pipeline is greater than or equal to a preset first time period and the synchronization flag has not been cleared.

[0164] In some embodiments, the thread bundle exit device further includes: a second reporting unit, configured to report a second exception if any thread in the target thread bundle fails to exit within a preset second time period.

[0165] In some embodiments, the thread bundle exit device further includes: a second transmitting unit, configured to transmit a clearing signal to the target pipeline within a preset third time period when the target thread bundle fails to exit due to an abnormality, so as to cause the target pipeline to perform a clearing operation; an eighth determining unit, configured to determine that the clearing operation of the target pipeline has been completed when a clearing completion signal is received from the target pipeline in response to the clearing signal; and a reset unit, configured to reset the synchronization flag.

[0166] It should be noted that the units included in the thread bundle exit device provided in this application embodiment can be implemented by a processor in an electronic device; of course, they can also be implemented by specific logic circuits; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field-programmable gate array (FPGA), etc.

[0167] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0168] It should be noted that, in the embodiments of this application, if the above-mentioned thread termination method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware and software combination.

[0169] This application provides an electronic device that can implement the thread bundle exit method described above.

[0170] In one example, reference Figure 8 The electronic device 80, as shown, includes: a processor 801, at least one communication bus 802, a user interface 803, at least one external communication interface 804, and a memory 805. The communication bus 802 is configured to enable communication between these components. The user interface 803 may include a display screen, and the external communication interface 804 may include standard wired and wireless interfaces.

[0171] The memory 805 is configured to store instructions and applications executable by the processor 801, and can also cache data to be processed or already processed by the processor 801 and various modules in the electronic device (e.g., image data, audio data, voice communication data and video communication data), and can be implemented by flash memory or random access memory (RAM).

[0172] This application provides a storage medium, namely a computer-readable storage medium, on which a computer program or instructions are stored. When the computer program or instructions are executed by a processor, they implement the steps in any of the thread bundle exit methods provided in the above embodiments.

[0173] This application provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a processor, they implement the steps in any of the thread bundle exit methods provided in the above embodiments.

[0174] It should be noted that the descriptions of the above embodiments of storage media, devices, apparatuses, and program products are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of storage media, devices, apparatuses, and program products of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0175] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0176] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0177] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0178] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0179] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0180] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks. Alternatively, if the integrated units of this application are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0181] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A thread termination method, characterized in that, The method includes: When the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline, the synchronization flag corresponding to the target thread bundle undergoes a first process; the first process indicates that the target thread bundle has started execution. Upon receiving a feedback signal from the target instruction sequence, a second processing is performed on the synchronization identifier corresponding to the target thread bundle; the feedback signal indicates that an instruction in the target instruction sequence has been completed; the second processing indicates that the target thread bundle has been completed; the synchronization identifiers corresponding to the first processing and the second processing are different; When the target pipeline has executed all the instructions in the target instruction sequence, the exit operation of the target thread bundle is performed.

2. The method according to claim 1, characterized in that, The method further includes: Obtain the processing signals for each of the multiple thread bundles; the processing signals are used to reflect the adjustment mechanism of the synchronization flag of the corresponding thread bundle; Accordingly, the first processing of the synchronization identifier corresponding to the target thread bundle includes: The synchronization identifier corresponding to the target thread bundle is processed first according to the first processing signal in the target processing signal corresponding to the target thread bundle; Accordingly, the second processing of the synchronization identifier corresponding to the target thread bundle includes: The synchronization identifier corresponding to the target thread bundle is subjected to second processing based on the second processing signal in the target processing signal corresponding to the target thread bundle.

3. The method according to claim 2, characterized in that, If the target processing signal includes a counter, the count value of the counter is used as the synchronization identifier; The first processing of the synchronization identifier corresponding to the target thread bundle based on the first processing signal in the target processing signal corresponding to the target thread bundle includes: The current count value of the counter is incremented to obtain a first count value; Accordingly, the step of performing second processing on the synchronization identifier corresponding to the target thread bundle based on the second processing signal in the target processing signal corresponding to the target thread bundle includes: The current count value of the counter is decremented to obtain a second count value.

4. The method according to claim 2, characterized in that, If the target processing signal includes a counter, the count value of the counter is used as the synchronization identifier; The first processing of the synchronization identifier corresponding to the target thread bundle based on the first processing signal in the target processing signal corresponding to the target thread bundle includes: The current count value of the counter is decremented to obtain a third count value; Accordingly, the step of performing second processing on the synchronization identifier corresponding to the target thread bundle based on the second processing signal in the target processing signal corresponding to the target thread bundle includes: The current count value of the counter is incremented to obtain a fourth count value.

5. The method according to any one of claims 1 to 4, characterized in that, The step of exiting the target thread bundle after all instructions in the target instruction sequence have been executed in the target pipeline includes: The synchronization flag is cleared once the target pipeline has executed all the instructions in the target instruction sequence. After the synchronization flag is cleared, check the status information of the target thread bundle and the status information of the target instruction sequence; If the status information meets the exit conditions, the exit operation of the target thread bundle is executed.

6. The method according to claim 5, characterized in that, If the target processing signal includes a counter, the count value of the counter is used as the synchronization identifier; The status information satisfies the exit condition, which includes at least one of the following: The current count value of the counter is the initial count value; the current count value of the counter being the initial count value indicates that the execution of the target thread bundle and the target instruction sequence has ended. The processes of the target thread bundle and the target instruction sequence have both ended; The resources of the target thread bundle and the target instruction sequence have been released.

7. The method according to any one of claims 1 to 4, characterized in that, The method further includes: For any target instruction in the target instruction sequence, based on the instruction type corresponding to the target instruction and the correspondence between the instruction type and the transmission port, a target transmission port matching the instruction type corresponding to the target instruction is determined from multiple transmission ports; each transmission port transmits an instruction of the corresponding instruction type; Based on the instruction type corresponding to the target instruction and the correspondence between the instruction type and the pipeline, a target pipeline that matches the instruction type corresponding to the target instruction is determined from multiple pipelines of the target transmit port; The target command is transmitted to the target pipeline through the target transmission port.

8. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Based on the judgment conditions, determine the branch corresponding to each thread in the target thread bundle; Determine the mask corresponding to each thread based on the branch corresponding to each thread; Based on the masks corresponding to all the threads, determine the mask of the target thread bundle; If the mask of the target thread bundle indicates that the target thread bundle is valid, an instruction fetch operation is performed from the target instruction sequence.

9. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Determine the start time and response time of the target thread bundle; the start time is the time when the target instruction sequence is acquired, or the time when the target instruction is first emitted into the target pipeline; Based on the start time and the response time, the test time period of the target pipeline is determined; If the time period for reaching the target pipeline is greater than or equal to the preset first time period, and the synchronization flag has not been cleared, a first anomaly is reported.

10. The method according to claim 5, characterized in that, The method further includes: If any thread in the target thread bundle fails to exit within the preset second time period, a second exception is reported.

11. The method according to any one of claims 1 to 4, characterized in that, The method further includes: If the target thread bundle encounters an abnormality and cannot exit, a clearing signal is sent to the target pipeline within a preset third time period to cause the target pipeline to perform a clearing operation. Upon receiving a clearing completion signal returned by the target pipeline in response to the clearing signal, it is determined that the clearing operation of the target pipeline has been completed. The synchronization identifier is reset.

12. A thread bundle exit device, characterized in that, The device includes: The first processing unit is configured to perform a first processing on the synchronization flag corresponding to the target thread bundle when the target instruction sequence corresponding to the target thread bundle arrives at the target pipeline; the first processing indicates that the target thread bundle has started execution. The second processing unit is configured to perform a second processing on the synchronization identifier corresponding to the target thread bundle upon receiving a feedback signal of the target instruction sequence; the feedback signal indicates that an instruction in the target instruction sequence has been completed; the second processing indicates that the target thread bundle has been completed; the synchronization identifiers corresponding to the first processing and the second processing are different; The first execution unit is configured to execute the exit operation of the target thread bundle after the target pipeline has executed all the instructions in the target instruction sequence.

13. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 11.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 11.

15. A computer program product comprising a non-transitory computer-readable storage medium storing a computer program, wherein when read and executed by a computer, the computer program implements the steps of the method of any one of claims 1 to 11.

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