Hardware synchronous lock

Abstract

The hardware synchronous lock comprises a counter, under the condition that a plurality of first hardware computing units holding the hardware synchronous lock release the hardware synchronous lock to the same second hardware computing unit, when any one of the plurality of first hardware computing units releases the hardware synchronous lock to the second hardware computing unit, 1 is added to the count value of the counter; when the count value of the counter is larger than or equal to a first specified value, the second hardware computing units are allowed to execute the to-be-executed task, and the first specified value is equal to the sum of the initial value of the counter and the number of the first hardware computing units.

Description

Technical Field

[0001] This disclosure relates to the field of computers, and more specifically to a hardware synchronization lock. Background Technology

[0002] To accelerate artificial intelligence (AI) computing, a common approach is to design hardware specifically optimized for AI computation, such as matrix computation units and vector computation units. These hardware units exhibit excellent efficiency and power consumption when performing specific AI calculations. Since AI computing involves a large number of parallel computational tasks, it's easy to accelerate AI computation by simply increasing the number of these hardware units. In recent years, AI has entered a period of rapid development, with new algorithms and models emerging constantly. These hardware units have revealed their limitations in terms of scalability when handling these new algorithms and models. On the other hand, general-purpose processing units based on architectures such as x86 / arm / RISCV, such as the Central Processing Unit (CPU), due to their excellent scalability, can quickly support computational tasks in new algorithms and models that these hardware units are not adept at handling. Summary of the Invention

[0003] In one aspect, this disclosure provides a hardware synchronization lock, including a counter configured to: when any one of the first hardware computing units holding the hardware synchronization lock releases the hardware synchronization lock to the same second hardware computing unit, increment the counter by 1; and when the counter's count is greater than or equal to a first specified value, allow the second hardware computing unit to execute a task to be executed, wherein the first specified value is equal to the initial value of the counter and the sum of the number of the first hardware computing units.

[0004] In another aspect, this disclosure provides a hardware synchronization lock, including a counter, configured to: when a first hardware computing unit holding the hardware synchronization lock releases the hardware synchronization lock to a plurality of second hardware computing units: set the count value of the counter to the sum of the initial value of the counter and the number of the plurality of second hardware computing units; decrement the count value of the counter by 1 when the first hardware computing unit releases the hardware synchronization lock to any one of the plurality of second hardware computing units; and allow each of the plurality of second hardware computing units to execute a corresponding pending task when the count value of the counter decreases to the initial value of the counter. Attached Figure Description

[0005] When read in conjunction with the accompanying drawings, various aspects of this disclosure are best understood through the following detailed description. It should be noted that, in accordance with standard practice in the art, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0006] Figure 1 A schematic diagram is shown of the execution process of a computing task in a computing device employing a hardware synchronization lock according to an embodiment of the present disclosure.

[0007] Figure 2 A schematic block diagram of a computing device that may employ a hardware synchronization lock according to an embodiment of the present disclosure is shown. Detailed Implementation

[0008] Features and exemplary embodiments of various aspects of this disclosure will now be described in detail. Numerous specific details are set forth in the following detailed description in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this disclosure by illustrating examples. This disclosure is by no means limited to any specific configuration presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of this disclosure. Well-known structures and techniques are not shown in the accompanying drawings and the following description to avoid unnecessarily obscuring this disclosure.

[0009] Furthermore, the various operations will be described as multiple discrete operations in a manner most conducive to understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must depend on the order. In particular, these operations do not need to be performed in the order presented.

[0010] The phrases “in an embodiment,” “in one embodiment,” and “in some embodiments” are used repeatedly throughout this document. These phrases do not typically refer to the same embodiment; however, they may refer to the same embodiment. Unless the context otherwise requires, the terms “comprising,” “having,” and “including” are synonyms. The phrases “A or B” and “A / B” mean “(A), (B), or (A and B).”

[0011] This disclosure proposes a hardware synchronization lock that enables efficient collaboration between various hardware computing units in a computing device, maximizing the performance and power consumption advantages of these units to support various new AI algorithms and models.

[0012] Specifically, according to embodiments of this disclosure, a first hardware synchronization lock can be released by multiple hardware computing units to the same hardware computing unit, and a second hardware synchronization lock according to embodiments of this disclosure can be released by one hardware computing unit to multiple hardware computing units. For convenience, the hardware computing unit that releases the first or second hardware synchronization lock will be referred to as the first hardware computing unit, and the hardware computing unit waiting for the first or second hardware synchronization lock will be referred to as the second hardware computing unit.

[0013] In some embodiments, the first hardware synchronization lock according to the present disclosure includes a first counter, configured to: when any one of the plurality of first hardware computing units (hereinafter referred to as first hardware computing units U11 to U1N) holding the first hardware synchronization lock releases the first hardware synchronization lock to the same second hardware computing unit (hereinafter referred to as second hardware computing unit U2 for simplicity): when any one of the plurality of first hardware computing units U11 to U1N releases the first hardware synchronization lock to the second hardware computing unit U2, increment the count value of the first counter by 1; and when the count value of the first counter is greater than or equal to a first specified value, allow the second hardware computing unit U2 to execute the task to be executed, wherein the first specified value is equal to the sum of the initial value of the first counter (hereinafter referred to as the initial value C1 for simplicity) and the number of the plurality of first hardware computing units U11 to U1N (i.e., the first specified value is equal to (C1+N)).

[0014] The second hardware synchronization lock according to an embodiment of the present disclosure includes a second counter, configured to: when a first hardware computing unit (hereinafter referred to as the first hardware computing unit U1) holding the second hardware synchronization lock releases the second hardware synchronization lock to a plurality of second hardware computing units (hereinafter referred to as second hardware computing units U21 to U2M for convenience); set the count value of the second counter to the sum of the initial value of the second counter (hereinafter referred to as the initial value C2 for convenience) and the number of the plurality of second hardware computing units U21 to U2M (i.e., set the count value of the second counter to (C2+M)); when the first hardware computing unit U1 releases the second hardware synchronization lock to any one of the plurality of second hardware computing units U21 to U2M, decrement the count value of the second counter by 1; and when the count value of the second counter decreases to the initial value C2 of the second counter, allow each of the plurality of second hardware computing units U21 to U2M to execute a corresponding task to be executed.

[0015] In some embodiments, the first hardware synchronization lock is further configured to, in the case of a release notification mode: set a first specified value to a release notification trigger threshold; and when the count value of the first counter reaches the release notification trigger threshold, generate a release signal and send the release signal to the second hardware computing unit U2, so that the second hardware computing unit U2 starts executing the task to be executed in response to the release signal.

[0016] In some embodiments, the first hardware synchronization lock is further configured to, in polling mode, have the second hardware computing unit U2 poll the count value of the first counter, and start executing the task to be executed in response to the count value of the first counter being greater than or equal to a first specified value.

[0017] In some embodiments, the first hardware synchronization lock is further configured to set the initial value C1 of the first counter, and after the plurality of first hardware computing units U11 to U1N release the first hardware synchronization lock to the second hardware computing unit U2, the count value of the first counter is reset to the initial value C1 of the first counter.

[0018] In some embodiments, the second hardware synchronization lock is further configured to, in the case of a release notification mode: set the initial value C2 of the second counter to a release notification trigger threshold; and when the count value of the second counter decreases to the release notification trigger threshold, generate a release signal and send the release signal to a plurality of second hardware computing units U21 to U2M, so that each of the plurality of second hardware computing units U21 to U2M starts executing a corresponding task to be executed in response to the release signal.

[0019] In some embodiments, the second hardware synchronization lock is further configured to, in polling mode, have each of the plurality of second hardware computing units U21 to U2M poll the count value of the second counter, and to begin executing the corresponding task to be executed in response to the count value of the second counter decreasing to the initial value C2 of the second counter.

[0020] In some embodiments, the second hardware synchronization lock can also be configured to set the initial value C2 of the second counter.

[0021] In some embodiments, when a plurality of first hardware computing units U11 to U1N release a first hardware synchronization lock to a second hardware computing unit U2, the plurality of first hardware computing units U11 to U1N may include at least one of a hardware computing unit specifically for AI computing and a central processing unit, and the second hardware computing unit U2 may be either a hardware computing unit specifically for AI computing or a central processing unit. Here, the hardware computing unit specifically for AI computing may include, for example, a matrix computing unit, a vector computing unit, etc.

[0022] In some embodiments, when the first hardware computing unit U1 releases the second hardware synchronization lock to a plurality of second hardware computing units U21 to U2M, the first hardware computing unit U1 may be a hardware computing unit specifically for AI computing or a central processing unit, and the plurality of second hardware computing units U21 to U2M may include at least one of a hardware computing unit specifically for AI computing and a central processing unit. Similarly, a hardware computing unit specifically for AI computing may include, for example, a matrix computing unit, a vector computing unit, etc.

[0023] Depending on the needs of the actual application, the computing device may include one or more first hardware synchronization locks and one or more second hardware synchronization locks. Figure 1 A schematic diagram illustrating the execution process of a computing task in a computing device employing a hardware synchronization lock according to an embodiment of the present disclosure is shown. Figure 1 As shown, the computing device includes two CPUs (CPU0 and CPU1, for example, an asymmetric multiprocessing (SMP) CPU), a video processing unit (VPU), a shader processing unit (SPU), and three hardware synchronization locks (0 to 2). Synchronization locks 0 and 1 can be implemented by a first hardware synchronization lock, and synchronization lock 2 is implemented by a second hardware synchronization lock. The initial values ​​of the counters for synchronization locks 0 to 2 are all 0. Assume there is a computing task to be executed, which includes seven subtasks (task1 to task7) executed on CPU0, CPU1, VPU, and SPU respectively. The execution body of each subtask is as follows... Figure 1 As shown, the dependencies between subtasks 1 to 7 are as follows: task 3 needs to wait for task 1 to complete before it can be executed; task 4 needs to wait for task 2 and task 3 to complete before it can be executed; task 5 needs to wait for task 4 to complete before it can be executed; and task 6 and task 7 need to wait for task 5 to complete before they can be executed.

[0024] exist Figure 1During the execution of the computation task shown, after completing task 1, the VPU releases synchronization lock 0 to the SPU, and the counter value of synchronization lock 0 is incremented by 1; the SPU waits for the VPU to release synchronization lock 0 (i.e., waits for the counter value of synchronization lock 0 to be greater than or equal to 1), executes task 3 while holding synchronization lock 0, and resets the counter value of synchronization lock 0 to 0, and after completing task 3, releases synchronization lock 1 to CPU0, and the counter value of synchronization lock 1 is incremented by 1; after completing task 2, the VPU releases synchronization lock 1 to CPU0, and the counter value of synchronization lock 1 is incremented by 1; CPU0 waits for VPU and SPU to release synchronization lock 1 (i.e., the counter for waiting for synchronization lock 1 is greater than or equal to 2). While holding synchronization lock 1, it executes task 4 and resets the counter for synchronization lock 1 to 0. After executing task 4, it releases synchronization lock 0 to CPU1 and increments the counter for synchronization lock 0 by 1. CPU1 waits for CPU0 to release synchronization lock 0 (i.e., the counter for waiting for synchronization lock 0 is greater than or equal to 1). While holding synchronization lock 0, it executes task 5 and resets the counter for synchronization lock 0 to 0. After executing task 5, it releases synchronization lock 2 to VPU and SPU and increments the counter for synchronization lock 2 by 2. VPU waits for CPU1 to release synchronization lock 2 (i.e., the counter for waiting for synchronization lock 2 is less than or equal to 0) and executes task 6 while holding synchronization lock 2. SPU waits for CPU1 to release synchronization lock 2 (i.e., the counter for waiting for synchronization lock 2 is less than or equal to 0) and executes task 7 while holding synchronization lock 2.

[0025] Figure 2 A schematic block diagram of a computing device that can employ a hardware synchronization lock according to embodiments of the present disclosure is shown. Figure 2 As shown, computing device 200 may include bus 202 or other communication mechanism for transmitting information, and one or more hardware processors 204 coupled to bus 202 for processing information. The one or more hardware processors 204 may include, for example, one or more general-purpose microprocessors.

[0026] like Figure 2As shown, in some embodiments, computing device 200 may further include main memory 206 coupled to bus 202. Main memory 206 is used to store information and instructions executed by one or more processors 204, such as random access memory (RAM), cache, and / or other dynamic storage devices. Main memory 206 may also be used to store temporary variables or other intermediate information during the execution of instructions executed by one or more processors 204. When these instructions are stored in storage media accessible to one or more processors 204, they can cause computing device 200 to become a dedicated machine customized to perform the operations specified in the instructions. Storage device 208 may include non-volatile and / or volatile storage media. Non-volatile storage media may include, for example, optical discs or magnetic disks. Volatile storage media may include dynamic memory. Common forms of storage media may include, for example, floppy disks, hard disks, solid-state drives, magnetic tape, or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, DRAM, PROM, and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cartridge, or their networking versions.

[0027] like Figure 2 As shown, in some embodiments, computing device 200 may further include one or more communication interfaces or network interfaces 210 coupled to bus 202. Network interface 210 may provide bidirectional data communication coupling to one or more network links connected to one or more networks. As another example, network interface 210 may be a local area network (LAN) card to provide data communication connectivity to a LAN-compatible (or WAN component communicating with a WAN) network. Wireless links may also be implemented.

[0028] The execution of certain operations can be distributed across processors rather than residing within a single machine, but rather deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0029] Each of the processes, methods, and algorithms described in the preceding sections may be embodied in code modules executed by one or more computer systems or computer processors including computer hardware, and may be fully or partially automated by these code modules. The processes and algorithms may be implemented, partially or fully, in dedicated circuit systems.

[0030] When the functions disclosed herein are implemented as software functional units and sold or used as stand-alone products, they may be stored in a processor-executable, non-volatile, computer-readable storage medium. Specific technical solutions (all or part) disclosed herein, or aspects contributing to the prior art, may be embodied in the form of a software product. The software product may be stored in a storage medium and includes several instructions that cause a computing device (which may be a personal computer, server, network device, etc.) to perform all or some steps of the methods of the embodiments of this application. The storage medium may include a flash drive, portable hard disk drive, ROM, RAM, magnetic disk, optical disk, other media operable to store program code, or any combination thereof.

[0031] Specific embodiments further provide a system including a processor and a non-transitory computer-readable storage medium storing instructions executable by the processor to cause the system to perform operations corresponding to steps in any method of the embodiments disclosed above. Specific embodiments further provide a non-transitory computer-readable storage medium storing instructions executable by one or more processors to cause the one or more processors to perform operations corresponding to steps in any method of the embodiments disclosed above.

[0032] The embodiments disclosed herein can be implemented via a cloud platform, server, or server cluster (collectively referred to below as the "Service System") that interacts with a client. The client can be a terminal device or a client registered by a user at the platform, wherein the terminal device can be a mobile terminal, a personal computer (PC), or any device that can have the platform application installed.

[0033] The various features and processes described above can be used independently of each other or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Additionally, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and their associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in an order other than that specifically disclosed, or multiple blocks or states may be combined into a single block or state. Example blocks or states may be executed sequentially, in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The exemplary systems and components described herein may be configured differently than described. For example, components may be added to, removed from, or rearranged compared to the disclosed example embodiments.

[0034] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. The algorithm may be included in program code or instructions stored in memory (e.g., the aforementioned non-transitory computer-readable storage medium). This algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not explicitly refer to the computer as performing the function but may learn from training data to generate a predictive model of the function.

[0035] The various operations of the exemplary methods described herein can be performed, at least in part, by one or more processors that are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, these processors can constitute an engine of processor implementation that operates to perform one or more of the operations or functions described herein.

[0036] Similarly, the methods described herein may be implemented at least in part by a processor, wherein one or more specific processors are instances of hardware. For example, at least some operations of the methods may be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors may also be operable to support the execution of relevant operations in a “cloud computing” environment or as the execution of relevant operations in a “Software as a Service” (SaaS) context. For example, at least some operations may be performed by a group of computers (as an example of a machine containing processors), wherein these operations are accessible via a network (e.g., the Internet) and via one or more appropriate interfaces (e.g., application programming interfaces (APIs)).

[0037] The execution of certain operations can be distributed across processors rather than residing within a single machine, and can be deployed across multiple machines. In some example embodiments, the processor or processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other example embodiments, the processor or processor-implemented engine may be distributed across multiple geographic locations.

[0038] Throughout this specification, multiple instances may be implemented as components, operations, or structures described as a single instance. Although individual operations of one or more methods are illustrated and described as separate operations, one or more of these individual operations may be performed simultaneously, and not necessarily in the order illustrated. Structures and functions presented as separate components in the example configuration may be implemented as composite structures or components. Similarly, structures and functions presented as single components may be implemented as single components. These and other variations, modifications, additions, and improvements fall within the scope of this document.

[0039] As used herein, "or" is inclusive rather than exclusive unless explicitly indicated by the context. Therefore, in this document, "A, B, or C" means "A, B, A and B, A and C, B and C, or A, B, and C" unless explicitly indicated by the context. Furthermore, "and" is combined and separate unless explicitly indicated by the context. Therefore, in this document, "A and B" means "A and B, combined or separate" unless explicitly indicated by the context. Additionally, multiple instances of resources, operations, or structures described herein may be provided as a single instance. Furthermore, the boundaries between various resources, operations, engines, and data storage devices are somewhat arbitrary and specific operations are illustrated within the context of a particular illustrative configuration. Other functional assignments are foreseeable and fall within the scope of various embodiments of this disclosure. Generally, structures and functions presented as individual resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functions presented as single resources may be implemented as single resources. These and other changes, modifications, additions, and improvements fall within the scope of the embodiments of this disclosure as expressed in the appended claims. Therefore, this specification and drawings should be considered illustrative rather than restrictive.

[0040] The terms “comprising” or “including” are used to indicate the presence of a subsequently claimed feature, but do not preclude the addition of other features. Unless otherwise specifically stated or otherwise understood in the context in which they are used, conditional language such as “may,” “can,” “may,” and “can” is generally intended to convey that certain embodiments include certain features, components, and / or steps that are not included in other embodiments. Therefore, this conditional language is generally not intended to imply that one or more embodiments require features, components, and / or steps in any way, or that one or more embodiments must include logic for determining whether such features, components, and / or steps are included in or performed in any particular embodiment, with or without user input or prompts.

[0041] Although the general outline of the subject matter has been described with reference to specific exemplary embodiments, various modifications and changes may be made to these embodiments without departing from the broad scope of embodiments of this disclosure. Where more than one embodiment is disclosed, these embodiments of the subject matter may be referred to individually or collectively herein as the term "invention," this is for convenience only and is not intended to automatically limit the scope of this application to any single disclosure or concept.

[0042] The embodiments illustrated herein are described in detail to enable those skilled in the art to practice the disclosed teachings. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. Therefore, “implementation” is not intended to be limiting, and the scope of the various embodiments is defined only by the appended claims and their full scope.

Claims

1. A hardware synchronization lock, characterized in that, Includes a counter, and is configured to, in the event that multiple first hardware computing units holding the hardware synchronization lock release the hardware synchronization lock to the same second hardware computing unit: When any one of the plurality of first hardware computing units releases the hardware synchronization lock to the second hardware computing unit, the count value of the counter is incremented by 1; as well as When the counter's count value is greater than or equal to a first specified value, the second hardware computing unit is allowed to execute the task to be executed, wherein the first specified value is equal to the sum of the initial value of the counter and the number of the plurality of first hardware computing units.

2. The hardware synchronization lock according to claim 1, characterized in that, It is also configured to be in release notification mode: Set the first specified value as the release notification trigger threshold; and When the counter reaches the release notification trigger threshold, a release signal is generated and sent to the second hardware computing unit, so that the second hardware computing unit starts executing the task to be executed in response to the release signal.

3. The hardware synchronization lock according to claim 1, characterized in that, It is also configured to, in polling mode, have the second hardware computing unit poll the counter's count value, and to begin executing the task to be executed in response to the counter's count value being greater than or equal to the first specified value.

4. The hardware synchronization lock according to claim 1, characterized in that, It is also configured as: Set the initial value of the counter; as well as After the plurality of first hardware computing units release the hardware synchronization lock to the second hardware computing unit, the count value of the counter is reset to the initial value of the counter.

5. The hardware synchronization lock according to claim 1, characterized in that, The plurality of first hardware computing units include at least one of a hardware computing unit specifically designed for artificial intelligence computing and a central processing unit.

6. The hardware synchronization lock according to claim 1, characterized in that, The second hardware computing unit is a central processing unit or a hardware computing unit specifically designed for artificial intelligence computing.

7. A hardware synchronization lock, characterized in that, Includes a counter, and is configured to release the hardware synchronization lock to multiple second hardware computing units when a first hardware computing unit holding the hardware synchronization lock releases the hardware synchronization lock: The counter value is set to the sum of the initial value of the counter and the number of the plurality of second hardware computing units; When the first hardware computing unit releases the hardware synchronization lock to any one of the plurality of second hardware computing units, the count value of the counter is decremented by 1. as well as When the counter value decreases to the initial value of the counter, each of the plurality of second hardware computing units is allowed to execute the corresponding task to be executed.

8. The hardware synchronization lock according to claim 7, characterized in that, It is also configured to be in release notification mode: Set the initial value of the counter to the release notification trigger threshold; and When the counter value decreases to the release notification trigger threshold, a release signal is generated and sent to the plurality of second hardware computing units, so that each of the plurality of second hardware computing units responds to the release signal and begins to execute the corresponding task to be executed.

9. The hardware synchronization lock according to claim 7, characterized in that, It is also configured to, in polling mode, have each of the plurality of second hardware computing units poll the count value of the counter, and to begin executing the corresponding pending task in response to the count value of the counter decreasing to the initial value of the counter.

10. The hardware synchronization lock according to claim 7, characterized in that, It is also configured to set the initial value of the counter.

11. The hardware synchronization lock according to claim 7, characterized in that, The plurality of second hardware computing units include at least one of a hardware computing unit specifically for artificial intelligence computing and a central processing unit.

12. The hardware synchronization lock according to claim 7, characterized in that, The first hardware computing unit is a central processing unit or a hardware computing unit specifically designed for artificial intelligence computing.

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