DDR test method, apparatus and device, and computer readable storage medium

Abstract

The invention relates to the technical field of storage testing, and discloses a DDR testing method, device and equipment and a computer readable storage medium. The method comprises the following steps: acquiring a bus signal of a test DDR, determining a first read address based on the bus signal, and reading first data from the test DDR based on the first read address; performing address mapping on the first read address on the basis of a preset unified logic address space and the type of a preset standard DDR to obtain a second read address, and reading second data from the preset standard DDR on the basis of the second read address; and comparing the first data with the second data to determine a test result for testing the DDR. The read data of the test DDR have the read data of the corresponding preset standard DDR, accidental errors occurring in a real scene are covered, meanwhile, only the read data of the test DDR and the read data of the standard DDR need to be compared, the accuracy of the DDR test is improved, and the complexity of the DDR test is reduced.

Description

Technical Field

[0001] This application relates to the field of storage testing technology, and in particular to a DDR testing method, apparatus, device, and computer-readable storage medium. Background Technology

[0002] Before DDR (Double Data Rate Synchronous Dynamic Random-Access Memory) can be put into use, it needs to be tested. Existing mainstream testing methods include SLT and ATE testing methods, which use algorithms to read and write to the DDR to detect errors; another method is to capture DDR signals and then analyze them to detect problems.

[0003] However, the method of detecting errors by reading and writing DDR data using algorithms, as disclosed in CN108039190B, cannot fully cover all scenarios. Some accidental errors occurring in real-world scenarios cannot be covered by read / write algorithms. Furthermore, the method of detecting errors by capturing and analyzing DDR signals requires expensive analytical instruments and extensive analysis, resulting in high costs. This leads to high complexity and low accuracy in DDR testing. Summary of the Invention

[0004] In view of this, the purpose of this application is to overcome the shortcomings of the prior art and provide a DDR testing method, the method comprising: Acquire the bus signal of the test DDR, determine the first read address based on the bus signal, and read the first data from the test DDR based on the first read address; Based on a preset unified logical address space and a preset standard DDR type, the first read address is mapped to obtain a second read address, and the second data is read from the preset standard DDR based on the second read address; The first data and the second data are compared to determine the test result of the DDR.

[0005] In one embodiment, the step of acquiring the bus signal of the test DDR and determining the first read address based on the bus signal includes: Acquire the bus signals of the test DDR and identify the type of the test DDR; Based on the type of the test DDR, analysis rules are determined, and the bus signals are analyzed based on the analysis rules to determine the first read address.

[0006] In one embodiment, the step of mapping the first read address to obtain the second read address based on a preset unified logical address space and a preset standard DDR type includes: Based on the preset unified logical address space, the first read address is addressed to obtain the target logical address; Based on the type of the preset standard DDR, the target logical address is converted into a second read address.

[0007] In one embodiment, the step of addressing the first read address based on the preset unified logical address space to obtain the target logical address includes: Based on the type of the test DDR, determine the first address parameter of the test DDR; In the first read address, determine the address field corresponding to each of the first address parameters; Based on the preset unified logical address space, the address fields corresponding to each of the first address parameters are addressed to obtain the target logical address.

[0008] In one embodiment, the step of converting the target logical address to a second read address based on the type of a preset standard DDR includes: Based on the type of the preset standard DDR, determine the second address parameter of the preset standard DDR and the field width of the second address parameter; Based on the preset truncation rules and the field width of each of the second address parameters, the target logical address is truncated to obtain the address field corresponding to each of the second address parameters; The second read address is determined based on the address field corresponding to each of the second address parameters.

[0009] In one embodiment, the method further includes: First data is read from the test DDR based on the first read address, and the first data is stored in a preset storage space; Detect whether second data has been acquired from the preset standard DDR based on the second read address; If the second data is obtained, the first data and the second data are compared.

[0010] In one embodiment, the method further includes: The bus signal of the test DDR is acquired, and a first write address and target write data are determined based on the bus signal. The target write data is then written to the test DDR based on the first write address. Based on the preset unified logical address space and the type of the preset standard DDR, the first write address is mapped to obtain the second write address, and the target write data is written to the preset standard DDR based on the second write address; When determining the read address corresponding to the first write address based on the bus signal, the third data of the first write address is read from the test DDR, and the fourth data of the second write address is read from the preset standard DDR; The third and fourth data are compared to determine the test result of the DDR.

[0011] This application also provides a DDR testing apparatus, the DDR testing apparatus comprising: The determination module is used to acquire the bus signal of the test DDR, determine a first read address based on the bus signal, and read first data from the test DDR based on the first read address; The mapping module is used to perform address mapping on the first read address based on a preset unified logical address space and a preset standard DDR type to obtain a second read address, and to read second data from the preset standard DDR based on the second read address; The comparison module is used to compare the first data and the second data to determine the test result of the test DDR.

[0012] This application also provides a computer device, the computer device including a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the above-described DDR testing method.

[0013] This application also provides a computer-readable storage medium storing a computer program that, when run on a processor, executes the above-described DDR testing method.

[0014] The embodiments of this application have the following beneficial effects: This application embodiment acquires the bus signal of the test DDR, determines a first read address based on the bus signal, and reads first data from the test DDR based on the first read address; based on a preset unified logical address space and a preset standard DDR type, the first read address is address-mapped to obtain a second read address, and second data is read from the preset standard DDR based on the second read address; the first data and the second data are compared to determine the test result of the test DDR. The read data of the test DDR has corresponding read data of the preset standard DDR, avoiding the inability to cover accidental errors that occur in real-world scenarios. Furthermore, only the read data of the test DDR and the standard DDR need to be compared, avoiding the need for extensive data analysis using expensive analytical instruments, thus improving the accuracy and reducing the complexity of DDR testing. Attached Figure Description

[0015] To more clearly illustrate the technical methods of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be considered as a limitation on the scope of protection of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A flowchart illustrating the first embodiment of the DDR testing method provided in this application; Figure 2 This is a flowchart illustrating a second embodiment of the DDR testing method provided in this application; Figure 3 A flowchart illustrating the third embodiment of the DDR testing method provided in this application; Figure 4 A schematic diagram of the address mapping process provided in this application; Figure 5 A flowchart illustrating the fourth embodiment of the DDR testing method provided in this application; Figure 6 A flowchart illustrating the fifth embodiment of the DDR testing method provided in this application; Figure 7 A flowchart illustrating the DDR testing process provided in this application; Figure 8 A schematic diagram of the DDR testing device provided in this application. Detailed Implementation

[0017] The technical methods in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0018] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0019] In the following, the terms “comprising,” “having,” and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as excluding, firstly, the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations thereof.

[0020] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0021] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0022] It is understood that the method of this application is applied to a memory testing device, which can be electrically or communicatively connected to DDR to test DDR. The memory testing device can be a smart terminal, PC terminal, mobile terminal, etc., and is not limited thereto. For ease of description, the following embodiments are described using the DDR testing device as the execution subject.

[0023] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a first embodiment of the DDR testing method provided in this application. The method includes: Step S101: Obtain the bus signal of the test DDR, determine the first read address based on the bus signal, and read the first data from the test DDR based on the first read address.

[0025] In this embodiment, the test DDR is connected to the host for communication. The host sends a bus signal to the test DDR to control the test DDR to work. The memory testing device obtains the bus signal sent by the host to the test DDR, analyzes the bus signal, determines the read instruction in the bus signal, and then determines the first read address corresponding to the read instruction. The memory testing device reads the first data from the test DDR based on the first read address.

[0026] Step S102: Based on the preset unified logical address space and the preset standard DDR type, the first read address is mapped to obtain the second read address, and the second data is read from the preset standard DDR based on the second read address.

[0027] In this embodiment, after determining the first read address, the memory testing device performs address mapping on the first read address based on a preset unified logical address space and the type of a preset standard DDR to obtain a second read address, and then reads the second data from the preset standard DDR based on the second read address. It should be noted that the second read address indicates the specific storage address of the second data to be read in the preset standard DDR. This storage address is the equivalent storage address of the specific storage address of the first data in the test DDR; that is, the specific storage address of the first data in the test DDR and the specific storage address of the second data in the preset standard DDR are logically equivalent addresses. It should also be noted that the type of the preset standard DDR is different from the type of the test DDR. The preset standard DDR is a normal DDR without read / write problems, verified through various testing methods. Therefore, the preset standard DDR can be used as a comparative reference for testing the test DDR.

[0028] Step S103: Compare the first data and the second data to determine the test result of the test DDR.

[0029] In this embodiment, the memory testing device compares the first data and the second data, records the comparison result, and then re-executes the following steps: acquiring the bus signal of the test DDR, determining the first read address based on the bus signal, and reading the first data from the test DDR based on the first read address; mapping the first read address to a second read address based on a preset unified logical address space and a preset standard DDR type, and reading the second data from the preset standard DDR based on the second read address, comparing the first data and the second data. This process continues until the comparison between the data in each valid memory address of the test DDR and the corresponding data in the preset standard DDR is completed, thus determining the test result of the test DDR.

[0030] It should be noted that if the first data and the second data are different, it indicates that there is a read / write error point in the test DDR. The read / write error point is the data storage area corresponding to the specific storage address of the first data in the test DDR.

[0031] The memory testing device in this embodiment acquires the bus signal of the test DDR, determines a first read address based on the bus signal, and reads first data from the test DDR based on the first read address. Based on a preset unified logical address space and a preset standard DDR type, it performs address mapping on the first read address to obtain a second read address, and reads second data from the preset standard DDR based on the second read address. The first data and the second data are compared to determine the test result of the test DDR. The read data of the test DDR has corresponding read data of the preset standard DDR, avoiding the inability to cover accidental errors occurring in real-world scenarios. Furthermore, only the read data of the test DDR and the standard DDR need to be compared, avoiding the need for extensive data analysis with expensive analytical instruments, thus improving the accuracy and reducing the complexity of DDR testing.

[0032] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a second embodiment of the DDR testing method provided in this application. The difference between the second embodiment and the first embodiment is that the step of acquiring the bus signal of the DDR being tested and determining the first read address based on the bus signal includes: Step S201: Obtain the bus signal of the test DDR and identify the type of the test DDR.

[0033] Step S202: Based on the type of the test DDR, determine the analysis rules, and analyze the bus signal based on the analysis rules to determine the first read address.

[0034] In this embodiment, the memory testing device acquires the bus signal of the test DDR and identifies the type of test DDR. Based on the type of test DDR, it determines the analysis rules and analyzes the bus signal according to the analysis rules to determine the first read address. It should be noted that DDR includes types such as DDR1, DDR2, DDR3, DDR4, DDR5, LPDDR4, and LPDDR5. DDR addresses include Rank, bank Group, Bank, Row, and Column, etc. The data structure of the read address differs for different types of DDR. Therefore, the memory testing device needs to determine the analysis rules based on the type of test DDR, and then analyze the bus signal according to the analysis rules to determine the first read address, in order to accurately determine the specific read address contained in the bus signal sent by the host to the test DDR.

[0035] The memory testing device in this embodiment acquires the bus signal of the test DDR and identifies the type of test DDR. Based on the type of test DDR, it determines the analysis rules and analyzes the bus signal based on the analysis rules to determine the first read address. This avoids confusion about the data structure of the read address of different types of test DDR and can accurately determine the specific read address contained in the bus signal sent by the host to the test DDR, which helps to improve the accuracy of subsequent DDR testing.

[0036] Please refer to Figure 3 , Figure 3 This is a flowchart illustrating a third embodiment of the DDR testing method provided in this application. The difference between the third embodiment and the first to second embodiments is that the step of mapping the first read address to obtain the second read address based on a preset unified logical address space and a preset standard DDR type includes: Step S301: Based on the preset unified logical address space, the first read address is addressed to obtain the target logical address.

[0037] In this embodiment, after determining the first read address, the memory testing device performs addressing processing on the first read address based on a preset unified logical address space to obtain the target logical address. It should be noted that the preset unified logical address space is a fixed-size, contiguous logical address space without physical type dependence (e.g., a 64GB address space). All read and write accesses of the tested DDR are mapped to this logical address space. This logical address space does not correspond to any real physical Bank / Row structure of the DDR; it is merely an abstract index. The original DDR address (including Rank / BG / Bank / Row / Col) sent by the host is not used directly but is sent as input to the mapping module. The logical address space is a standardized interface layer defined by the user and is a prerequisite for achieving cross-type compatibility.

[0038] In one embodiment, the step of addressing the first read address based on the preset unified logical address space to obtain the target logical address includes: Step S3011: Determine the first address parameter of the test DDR based on the type of the test DDR.

[0039] In this embodiment, the memory testing device determines the first address parameters of the DDR to be tested based on the type of DDR being tested. The first address parameters include Rank, bank group, bank, row, column, etc. For example, the first address parameters of DDR4 include Rank, bank, row, column, and the first address parameters of DDR5 include Rank, bank group, bank, row, column.

[0040] Step S3012: Determine the address field corresponding to each of the first address parameters in the first read address.

[0041] Step S3013: Based on the preset unified logical address space, addressing processing is performed on the address fields corresponding to each of the first address parameters to obtain the target logical address.

[0042] In this embodiment, the memory testing device determines the address field corresponding to each first address parameter in the first read address, performs addressing processing on the address field corresponding to each first address parameter based on a preset unified logical address space, and concatenates the addressed addresses of the address fields corresponding to each first address parameter to obtain the target logical address.

[0043] In one embodiment, the type of DDR being tested is DDR4, and the first read address is 0x12345678. The memory testing device, based on the preset DDR4 type configuration, deconstructs the first read address of DDR4 into the target logical address in the unified logical address space. Specifically, the memory testing equipment determines the first address parameters for testing DDR4: DDR_Type=DDR4, Rank=2, bankGroup=2, Bank=16, Row=16, Column=10; the memory testing equipment concatenates the DDR4 address fields according to weights into a 36-bit target logical address L (high bits padded with zeros, low bits aligned): L[35:0] = { Rank[0], BG[1:0], Bank[3:0], Row[15:0], Col[9:0], 0...0}, and disassembles the first read address 0x12345678 (according to the DDR4 protocol): Col[9:0] = 0x78&0x3FF = 0x78 (120), Row[15:0] = (0x12345678>>10)&0xFFFF = 0x48D1 (18641), Bank[3:0] = (0x12345678>>16)&0xF = 0x4 (Bank 4), BG[1:0] = (0x12345678>>30)&0x3 = 0x0 (BG 0), Rank[0] = (0x12345678>>31)&0x1 = 0x0 (Rank 0); concatenating these gives the target logical address L=0x0_0004_8D1_78_000= 0x00048D178000 (36-bit, hexadecimal).

[0044] Step S302: Based on the type of the preset standard DDR, the target logical address is converted into a second read address.

[0045] In this embodiment, the memory testing device converts the target logical address into a second read address based on the preset standard DDR type.

[0046] In one embodiment, the step of converting the target logical address to a second read address based on the type of a preset standard DDR includes: Step S3021: Based on the type of the preset standard DDR, determine the second address parameter of the preset standard DDR and the field width of the second address parameter.

[0047] Step S3022: Based on the preset truncation rules and the field width of each of the second address parameters, the target logical address is truncated to obtain the address field corresponding to each of the second address parameters.

[0048] Step S3023: Determine the second read address based on the address field corresponding to each of the second address parameters.

[0049] In this embodiment, the memory testing device determines the second address parameters and the field width of the preset standard DDR based on the type of the preset standard DDR. Based on the preset truncation rules and the field width of each second address parameter, it performs field truncation on the target logical address to obtain the address field corresponding to each second address parameter. Based on the address fields corresponding to each second address parameter, it concatenates them to determine the second read address.

[0050] In one embodiment, the preset standard DDR type is DDR5. The memory testing device, configured according to the preset DDR5 type, forward maps the target logical address L of the first read address to a DDR5 physical address field. Specifically, the memory testing device determines that the preset standard DDR5 second address parameters include: Rank, bank Group, Bank, Row, and Column. The field widths of each second address parameter are Rank_Count=1, BG_Count=4, Bank_Count=32, Row_Bits=17, and Col_Bits=8. Based on the forward mapping algorithm, the memory testing device sequentially extracts the 36-bit target logical address according to the DDR5 field width from high to low bits: L = 0x00048D178000 = 0000000000000100100011010001011110000000000000000 (36bit), truncation rules: Rank[0] ← L

[35] =0, BG[1:0] ← L[34:33]=00, Bank[4:0] ← L[32:28]=00100→ Bank 4, Row[16:0] ← L[27:11]= 10001101000101111 → 0x11A2F (72,239), Col[7:0] ← L[10:3]= 00000000 → 0x00, the address fields corresponding to each of the second address parameters are: Rank=0, BG=0, Bank=4, Row=0x11A2F, Col=0x00. By concatenating and merging the address fields corresponding to each of the second address parameters, the second read address can be synthesized as: 0x00011A2F00.

[0051] It is understandable that, such as Figure 4 As shown, the DDR type to be tested can be DDR4, DDR5, or LPDDR4. The memory testing equipment first performs addressing processing on the read address of the test DDR based on a preset unified logical address space to obtain the target logical address. Then, based on the preset standard DDR type DDR5, the target logical address is converted into the read address corresponding to the preset standard DDR, including parameters such as Rank, bank group, bank, row, and column.

[0052] The memory testing device in this embodiment, based on a preset unified logical address space, performs addressing processing on the first read address to obtain the target logical address. Based on the preset standard DDR type, the target logical address is converted into a second read address. This breaks through the hard constraint in the traditional mirrored DDR testing method that the test DDR and the preset reference DDR must have the same physical type (e.g., both are DDR4). Through unified abstraction of logical addresses and type-aware dynamic demapping, it achieves compatibility of a single standard DDR (e.g., fixed as DDR5) with read addresses of multiple test DDRs (DDR3 / DDR4 / DDR5 / LPDDR4, etc.). It can achieve the function of testing multiple DDR types with one standard DDR type, improving the flexibility of DDR testing and further reducing testing costs.

[0053] Please refer to Figure 5 , Figure 5 This is a flowchart illustrating a fourth embodiment of the DDR testing method provided in this application. The difference between the fourth embodiment and the first to third embodiments is that the method further includes: Step S401: Read the first data from the test DDR based on the first read address, and store the first data in a preset storage space.

[0054] In this embodiment, the memory testing device reads first data from the test DDR based on a first read address and stores the first data in a preset storage space. It should be noted that the test DDR communicates with the host. The host sends bus signals to the test DDR to control its operation. These bus signals include write and read commands. The host continuously sends bus signals to the test DDR, allowing the memory testing device to analyze these signals. Upon determining each read command, the corresponding read address can be identified, and the first data can then be read from the test DDR and stored in the preset storage space.

[0055] Step S402: Detect whether second data has been obtained from the preset standard DDR based on the second read address.

[0056] In this embodiment, after determining the first read address, the memory testing device needs to convert the first read address into a second read address, and then read the second data from the preset standard DDR based on the second read address. Therefore, the memory testing device reads the first data from the test DDR based on the first read address and the second data from the preset standard DDR based on the second read address not synchronously. Therefore, the memory testing device needs to detect in real time whether the second data read from the preset standard DDR based on the second read address has been obtained.

[0057] Step S403: If the second data is obtained, the first data and the second data are compared.

[0058] In this embodiment, if the memory testing device acquires second data read from the preset standard DDR based on the second read address, it extracts the corresponding first data from the preset storage space and compares the first data and the second data. It should be noted that if the memory testing device does not acquire second data read from the preset standard DDR based on the second read address, it continues real-time detection and simultaneously analyzes the bus signal in real-time to determine the corresponding read address, and then reads and stores the data from the test DDR in the preset storage space.

[0059] The memory testing device in this embodiment reads first data from the test DDR based on a first read address and stores the first data in a preset storage space. It then checks whether second data is obtained from a preset standard DDR based on a second read address. If second data is obtained, the first and second data are compared. Since reading the first data from the test DDR based on the first read address and reading the second data from the preset standard DDR based on the second read address are not performed synchronously, the first data read in advance is stored in the preset storage space. Only when the corresponding second data is obtained is the corresponding first data retrieved from the preset storage space and compared with the second data. This avoids the loss of the pre-obtained first data and improves the reliability of the DDR test.

[0060] Please refer to Figure 6 , Figure 6 This is a flowchart illustrating the fifth embodiment of the DDR testing method provided in this application. The difference between the fifth embodiment and the first to fourth embodiments is that the method further includes: Step S501: Obtain the bus signal of the test DDR, determine the first write address and target write data based on the bus signal, and write the target write data into the test DDR based on the first write address.

[0061] Step S502: Based on the preset unified logical address space and the preset standard DDR type, the first write address is mapped to obtain the second write address, and the target write data is written to the preset standard DDR based on the second write address.

[0062] In this embodiment, the memory testing device acquires the bus signal of the test DDR and analyzes the bus signal to determine the first write address and the target write data. Based on the first write address, the target write data is written to the test DDR. Simultaneously, based on a preset unified logical address space and a preset standard DDR type, the memory testing device performs address mapping on the first write address to obtain a second write address, and based on the second write address, the target write data is written to the preset standard DDR.

[0063] It should be noted that although the test only requires comparing the data read from the test DDR with the data read from the preset standard DDR, the write address also needs to be converted when writing data so that the target write data can be written to both the test DDR and the preset standard DDR, and the target write data is stored in logically equivalent addresses in the test DDR and the preset standard DDR.

[0064] Step S503: When determining the read address corresponding to the first write address based on the bus signal, read the third data of the first write address from the test DDR and read the fourth data of the second write address from the preset standard DDR.

[0065] Step S504: Compare the third data and the fourth data to determine the test result of the test DDR.

[0066] In this embodiment, the memory testing device analyzes the bus signal. If the read address corresponding to the first write address is obtained, the third data of the first write address is read from the test DDR, and the fourth data of the second write address is read from the preset standard DDR. The third data and the fourth data are compared to determine the test result of the test DDR.

[0067] It should be noted that, in specific implementation, such as Figure 7 As shown, the memory testing equipment analyzes the bus signals to obtain write commands and write data. Based on the write commands, it determines the write address of the test DDR, and then determines the write address of the preset standard DDR through address mapping. The write data is then written to both the test DDR and the preset standard DDR. Similarly, the memory testing equipment analyzes the bus signals to obtain read commands. Based on the read commands, it determines the read address of the test DDR, and then determines the read address of the preset standard DDR through address mapping. Data is then read from both the test DDR and the preset standard DDR for comparison to determine the test result of the test DDR. Since reading data from the test DDR and reading data from the preset standard DDR are not performed synchronously, the memory testing equipment needs to store the data read from the test DDR in a preset storage space first.

[0068] The memory testing device in this embodiment first writes the data to be written to the test DDR and the preset standard DDR respectively. After detecting the corresponding read command, it reads the data corresponding to the test DDR and the preset standard DDR for comparison and testing, which improves the completeness of DDR testing and is more conducive to improving the accuracy of data comparison.

[0069] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the DDR testing apparatus provided in this application. The DDR testing apparatus includes: The determination module 10 is used to acquire the bus signal of the test DDR, determine a first read address based on the bus signal, and read first data from the test DDR based on the first read address.

[0070] The mapping module 20 is used to perform address mapping on the first read address based on a preset unified logical address space and a preset standard DDR type to obtain a second read address, and to read second data from the preset standard DDR based on the second read address.

[0071] The comparison module 30 is used to compare the first data and the second data to determine the test result of the test DDR.

[0072] It is understood that the DDR testing device in this embodiment corresponds to the DDR testing method in the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0073] This application also provides a computer device, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer device to perform the DDR testing method described above by running the computer program.

[0074] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0075] The memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. The memory is used to store computer programs, and the processor can execute the computer programs accordingly after receiving execution instructions.

[0076] This application also provides a computer storage medium for storing the computer program used in the aforementioned computer device. The computer storage medium can be a readable storage medium, a non-volatile storage medium, or a volatile storage medium. For example, the computer storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0077] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0078] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0079] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a readable storage medium. Based on this understanding, the technical methods of this application, in essence, or the part that contributes to the prior art, or a part of the technical methods, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A DDR testing method, characterized in that, The method includes: Acquire the bus signal of the test DDR, determine the first read address based on the bus signal, and read the first data from the test DDR based on the first read address; Based on a preset unified logical address space and a preset standard DDR type, the first read address is mapped to obtain a second read address, and the second data is read from the preset standard DDR based on the second read address; The first data and the second data are compared to determine the test result of the DDR.

2. The DDR testing method according to claim 1, characterized in that, The step of acquiring the bus signal of the test DDR and determining the first read address based on the bus signal includes: Acquire the bus signals of the test DDR and identify the type of the test DDR; Based on the type of the test DDR, analysis rules are determined, and the bus signals are analyzed based on the analysis rules to determine the first read address.

3. The DDR testing method according to claim 1, characterized in that, The step of mapping the first read address to obtain the second read address based on a preset unified logical address space and a preset standard DDR type includes: Based on the preset unified logical address space, the first read address is addressed to obtain the target logical address; Based on the type of the preset standard DDR, the target logical address is converted into a second read address.

4. The DDR testing method according to claim 3, characterized in that, The step of addressing the first read address based on the preset unified logical address space to obtain the target logical address includes: Based on the type of the test DDR, determine the first address parameter of the test DDR; In the first read address, determine the address field corresponding to each of the first address parameters; Based on the preset unified logical address space, the address fields corresponding to each of the first address parameters are addressed to obtain the target logical address.

5. The DDR testing method according to claim 3, characterized in that, The step of converting the target logical address to a second read address based on the preset standard DDR type includes: Based on the type of the preset standard DDR, determine the second address parameter of the preset standard DDR and the field width of the second address parameter; Based on the preset truncation rules and the field width of each of the second address parameters, the target logical address is truncated to obtain the address field corresponding to each of the second address parameters; The second read address is determined based on the address field corresponding to each of the second address parameters.

6. The DDR testing method according to claim 1, characterized in that, The method further includes: First data is read from the test DDR based on the first read address, and the first data is stored in a preset storage space; Detect whether second data has been acquired from the preset standard DDR based on the second read address; If the second data is obtained, the first data and the second data are compared.

7. The DDR testing method according to claim 1, characterized in that, The method further includes: The bus signal of the test DDR is acquired, and a first write address and target write data are determined based on the bus signal. The target write data is then written to the test DDR based on the first write address. Based on the preset unified logical address space and the type of the preset standard DDR, the first write address is mapped to obtain the second write address, and the target write data is written to the preset standard DDR based on the second write address; When determining the read address corresponding to the first write address based on the bus signal, the third data of the first write address is read from the test DDR, and the fourth data of the second write address is read from the preset standard DDR; The third and fourth data are compared to determine the test result of the DDR.

8. A DDR testing device, characterized in that, The DDR testing device includes: The determination module is used to acquire the bus signal of the test DDR, determine a first read address based on the bus signal, and read first data from the test DDR based on the first read address; The mapping module is used to perform address mapping on the first read address based on a preset unified logical address space and a preset standard DDR type to obtain a second read address, and to read second data from the preset standard DDR based on the second read address; The comparison module is used to compare the first data and the second data to determine the test result of the test DDR.

9. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the DDR testing method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when run on a processor, executes the DDR testing method according to any one of claims 1-7.

Images