A third-party ip oriented on-chip debug and trace package system

Abstract

The present application relates to the technical field of system on chip, and particularly relates to a system on chip debugging and tracking encapsulation system for third-party IP, which inserts a debugging and tracking encapsulation module between a system bus and a third-party IP module, is used for forwarding access requests and response data, and monitors, records or debugs injection; meanwhile, a debugging and tracking control module is arranged, which issues a debugging command through the system bus and collects data. The present application inserts a debugging encapsulation module between the system bus and the third-party IP, realizes interface transparent monitoring and non-invasive debugging injection, significantly improves black-box IP state observation ability, shields various debugging interface standards, reduces fragmentation cost, and avoids interference to original functions and timing of the IP.

Description

Technical Field

[0001] This invention relates to the field of system-on-chip technology, and more specifically to an on-chip debugging and tracing packaging system for third-party IP. Background Technology

[0002] In the field of System-on-Chip (SoC) design, debugging and tracing are crucial aspects throughout the entire chip development process, widely used in early-stage functional verification, mid-stage system performance optimization, and later-stage mass production testing and fault analysis. Typical on-chip debug and trace systems mainly include the following three implementation paths:

[0003] 1. Debug tracing modules based on the central processing unit (CPU) core, such as ETM / STM or RISC-V Trace technology in the ARM CoreSight architecture, export CPU instruction streams and data access information through a dedicated Trace port. Their observation range is limited to the CPU core, and their visibility to other peripheral IPs in the SoC is limited.

[0004] 2. Bus-level monitoring solutions collect address, data, and handshake signals through AXI bus monitors, protocol checkers, etc., to evaluate performance indicators such as bandwidth and latency or verify protocol compliance. However, such methods can only reflect the interaction behavior at the bus transaction level and are difficult to deeply analyze the internal operating status of the IP.

[0005] 3. On-chip logic analyzer / probe solutions, such as integrated logic analyzers (ILAs) and signal taps commonly used in field-programmable gate array (FPGA) designs, or embedded logic analysis modules pre-embedded in application-specific integrated circuits (ASICs), capture critical signals by inserting probes inside the design. In ASIC design, this method requires pre-fixing observation points at the register transfer level (RTL) stage, and probes cannot be dynamically reconfigured after tape-out, lacking flexibility for newly added debugging needs later.

[0006] While the aforementioned existing technologies provide effective debugging methods in specific scenarios, they suffer from the following significant drawbacks when dealing with the large number of third-party IPs introduced in modern SoC designs (which are typically delivered in an unmodifiable black-box form, with their internal structure invisible to the integrator):

[0007] 1) Debugging capabilities are limited by the black-box nature of the IP, making it impossible to implant probes or observation points by modifying the internal logic. This results in a severe lack of visibility into the internal operating state of the IP, and can only rely on its limited external interfaces or inference from the side through bus behavior.

[0008] 2) Different IPs provide different Debug / Trace interface standards (JTAG, APB, special registers, etc.), lacking a unified encapsulation and access architecture, resulting in fragmented debugging environments and high reuse costs for toolchains and scripts;

[0009] 3) Some debugging mechanisms require modification of bus transactions or handshake behavior, which can easily interfere with the original timing assumptions or quality of service (QoS) guarantees of the IP, increasing the risk of functional verification.

[0010] 4) The lack of a mechanism for debugging access to third-party IPs under unified security domain management may introduce a security attack surface, especially when sensitive functions such as encryption or authentication are involved.

[0011] The above reasons together make it difficult for existing on-chip debugging systems to achieve unified, transparent and secure debugging and tracking of third-party IPs in SoCs without intruding on the internal logic of third-party IPs or relying on their private debugging interfaces. Summary of the Invention

[0012] To address the above technical problems, this invention provides an on-chip debugging and tracing packaging system for third-party IP.

[0013] The technical problem solved by this invention can be achieved by the following technical solution: an on-chip debugging and tracing packaging system for third-party IP, comprising: a system bus, connected to the master device of the on-chip system, used for transmitting function access requests and response data; a third-party IP module, used for performing on-chip operations; a debugging and tracing control module, connected to the system bus, used for issuing debugging control commands through the system bus and collecting debugging and tracing data; and a debugging and tracing packaging module, connected between the system bus and the third-party IP module, used for forwarding the access requests and response data between the system bus and the third-party IP module, and for monitoring, recording, or debugging injection access to the access requests and response data.

[0014] Preferably, the debug and trace encapsulation module includes: an upstream bus interface, connected to the system bus, for receiving function access requests from the master device; a mode and security control unit, connected to the debug and trace control module, for receiving and parsing the debug control commands to configure the working mode of the debug and trace encapsulation module, and for controlling access to the switching of the working mode based on a security policy; a protocol adaptation and timing bridging unit, connected to the upstream bus interface and the mode and security control unit, for performing protocol adaptation and timing adjustment on the function access requests according to the working mode, and generating bus transactions; and a transaction monitoring and filtering unit, connected to the mode and security control unit. The security control unit and the protocol adaptation and timing bridging unit are used to monitor and filter the bus transactions according to the working mode and preset filtering rules to extract transaction feature information; the tracking buffer and output unit, connected to the transaction monitoring and filtering unit and the debugging and tracking control module, is used to store the transaction feature information in the tracking buffer module and send it to the debugging and tracking control module according to preset cache trigger conditions; the downstream bus interface, connected to the protocol adaptation and timing bridging unit and the third-party IP module, is used to send the bus transactions to the third-party IP module and receive tracking response data from the third-party IP module.

[0015] Preferably, the debug and trace encapsulation module further includes a debug injection unit connected to the mode and security control unit, the debug and trace control module, and the downstream bus interface. The debug injection unit is used to: receive a debug injection command from the debug and trace control module, convert the debug injection command into a debug access transaction, and initiate the debug access transaction to the third-party IP module through the downstream bus interface; receive debug response data from the third-party IP module through the downstream bus interface, send the debug response data back to the debug and trace control module, and prevent the debug response data from returning to the system bus through the upstream bus interface.

[0016] Preferably, before sending the debug access transaction, the debug injection unit receives bus status information from the protocol adaptation and timing bridging unit to determine whether the protocol adaptation and timing bridging unit is in an idle state. If it is in an idle state, the debug access transaction is sent; if it is not in an idle state, the debug access transaction is sent when it becomes idle.

[0017] Preferably, the working modes of the debugging and tracing encapsulation module include a functional transparent mode, a tracing and monitoring mode, and a debugging injection mode; the debugging and tracing encapsulation module switches between the functional transparent mode, the tracing and monitoring mode, and the debugging injection mode according to the mode and the debugging control commands received and parsed by the security control unit.

[0018] Preferably, in the function transparent mode, the debug and trace encapsulation module disables the transaction monitoring and filtering unit, the debug injection unit, and the trace buffer and output unit. The debug and trace encapsulation module sends the function access request received by the upstream bus interface to the downstream bus interface through the protocol adaptation and timing bridging unit, and sends the trace response data received by the downstream bus interface to the upstream bus interface.

[0019] Preferably, in the tracking and monitoring mode, the debugging and tracking encapsulation module enables the transaction monitoring and filtering unit and the tracking buffer and output unit based on the data forwarding path in the functionally transparent mode.

[0020] Preferably, in the debug injection mode, the debug and trace encapsulation module enables the debug injection unit based on the data forwarding path and monitoring mechanism in the trace monitoring mode.

[0021] Preferably, the transaction feature information includes at least one of the following: address, data, burst length, burst type, transaction identifier, quality of service field, request timestamp, response timestamp, and response type; the filtering rules include at least one of the following: address range filtering rules, transaction type filtering rules, transaction identifier filtering rules, or quality of service filtering rules; the cache triggering conditions include: detecting an error response or accessing a preset address.

[0022] Preferably, the debugging and tracking control module supports multiple standard bus protocols, including at least one of AXI4, AXI4-Lite, AHB, and APB.

[0023] Beneficial effects: This invention achieves transparent monitoring and debugging injection of the external interfaces of black-box IPs by inserting a dedicated debugging and tracing encapsulation module between the system bus and third-party IP modules. This significantly improves the ability to observe the internal operating state of unmodifiable IPs and overcomes the lack of visibility caused by the black-box nature of IPs in traditional solutions. At the same time, this debugging and tracing encapsulation module, as a unified access architecture, shields the diverse debugging interface standards of the underlying IPs, reducing the fragmentation of the debugging environment and the cost of toolchain reuse. In addition, monitoring and debugging through the system bus rather than intruding into the internal logic of the IP avoids interference with the original functions, timing, or quality of service of the IP caused by modifying bus transactions or handshake behavior. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall system structure of the present invention;

[0025] Figure 2This is a schematic diagram of the debugging and tracing encapsulation module of the present invention;

[0026] Figure 3 This is a schematic diagram illustrating the working mode switching relationship of the debugging and tracing packaging module of the present invention;

[0027] Figure 4 This is a timing diagram of the bus tracing performed by the debugging and tracing encapsulation module of the present invention;

[0028] Figure 5 This is the timing diagram of the non-intrusive read and write interaction of the debugging and tracing encapsulation module of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0031] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0032] Reference Figure 1 This invention provides an on-chip debugging and trace wrapper system for third-party IP, comprising: a system bus 1, connected to a master device 6 of the on-chip system, used for transmitting function access requests and response data; a third-party IP module 2, used for performing on-chip operations; a debugging and trace control module 3, connected to the system bus 1, used for issuing debugging control commands through the system bus 1 and collecting debugging and trace data; and a debugging and trace wrapper module 4, connected between the system bus 1 and the third-party IP module 2, used for forwarding the access requests and response data between the system bus 1 and the third-party IP module 2, and for monitoring, recording, or injecting debug access into the access requests and response data.

[0033] Specifically, in this embodiment of the invention, in response to the problem that the internal state of third-party IP is not visible due to its black-box nature, and that the debugging interface standards are not uniform and lack unified management, the present invention inserts a debugging and tracing encapsulation module 4 between the system bus 1 and the third-party IP module 2, thereby realizing transparent monitoring and non-intrusive debugging injection of IP interface transactions. This avoids the functional interference and fragmentation problems introduced by traditional solutions due to modification of the internal logic of IP or reliance on private interfaces, and realizes unified observation and debugging of the operating status of the third-party IP module 2 in the on-chip system.

[0034] Specifically, in actual deployment, system bus 1 preferably adopts the standard AXI or AHB protocol as the backbone interconnect structure of the SoC system, connecting each master device 6 and slave device; then, it is mounted on system bus 1 through the standard protocol interface of third-party IP module 2, wherein the internal logic of third-party IP module 2 is a black box and cannot be modified; next, the debug and trace package module 4 is inserted between the standard interface of system bus 1 and third-party IP module 2.

[0035] Among them, the third-party IP module 2 is developed and licensed by an external supplier and integrated with the functional modules in the SoC.

[0036] Furthermore, the debug and trace control module 3, either as an independent debug controller or integrated into the existing DAP / CoreSight debug architecture, sends control commands to the lower-level debug and trace encapsulation module 4 through the system bus 1, and aggregates the debug and trace data returned by each encapsulation module, thereby building a transparent, unified and non-intrusive on-chip debug and trace mechanism for the third-party IP module 2.

[0037] As a preferred embodiment of the present invention, refer to Figure 2The debugging and tracing encapsulation module 4 includes: an upstream bus interface 41, connected to the system bus 1, for receiving function access requests from the master device 6; a mode and security control unit 42, connected to the debugging and tracing control module 3, for receiving and parsing the debugging control commands to configure the working mode of the debugging and tracing encapsulation module 4, and for controlling access permissions for switching the working mode based on security policies; a protocol adaptation and timing bridging unit 43, connected to the upstream bus interface 41 and the mode and security control unit 42, for performing protocol adaptation and timing adjustment on the function access requests according to the working mode, and generating bus transactions; a transaction monitoring and filtering unit 45, connected to the mode and security control unit 42 and the protocol adaptation and timing bridging unit 43, for monitoring and filtering the bus transactions according to the working mode and preset filtering rules to extract transaction feature information; and a tracing buffer and output buffer. Output unit 46, connected to the transaction monitoring and filtering unit 45 and the debugging and tracing control module 3, is used to store the transaction feature information in the tracing cache module 5 and send it to the debugging and tracing control module 3 according to preset cache trigger conditions; downstream bus interface 47, connected to the protocol adaptation and timing bridging unit 43 and the third-party IP module 2, is used to send the bus transaction to the third-party IP module 2 and receive tracing response data from the third-party IP module 2; wherein, the transaction feature information includes at least one of: address, data, burst length, burst type, transaction identifier, quality of service field, request timestamp, response timestamp, and response type; the filtering rules include at least one of: address range filtering rules, transaction type filtering rules, transaction identifier filtering rules, or quality of service filtering rules; the cache trigger conditions include: detecting an error response or accessing a preset address.

[0038] Specifically, in this embodiment of the invention, to address the problem of unobservable internal state of third-party IP, a debugging and tracing encapsulation module 4 is inserted between the system bus and the third-party IP module 2, thereby enabling fine-grained monitoring of the interface behavior of the third-party IP module 2.

[0039] Specifically, the upstream bus interface 41 (Bus Slave Interface) is the entry point for the debug and trace package module 4. As a standard slave interface, it is responsible for receiving function access requests from the CPU or other master devices 6 on the system bus 1.

[0040] The downstream bus interface 47 (Bus Master Interface) serves as the standard master interface, directly connecting to the third-party IP module 2. It sends the processed bus transactions to the third-party IP module 2 and receives the response data returned by the IP, thus achieving transparent protocol access to the third-party IP module 2.

[0041] The protocol adaptation and timing bridging unit 43 is located at the core of the data path, connecting the upstream bus interface 41 and the downstream bus interface 47. It is responsible for achieving precise matching of upstream and downstream bus protocols and timings, and can select to insert one or more pipeline registers (one or more pipelines) according to the back-end physical design requirements, thereby effectively ensuring timing convergence in complex SoC designs, while ensuring that function access requests are forwarded to the third-party IP module 2 without distortion.

[0042] The transaction monitoring and filtering unit 45 (Monitor & Filter) is connected in parallel to the data path in a non-intrusive manner, and is connected to the protocol adaptation and timing bridging unit 43. Without affecting the main data flow, it monitors the bus transactions in real time, and intelligently filters and extracts key transactions according to the filtering rules configured by the mode and security control unit 42, thereby accurately capturing events of interest to the debugger and avoiding interference from massive amounts of irrelevant data.

[0043] The transaction monitoring and filtering unit 45 samples each bus transaction (including request and response transactions) and extracts key transaction feature information including: protocol attribute fields such as address, data, burst length, burst type, and transaction ID; records the request initiation timestamp and response return timestamp to calculate the complete delay from transaction initiation to completion; and records the response type to distinguish whether the transaction was completed normally or returned an error response.

[0044] The filtering rules are dynamically set by the mode and security control unit 42 through the configuration register, supporting a variety of flexible filtering strategies, including: filtering by address range, i.e. only recording transactions that access the internal register space of a specific IP; filtering by transaction type, i.e. only capturing specific types of operations such as read transactions or write transactions; and filtering by transaction identifier or quality of service field, i.e. only recording transactions from a specific master device 6 or transactions with specific priority attributes.

[0045] By combining the above filtering rules, the transaction monitoring and filtering unit 45 can accurately filter out the bus activities that the debugger is concerned about, significantly reducing the amount of data collected and improving debugging efficiency.

[0046] The Trace Buffer & Export unit 46 is connected to the transaction monitoring and filtering unit 45 and is responsible for temporarily storing the feature information extracted by the monitoring unit in the trace cache module 5. It supports flexible trigger condition settings (such as starting / stopping recording when an error response is detected, or triggering a recording window when a specific address is accessed) and depth control. When the conditions are met or the cache is about to be full, the cached data is efficiently exported to the debug and trace control module 3 through the debug control path for further processing by external debugging tools or on-chip analysis units.

[0047] The trace cache module 5 is an optional on-chip storage resource, which can be implemented using static random access memory (SRAM) or a dedicated trace buffer. When the SoC system integrates the trace cache module 5, the trace buffer and output unit 46 will preferentially store the transaction feature information in it to reduce the bandwidth occupation of the system bus 1. When the SoC system does not integrate the trace cache module 5, the trace buffer and output unit 46 will directly export the transaction feature information to the off-chip debugging tool in real time through the debugging and trace control module 3.

[0048] The Mode & Security Control Unit 42, serving as the configuration core of the debug and trace packaging module 4, connects to the debug and trace control module 3. Internally, it contains configuration registers and a state machine to receive and parse debug control commands, controlling the operating mode of the entire packaging module. More importantly, the Mode & Security Control Unit 42 is deeply integrated with the SoC's global security domain mechanism, ensuring that only units within the secure world or privileged level (such as trusted debug controllers) can modify the operating mode or enable debug functions, thereby preventing unauthorized access and effectively enhancing system security.

[0049] In this way, through the collaborative work of the above units, the debugging and tracking encapsulation module 4 achieves transparent monitoring, precise filtering, efficient caching and reporting, and secure mode control of the interface transactions of the third-party IP module 2 without modifying its internal logic.

[0050] As a preferred embodiment of the present invention, refer to Figure 2The debug and trace encapsulation module 4 further includes a debug injection unit 44, which is connected to the mode and security control unit 42, the debug and trace control module 3, and the downstream bus interface 47. The debug injection unit 44 is used to: receive a debug injection command from the debug and trace control module 3, convert the debug injection command into a debug access transaction, and initiate the debug access transaction to the third-party IP module 2 through the downstream bus interface 47; receive debug response data from the third-party IP module 2 through the downstream bus interface 47, send the debug response data back to the debug and trace control module 3, and prevent the debug response data from returning to the system bus 1 through the upstream bus interface 41.

[0051] Specifically, since the third-party IP module 2 is a black box, its internal register state is usually not directly accessible through the system bus 1. Based on this, in this embodiment of the invention, a mechanism for actively probing the internal state of the IP is provided by adding a debug injection unit 44 (Debug InjectionEngine).

[0052] Specifically, the debug injection unit 44 has independent arbitration and scheduling logic. When the debug and trace control module 3 needs to obtain specific information within the IP (such as reading a private status register), it sends a debug injection command to the mode and security control unit 42 via the system bus 1. The latter forwards the command to the debug injection unit 44. The debug injection unit 44 then generates a standard access transaction (such as a single read or write operation) conforming to the downstream bus protocol and actively sends it to the third-party IP module 2 via the downstream bus interface 47.

[0053] During the injection process, the debug injection unit 44 strictly follows the bus protocol constraints to initiate access and properly handles the arbitration relationship between the debug injection and normal function access, ensuring that for the third-party IP module 2, these debug injection accesses are no different from accesses initiated by ordinary master devices, thus fully complying with the timing assumptions of the third-party IP module 2 and not disrupting its normal function behavior or QoS guarantee.

[0054] The debug response data returned by the third-party IP module 2 is returned to the debug injection unit 44 through the downstream bus interface 47 and directly transmitted back to the debug and trace control module 3. At the same time, it is strictly prevented from returning to the system bus 1 through the upstream bus interface 41, thereby avoiding interference or pollution of the main system function path by debug traffic.

[0055] In this way, by debugging the injection unit 44, it is possible to achieve non-intrusive, protocol-transparent, and securely isolated internal state detection of the third-party IP module 2.

[0056] In a preferred embodiment of the present invention, before sending the debug access transaction, the debug injection unit 44 receives bus status information from the protocol adaptation and timing bridging unit 43 to determine whether the protocol adaptation and timing bridging unit 43 is in an idle state. If it is in an idle state, the debug access transaction is sent; if it is not in an idle state, the debug access transaction is sent when it becomes idle.

[0057] Specifically, since the debugging injection operation cannot interfere with the normal functional access of the third-party IP module 2, in this embodiment of the invention, the debugging injection unit 44 must strictly adhere to the arbitration and time isolation principles with functional transactions.

[0058] Specifically, the debug injection unit 44 integrates arbitration and scheduling logic to ensure that the debug access transactions it initiates do not disrupt or violate the original arbitration rules of the system bus 1.

[0059] In actual operation, the debug injection unit 44 listens to the bus status information of the protocol adaptor and timing bridge unit 43, and prioritizes inserting debug access transactions during the bus idle period; if the bus is busy, it automatically waits until it is idle, thereby minimizing the delay impact on normal function access.

[0060] For interfaces using multi-ID bus protocols such as AXI, the debug injection unit 44 uses a dedicated debug transaction identifier (Debug ID) when generating debug access transactions and strictly limits the number of concurrent outstanding transactions to ensure that its behavior fully complies with the assumptions of the third-party IP module 2 regarding ID quantity limits and transaction order, thus avoiding damage to the original timing constraints or quality of service guarantees of the IP due to debug injection.

[0061] In a preferred embodiment of the present invention, the working modes of the debugging and tracing encapsulation module 4 include a functional transparent mode, a tracing and monitoring mode, and a debugging injection mode; the debugging and tracing encapsulation module 4 switches between the functional transparent mode, the tracing and monitoring mode, and the debugging injection mode according to the debugging control commands received and parsed by the mode and the security control unit 42.

[0062] Specifically, refer to Figure 3In this embodiment of the invention, the three working modes of the debug and trace encapsulation module 4 are switched via control commands such as turning trace on / off and disabling / allowing debug injection. Specifically, the functional bypass mode is the default working mode after system power-on. In this mode, the trace function is off, the debug injection function is disabled, and the debug and trace encapsulation module 4 acts only as a simple bridging path, transparently forwarding function access requests and response data between the system bus 1 and the third-party IP module 2 without interfering with or incurring any additional overhead on system behavior. When the debug and trace control module 3 issues a control command to enable trace, the debug and trace encapsulation module 4 switches from the functional bypass mode to the trace monitoring mode. In this mode, the transaction monitoring and filtering unit 45 is enabled, and begins sampling and recording bus transactions, but the debug injection function remains disabled. In the trace monitoring mode, if the debug and trace control module 3 further issues a command to allow debug injection, the module enters the debug injection mode. In this mode, while the tracing function remains on, the debug injection unit 44 is enabled and can actively initiate debug access transactions to the third-party IP module 2. When returning from the debug injection mode, the tracing and monitoring mode can be switched back by issuing a command to disable debug injection, and the function transparent mode can be directly returned from the tracing and monitoring mode or the debug injection mode by issuing a command to turn off tracing, thereby realizing the observation and control of the third-party IP module 2 at different granularities.

[0063] In a preferred embodiment of the present invention, in the function pass-through mode, the debug and trace encapsulation module 4 disables the transaction monitoring and filtering unit 45, the debug injection unit 44, and the trace buffer and output unit 46. The debug and trace encapsulation module 4 sends the function access request received by the upstream bus interface 41 to the downstream bus interface 47 through the protocol adaptation and timing bridging unit 43, and sends the trace response data received by the downstream bus interface 47 to the upstream bus interface 41.

[0064] Specifically, in this embodiment of the invention, the functionally transparent mode is the default working mode after the system is powered on, which is completely transparent to the functional logic of the third-party IP module 2.

[0065] Specifically, in this transparent function mode, the debug and trace encapsulation module 4 performs the following operations: it receives a function access request from the system bus 1 through the upstream bus interface 41; then, after the function access request is processed by the protocol adaptation and timing bridging unit 43 for protocol matching and fixed pipeline delay (e.g., introducing only a predictable delay of 1 clock cycle), it is directly sent to the downstream bus interface 47, and forwarded by the downstream bus interface 47 to the third-party IP module 2; the response data returned by the third-party IP module 2 is received by the downstream bus interface 47 through the same path, and then returned to the upstream bus interface 41 through the protocol adaptation and timing bridging unit 43, and finally delivered to the system bus 1.

[0066] Meanwhile, throughout the entire forwarding process, the debugging and tracing encapsulation module 4 does not change the transaction content or add any additional transactions. It only introduces fixed and predictable pipeline delays through the protocol adaptation and timing bridging unit 43 to ensure that the atomicity and integrity of the transactions are not affected.

[0067] In addition, the transaction monitoring and filtering unit 45 is completely turned off, or used only for very lightweight statistics (such as simple counting), without performing any deep tracking sampling; the tracking buffer and output unit 46 and the debug injection unit 44 do not participate in the data path, and their clocks can be gated to reduce power consumption.

[0068] In this way, through the above mechanism, in the functional transparency mode, the environment perceived by the third-party IP module 2 in terms of protocol and timing is almost completely equivalent to that directly connected to the system bus 1, realizing complete transparency of the system to the functional logic, and ensuring zero interference and zero additional overhead in system performance when no debugging is performed.

[0069] In a preferred embodiment of the present invention, in the tracking and monitoring mode, the debugging and tracking encapsulation module 4 enables the transaction monitoring and filtering unit 45 and the tracking buffer and output unit 46 based on the data forwarding path in the functionally transparent mode.

[0070] Specifically, in this embodiment of the invention, the tracking and monitoring mode is mainly used to observe the behavior of the third-party IP module 2 at the system bus level without interfering with its normal function, without requiring any modifications to the internal IP.

[0071] Specifically, in this tracking and monitoring mode, the debugging and tracking encapsulation module 4 performs the following operations:

[0072] First, the upstream and downstream data paths are exactly the same as in the transparent function mode: the function access request received by the upstream bus interface 41 is processed by the protocol adaptation and timing bridging unit 43 and then forwarded to the downstream bus interface 47 to be sent to the third-party IP module 2. The response data is returned via the same path. This mechanism ensures that the third-party IP module 2 can still work normally in the tracking and monitoring mode and is completely unaware of the existence of the monitoring behavior.

[0073] Meanwhile, the transaction monitoring and filtering unit 45 samples each bus transaction in real time in a non-intrusive manner and extracts key transaction feature information based on preset filtering rules, including protocol attribute fields such as address, data, burst length, burst type, and transaction identifier; it also records the request initiation timestamp and response return timestamp to calculate the complete delay from transaction issuance to completion; in addition, it includes the response type to distinguish whether the transaction was completed normally or returned an error response.

[0074] Then, the tracing buffer and triggering mechanism are enabled. Specifically, transaction records selected and sampled by the transaction monitoring and filtering unit 45 are sent to the tracing buffer and output unit 46 and written to the on-chip tracing cache module 5 (which can be implemented using SRAM or FIFO). This unit supports flexible triggering condition settings, such as starting or stopping recording when an error response is detected; triggering the recording window when a preset specific address is accessed. The debug and tracing control module 3 can read the contents of the tracing cache module 5 as needed via the system bus 1 for subsequent analysis of the behavioral characteristics and performance bottlenecks of the third-party IP module 2.

[0075] Reference Figure 4 Taking a typical AXI protocol scenario as an example, where the debug and trace encapsulation module 4 performs bus tracing on the third-party IP module 2, the above tracing and monitoring process is explained in detail: When the master device 6 initiates a write request to the third-party IP module 2 through the system bus 1, the write request is forwarded to the third-party IP module 2 by the downstream bus interface 47 via the upstream bus interface 41 and the protocol adaptation and timing bridging unit 43 of the debug and trace encapsulation module 4; subsequently, the third-party IP module 2 returns a write response, which is returned to the upstream bus interface 41 via the downstream bus interface 47 and the protocol adaptation and timing bridging unit 43, and finally delivered to the master device 6; at the same time, the transaction monitoring and filtering unit 45 captures the write request transaction and the write response transaction in parallel, records its address, data, burst length, transaction identifier and other key information, and stores it in the tracing cache module 5, thereby completing the tracing record of a complete write transaction.

[0076] Similarly, when the master device 6 initiates a read request, the read request is forwarded to the third-party IP module 2 via the same path. The third-party IP module 2 returns read response data and returns it to the master device 6 via the upstream bus interface 41. At the same time, the transaction monitoring and filtering unit 45 captures the read request transaction and the read response data transaction respectively, records the complete address, data, burst length, transaction identifier and other key information, and stores them in the tracking cache module 5, thereby completing the tracking and recording of a complete read transaction.

[0077] In a preferred embodiment of the present invention, in the debug injection mode, the debug and trace encapsulation module 4 enables the debug injection unit 44 based on the data forwarding path and monitoring mechanism in the trace monitoring mode.

[0078] Specifically, in this embodiment of the invention, the debug injection mode provides the third-party IP module 2 with a non-intrusive, protocol-consistent, and controllable register-level active access capability while maintaining the tracking and monitoring capability, without requiring the addition of an extra backdoor interface inside the IP.

[0079] Specifically, refer to Figure 5 In this debug injection mode, the debug and trace encapsulation module 4 performs the following operations:

[0080] First, the debug and trace control module 3 issues an additional access request. Specifically, the debug and trace control module 3 issues a debug injection command to the mode and security control unit 42 in the debug and trace encapsulation module 4 via a dedicated control bus or register interface.

[0081] For example: READ addr=IP_BASE+0x100, WRITE addr=....

[0082] Next, after the mode and security control unit 42 checks that the current working mode and operation permissions are correct, it forwards the command to the debug injection unit 44. The debug injection unit 44 converts these instructions into legal transactions that conform to the downstream bus protocol and actively initiates them to the third-party IP module 2 through the downstream bus interface 47.

[0083] Meanwhile, the debug injection unit 44 strictly follows the arbitration and time isolation principle of functional transactions. Before sending debug access transactions to the third-party IP module 2, it receives bus status information from the protocol adaptation and timing bridging unit 43 to determine whether it is currently in an idle state. If the bus is busy, it will automatically wait until the idle period before inserting the debug access transaction, or arbitrate with a lower priority to ensure that the original arbitration rules of the system bus 1 are not disrupted or violated.

[0084] In particular, for interfaces using multi-ID bus protocols such as AXI, a dedicated debug transaction identifier (Debug ID) can be used, and the number of concurrent outstanding transactions can be strictly limited to ensure that its behavior fully complies with the assumptions of the third-party IP module 2 regarding ID quantity limits and transaction order, thus avoiding the destruction of the original timing constraints or quality of service guarantees of the IP due to debug injection.

[0085] Then, when the read transaction initiated by the debug injection unit 44 reaches the third-party IP module 2, the read response data returned by the third-party IP module 2 is received by the downstream bus interface 47. The debug injection unit 44 intercepts the response data and sends it back directly to the debug and trace control module 3. At the same time, it prevents the response data from returning to the system bus 1 through the upstream bus interface 41, thereby avoiding interference of debug traffic to the functional path of the master device 6.

[0086] Finally, the transaction monitoring and filtering unit 45 continues to sample and record the normal functional transactions and the debugging transactions initiated by the debugging injection unit 44, and the relevant information is stored in the tracking cache module 5 through the tracking buffer and output unit 46 to provide complete observation data for subsequent analysis.

[0087] In addition, the mode and security control unit 42 has a built-in hardware address filtering mechanism that can strictly limit the address range of debug injection access, preventing accidental impact on sensitive registers or security-related areas in the third-party IP module 2.

[0088] In particular, the enabling of debug injection mode, user authentication, and the range of allowed addresses are all managed uniformly by security control logic, making them available only in experimental mode or secure debug mode. In mass production environments, they can be partially or completely disabled as needed, thereby effectively preventing security risks.

[0089] In a preferred embodiment of the present invention, the debugging and tracking control module 3 supports multiple standard bus protocols, including at least one of AXI4, AXI4-Lite, AHB, and APB.

[0090] Specifically, in this embodiment of the invention, the debugging and tracing encapsulation module 4 achieves comprehensive support for a variety of common bus protocols through parameterized design.

[0091] Specifically, for the AXI4 / AXI4-Lite protocol, it has independent read address channel, write address channel, read data channel, write data channel, and write response channel. The protocol adaptation and timing bridging unit 43 needs to handle the handshake and synchronization relationship between each channel separately. For the AHB protocol, it adopts a single-channel bus architecture and includes key control signals such as HTRANS transfer type indicator and HREADY transfer completion indicator. For the APB protocol, it is a simple register access bus with simplified control signals such as PSEL, PENABLE, and PREADY.

[0092] For each of the above protocols, the protocol adaptation and timing bridging unit 43 implements the following functions: precise mapping of signals from the upstream bus interface 41 to the downstream bus interface 47; necessary handshake timing adjustments according to the protocol handshake specifications; support for configurable pipeline register insertion (one-step or multi-step pipeline) to ensure timing convergence in complex SoC designs; and unified abstraction of bus signals of different protocols into a standardized "transaction record entry" format, that is, unified encapsulation of information such as address, data, control attributes, and timestamps, which facilitates subsequent processing by the transaction monitoring and filtering unit 45, thereby achieving protocol-independent tracing and debugging capabilities.

[0093] As a preferred embodiment of the present invention, when multiple third-party IP modules 2 are integrated into a large SoC, this technical solution can combine electronic design automation script tools to realize the automatic packaging process of debugging and tracking packaging modules 4.

[0094] Specifically, in this embodiment of the invention, the following automated encapsulation process can cover a large number of third-party IP modules 2 with the debugging and tracing capabilities of this technical solution at a relatively low cost, without having to manually modify the connections or change the internal logic of each IP module: First, by scanning the top-level register transfer level code or netlist with a script, all third-party IP instances that conform to specific interface specifications are automatically identified, such as all modules with standard AXI slave interface, AHB slave interface, or APB slave interface; then, an encapsulation insertion operation is performed on each identified target third-party IP module 2: disconnecting its original interface directly connected to the system bus 1; inserting an instance of a debugging and tracing encapsulation module 4 between it and the system bus 1; Reconnect the system bus signal originally connected to the third-party IP module 2 to the upstream bus interface 41 of the debug and trace package module 4; connect the downstream bus interface 47 of the debug and trace package module 4 to the bus interface of the third-party IP module 2; then, according to the interface type and debugging requirements of each third-party IP module 2, perform parameterized configuration for each debug and trace package module 4 instance, including protocol type (such as AXI4, AHB or APB), monitoring address range, transaction filtering rules, default working mode of debug and trace functions (such as functional transparent mode), etc.; finally, re-execute the synthesis and placement and routing process to ensure the timing convergence of the design after inserting the package module and verify the correctness of the function.

[0095] Through the above-described automated packaging process, this technical solution can efficiently and cost-effectively inject unified debugging and tracing capabilities into a large number of third-party IP modules in large-scale SoC designs, without having to manually modify every interface connection or delve into the internal implementation details of the IP.

[0096] The above system can be further illustrated through the following three specific embodiments to demonstrate the application effect of the present invention in actual SoC integration and debugging scenarios:

[0097] Example 1: Bandwidth / Latency Analysis of Third-Party Storage Controller IP

[0098] In the tracking and monitoring mode, all bus access transactions within the address range of the IP are recorded, and the following statistics are compiled: average latency, maximum latency, throughput bandwidth, and error response status. By analyzing the tracking data, performance bottlenecks and system integration issues can be assessed without modifying the IP.

[0099] Example 2: Controlled monitoring of third-party encrypted IP in a secure SoC

[0100] The mode control and security control logic of the debugging and tracing encapsulation module 4 are bound together. For example, the tracing and monitoring mode is only allowed to be enabled under the security world firmware authorization. Statistics and anomaly detection are performed on bus transactions that access the encrypted IP, such as frequency, address range, error rate, etc. The debug injection function is strictly restricted, and access to register areas involving keys is not allowed.

[0101] As can be seen from the above embodiment 2, the present invention provides a unified, scalable, secure and controllable control and tracking capability for third-party IP without modifying its internal structure or breaking its interface protocol, which is beneficial for SoC-level debugging, verification and product iteration.

[0102] Example 3: Register-level debugging of third-party peripheral IP

[0103] During the laboratory debugging phase, the debug injection mode is enabled; read / write commands are sent to the debug injection unit 44 through the debug and trace control module 3 to access the IP registers; access is inserted when the IP function bus is idle to confirm whether the register contents meet expectations; there is no need to open the dedicated JTAG port provided by the IP Vendor, nor is it necessary to reserve a dedicated debug register inside the IP.

[0104] In summary, this invention proposes an on-chip debugging and tracing encapsulation system for third-party IP. By inserting a dedicated debugging and tracing encapsulation module between the system bus and the third-party IP module, a multi-mode working mechanism including a functionally transparent mode, a tracing and monitoring mode, and a debug injection mode is constructed. The system utilizes a protocol adaptation and timing bridging unit to ensure transparent compatibility and timing convergence with the third-party IP interface protocol. It achieves non-intrusive bus transaction sampling, filtering, and recording through a transaction monitoring and filtering unit and a tracing buffer and output unit. With the help of a debug injection unit, it enables active probing access to the internal registers of the IP under strict arbitration and time isolation principles. And through a mode and security control unit, it integrates a security domain management mechanism to uniformly manage debugging permissions and access scope. Thus, without modifying the internal logic of the third-party IP or relying on its private debugging interface, it achieves observability, probing, and controllability of the black-box IP's operating state. This solves the problems of lack of visibility, fragmented interface standards, functional interference, and security risks caused by the black-box nature of IP in traditional debugging solutions. It provides a unified, transparent, secure, and scalable on-chip debugging and tracing solution for SoC integration of third-party IP.

[0105] Compared with the prior art, the present invention has the following significant effects:

[0106] This invention significantly improves observability and debuggability without modifying the internal logic of third-party IP. By inserting a universal debug and trace package module outside the standard bus interface of third-party IP, the SoC integrator can precisely observe the IP's access behavior, data content, response latency, and error status at the bus level without obtaining the IP's internal RTL or modification permissions. Compared to traditional solutions that can only rely on the limited debug interfaces provided by the IP vendor or pure software logs, this invention can obtain richer runtime information in the IP's black-box state.

[0107] The functional path is transparent, minimizing the impact on the timing and protocol of the main function. In functional mode, the encapsulated module in this invention only acts as a timing bridge and protocol forwarding unit, presenting a standard bus interface to both upstream and downstream without inserting any additional functional transactions. Through reasonable pipeline design, the delay introduced by the module is strictly limited to 1-2 predictable clock cycles, facilitating timing convergence and system analysis. Compared to solutions that hard-insert debugging logic within the IP or insert complex analysis modules into the bus, this invention causes less interference to the main functional path, thus helping to ensure system performance and stability.

[0108] Establishing a unified debugging and tracing architecture significantly reduces the complexity and development cost of SoC debugging. This invention unifies the debugging capabilities of different IPs under a single architecture through a universal encapsulation module: for upper-layer debugging tools, they only need to face a unified control interface, without needing to learn and adapt to the private debugging protocols of each IP; in a typical SoC containing more than ten third-party IPs, each IP originally needed to have a separate debugging port and different scripts configured. After introducing this invention, they can be centrally managed through a unified debugging control module, which is expected to reduce the workload of debugging script development and maintenance by more than 30%, and correspondingly shorten the startup cycle of the first tape-out.

[0109] Enhances on-site problem localization and mass production quality control capabilities. By recording the bus access trajectory and performance statistics of third-party IPs through a tracking and monitoring mode, the source of problems can be quickly located in the laboratory and mass production field. Examples include sudden increases in response latency under specific loads, abnormal error responses in address ranges, and bandwidth bottlenecks caused by abnormal master device access patterns. This invention provides a low-cost "on-chip black-box IP behavior logger" without relying on internal logic probes, which helps improve problem analysis efficiency, reduce rework and after-sales maintenance costs, and has significant engineering and economic benefits.

[0110] This invention provides controlled debug injection capabilities, significantly improving the accuracy of problem reproduction and diagnosis. In debug injection mode, the invention allows controlled register read / write operations to third-party IPs via a wrapper module. Compared to relying entirely on upper-layer software or external JTAG tools, the wrapper module can insert debug transactions during bus idle periods or at low priority, avoiding interference with normal business operations. Simultaneously, debug access can be combined with trace data to achieve a closed-loop diagnosis of "observation first, then active probing." For example, in scenarios involving abnormal storage controller IPs, internal status registers can be directly verified through injected read operations without modifying IP logic or exposing vendor-specific debug ports.

[0111] This invention enables secure and controllable debugging capabilities, facilitating compliance with security and compliance requirements. It integrates the mode control and access permissions of the packaged module into the unified management of the SoC security domain. The debug mode and accessible address range are configured by secure firmware or security control logic, preventing ordinary application software from directly enabling debugging functionality. For sensitive address ranges (such as key registers and authentication-related registers), hardware address filtering can prevent debug injection access. Compared to directly exposing the dedicated debug interface of third-party IP through the package, the debug channel of this invention is more easily integrated into the overall security architecture and authentication process, thus improving the overall security level of the device.

[0112] It possesses excellent scalability and product line reuse value. The packaging module of this invention adopts a parametric design, which can be configured to support different bus protocols (AXI / AHB / APB, etc.) and different debug depths (such as whether debug injection is supported, trace buffer size, etc.) according to specific projects. Within multiple SoC projects within the same company, this module can be reused as a general IP: when integrating new third-party IP, only the package instance needs to be inserted at its bus interface via an automatic script; new requirements for debugging functions are mainly achieved through configuration and toolchain upgrades, without modifying the internal IP or the top-level structure of the SoC. In the long term, it helps to form a unified "third-party IP debugging infrastructure," reducing the risk and cost of introducing new projects.

[0113] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. An on-chip debugging and tracing packaging system for third-party IP, characterized in that, include: The system bus (1) connects to the master device (6) of the on-chip system and is used to transmit function access request and response data; A third-party IP module (2) is used to perform on-chip operations; The debugging and tracking control module (3) is connected to the system bus (1) and is used to issue debugging control commands through the system bus (1) and collect debugging and tracking data. The debugging and tracing encapsulation module (4) is connected between the system bus (1) and the third-party IP module (2) and is used to forward the access request and response data between the system bus (1) and the third-party IP module (2), and to monitor, record or debug the access request and response data. The debugging and tracing encapsulation module (4) includes: The upstream bus interface (41) is connected to the system bus (1) and is used to receive function access requests from the master device (6); The mode and security control unit (42) is connected to the debugging and tracing control module (3) and is used to receive and parse the debugging control command to configure the working mode of the debugging and tracing encapsulation module (4) and to perform permission control on the switching of the working mode based on the security policy. Protocol adaptation and timing bridging unit (43) is connected to the upstream bus interface (41) and the mode and security control unit (42) for adapting the protocol and adjusting the timing of the function access request according to the working mode, and generating bus transactions; The transaction monitoring and filtering unit (45) is connected to the mode and security control unit (42) and the protocol adaptation and timing bridging unit (43), and is used to monitor and filter the bus transactions according to the working mode and preset filtering rules in order to extract transaction feature information. The tracking buffer and output unit (46) is connected to the transaction monitoring and filtering unit (45) and the debugging and tracking control module (3). It is used to store the transaction feature information in the tracking cache module (5) and send it to the debugging and tracking control module (3) according to the preset cache triggering conditions. The downstream bus interface (47) connects the protocol adaptation and timing bridging unit (43) and the third-party IP module (2), and is used to send the bus transactions to the third-party IP module (2) and receive tracking response data from the third-party IP module (2).

2. The on-chip debugging and tracing packaging system for third-party IP according to claim 1, characterized in that, The debug and trace encapsulation module (4) further includes a debug injection unit (44), which connects the mode and security control unit (42), the debug and trace control module (3), and the downstream bus interface (47). The debug injection unit (44) is used for: Receive the debug injection command from the debug and trace control module (3), convert the debug injection command into a debug access transaction, and initiate the debug access transaction to the third-party IP module (2) through the downstream bus interface (47). The downstream bus interface (47) receives debug response data from the third-party IP module (2), transmits the debug response data back to the debug and trace control module (3), and prevents the debug response data from returning to the system bus (1) through the upstream bus interface (41).

3. The on-chip debugging and tracing packaging system for third-party IP according to claim 2, characterized in that, Before sending the debug access transaction, the debug injection unit (44) receives bus status information from the protocol adaptation and timing bridging unit (43) to determine whether the protocol adaptation and timing bridging unit (43) is in an idle state. If it is in an idle state, the debug access transaction is sent. If it is not in an idle state, the debug access transaction is sent when it is in an idle state.

4. The on-chip debugging and tracing packaging system for third-party IP according to claim 2, characterized in that, The working modes of the debugging and tracing encapsulation module (4) include functional transparency mode, tracing and monitoring mode and debugging injection mode; The debugging and tracking encapsulation module (4) switches between the function transparency mode, the tracking and monitoring mode and the debugging injection mode based on the debugging control command received and parsed by the mode and security control unit (42).

5. The on-chip debugging and tracing packaging system for third-party IP according to claim 4, characterized in that, In the functionally transparent mode, the debug and trace encapsulation module (4) disables the transaction monitoring and filtering unit (45), the debug injection unit (44), and the trace buffer and output unit (46). The debugging and tracing encapsulation module (4) sends the function access request received by the upstream bus interface (41) to the downstream bus interface (47) through the protocol adaptation and timing bridging unit (43), and sends the tracing response data received by the downstream bus interface (47) to the upstream bus interface (41).

6. The on-chip debugging and tracing packaging system for third-party IP according to claim 4, characterized in that, In the tracking and monitoring mode, the debugging and tracking encapsulation module (4) enables the transaction monitoring and filtering unit (45) and the tracking buffer and output unit (46) based on the data forwarding path in the functional transparency mode.

7. The on-chip debugging and tracing packaging system for third-party IP according to claim 4, characterized in that, In the debug injection mode, the debug and trace encapsulation module (4) enables the debug injection unit (44) based on the data forwarding path and monitoring mechanism in the trace monitoring mode.

8. The on-chip debugging and tracing packaging system for third-party IP according to claim 1, characterized in that, The transaction characteristic information includes at least one of the following: address, data, burst length, burst type, transaction identifier, quality of service field, request timestamp, response timestamp, and response type; The filtering rules include at least one of the following: address range filtering rules, transaction type filtering rules, transaction identifier filtering rules, or quality of service filtering rules; The cache triggering conditions include: detecting an error response or accessing a preset address.

9. The on-chip debugging and tracing packaging system for third-party IP according to claim 1, characterized in that, The debugging and tracking control module (3) supports multiple standard bus protocols, including at least one of AXI4, AXI4-Lite, AHB and APB.

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