Multi-channel microvolt signal collector

Abstract

Compared with the prior art, the multichannel microvolt signal collector is additionally provided with two 400KHz PWM (Pulse Width Modulation) paths and four 2MSPS 10bit DAC (Digital-to-Analog Converter) paths through the power panel, and can be externally connected with an Mos bridge to drive two motors; double 6D IMU complementary error correction is adopted, so that higher-precision 6D signal tracking is realized; through BTB and FPC redundancy design, multi-board combined high-throughput data acquisition can be realized. And the FPGA is used for realizing 480Mbps USB2.0 (Universal Serial Bus 2.0) communication through the ULPI interface. Under the condition of no group connection, video signals such as an SSVEP flicker stimulation interface can be output through the expansion interface, and meanwhile, the Bluetooth earphone can be expanded to transmit audios. And a 16 Mb Flash is sealed by the WIL5025, and a 4 Mb Flash is sealed by the ESP32-C3FH4, so that a remote OTA function can be realized. In an application scene, the LHA7668 can be configured with a constant current source to excite an external resistive resistor.

Description

Technical Field

[0001] This invention belongs to the field of signal detection, specifically relating to a multi-channel microvolt signal acquisition device. Background Technology

[0002] Multichannel microvolt-level signal acquisition technology is widely used in bioelectrical signal monitoring (such as EEG, EMG, ECG) and structural health monitoring (SHM, such as acoustic emission and strain). With the increase in the number of channels, achieving a high-precision (microvolt-level resolution), low-noise, low-crosstalk, and high-stability acquisition system faces significant challenges. The repetitive cost of high-performance analog front-end circuits (low-noise amplifiers, precision filters, high-resolution ADCs) is high; the complexity of crosstalk suppression and signal integrity maintenance between multiple channels increases dramatically; and ensuring long-term system stability (such as temperature drift and gain consistency) becomes more difficult. Therefore, effectively reducing the cost of high-channel-count microvolt-level signal acquisition systems while maintaining or improving system performance and reliability is the core challenge currently facing this technology. Summary of the Invention

[0003] The signal acquisition board of this invention (e.g.) Figure 1 , 2 The overall structure of ) (such as Figure 8 It uses the WIL5025 FPGA chip as the main core, connects to a K4B4G1646E-BCNB DDR3 chip to provide extended running memory, and connects to 8 LHA7668 ADC chips and 2 LSM6DSOWTR IMU chips to provide core microvolt signal acquisition, gyroscope and accelerometer signal acquisition. At the same time, it can acquire signals through the FPC interface and can connect to the FPC electrode / ribbon cable to input microvolt signals. The digital power supply area is powered by 3.3V, 2.5V, 1.5V, and 1.2V voltages provided by BCT2057ELT33-TR, BCT2057ELT25-TR, BCT2057ELT15-TR, and BCT2057ELT12-TR. An LM27762DSSR outputs ±2.7V to provide analog voltages for the AVDD and AVSS pins of the LHA7668. Simultaneously, an ±2.5V analog reference voltage is provided by the LM27762DSSR and REF3450IDBVR. After communication with the FPGA via QSPI through the ESP32-C3FH4, data is wirelessly transmitted via Wi-Fi. Communication with the FPGA via the CH132 using the ULPI interface and with the ESP32-C3 via the CH340X using the UART interface enables data communication between the FPGA and the ESP32-C3 via USB 2.0 (480Mbps), as well as data download and USB 2.0 (2Mbps) data communication.

[0004] Power board (e.g.) Figure 5, 6 )The interface of 40PIN BTB realizes the communication with the signal acquisition board and the power supply, and outputs 2-way PWM up to 400KHz (0.1% resolution). The TP5400 realizes the charging and discharging of 1000mA 503450 battery, and realizes the voltage conversion of 3.7V battery to 5V. The MAX5741EUB+ realizes 4-way 2MSPS 10bit DAC. The XR6800B and the switch realize the power supply of the battery and the USB as a whole.

[0005] On the expansion interface, the signal acquisition board provides 2-way 10PIN FPC interface, realizes the connection of multiple multi-channel microvolt signal collectors. At the same time, the signal acquisition board provides SD (SD card and FPGA connection) slot interface, inserts 64G flash TF card, provides data storage and storage of other extended files. The 24PIN BTB interface is connected with the 1.83-inch touch screen, provides data display and touch, and at the same time, when the touch screen is not used, the FPGA pin of the interface is multiplexed with 2 30PIN BTB pin, provides redundancy function.

[0006] On the interface test (such as Figure 3 、 4 ), the application designs a PI material electrode for matching the 32PIN FP interface. At the same time, a FPC and wire-to-board slot to 2.54mm TTL PCB is designed, which is convenient for signal test.

[0007] In the process of signal acquisition (such as Figures 9 to 14 ), the ADC is provided with 64-way first-order passive differential anti-aliasing filter, wherein the differential resistance of the filter is 1kn, the differential capacitance is 2.2nf, and the common mode capacitance is 220pf. When the input signal is a differential signal, the-3dB frequency point is about 34KHz, and the-4dB frequency point is about 40KHz. When the input signal is a single-ended signal, the suppression at 40KHz is only 0.3db, which cannot meet the suppression of high-frequency signals. At this time, 1D Filter in FPGA is needed for filtering processing.

[0008] On the host computer software (such as Figure 14 、 15 ), the built-in SSVEP paradigm flicker stimulation interface is realized through WIFI and USB communication.

[0009] On the shell design (such as Figure 16 ), the application inserts 8 2mm*5mm and 2 3mm*5mm cylindrical magnets through the top shell and the bottom shell respectively, which is convenient for the connection of multiple multi-channel microvolt signal collectors. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure (1) is the front side of the signal acquisition PCB, in which the IC contains the main core device of the multi-channel micro-voltage signal acquisition device.

[0011] Figure (2) is the back side of the signal acquisition PCB, which is mainly used to connect with the power PCB through the BTB interface.

[0012] Figure (3) is the FPC (PI material) electrode, which is mainly divided into four electrodes, each containing 32 test points, and can be directly connected with the signal acquisition PCB through the FPC.

[0013] Figure (4) is a signal adapter board, which mainly converts the interface of the signal acquisition PCB and the power PCB to a 2.54mm TTL interface, facilitating signal testing.

[0014] Figure (5) is the front side of the power PCB, which mainly charges the lithium battery and provides four-way DAC signals.

[0015] Figure (6) is the back side of the power PCB, which is mainly connected with the signal acquisition PCB through the BTB interface and provides power for the signal acquisition PCB.

[0016] Figure (7) is the main acquisition process, which includes channel configuration, module configuration, conversion process and end process.

[0017] Figure (8) is the main structure framework, which describes the devices and functions used in the entire multi-channel micro-voltage signal acquisition device.

[0018] Figure (9) is the first-order anti-aliasing filter ltspice simulation circuit for differential input, which is the front-end passive filter circuit of the ADC of the signal acquisition PCB.

[0019] Figure (10) is the -3dB Bode plot simulation result of the first-order anti-aliasing filter ltspice for differential input.

[0020] Figure (11) is the -4dB Bode plot simulation result of the first-order anti-aliasing filter ltspice for differential input.

[0021] Figure (12) is the first-order anti-aliasing filter ltspice simulation circuit for single-ended input, which is the front-end passive filter circuit of the ADC of the signal acquisition PCB.

[0022] Figure (13) is the simulation result of the first-order anti-aliasing filter ltspice at 40KHz for single-ended input. At this time, the single-ended signal cannot be effectively filtered, and needs to be filtered in the subsequent software, such as calling the 1D filter IP core in the FPGA.

[0023] Figure (14) is the flashing stimulation interface built in the host computer software of the multi-channel microvolt signal collector, which mainly assists the multi-channel microvolt signal collector to complete the physiological stimulation paradigm.

[0024] Figure (15) is the main interface built in the host computer software of the multi-channel microvolt signal collector, which mainly contains the waveform display of the collected signal.

[0025] Figure (16) is the shell structure of the multi-channel microvolt signal collector. DETAILED DESCRIPTION

[0026] After the multi-channel microvolt signal collector is powered on, the basic ADC, FLASH, DAC, WIFI, SD, LCD, IMU, etc. register address read-write are completed (such as Figure 7 ), first, whether it is a multi-block multi-channel microvolt signal collector connected for collection is configured through the host computer software, and the WIRE (wired), WIFI, SD, BLE, LCD, etc. data communication, data storage, data acquisition, etc. are configured. Then, the conversion speed, conversion accuracy, built-in filter, etc. of the ADC and IMU are configured. Next, the data collection is started, and the collection process can be paused, modified, and configured. Finally, after the conversion is completed, the WIRE (wired), WIFI, SD, BLE, LCD, ADC, IMU data communication is disconnected, uploaded, data storage is saved, and low-power consumption configuration is configured.

[0027] Multi-channel micro-volt signal collector increases 2-way PWM to 400KHz (0.1% resolution) and 4-way 2MSPS 10bit DAC through power board, can be externally connected to Mos bridge to drive brushless motor, drive two, adopt two 6D IMU units to complement error correction, realize higher precision 6D signal tracking, at the same time through BTB interface, FPC interface, there is redundant design, can realize multi-board group connection high flux micro-volt signal data acquisition. FPGA realizes 480Mbps USB2.0 data communication through ULPI interface, data load fully meets the data communication of 8 copies of the same type product group connection, at the same time under the condition of not group connection, the remaining communication data, can pass through the expansion interface, output video signal, such as SSVEP flicker stimulation interface signal. Communication interface adopts WIFI communication, redundant Bluetooth communication, can expand the connection Bluetooth earphone, transmits audio file. At the same time, because WIL5025 encapsulates 16Mb Flash, ESP32-C3FH4 encapsulates 4Mb Flash, can realize remote OTA function through the address planning of Flash. In application scene, LHA7668 and AD7124 are PINtoPIN domestic chip replacement, ADC contains two configurable constant current sources, which can be set to 50uA, 100uA, 250uA, 500uA, 750uA, or 1mA through programming. These current sources can be used to excite external resistive resistors.

Claims

1. A multi-channel microvolt signal acquisition system, characterized in that, include: The signal acquisition board is equipped with an FPGA main control chip (WIL5025), DDR3 memory (K4B4G1646E-BCNB), an 8-channel ADC chip (LHA7668) and a 2-channel IMU chip (ISM6DSOWTR), and receives microvolt-level signals through the FPC interface. The power supply unit includes multiple voltage conversion circuits (±2.7V / ±2.5V / 1.5V / 1.2V) and a constant current source module to provide precise power supply for the analog front end; The data transmission unit integrates WIFI, USB 2.0 (480Mbps), and UART interfaces, supporting multi-device networking and data distribution; The anti-aliasing filter circuit includes 64 first-order passive differential filters (differential resistors 1kΩ, capacitors 2.2nF / 220pF), which need to be combined with FPGA digital filtering algorithms. The battery management module, including the TP5400 battery management unit, supports charging and discharging of 503450 lithium batteries and 3.7V→5V boost conversion. The output unit includes a 4-channel 2MSPS 10-bit DAC (Max5471) and a 2-channel PWM up to 400KHz (0.1% resolution) housing structure. It can achieve multi-board cascading through a magnetic BTB / FPC interface and integrates a 1.83-inch touch screen and SD card slot.

2. The system according to claim 1, characterized in that: The ADC chip (LHA7668) is equipped with dual constant current sources (adjustable from 50μA to 1mA) for resistive sensor excitation. The two IMU chips employ a 6-axis complementary error correction algorithm, which corrects each other's errors while separately measuring angular velocity and acceleration signals, thereby achieving high-precision motion tracking. The output unit supports DAC input as a square wave signal and can be expanded to include brushless motor drive input.

3. The system according to claim 1, characterized in that: The FPGA chip achieves 480Mbps high-speed USB communication via the ULPI interface and reserves a video signal output channel. The host computer software integrates the SSVEP paradigm stimulation interface and supports WIFI / USB dual-mode data interaction. The system supports OTA firmware upgrades and enables remote program updates through Flash address planning.

4. A multi-channel microvolt signal acquisition method, characterized in that, Including the following Step a) Acquire microvolt-level signals through differential / single-ended input channels, and suppress high-frequency noise through first-order passive filtering; Step b) Utilize FPGA for digital filtering and clock synchronization to achieve 120-channel single-ended / 64-channel differential signal multiplexing and acquisition; Step c) Data transmission is achieved through multi-protocol interfaces (WIFI / USB / UART), supporting multi-device networking and real-time monitoring; Step d) Implement multi-board cascaded communication via FPC / BTB to achieve high-throughput data acquisition.

5. The method according to claim 4, characterized in that: In step a), the single-ended signal has a rejection ratio of 0.3dB at a frequency of 40kHz, which requires FPGA digital filtering compensation. In step c), the WIFI communication supports redundant Bluetooth connections and can expand audio transmission functionality; In step d), the modules implement redundant power and signal design through the FPC / BTB interface, while also supporting hot-swapping operation.

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