Simulator pre-simulation method for hardware simulation scene

Abstract

The invention discloses a simulator pre-simulation method for a hardware simulation scene, and relates to the technical field of simulator pre-simulation, and the method comprises the following steps: S1, constructing a performance mapping relation model for a simulator; s2, on the basis of the performance mapping relation model, analyzing the multi-thread parallel issuing performance, and generating multi-thread prediction performance; and S3, receiving an original instruction stream, and performing heterogeneous scene optimization in combination with multi-thread prediction performance to complete pre-simulation. According to the method, rapid and accurate simulator estimation facing a hardware simulation scene is realized, the problems of long hardware simulation time, difficulty in resource planning, long performance optimization period and the like are effectively solved, compared with a traditional method, the working efficiency is greatly improved, the method has good expansibility, and the method is not only suitable for mapping between NEMU and lego-sim, but also suitable for mapping between NEMU and lego-sim. And the method can be expanded to other simulator platforms and has a wide application prospect.

Description

Technical Field

[0001] This invention relates to the field of simulator pre-simulation technology, and specifically to a simulator pre-simulation method for hardware simulation scenarios. Background Technology

[0002] Currently, the simulation of benchmark programs in the field of computer architecture research mainly relies on professional simulation tools. Typical technical solutions include the following three categories: 1. gem5 simulator: As a typical representative of open-source computer system simulation platforms, gem5's technical architecture incorporates multi-layered innovations: In terms of instruction set compatibility, it adopts a modular instruction decoder design to achieve accurate periodic simulation of multiple architectures such as x86, ARM, and RISC-V; in terms of system modeling, it constructs a dual-mode engine for full-system simulation and system call simulation, supporting seamless switching from bare-metal programs to a complete operating system environment; at the processor microarchitecture level, it integrates a configurable pipeline model library, covering various computational core templates from classic five-level sequential execution (AtomicSimpleCPU) to superscalar out-of-order execution (O3CPU). This platform implements component parameterization configuration through a Python and C++ hybrid programming framework, allowing researchers to customize cache hierarchy, memory controller strategies, and bus interconnect protocols. The simulation data acquisition module has a built-in performance counter simulation function, which can output key indicators such as instruction throughput and cache hit rate in real time. 2. GPGPU-Sim Emulator: GPGPU-Sim achieves a breakthrough in fine-grained modeling in the field of GPU architecture simulation. Its core technology architecture comprises three subsystems: a streaming multiprocessor (SM) simulation unit employing a multi-threaded parallel scheduling algorithm to accurately reproduce NVIDIA GPU's warp scheduling mechanism and SIMT execution pipeline; a storage subsystem constructing a hierarchical timing model to simulate the physical characteristics of global memory, shared memory, and texture cache, supporting memory access merging optimization and memory conflict detection; and a CUDA runtime interface layer implementing API instruction interception and conversion, mapping PTX intermediate instructions to underlying hardware operation sequences. This emulator simulates the bandwidth and latency characteristics of memory technologies such as GDDR5 / HBM through a periodically accurate DRAM controller model and supports adaptive configuration of L1 / L2 cache replacement strategies. 3. Sniper Emulator: Sniper introduces an innovative methodology in the field of multi-core processor simulation. Its technology is based on a dynamic binary instrumentation core engine, constructing fine-grained execution trajectories through real-time instruction capture and parsing. This platform proposes a theoretical framework for interval models and employs a dual-dimensional analysis method combining instruction-level and memory-level parallelism to optimize computational resource consumption while ensuring simulation accuracy. The multi-core interconnect network module integrates various topology modeling tools, supporting latency-bandwidth characteristic simulations for connection methods such as Mesh, Ring, and Crossbar. The cache coherence protocol simulation layer implements multiple state machine models, including MESI and MOESI, and allows real-time monitoring of cache line state transitions using visualization tools.

[0003] Although existing simulation technology systems have formed a professional development path, the following core defects still restrict their engineering application efficiency: 1. Simulation time overhead and resource consumption increase exponentially. Mainstream simulators face the problem of non-linearly increasing computational complexity when pursuing accurate modeling. In gem5's full-system simulation mode, the single startup time can be thousands of times that of a physical machine. Especially when superscalar out-of-order cores and multi-level cache co-simulation are performed, the instruction-level event-driven mechanism generates massive interrupt response overhead. GPGPU-Sim requires the maintenance of tens of thousands of concurrent thread state machines for thread-level parallel simulation of GPU many-core architecture, resulting in memory usage exceeding hundreds of GB. Although Sniper uses a statistical sampling strategy to reduce instruction tracing load, its dynamic instrumentation mechanism still introduces an additional 20%-30% performance loss. Such time bottlenecks severely restrict the rapid exploration of architectural design space. 2. The high complexity of the framework leads to a steep learning curve. Existing platforms mostly adopt multi-layer abstract architectures, and the coupling between modules is not adequately controlled. Gem5's Python / C++ hybrid programming paradigm requires developers to master the interface mapping rules of both languages ​​simultaneously, and the component initialization sequence involves more than ten interlocked configuration stages; the PTX instruction to micro-operation translation layer of GPGPU-Sim has a non-transparent mapping relationship, requiring reverse inference of hardware execution semantics during debugging; Sniper's interval model theory relies on prior knowledge of ILP / MLP parameters, and misconfiguration of parameters can easily lead to simulation distortion. New users need an average of 3-6 months to complete the proficient deployment of the toolchain and the development of basic functions. 3. Benchmark debugging support mechanisms are weak, and existing simulators have key toolchain gaps in the dimension of program behavior observation. Gem5's GDB debugging interface only supports single-step tracing at the instruction set level; Sniper's dynamic instrumentation will destroy the original program stack structure, making it impossible for standard debuggers to directly attach to the process. Summary of the Invention

[0004] To address the problem of long simulation times in current simulators, this invention proposes a simulator pre-simulation method for hardware simulation scenarios.

[0005] The technical solution of this invention is: a simulator pre-simulation method for hardware simulation scenarios, comprising the following steps:

[0006] S1. Construct a performance mapping model for the simulator;

[0007] S2. Based on the performance mapping relationship model, analyze multi-threaded concurrent behavior and generate multi-threaded predicted performance;

[0008] S3 receives the raw instruction stream and combines multi-threaded prediction performance to optimize heterogeneous scenarios, completing the pre-simulation.

[0009] Furthermore, in S1, the performance mapping relationship model includes a simulation time linear relationship model, a cycle number mapping model based on simulation time, and a cycle number mapping model based on instruction statistics.

[0010] Furthermore, the simulation time linear relationship model The expression is:

[0011] ;

[0012] In the formula, For the time required for pre-simulation using NEMU, This is the proportionality coefficient. For fixed expenses;

[0013] Period number mapping model based on simulation time The expression is:

[0014] ;

[0015] In the formula, This is the ratio of simulation time to the number of cycles. The offset mapped to the number of cycles;

[0016] Cycle number mapping model based on instruction statistics The expression is:

[0017] ;

[0018] In the formula, For arithmetic logic instructions, For the first The number of times arithmetic logic instructions are executed. For the first Weighting coefficients for arithmetic logic instructions. For memory access instructions, For the first The number of times a class memory access instruction is executed. For the first Weighting coefficients for class memory access instructions The memory access mode influencing factor. For the first The number of times a branch prediction instruction is executed. For the first Weighting coefficients for branch prediction instructions. For branch prediction impact factors, For control flow instructions, These are user-defined parameters.

[0019] Furthermore, S2 includes the following sub-steps:

[0020] S21. Collect thread lifecycle data using thread event monitoring functions;

[0021] S22. Collect synchronization operation data using synchronization primitive monitoring functions;

[0022] S23. Use memory access monitoring functions to exchange memory data;

[0023] S24. Generate a structured model based on thread lifecycle data, synchronization operation data, and memory interaction data;

[0024] S25. Generate multi-threaded performance predictions based on the structured model and performance mapping relationship model.

[0025] Furthermore, in S21, the thread event monitoring function The expression is:

[0026] ;

[0027] in, For threads, For creation time, Due to scheduling delay, For context switching time, For the time of destruction;

[0028] In S21, thread lifecycle data The expression is:

[0029] ;

[0030] in, This is the first thread state. The timestamp of the first thread state. This is the second thread state. This is the timestamp for the second thread state. For the first Each thread state For the first The timestamp of each thread's state.

[0031] Furthermore, in S22, the synchronization primitive monitoring function The expression is:

[0032] ;

[0033] in, To synchronize primitive objects, For synchronization primitive type, To synchronize operation time, For waiting time, To the extent of competition;

[0034] In S22, the lock contention strength for synchronizing operation data The expression is:

[0035] ;

[0036] in, For the first Next wait lock Time, For the first The duration of each lock holding. This represents the number of times the lock is waited for.

[0037] Furthermore, in S23, the memory access monitoring function The expression is:

[0038] ;

[0039] in, For memory access objects, For access address, Access type (read / write) For the execution thread ID, For access timestamps, For cache line identifier;

[0040] In S23, the temporal locality index of memory-interacting data The expression is:

[0041]

[0042] in, For address No. The time of the second visit. For address No. The time of the second visit.

[0043] Furthermore, in S24, the expression for the structured model is:

[0044] ;

[0045] in, For thread lifecycle data, To synchronize primitive data, For memory-interactive data, For performance feature extraction layer, For thread lifecycle model, For the synchronization primitive performance model, For memory consistency model;

[0046] In S25, a performance prediction function for generating multi-threaded prediction performance is provided. The expression is:

[0047] ;

[0048] in, For the model parameter set, For performance indicators, For bottleneck analysis, Suggestions for optimization.

[0049] Furthermore, S3 includes the following sub-steps:

[0050] S31. Receive the original instruction stream and construct a complete dataset based on the original instruction stream;

[0051] S32. In the complete dataset, calculate the instruction-level speedup, the execution time difference between different instruction sets, and the resource consumption of various instructions;

[0052] S32. Based on the instruction-level speedup, the execution time differences between different instruction sets, and the resource consumption of various instructions, construct a performance gain prediction function;

[0053] S33. Based on the performance-benefit prediction function, construct a prediction model and train the prediction model.

[0054] S34. Optimize heterogeneous scenarios using the trained prediction model and multi-threaded prediction performance to complete pre-simulation.

[0055] Furthermore, in S32, the instruction-level speedup is... The expression is:

[0056] ;

[0057] in, For instruction set , For instruction set , For instruction set efficiency, For instruction set Efficiency;

[0058] In S32, the execution time difference between different instruction sets The expression is:

[0059] ;

[0060] Resource consumption of various instructions in S32 The expression is:

[0061] ;

[0062] in, For resource weight, For the corresponding resource utilization rate, The upper limit;

[0063] In S32, the performance gain prediction function The expression is:

[0064] ;

[0065] in, For instruction set, For the target architecture, Configure the compiler. For hardware characteristics, As the first weighting coefficient, This is the second weighting coefficient. This is the third weighting coefficient. For instruction speedup, Due to differences in execution time;

[0066] In S33, the error function of the prediction model The expression is:

[0067] ;

[0068] in, For the first Predicted performance gains per instruction, For the first The actual performance gain per instruction The total number of test samples;

[0069] In S3, heterogeneous tasks are optimized for heterogeneous scenarios. The expression is:

[0070] ;

[0071] in, For the first task, This is the processing unit for the first task. For the second task, This is the processing unit for the second task. For the first One task, For the first A processing unit for each task.

[0072] The beneficial effects of this invention are: it enables rapid and accurate prediction of simulators for hardware simulation scenarios, effectively solving problems such as long hardware simulation time, difficult resource planning, and long performance optimization cycle. Compared with traditional methods, it significantly improves work efficiency and has good scalability. It is not only applicable to the mapping between NEMU and lego-sim, but can also be extended to other simulator platforms, showing broad application prospects. Attached Figure Description

[0073] Figure 1 This is a flowchart of a simulator pre-simulation method for hardware simulation scenarios. Detailed Implementation

[0074] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0075] like Figure 1 As shown, this invention provides a simulator pre-simulation method for hardware simulation scenarios, including the following steps:

[0076] S1. Construct a performance mapping model for the simulator;

[0077] S2. Based on the performance mapping relationship model, analyze multi-threaded concurrent behavior and generate multi-threaded predicted performance;

[0078] S3 receives the raw instruction stream and combines multi-threaded prediction performance to optimize heterogeneous scenarios, completing the pre-simulation.

[0079] In this embodiment of the invention, in S1, the performance mapping relationship model includes a simulation time linear relationship model, a cycle number mapping model based on simulation time, and a cycle number mapping model based on instruction statistics.

[0080] This model establishes a performance mapping relationship between the lightweight pre-simulation tool NEMU and the system-level co-simulation tool LegoSim, resolving the trade-off between rapid performance evaluation and accurate simulation in computer architecture research. The model includes: a linear simulation time model (directly mapping the time overhead of the two simulators via linear equations for rapid estimation); a cycle number mapping model (deriving LegoSim cycle numbers from NEMU simulation time, suitable for performance comparison scenarios); and an instruction statistics cycle number mapping model (constructing a more accurate cycle number prediction model based on microarchitectural features such as instruction types and cache hit rates collected by NEMU, with errors controlled within ±2%).

[0081] In this embodiment of the invention, a simulation time linear relationship model is used. The expression is:

[0082] ;

[0083] In the formula, For the time required for pre-simulation using NEMU, This is the proportionality coefficient. For fixed expenses;

[0084] Based on the experimental data, two representative sets of test results were selected to solve for the coefficients. and :

[0085] Test Case 1: Parallel Matrix Operations (64×64); NEMU Simulation Time: Seconds; LegoSim simulation time: Second.

[0086] Test Case 2: Multilayer Perceptron (MLP); NEMU Simulation Time: Seconds; LegoSim simulation time: Second.

[0087] According to the system of linear equations Solve for the proportionality constant. .

[0088] Solving for bias : .

[0089] Therefore, the simulation time relationship between LegoSimNEMU can be expressed as:

[0090] ;

[0091] This relationship indicates that LegoSim's computational density is approximately 125 times that of NEMU, primarily due to simulating more detailed microarchitectures and communication overhead. There is a fixed overhead of approximately 38.53 seconds arising from system initialization and iterative convergence. As the workload increases, LegoSim's time overhead grows even faster; therefore, it is recommended to prioritize the use of NEMU during large-scale design space exploration phases.

[0092] Period number mapping model based on simulation time The expression is:

[0093] ;

[0094] In the formula, This is the ratio of simulation time to the number of cycles. The offset mapped to the number of cycles;

[0095] Based on two sets of known data:

[0096] Parallel matrix operations (64×64): Second, cycle;

[0097] Multilayer Perceptron (MLP) forward propagation: Second, cycle;

[0098] Solving for coefficients and : , .

[0099] Therefore, the mapping relationship from NEMU simulation time to LegoSim cycle number is as follows:

[0100] .

[0101] Cycle number mapping model based on instruction statistics The expression is:

[0102] ;

[0103] In the formula, For arithmetic logic instructions, For the first The number of times arithmetic logic instructions are executed. For the first Weighting coefficients for arithmetic logic instructions. For memory access instructions, For the first The number of times a class memory access instruction is executed. For the first Weighting coefficients for class memory access instructions The memory access mode influencing factor. For the first The number of times a branch prediction instruction is executed. For the first Weighting coefficients for branch prediction instructions. For branch prediction impact factors, For control flow instructions, These are user-defined parameters.

[0104] The parallel matrix operation and multilayer perceptron benchmark programs were tested. Example instruction statistics are shown in Table 1.

[0105] Table 1

[0106]

[0107] The comparison of the prediction accuracy of the number of cycles is shown in Table 2.

[0108] Table 2

[0109]

[0110] The results show that the error .

[0111] In this embodiment of the invention, S2 includes the following sub-steps:

[0112] S21. Collect thread lifecycle data using thread event monitoring functions;

[0113] S22. Collect synchronization operation data using synchronization primitive monitoring functions;

[0114] S23. Use memory access monitoring functions to exchange memory data;

[0115] S24. Generate a structured model based on thread lifecycle data, synchronization operation data, and memory interaction data;

[0116] S25. Generate multi-threaded performance predictions based on the structured model and performance mapping relationship model.

[0117] Built upon the NEMU instruction-level execution engine, this system provides a comprehensive concurrency performance analysis framework by extending multi-threading support. At its core, the system comprises three main monitoring modules: thread event monitoring, synchronization primitive interception, and memory access tracing. These modules collectively form the thread behavior capture layer, responsible for collecting thread lifecycle data (creation / destruction, context switching, scheduling latency), synchronization operation data (locks, condition variables, semaphores), and memory interaction data (access patterns, cache contention, memory barriers), providing comprehensive raw data support for upper-level analysis. The system employs low-overhead instrumentation technology, setting hook functions at critical system calls and synchronization primitive entry points to minimize the impact of data collection on the analyzed program while maintaining high-precision timestamp recordings, enabling the tracking of microsecond-level thread behavior changes. For memory access, the system implements a lightweight tracing mechanism based on page table monitoring, capable of identifying data sharing hotspots and potential false-sharing issues between different threads.

[0118] The collected raw data is processed by a performance feature extraction layer and transformed into three structured models: a thread lifecycle model, a synchronization primitive performance model, and a memory consistency model. These three models serve as input to a machine learning prediction engine, which, after deep analysis, generates multi-threaded performance predictions, bottleneck identification, and optimization suggestions. The prediction engine employs a specially trained algorithm capable of accurately evaluating performance under different thread configurations based on historical data and current observations, and identifying key factors affecting system scalability. The model training process utilizes a large amount of pre-collected multi-threaded program execution data, covering various typical concurrency patterns and synchronization strategies, enabling the system to adapt to various concurrent architectures, from simple producer-consumer models to complex multi-stage pipelines. The prediction engine considers not only the number of threads but also CPU topology, NUMA effects, and scheduling strategies, providing performance estimates that more closely reflect real-world hardware environments.

[0119] The system's advanced analytics capabilities provide developers with practical tools for diagnosing and optimizing concurrency issues, including data race prediction (analyzing potential shared data conflicts), deadlock risk assessment (identifying synchronization patterns that could lead to system deadlocks), and parallelism optimization suggestions (recommending optimal thread counts and resource allocation strategies). These analytical results are ultimately integrated into a comprehensive performance report, providing developers with a one-stop solution for multi-threaded performance optimization, significantly improving development efficiency and reducing the complexity and risk of concurrent programming. The system uses a visual interface to display key performance indicators and concurrency behavior patterns, including hotspot lock analysis, wait graphs, and resource contention intensity heatmaps, helping developers intuitively understand complex concurrent execution scenarios. Especially for large-scale multi-threaded applications, the system can automatically identify parallelizable code segments and provide improvement suggestions, even generating code templates for specific parallelism patterns, further shortening the optimization cycle. In actual deployments, the system has been successfully applied to high-concurrency scenarios such as database engines, web servers, and scientific computing applications, achieving an average performance improvement of 20-35%.

[0120] In this embodiment of the invention, in S21, the thread event monitoring function... The expression is:

[0121] ;

[0122] in, For threads, For creation time, Due to scheduling delay, For context switching time, For the time of destruction;

[0123] In S21, thread lifecycle data The expression is:

[0124] ;

[0125] in, This is the first thread state. The timestamp of the first thread state. This is the second thread state. This is the timestamp for the second thread state. For the first Each thread state For the first The timestamp of each thread's state.

[0126] In this embodiment of the invention, in S22, the synchronization primitive monitoring function The expression is:

[0127] ;

[0128] in, To synchronize primitive objects, For synchronization primitive type, To synchronize operation time, For waiting time, To the extent of competition;

[0129] In S22, the lock contention strength for synchronizing operation data The expression is:

[0130] ;

[0131] in, For the first Next wait lock Time, For the first The duration of each lock holding. This represents the number of times the lock is waited for.

[0132] In this embodiment of the invention, in S23, the memory access monitoring function... The expression is:

[0133] ;

[0134] in, For memory access objects, For access address, Access type (read / write) For the execution thread ID, For access timestamps, For cache line identifier;

[0135] In S23, the temporal locality index of memory-interacting data The expression is:

[0136]

[0137] in, For address No. The time of the second visit. For address No. The time of the second visit.

[0138] Thread scheduling patterns can be represented as Markov processes. ,in, It is a set of thread states. It is the state transition probability matrix, and its expression is:

[0139] ;

[0140] in, Let t be the thread state at time t. This represents the thread state at time t+1. Let be the probability of transitioning from state i to state j.

[0141] The waiting efficiency of condition variables generated by the synchronous behavior model It can be represented as:

[0142]

[0143] in, It is the number of signals. It is the number of times you wait. This is the average waiting time.

[0144] In this embodiment of the invention, in S24, the expression of the structured model is:

[0145] ;

[0146] in, For thread lifecycle data, To synchronize primitive data, For memory-interactive data, For performance feature extraction layer, For thread lifecycle model, For the synchronization primitive performance model, For memory consistency model;

[0147] In S25, a performance prediction function for generating multi-threaded prediction performance is provided. The expression is:

[0148] ;

[0149] in, For the model parameter set, For performance indicators, For bottleneck analysis, Suggestions for optimization.

[0150] In this embodiment of the invention, S3 includes the following sub-steps:

[0151] S31. Receive the original instruction stream and construct a complete dataset based on the original instruction stream;

[0152] S32. In the complete dataset, calculate the instruction-level speedup, the execution time difference between different instruction sets, and the resource consumption of various instructions;

[0153] S32. Based on the instruction-level speedup, the execution time differences between different instruction sets, and the resource consumption of various instructions, construct a performance gain prediction function;

[0154] S33. Based on the performance-benefit prediction function, construct a prediction model and train the prediction model.

[0155] S34. Optimize heterogeneous scenarios using the trained prediction model and multi-threaded prediction performance to complete pre-simulation.

[0156] This invention constructs an adaptive simulation and optimization system across heterogeneous instruction sets. First, the NEMU core framework provides basic simulation capabilities through instruction decoding and execution engines, while simultaneously collecting key execution statistics. Building upon this, a heterogeneous instruction set extension mechanism enables accurate simulation of various special instruction types (scalar, vector, cryptographic, and AI-accelerated instructions) and records the benchmark performance metrics for each type of instruction. In the performance modeling phase, this data is used to construct speedup calculation, time difference analysis, and resource consumption models, and a predictive model is trained through a self-learning algorithm. Finally, the system provides instruction replacement suggestions, code segment optimization identification, and task partitioning strategies in heterogeneous scenarios, generating a comprehensive performance evaluation report and achieving intelligent optimization across instruction sets.

[0157] The heterogeneous instruction set extension mechanism employs an adaptive identification and distribution strategy. The instruction set parser receives extension requests from the core decoder and accurately determines the instruction type through multi-dimensional feature extraction. The system implements dedicated simulators for different instruction types: a basic instruction executor handles regular scalar instructions; a vector instruction simulator enables SIMD parallel computing; a dedicated instruction simulator supports complex encryption algorithms; and an AI-accelerated instruction simulator provides efficient simulation for neural network operations. The execution results of each simulator are aggregated into a benchmark performance recording module, providing fine-grained performance metrics. ,in Indicates instruction set, This represents the target architecture and integrates it with core statistics to provide a complete dataset for performance modeling. .

[0158] After the prediction model is trained, the system enters the heterogeneous scenario optimization phase, achieving comprehensive performance improvement through three parallel optimization paths. The instruction replacement suggestion generator analyzes inefficiencies in the instruction sequence and recommends suitable alternative instruction combinations for the target architecture. , making ;in, This is the first substitution instruction. This is the second substitution instruction. For the k-th substitution instruction, To improve the efficiency of replacement instructions, For initial instruction efficiency, As a replacement instruction set, This forms the initial instruction set. The code segment optimization opportunity identifyer then discovers code regions that can be parallelized or accelerated by special instructions at a higher level of abstraction. The heterogeneous task partitioning strategy analyzer provides task allocation schemes at the system level. ,in Indicates the task. This represents the processing unit, determining which code blocks are suitable for execution on a specific processing unit. The results of these three optimization approaches are ultimately integrated into a comprehensive performance evaluation report, providing the expected performance gains. Quantitative analysis of resource consumption and implementation costs provides comprehensive guidance for performance optimization of heterogeneous systems.

[0159] In this embodiment of the invention, in S32, the instruction-level speedup ratio The expression is:

[0160] ;

[0161] in, For instruction set , For instruction set , For instruction set efficiency, For instruction set Efficiency;

[0162] In S32, the execution time difference between different instruction sets The expression is:

[0163] ;

[0164] Resource consumption of various instructions in S32 The expression is:

[0165] ;

[0166] in, For resource weight, For the corresponding resource utilization rate, The upper limit;

[0167] In S32, the performance gain prediction function The expression is:

[0168] ;

[0169] in, For instruction set, For the target architecture, Configure the compiler. For hardware characteristics, As the first weighting coefficient, This is the second weighting coefficient. This is the third weighting coefficient. For instruction speedup, Due to differences in execution time;

[0170] In S33, the error function of the prediction model The expression is:

[0171] ;

[0172] in, For the first Predicted performance gains per instruction, For the first The actual performance gain per instruction The total number of test samples;

[0173] In S3, heterogeneous tasks are optimized for heterogeneous scenarios. The expression is:

[0174] ;

[0175] in, For the first task, This is the processing unit for the first task. For the second task, This is the processing unit for the second task. For the first One task, For the first A processing unit for each task.

[0176] In this embodiment of the invention, the precise quantization of the performance gain of the SIMD vector instruction is expressed as:

[0177] ;

[0178] in, Let be the execution time of the i-th scalar instruction. Let be the execution time of the j-th vector instruction.

[0179] Performance mapping and prediction in heterogeneous computing scenarios are represented by a mapping function:

[0180] ;

[0181] in, For the instruction set on architecture A, For performance under architecture B, and For different architectures;

[0182] Value assessment of new instruction set extensions Represented as:

[0183] ;

[0184] in, For workload space, The workload distribution function, To extend the instruction set, It is a standard instruction set.

[0185] This innovation enables researchers to quickly assess the impact of hardware instruction set innovations on software performance, providing precise guidance for architecture research. Overall Value Quantifiable as

[0186] ;

[0187] in, , , These are the weighting coefficients. To improve performance, To save energy, For implementation costs.

[0188] The following description is based on specific embodiments.

[0189] Experimental setup

[0190] Test program 1: Three-layer MLP forward propagation (input layer: 784, hidden layer: 256, output layer: 10);

[0191] Test Program 2: Two Parallel matrix multiplication (using OpenMP);

[0192] Hardware configuration: Simulates a quad-core processor, 2.5GHz per core, 32KB L1 cache, 256KB L2 cache, and 8MB shared L3 cache.

[0193] The characteristics of the three simulators are compared in Table 3.

[0194] Table 3

[0195]

[0196] The conclusion is:

[0197] 1. NEMU: Suitable for rapid prototyping and teaching purposes, with fast simulation speed but limited support for parallel programming.

[0198] 2. gem5: Provides the most accurate system-level simulation, suitable for detailed architecture studies, but has the slowest simulation speed.

[0199] 3. Snipersim: Achieves a good balance between speed and accuracy, making it particularly suitable for performance analysis of multi-core parallel programs.

[0200] For computationally intensive programs like MLPs, all three simulators can provide reasonably accurate performance estimates; however, for programs like parallel matrix multiplication that require precise simulation of multi-core collaboration, gem5 and Snipersim yield more reliable results. The choice of simulator should be based on the research objectives, required accuracy, and acceptable simulation time.

[0201] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention, and should be understood that the scope of protection of the invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this invention without departing from the spirit of the invention, and these modifications and combinations are still within the scope of protection of this invention.

Claims

1. A simulator pre-simulation method for a hardware simulation scenario, characterized in that, The method comprises the following steps: S1, constructing a performance mapping relationship model for the simulator; S2, analyzing the multi-thread concurrent behavior based on the performance mapping relationship model to generate multi-thread predicted performance; S3, receiving the original instruction stream and performing heterogeneous scene optimization in combination with the multi-thread predicted performance to complete pre-simulation.

2. The hardware emulation scenario oriented simulator pre-simulation method of claim 1, wherein, In the S1, the performance mapping relationship model comprises a simulation time linear relationship model, a cycle number mapping model based on simulation time, and a cycle number mapping model based on instruction statistics.

3. The hardware emulation scenario oriented simulator pre-simulation method of claim 2, wherein, The expression of the simulation time linear relationship model is: ； In the formula, the time for pre-simulation using NEMU, is a proportional coefficient, is a fixed overhead; The number of cycles based on simulation time mapping model The expression is: ； In the formula, is a proportionality coefficient of the simulation time to the number of cycles, is an offset of the number of cycles mapping; The instruction statistics-based cycle number mapping model The expression is: ； wherein, is an arithmetic logic instruction, is a first arithmetic logic instruction, is a number of executions of a first arithmetic logic instruction, is a memory access instruction, is a first memory access instruction, is a number of executions of a first memory access instruction, is a memory access pattern impact factor, is a first branch prediction instruction, is a number of executions of a first branch prediction instruction, is a branch prediction impact factor, is a control flow instruction, is a self-defined parameter.

4. The hardware emulation scenario oriented simulator pre-simulation method of claim 1, wherein, The S2 comprises the following sub-steps: S21, collecting thread life cycle data by using a thread event monitoring function; S22, collecting synchronization operation data by using a synchronization primitive monitoring function; S23, collecting memory interaction data by using a memory access monitoring function; S24, generating a structured model according to the thread life cycle data, the synchronization operation data, and the memory interaction data; S25, generating multi-thread predicted performance according to the structured model and the performance mapping relationship model.

5. The hardware emulation scenario oriented simulator pre-simulation method of claim 4, wherein, In the S21, the thread event monitoring function The expression of the formula is: ； wherein, is a thread, is a creation time, is a scheduling delay, is a context switch time, is a destruction time; In the S21, the thread life cycle data The expression of the thread life cycle data is: ； wherein, is a first thread state, is a timestamp of the first thread state, is a second thread state, is a timestamp of the second thread state, is a third thread state, is a fourth thread state, is a timestamp of the third thread state, is a timestamp of the fourth thread state.

6. The hardware emulation scenario oriented simulator pre-simulation method of claim 4, wherein, In the S22, the synchronization primitive monitoring function The expression is: ； wherein, is a synchronization primitive object, is a synchronization primitive type, is a synchronization operation time, is a waiting duration, is a contention degree; In the S22, the lock contention intensity of the synchronization operation data The expression is: ； wherein, is the time the lock was held, is the time the lock was held, is the time the lock was held, is the number of times the lock was waited for.

7. The hardware emulation scenario oriented simulator pre-simulation method of claim 4, wherein, In the S23, the memory access monitoring function The expression is: ； wherein, is a memory access object, is an access address, is an access type, is an execution thread ID, is an access timestamp, is a cache line identification; In the S23, the time locality index of the memory interaction data The expression is: wherein is the address the first time the address is the address the first time the address 8. The hardware emulation scenario oriented simulator pre-simulation method of claim 4, wherein, In the S24, the expression of the structured model is: ； wherein, is thread life cycle data, is synchronization primitive data, is memory interaction data, is a performance feature extraction layer, is a thread life cycle model, is a synchronization primitive performance model, is a memory consistency model; In the S25, a performance prediction function of the multithreaded prediction performance is generated The expression is: ； wherein, is a model parameter set, is a performance indicator, is a bottleneck analysis, is an optimization recommendation.

9. The hardware emulation scenario oriented simulator pre-simulation method of claim 1, wherein, The S3 comprises the following sub-steps: S31, receiving the original instruction stream and constructing a complete data set according to the original instruction stream; S32, calculating instruction-level speedup, execution time difference between different instruction sets, and resource consumption of various instructions in the complete data set; S32, constructing a performance benefit prediction function according to the instruction-level speedup, the execution time difference between different instruction sets, and the resource consumption of various instructions; S33, constructing a prediction model according to the performance benefit prediction function and training the prediction model; S34, performing heterogeneous scene optimization by using the trained prediction model and the multi-thread predicted performance to complete pre-simulation.

10. The hardware emulation scenario oriented simulator pre-simulation method of claim 9, wherein, In the S32, the instruction level acceleration ratio The expression is: ； wherein is a set of instructions , is a set of instructions , is a set of instructions efficiency of, is a set of instructions efficiency of; In the S32, the execution time difference between different instruction sets The expression is: ； In the S32, the resource consumption of each type of instruction The expression is: ； wherein, is a resource weight, is a corresponding resource occupancy rate, is an upper limit; In the S32, the performance benefit prediction function The expression of the performance benefit prediction function is ； wherein, is an instruction set, is a target architecture, is a compiler configuration, is a hardware feature, is a first weight coefficient, is a second weight coefficient, is a third weight coefficient, is an instruction speedup ratio, is an execution time difference; In the S33, an error function of the prediction model is expressed as ； wherein, is the predicted performance benefit of the th instruction, is the actual performance benefit of the th instruction, is the total number of test samples; In the S3, the heterogeneous task of heterogeneous scene optimization is performed The expression is: ； wherein is a first task, is a processing unit for the first task, is a second task, is a processing unit for the second task, is a third task, is a processing unit for the third task, is a fourth task, is a processing unit for the fourth task.

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