Reference voltage adjusting method, memory controller, memory read-write system and equipment
By using parity checking and instruction error correction detection in the memory controller, the reference voltage on the memory or memory controller side is dynamically adjusted, solving the bit flipping problem caused by changes in link signals and ensuring that data transmission reliability does not degrade performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-04-10
AI Technical Summary
In the data link between the memory chip and the processor, changes in temperature and workload can cause bit flips due to variations in the optimal sampling phase or reference voltage of the link signal. Existing technologies require pausing memory access when adjusting the reference voltage through periodic training, which reduces performance.
By performing parity checks and instruction error correction detection in the memory controller, the direction and polarity of data link errors can be determined, and the reference voltage on the memory or memory controller side can be dynamically adjusted to avoid pausing memory access.
It enables accurate adjustment of the reference voltage without affecting memory access performance, thereby reducing data link errors and improving data transmission reliability.
Smart Images
Figure CN121838828A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of automatic control, and more specifically, to a method for adjusting a reference voltage, a memory controller, a memory read / write system, and a device. Background Technology
[0002] Most current electronic devices integrate processors and memory chips. As performance demands increase, memory chip bandwidth is increasing, leading to a rise in the data link rate between the processor and the memory chips, and consequently, a rise in the bit error rate on this link.
[0003] In actual use of memory chips, changes in temperature and workload can alter the optimal sampling phase or reference voltage of the link signal, leading to bit flips. Currently, periodic training is typically used to address this reference voltage variation; however, periodic training to achieve the optimal reference voltage under the current environment requires pausing memory access, reducing memory access performance. Summary of the Invention
[0004] This application provides a method for adjusting a reference voltage, a memory controller, a memory read / write system, and a device to achieve adjustment of the reference voltage without pausing memory access.
[0005] In a first aspect, this application provides a method for adjusting a reference voltage, applied to a memory controller. The method includes: recording a first address of the first data when a first parity check result indicates that the first data has an error; performing parity check on the second data when reading second data from the memory to obtain a second parity check result; performing instruction error correction detection on the second data to obtain a third detection result; and adjusting the reference voltage on the memory side of the data link between the memory and the memory controller according to the error correction polarity type included in the third detection result when there is a first address that is the same as a second address of the second data in the memory, and the second parity check result indicates no error, but the third detection result indicates an error.
[0006] In this embodiment, the first verification result is obtained by parity checking of the first data written to memory. Therefore, the first verification result can determine whether an error has occurred in the write direction (from memory controller to memory). The second verification result is obtained by parity checking of the second data read from memory. Therefore, the second verification result can determine whether an error has occurred in the read direction (from memory to memory controller). Thus, when a first address and a second address are identical, and the second verification result indicates no error, it indicates that only the write direction is incorrect, and therefore the reference voltage on the memory side needs to be adjusted. This method accurately determines the side of the data path where the reference voltage needs adjustment. Simultaneously, the specific reference voltage adjustment strategy can be determined by the error correction polarity type. This method can adjust the reference voltage of the data link during normal memory operation without pausing memory access, thus not degrading memory access performance.
[0007] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, adjusting the reference voltage of the data link between the memory and the memory controller on the memory side according to the error correction polarity type included in the third detection result includes: if the error correction polarity type characterization changes from 0 to 1, increasing the reference voltage on the memory side; if the error correction polarity type characterization changes from 1 to 0, decreasing the reference voltage on the memory side.
[0008] In this embodiment, when the error correction polarity type characterization changes from 0 to 1, it indicates that a low voltage was incorrectly identified as a high voltage, therefore, the reference voltage needs to be increased. Conversely, when the error correction polarity type characterization changes from 1 to 0, it indicates that a high voltage was incorrectly identified as a low voltage, therefore, the reference voltage needs to be increased. Thus, the specific adjustment method of the reference voltage can be achieved through error correction polarity, thereby achieving the effect of accurately increasing the reference voltage.
[0009] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, if the data transmission method is parallel transmission and the number of parallel transmission channels is N, then the third detection result also includes an error correction position, where the error correction position represents the bit bit in the second data that has an error; adjusting the reference voltage of the data link between the memory and the memory controller on the memory side according to the error correction polarity type included in the third detection result includes: determining a second target channel whose reference voltage needs to be adjusted from the N channels on the memory side based on the error correction position and the number of channels; if the error correction polarity type changes from 0 to 1, increasing the reference voltage of the second target channel; if the error correction polarity type changes from 1 to 0, decreasing the reference voltage of the second target channel.
[0010] In this embodiment, when there are N data transmission channels, the faulty second target channel can be quickly and accurately located by determining the error correction position and the number of channels. This enables accurate adjustment of the reference voltage.
[0011] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, when there is no first address that is the same as the second address of the second data in memory, and the second verification result indicates an error, the reference voltage of the data link between the memory and the memory controller located on the memory controller side is adjusted according to the error correction polarity type.
[0012] In this embodiment, if there is no first address that is the same as the second address and the second verification result indicates an error, it indicates that the read direction is wrong. Therefore, the reference voltage on the memory controller side needs to be adjusted.
[0013] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, adjusting the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the error correction polarity type included in the third detection result includes: if the error correction polarity type characterization changes from 0 to 1, increasing the reference voltage on the memory controller side; if the error correction polarity type characterization changes from 1 to 0, decreasing the reference voltage on the memory controller side.
[0014] In this embodiment, when the error correction polarity type characterization changes from 0 to 1, it indicates that a low voltage was incorrectly identified as a high voltage, therefore, the reference voltage needs to be increased. Conversely, when the error correction polarity type characterization changes from 1 to 0, it indicates that a high voltage was incorrectly identified as a low voltage, therefore, the reference voltage needs to be decreased. Thus, the specific adjustment method of the reference voltage can be achieved through error correction polarity, thereby achieving the effect of accurately increasing the reference voltage.
[0015] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, if the data transmission method is parallel transmission and the number of parallel transmission channels is N, then the third detection result also includes an error correction position, where the error correction position represents the bit bit in the second data that has an error; adjusting the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the error correction polarity type included in the third detection result includes: determining a first target channel whose reference voltage needs to be adjusted from the N channels on the memory controller side based on the error correction position and the number of channels; increasing the reference voltage of the first target channel if the error correction polarity type changes from 0 to 1; and decreasing the reference voltage of the first target channel if the error correction polarity type changes from 1 to 0.
[0016] In this embodiment, when there are N data transmission channels, the first target channel with the error can be quickly and accurately located by determining the error correction position and the number of channels. This enables accurate adjustment of the reference voltage.
[0017] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the magnitude of each adjustment to the reference voltage does not exceed ±30% of the current value of the reference voltage.
[0018] In this embodiment, by limiting the voltage adjustment range to no more than ±30% of the current reference voltage, excessive adjustment of the reference voltage is prevented, which could lead to more errors in subsequent data transmission.
[0019] In conjunction with the technical solution provided in the first aspect above, in some possible implementations, the method further includes: issuing an alarm when there is a first address that is the same as the second address and the second verification result indicates an error.
[0020] In this embodiment, if a first address and a second address are identical, and the second verification result indicates an error, it means that errors have occurred in both the data writing and reading processes. Therefore, an alarm is issued to indicate that an error has occurred.
[0021] Secondly, this application provides a memory controller, including: a reference voltage compensation module, a parity check module, and an instruction error correction module; the reference voltage compensation module is used to record a first address of the first data when a first parity check result indicates that the first data has an error; the parity check module is used to perform parity check on second data read from the memory to obtain a second check result; the instruction error correction module is used to perform instruction error correction detection on the second data to obtain a third detection result; the reference voltage compensation module is further used to adjust the reference voltage of the data link between the memory and the memory controller on the memory side according to the error correction polarity type included in the third detection result when there is a first address that is the same as the second address of the second data in the memory, and the second check result indicates that there is no error, but the third detection result indicates that there is an error, wherein the error correction polarity type indicates the type of error detected by the error correction detection.
[0022] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, the reference voltage compensation module is further used to adjust the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the error correction polarity type included in the third detection result when there is no first address that is the same as the second address of the second data in memory, and the second verification result indicates an error.
[0023] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, the reference voltage compensation module includes: a detection result recording unit, a read / write error direction judgment unit, and a reference voltage adjustment unit; the detection result recording unit is used to record the first address of the first data when the first parity check result of the first data written in memory indicates that an error has occurred in the first data; the read / write error direction judgment unit is used to determine the read / write error direction based on the recorded first address, the second parity check result, and the second address of the second data in memory; the reference voltage adjustment unit is used to adjust the reference voltage of the data link between the memory controller and the memory based on the read / write error direction and the error correction polarity.
[0024] In conjunction with the technical solution provided in the second aspect above, in some possible implementations, the read / write error direction determination unit is specifically used to determine the read / write error direction as the write direction when there is a first address that is the same as the second address and the second verification result indicates no error; and to determine the read / write error direction as the read direction when there is no first address that is the same as the second address and the second verification result indicates an error.
[0025] Thirdly, this application provides a memory read / write system, comprising: a memory controller and memory as described in the second aspect and / or in combination with any possible implementation of the second aspect; the memory being used to perform parity checking on written first data to obtain a first verification result; the memory controller being used to record a first address of the first data when the first verification result of the parity check on the written first data in the memory indicates that the first data has an error; when reading second data from the memory, performing parity checking on the second data to obtain a second verification result; and performing instruction error correction detection on the second data to obtain a third detection result; when there exists a first address that is the same as a second address of the second data in the memory, and the second verification result indicates that there is no error, but the third detection result indicates that there is an error, adjusting the reference voltage of the data link between the memory and the memory controller on the memory side according to the error correction polarity type included in the third detection result.
[0026] In conjunction with the technical solution provided in the third aspect above, in some possible implementations, when there is no first address that is the same as the second address of the second data in memory, and the second verification result indicates an error, and the third detection result indicates an error, the reference voltage of the data link between the memory and the memory controller located on the memory controller side is adjusted according to the error correction polarity type included in the third detection result.
[0027] Fourthly, this application provides an electronic device, including: a processor and the memory read / write system described in the third aspect above; the processor and the memory read / write system are connected. Attached Figure Description
[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic flowchart illustrating a method for adjusting a reference voltage according to an embodiment of this application; Figure 2 This application illustrates the positional relationship between the first reference voltage and the corresponding Vref Margins for each of the three channels in an embodiment of the present application. Figure 3 This application illustrates the positional relationship between the second reference voltage and the Vref Margin corresponding to each of the three channels in an embodiment of the present application. Figure 4 This is a schematic diagram illustrating the storage location of different data written to memory, as shown in an embodiment of this application. Figure 5 This is a structural block diagram of a first type of memory controller shown in an embodiment of this application; Figure 6 This is a structural block diagram of a second type of memory controller shown in an embodiment of this application; Figure 7 This is a structural block diagram of a memory read / write system shown in an embodiment of this application; Figure 8 This is a structural block diagram of an electronic device shown in an embodiment of this application. Detailed Implementation
[0030] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0032] Please see Figure 1 , Figure 1 This application illustrates a method for adjusting the reference voltage of a memory controller, which will be described below in conjunction with... Figure 1 The steps involved are explained.
[0033] S100: When the parity check result of the first data written to memory indicates that the first data has an error, record the first address of the first data.
[0034] The memory performs a parity check on the first piece of data written, obtaining a first check result. If the first check result indicates an error, the memory address of the erroneous first piece of data is sent to the memory controller. The memory controller records the received first address.
[0035] Parity checking, also known as parity verification, is a method for verifying the correctness of transmitted code. It verifies the correctness based on whether the number of "1"s in the transmitted binary code is odd or even. Odd numbers indicate odd parity, and even numbers indicate even parity. The specific logic and implementation of parity checking are well-known to those skilled in the art and will not be elaborated upon here for brevity.
[0036] S200: When reading the second data from memory, perform parity checking on the second data to obtain a second check result; and perform instruction error correction detection on the second data to obtain a third detection result.
[0037] When an error is represented in the third detection result, the third detection result includes an error correction polarity type. The error correction polarity type indicates the type of error that occurred during error correction detection. For example, the error correction polarity type might represent a bit in the second data changing from 0 to 1, or from 1 to 0.
[0038] The memory controller performs parity checks and instruction error correction checks on the second data read from memory to obtain the second check result and the third check result, respectively.
[0039] Error checking and correcting (ECC) is a computer memory error correction technique designed to address the shortcomings of parity check codes and to detect and correct memory errors. The specific logic and implementation of ECC are well-known to those skilled in the art and will not be elaborated upon here for brevity.
[0040] The error correction polarity obtained from instruction error correction detection can determine whether a single-bit error is a 0 to 1 (identifying a low level as a high level) or a 1 to 0 (identifying a high level as a low level) when the instruction error correction detection finds a single-bit error.
[0041] S300: When there is a first address and a second address in memory that are the same as the second address of the second data, and the second verification result indicates no error, but the third detection result indicates an error, the reference voltage of the data link between the memory and the memory controller on the memory side is adjusted according to the error correction polarity type included in the third detection result.
[0042] Since the first parity check result is obtained by parity checking the first data written to memory, it can determine whether the error is in the write direction (from memory controller to memory). The second parity check result is obtained by parity checking the second data read from memory; therefore, it can determine whether the error is in the read direction (from memory to memory controller). Therefore, if the first and second addresses are the same, and the second parity check result indicates no error, it indicates that only the write direction is incorrect, and thus the reference voltage on the memory side needs to be adjusted.
[0043] The reference voltage on the memory side refers to the data link between the memory and the memory controller, which is the reference voltage for the interface between the memory and the memory controller for data reading and writing.
[0044] In one implementation, adjusting the reference voltage on the memory side of the data link between the memory and the memory controller based on the error correction polarity type included in the third detection result can be done as follows: if the error correction polarity type characterization changes from 0 to 1, the reference voltage on the memory side is increased; if the error correction polarity type characterization changes from 1 to 0, the reference voltage on the memory side is decreased.
[0045] When the error correction polarity type changes from 0 to 1, it indicates an error in identifying a low voltage as a high voltage. Since the identification process compares the voltage of the electrical signal with a reference voltage, if the signal is greater than the reference voltage, it is identified as 1; if the signal is less than the reference voltage, it is identified as 0. Therefore, identifying a low voltage as a high voltage indicates that the reference voltage is too low, and thus needs to be increased. Similarly, identifying a high voltage as a low voltage indicates that the reference voltage is too high, and thus needs to be decreased.
[0046] In one implementation, each time the reference voltage on the memory side is adjusted (increased or decreased), the adjustment range can be a preset fixed value.
[0047] For example, each adjustment is 0.1mV, 0.2mV, etc. The specific value of this preset fixed value can be set according to the actual situation, and its specific value is not restricted here.
[0048] Alternatively, each adjustment (increase or decrease) to the reference voltage may not exceed ±30% of the current value of the reference voltage.
[0049] Each time the reference voltage is adjusted, the adjustment range can be any non-zero value within ±30%, such as increasing the current reference voltage by 10% or decreasing it by 5%. A positive adjustment indicates an increase in the reference voltage, while a negative adjustment indicates a decrease.
[0050] To make it easier to understand, let's take an example where the current reference voltage is 5V and the adjustment (increase or decrease) is 10% of the current reference voltage each time.
[0051] If the reference voltage needs to be increased, the increased reference voltage value will be 5 + 5 × 10% = 5.5V. The increased reference voltage is 5.5V.
[0052] If the reference voltage needs to be reduced further, the value of the reduced reference voltage will be 5.5 - 5.5 × 10% = 4.95V, and the value of the reference voltage after adjustment will be 4.95V.
[0053] The examples provided are for illustrative purposes only. In practical applications, the magnitude of increasing the reference voltage may differ from the magnitude of decreasing the reference voltage. These examples should not be construed as limiting the scope of this application.
[0054] In one implementation, if the data transmission method is parallel transmission and the number of parallel transmission channels is N, the third detection result also includes error correction positions, where the error correction position represents the bit bit in the second data that has an error. In this case, the method for adjusting the reference voltage of the data link between the memory and the memory controller on the memory side according to the error correction polarity type included in the third detection result can be as follows: based on the error correction position and the number of channels, determine a second target channel from the N channels on the memory side whose reference voltage needs to be adjusted. If the error correction polarity type changes from 0 to 1, increase the reference voltage of the second target channel. If the error correction polarity type changes from 1 to 0, decrease the reference voltage of the second target channel.
[0055] When there are N data transmission channels, the faulty second target channel can be quickly and accurately located by determining the error correction position and the number of channels. This allows for accurate adjustment of the reference voltage.
[0056] The method for adjusting the reference voltage of the second target channel is the same as the method for adjusting the reference voltage described above, and will not be repeated here for the sake of brevity.
[0057] The N channels on the memory side refer to the N channels that enable data reading and writing between the memory implementation and the memory controller.
[0058] Since the number of parallel transmission channels is N, each parallel transmission transmits N bits of data at a time, and the data is transmitted in the order of the N channels. That is, the first channel transmits the first bit of data, the second channel transmits the second bit of data, and so on, until the Nth channel transmits the Nth bit of data.
[0059] Optionally, based on the error correction location and the number of channels, the method to determine the second target channel that needs to be adjusted from the N channels on the memory side can be: divide the error correction location by N, and the remainder is the order of the second target channel among the N channels.
[0060] When the remainder is 0, it indicates that the last of the N channels has an error.
[0061] For ease of understanding, let N=8, and the order of the channels be D0, D1, D2, D3, D4, D5, D6, D7, with the error correction position being 105 (the 105th bit in the second data contains the error). Then 105 ÷ 8 = 13...1, meaning the remainder is 1. Therefore, the first channel D0 out of the N channels is determined as the second target channel. Consequently, the reference voltage for this second target channel is adjusted.
[0062] In one implementation, if the data transmission method is parallel transmission, and the number of parallel transmission channels is N, but these N channels share a single reference voltage, then the method for adjusting the reference voltage on the memory side of the data link between the memory and the memory controller based on the error correction polarity type included in the third detection result can be: if the error correction polarity type changes from 0 to 1, increase the shared reference voltage on the memory side; if the error correction polarity type changes from 1 to 0, decrease the shared reference voltage on the memory side.
[0063] This method of adjusting the shared reference voltage across N channels allows the reference voltage to be adjusted to overlap with the Vref Margin (the fault tolerance range of the reference voltage) of each of the N channels. This ultimately results in a reference voltage that meets the requirements of each channel.
[0064] The specific implementation method for adjusting (increasing or decreasing) the common reference voltage on the memory side is the same as the aforementioned implementation method for adjusting the reference voltage on the memory side, and will not be repeated here for the sake of brevity.
[0065] For ease of understanding, such as Figure 2 As shown. Figure 2 The diagram shows the Vref Margins (vertical lines) for each of the three channels. In stage 1, the reference voltage is only within the Vref Margin range of channels DQ1 and DQ2. Through a single adjustment, in stage 2, the reference voltage is adjusted to be within the Vref Margin range of all three channels DQ0, DQ1, and DQ2 simultaneously. This ensures that the reference voltage in stage 2 meets the requirements of channels DQ0, DQ1, and DQ2.
[0066] If the Vref Margin ranges of each channel do not intersect, such as Figure 3 As shown, this scheme cannot find a reference voltage that can simultaneously meet the needs of different channels.
[0067] S400: When there is no first address that is the same as the second address of the second data in memory, and the second check result indicates an error, and the third detection result indicates an error, the reference voltage of the data link between the memory and the memory controller on the memory controller side is adjusted according to the error correction polarity type included in the third detection result.
[0068] Since the first check result is obtained by parity checking of the first data written to memory, it can determine whether an error has occurred in the write direction (from memory controller to memory). The second check result is obtained by parity checking of the second data read from memory; therefore, it can determine whether an error has occurred in the read direction (from memory to memory controller). Therefore, if no first address matches the second address of the second data in memory (indicating that the first check result is correct), and the second check result indicates an error, it indicates that only the read direction is incorrect, and thus the reference voltage on the memory controller side needs to be adjusted.
[0069] The data link between the memory and the memory controller is located at the reference voltage on the memory controller side, which is the reference voltage for the memory controller to implement the interface for data reading and writing with the memory.
[0070] In one implementation, adjusting the reference voltage of the data link between the memory and the memory controller on the memory controller side based on the error correction polarity type included in the third detection result can be done as follows: if the error correction polarity type characterization changes from 0 to 1, the reference voltage on the memory controller side is increased; if the error correction polarity type characterization changes from 1 to 0, the reference voltage on the memory controller side is decreased.
[0071] When the error correction polarity type changes from 0 to 1, it indicates an error in identifying a low voltage as a high voltage. Since the identification process compares the voltage of the electrical signal with a reference voltage, if the signal is greater than the reference voltage, it is identified as 1; if the signal is less than the reference voltage, it is identified as 0. Therefore, identifying a low voltage as a high voltage indicates that the reference voltage is too low, and thus needs to be increased. Similarly, identifying a high voltage as a low voltage indicates that the reference voltage is too high, and thus needs to be decreased.
[0072] The specific implementation method for adjusting (increasing or decreasing) the reference voltage on the memory controller side is the same as the aforementioned implementation method for adjusting the reference voltage on the memory side, and will not be repeated here for the sake of brevity.
[0073] In one implementation, if the data transmission method is parallel transmission and the number of parallel transmission channels is N, the third detection result also includes an error correction position, which represents the bit bit in the second data that has an error. The way to adjust the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the error correction polarity type included in the third detection result can be: based on the error correction position and the number of channels, determine the first target channel whose reference voltage needs to be adjusted from the N channels on the memory controller side.
[0074] If the error correction polarity type characterization changes from 0 to 1, the reference voltage of the first target channel is increased. If the error correction polarity type characterization changes from 1 to 0, the reference voltage of the first target channel is decreased.
[0075] When there are N data transmission channels, the first target channel with the error can be quickly and accurately located by determining the error correction position and the number of channels. This allows for accurate adjustment of the reference voltage.
[0076] The N channels on the memory controller side refer to the N channels that enable the memory controller to perform data reading and writing with the memory.
[0077] The method for determining the first target channel is the same as the method for determining the second target channel described above; the method for adjusting the reference voltage of the first target channel is the same as the method for adjusting the reference voltage of the second target channel described above. For the sake of brevity, these details will not be repeated here.
[0078] In one implementation, if the data transmission method is parallel transmission, and the number of parallel transmission channels is N, but these N channels share a single reference voltage, then the method for adjusting the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the error correction polarity type included in the third detection result can be: if the error correction polarity type changes from 0 to 1, increase the shared reference voltage on the memory controller side; if the error correction polarity type changes from 1 to 0, decrease the shared reference voltage on the memory controller side.
[0079] The specific implementation method for adjusting (increasing or decreasing) the common reference voltage on the memory controller side is the same as the aforementioned implementation method for adjusting the reference voltage on the memory side, and will not be repeated here for the sake of brevity.
[0080] In one implementation, an alarm is issued when a first address and a second address are identical, and the second verification result indicates an error.
[0081] If the first address and the second address are identical, and the second check result indicates an error, it means that errors have occurred in both the data writing and reading processes. However, if at least two bits are incorrect simultaneously, the instruction error correction detection cannot determine the error correction polarity; therefore, an alarm is issued to indicate that an error has occurred.
[0082] To facilitate understanding of the above-mentioned method for adjusting the reference voltage, the following will combine... Figure 4 The specific execution logic is explained.
[0083] Figure 4 This illustrates the storage location of different data in memory.
[0084] When data A is written into memory, the memory performs a parity check on data A and obtains a first check result. Since the first check result indicates an error, the memory controller records the address of data A in memory (address 1 - address 2). At this time, the address recorded in the memory controller includes address 1 - address 2.
[0085] When data B is written into memory, the memory performs a parity check on data B, obtaining the first parity result corresponding to data B. Since the first parity result for data B indicates that no error has occurred, the memory controller does not need to record the address of data B in memory.
[0086] When data C is written into memory, the memory performs parity checking on data C, obtaining the first parity result corresponding to data C. Since this first parity result indicates an error, the memory controller records the address of data C in memory (address 5-address 6). At this point, the addresses recorded in the memory controller include addresses 1-2 and addresses 5-6.
[0087] Next, the memory controller reads data A from memory and performs parity checking and instruction error correction checks on data A, obtaining a second check result and a third check result corresponding to data A. The second check result indicates no error, while the third check result indicates an error, including the error correction polarity. Therefore, the memory controller matches the second address of data A in memory with each recorded first address, determining that there exists a first address that matches the second address corresponding to data A. Thus, it is determined that an error occurred during the write process for data A, and the reference voltage on the memory side of the data link between the memory and the memory controller is adjusted based on the error correction polarity type in the third check result corresponding to data A.
[0088] The memory controller reads data B from memory and performs parity checking and instruction error correction checks on data B, obtaining a second check result and a third check result corresponding to data B. The second check result for data B indicates an error, and the third check result for data B also indicates an error, including the error correction polarity. The memory controller matches the second address of data B in memory with each recorded first address, determining that no first address matches the second address corresponding to data B. Therefore, it is determined that an error occurred during the read process, and the reference voltage of the data link between the memory and the memory controller is adjusted on the memory controller side based on the error correction polarity type in the third check result for data B.
[0089] The memory controller reads data C from memory and performs parity checking and instruction error correction checks on data C, obtaining a second check result and a third check result for data C. The second check result and the third check result both indicate an error. Therefore, the memory controller matches the second address of data C in memory with each recorded first address, determining that there exists a first address that matches the second address of data C. Thus, it is determined that an error occurred in both the write and read processes of data C, and an alarm is issued.
[0090] The examples provided are for illustrative purposes only and should not be construed as limiting the scope of this application.
[0091] Based on the same technical concept, this application also provides a memory controller, such as... Figure 5 As shown, the memory controller 100 includes a reference voltage compensation module 110, a parity check module 120, and an instruction error correction module 130.
[0092] The reference voltage compensation module 110 is used to record the first address of the first data when the first parity check result of the first data written in memory indicates that the first data has an error.
[0093] The parity check module 120 is used to perform parity check on the second data read from memory and obtain the second check result.
[0094] Optionally, the parity check module 120 can be any existing functional module that can implement parity check, such as a common functional module that includes parity check and cyclic redundancy check. The specific type of the parity check module 120 is not limited here.
[0095] The instruction error correction module 130 is used to perform instruction error correction detection on the second data to obtain the third detection result.
[0096] Optionally, the instruction error correction module 130 can be any existing functional module that can implement instruction error correction and detection, such as an ECC module implemented using the Hamming code algorithm. There is no restriction on the specific type of the instruction error correction module 130 here.
[0097] The reference voltage compensation module 110 is also used to adjust the reference voltage on the memory side of the data link between the memory and the memory controller according to the error correction polarity type included in the third detection result when there is a first address and a second address of the second data in memory that are the same, and the second verification result indicates no error, but the third detection result indicates an error.
[0098] The reference voltage compensation module 110 is also used to adjust the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the error correction polarity type included in the third detection result when there is no first address and second address of the second data in memory that are the same, and the second verification result indicates an error.
[0099] In one implementation, the reference voltage compensation module 110 may be a software function module implemented by software.
[0100] In one embodiment, the reference voltage compensation module 110 may include a detection result recording unit 111, a read / write error direction judgment unit 112, and a reference voltage adjustment unit 113, such as... Figure 6 As shown.
[0101] The detection result recording unit 111 is used to record the first address of the first data when the first parity check result of the first data written in memory indicates that the first data has an error.
[0102] The detection result recording unit 111 can be a functional module with storage function, such as a register or memory, to record the first address of the first data.
[0103] The read / write error direction judgment unit 112 is used to determine the read / write error direction based on the first address of the record, the second verification result, and the second address of the second data in memory.
[0104] Optionally, the read / write error direction judgment unit 112 is specifically used to determine the read / write error direction as the write direction when there is a first address and a second address that are the same, and the second verification result indicates no error, but the third detection result indicates an error; and to determine the read / write error direction as the read direction when there is no first address and a second address that are the same, and the second verification result indicates an error.
[0105] The read / write error direction determination unit 112 can be implemented by existing circuits or electronic devices, which can implement the above-mentioned read / write error direction determination unit 112 execution logic.
[0106] The reference voltage adjustment unit 113 is used to adjust the reference voltage of the data link between the memory controller and the memory according to the direction of read / write errors and the polarity of error correction.
[0107] The reference voltage adjustment unit 113 is specifically used to adjust the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the error correction polarity type included in the third detection result when the read / write error direction is the read direction. When the read / write error direction is the write direction, it adjusts the reference voltage of the data link between the memory and the memory controller on the memory side according to the error correction polarity type included in the third detection result.
[0108] The reference voltage adjustment unit 113 is specifically used to increase the reference voltage on the memory controller side when the error direction is read and the error correction polarity type characterization changes from 0 to 1; and to decrease the reference voltage on the memory controller side when the error correction polarity type characterization changes from 1 to 0.
[0109] The reference voltage adjustment unit 113 is specifically used to increase the reference voltage on the memory side when the error direction is the write direction, if the error correction polarity type indicator changes from 0 to 1; and to decrease the reference voltage on the memory side when the error correction polarity type indicator changes from 1 to 0.
[0110] In one implementation, if the data transmission method is parallel transmission and the number of parallel transmission channels is N, the third detection result also includes an error correction position, which represents the bit in the second data that has an error. When there is no first address that is the same as the second address of the second data in memory, and the second verification result indicates an error, the reference voltage adjustment unit 113 is further configured to, when the read / write error direction is the read direction, determine the first target channel whose reference voltage needs to be adjusted from the N channels on the memory controller side based on the error correction position and the number of channels; if the error correction polarity type characterization changes from 0 to 1, increase the reference voltage of the first target channel; if the error correction polarity type characterization changes from 1 to 0, decrease the reference voltage of the first target channel.
[0111] In one implementation, if the data transmission method is parallel transmission and the number of parallel transmission channels is N, the third detection result also includes an error correction position, which represents the bit in the second data where an error occurred. When there exists a first address that is the same as the second address of the second data in memory, and the second verification result indicates no error, the reference voltage adjustment unit 113 is further configured to determine, based on the error correction position and the number of channels, a second target channel from the N channels on the memory side whose reference voltage needs to be adjusted. If the error correction polarity type characterization changes from 0 to 1, the reference voltage of the second target channel is increased; if the error correction polarity type characterization changes from 1 to 0, the reference voltage of the second target channel is decreased.
[0112] The reference voltage adjustment unit 113 can be implemented by existing circuits or electronic devices that can implement the execution logic of the reference voltage adjustment unit 113.
[0113] The specific execution steps and execution logic of the reference voltage compensation module 110 (detection result recording unit 111, read / write error direction judgment unit 112, reference voltage adjustment unit 113), parity check module 120, and instruction error correction module 130 have been described in detail in the aforementioned reference voltage adjustment method. For the sake of brevity, any parts not mentioned in the memory controller embodiment can be referred to the corresponding content in the aforementioned reference voltage adjustment method embodiment.
[0114] Based on the same technical concept, this application also provides a memory read / write system 10. For example... Figure 7 As shown, the memory read / write system 10 includes a memory controller 100 and a memory 200.
[0115] Memory 200 is used to perform parity checking on the first data written and obtain the first check result.
[0116] Memory 200 can be any existing type of memory, such as DDR (Double Data Rate Synchronous Dynamic Random-Access Memory), SDRAM (Synchronous Dynamic Random-Access Memory), etc. The specific type of memory is not limited to the implementation method exemplified here.
[0117] The memory controller 100 is configured to: record the first address of the first data when the first parity check result of the first data written to the memory 200 indicates an error in the first data; perform parity check on the second data when reading the second data from the memory 200 to obtain a second parity check result; and perform instruction error correction detection on the second data to obtain a third detection result; and adjust the reference voltage on the memory side of the data link between the memory 200 and the memory controller 100 according to the error correction polarity type included in the third detection result when the first address is the same as the second address of the second data in memory, the second parity check result indicates no error, and the third detection result indicates an error.
[0118] The memory controller 100 is also used to adjust the reference voltage of the data link between the memory 200 and the memory controller 100 on the memory controller side according to the error correction polarity type included in the third detection result when there is no first address that is the same as the second address of the second data in memory, and the second verification result indicates an error.
[0119] The specific structure of the memory controller 100 has been described in detail above, and will not be repeated here for the sake of brevity.
[0120] Based on the same technical concept, this application also provides an electronic device 1, such as... Figure 8As shown, the electronic device includes a processor 20 and a memory read / write system 10.
[0121] The processor 20 is connected to the memory read / write system 10.
[0122] Optionally, the processor 20 and the memory read / write system 10 can be connected via a data bus.
[0123] The processor 20 can be a CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be a DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.
[0124] The specific implementation of the memory read / write system 10 has been clearly described above, and will not be repeated here for the sake of brevity.
[0125] Electronic device 1 can be, for example, a computer, a server, or other devices, and the specific type of electronic device is not limited to the examples given here.
[0126] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method of adjusting a reference voltage, characterized by, The method is applied to a memory controller, and comprises the following steps: When a first parity check result of first data written in a memory indicates that the first data has an error, a first address of the first data is recorded; When second data is read from the memory, the second data is subjected to parity check to obtain a second check result, and the second data is subjected to instruction error correction detection to obtain a third detection result; When the first address is the same as a second address of the second data in the memory, the second check result indicates that there is no error, and the third detection result indicates that there is an error, a reference voltage of a data link between the memory and the memory controller is adjusted according to an error correction polarity type included in the third detection result; wherein the error correction polarity type represents a type of error in error correction detection.
2. The method of claim 1, wherein, The reference voltage of the data link between the memory and the memory controller is adjusted according to the error correction polarity type included in the third detection result, comprising: If the error correction polarity type indicates that a bit changes from 0 to 1, the reference voltage of the memory side is increased; If the error correction polarity type indicates that a bit changes from 1 to 0, the reference voltage of the memory side is decreased.
3. The method of claim 1, wherein, If the transmission mode of the data is parallel transmission, and the number of parallel transmission channels is N, the third detection result further includes an error correction position, which indicates a bit position of the second data where an error occurs; the reference voltage of the data link between the memory and the memory controller is adjusted according to the error correction polarity type included in the third detection result, comprising: Based on the error correction position and the number of channels, a second target channel whose reference voltage needs to be adjusted is determined from N channels of the memory side; If the error correction polarity type indicates that a bit changes from 0 to 1, the reference voltage of the second target channel is increased; If the error correction polarity type indicates that a bit changes from 1 to 0, the reference voltage of the second target channel is decreased.
4. The method of claim 1, wherein, The method further comprises: When the first address is not the same as the second address of the second data in the memory, the second check result indicates that there is an error, and the third detection result indicates that there is an error, a reference voltage of a data link between the memory and the memory controller is adjusted according to an error correction polarity type included in the third detection result.
5. The method of claim 4, wherein, The reference voltage of the data link between the memory and the memory controller is adjusted according to the error correction polarity type included in the third detection result, comprising: If the error correction polarity type indicates that a bit changes from 0 to 1, the reference voltage of the memory side is increased; If the error correction polarity type indicates that a bit changes from 1 to 0, the reference voltage of the memory side is decreased.
6. The method of claim 4, wherein, If the data transmission mode is parallel transmission, and the number of parallel transmission channels is N, the third detection result further includes an error correction position, the error correction position representing a bit position of the second data where an error occurs; and the reference voltage of the data link between the memory and the memory controller on the memory controller side is adjusted according to the error correction polarity type included in the third detection result, including: determining a first target channel for which the reference voltage needs to be adjusted from the N channels on the memory controller side based on the error correction position and the number of channels; if the error correction polarity type represents a change from 0 to 1, increasing the reference voltage of the first target channel; if the error correction polarity type represents a change from 1 to 0, decreasing the reference voltage of the first target channel.
7. The method of claim 1, wherein, The amplitude of each adjustment of the reference voltage does not exceed ±30% of the current size of the reference voltage.
8. The method of claim 1, wherein, The method further includes: issuing an alarm when the first address is the same as the second address, and the second check result indicates an error.
9. A memory controller, comprising: including: a reference voltage compensation module, a parity check module, and an instruction error correction module; the reference voltage compensation module is configured to record a first address of first data when a first check result of parity check of the first data by the memory indicates that the first data has an error; the parity check module is configured to perform parity check on second data read from the memory to obtain a second check result; the instruction error correction module is configured to perform instruction error correction detection on the second data to obtain a third detection result; the reference voltage compensation module is further configured to adjust the reference voltage of the data link between the memory and the memory controller on the memory side according to an error correction polarity type included in the third detection result when the first address is the same as a second address of the second data in the memory, and the second check result indicates no error and the third detection result indicates an error, wherein the error correction polarity type represents a type of error in the error correction detection.
10. The memory controller of claim 9, wherein, the reference voltage compensation module is further configured to adjust the reference voltage of the data link between the memory and the memory controller on the memory controller side according to an error correction polarity type included in the third detection result when the first address is not the same as the second address of the second data in the memory, and the second check result indicates an error and the third detection result indicates an error.
11. The memory controller of claim 9, wherein, the reference voltage compensation module includes: a detection result recording unit, a read-write error direction judgment unit, and a reference voltage adjustment unit; the detection result recording unit is configured to record a first address of first data when a first check result of parity check of the first data by the memory indicates that the first data has an error; the read-write error direction judgment unit is configured to determine a read-write error direction according to the recorded first address, the second check result, and a second address of the second data in the memory; and the reference voltage adjustment unit is configured to adjust the reference voltage of the data link between the memory and the memory controller on the memory controller side according to the read-write error direction. The reference voltage adjustment unit is configured to adjust a reference voltage of a data link between the memory controller and the memory according to the read-write error direction and the error correction polarity.
12. The memory controller of claim 11, wherein, The read-write error direction judgment unit is specifically configured to determine that the read-write error direction is a write direction when there is a first address same as the second address and the second check result represents no error; and determine that the read-write error direction is a read direction when there is no first address same as the second address and the second check result represents an error.
13. A memory read / write system, characterized by, The memory controller and the memory according to any one of claims 9-12; The memory is configured to perform parity check on the first data written to obtain a first check result. The memory controller is configured to record a first address of the first data when the first check result of the parity check performed by the memory on the first data written to represents an error of the first data. In a case of reading second data from the memory, performing parity check on the second data to obtain a second check result, and performing instruction error correction detection on the second data to obtain a third detection result; when there is a first address same as a second address of the second data in the memory, and the second check result represents no error and the third detection result represents an error, adjusting a reference voltage of a data link between the memory and the memory controller located at the memory side according to an error correction polarity type included in the third detection result. The memory controller is further configured to adjust a reference voltage of a data link between the memory and the memory controller located at the memory controller side according to an error correction polarity type included in the third detection result when there is no first address same as a second address of the second data in the memory, and the second check result represents an error and the third detection result represents an error.
14. The memory read / write system of claim 13, wherein, The memory controller and the memory according to any one of claims 9-12; 15. An electronic device, comprising: The processor and the memory read-write system are connected.