Clock signal gating circuit

Abstract

The invention provides a clock signal gating circuit. The clock signal gating circuit comprises a clock signal input buffer, a first logic circuit, a second logic circuit and a latch circuit, the clock signal input buffer receives a clock signal and outputs an internal clock signal based on a clock switching signal. The first logic circuit receives an asynchronous clock enable signal and a synchronous clock enable signal and outputs a clock switching signal. The second logic circuit receives the asynchronous clock enable signal, the synchronous clock enable signal and the internal clock signal and outputs a clock gating signal. The latch circuit receives an asynchronous clock enable signal and a clock gating signal to output a synchronous clock enable signal.

Description

Technical Field

[0001] This invention relates to a clock control technology, and more particularly to a clock signal gate circuit. Background Technology

[0002] The clock enable signal CKE of memory devices such as DRAM is used to switch the clock signal input buffer on and off. Figure 1 The control circuit of a known pulse signal input buffer is shown. For example... Figure 1 As shown, clock signal input buffer 14 receives a pair of complementary clock signals CLK_T and CLK_C, and outputs an internal clock signal CK_t. Input buffer 10 receives a clock enable signal CKE and a reference voltage signal VREF, and generates an asynchronous clock enable signal CKE_ASYNC accordingly. Furthermore, latch circuit 12 receives the asynchronous clock enable signal CKE_ASYNC and the internal clock signal CK_t, thereby generating a synchronous clock enable signal CKE_SYNC.

[0003] Therefore, the clock enable signal CKE in the circuit is divided into an asynchronous clock enable signal CKE_ASYNC and a synchronous clock enable signal CKE_SYNC. These are then passed through an OR gate 16 and combined to become the clock switching signal CLK_EN for the pulse signal input buffer. In known technologies, the synchronous clock enable signal CKE_SYNC is continuously active when the clock enable signal CKE is high. Therefore, even in standby mode, the entire circuit continuously consumes power. Reducing this power consumption is therefore a key challenge. Summary of the Invention

[0004] Based on the above description, according to an embodiment of the present invention, a clock signal gate control circuit is provided, comprising: a clock signal input buffer, a first logic circuit, a second logic circuit, and a latch circuit. The clock signal input buffer receives a clock signal and outputs an internal clock signal based on a clock switch signal. The first logic circuit receives an asynchronous clock enable signal and a synchronous clock enable signal, and outputs the clock switch signal. The second logic circuit receives the asynchronous clock enable signal, the synchronous clock enable signal, and the internal clock signal, and outputs a clock gate control signal. The latch circuit receives the asynchronous clock enable signal and the clock gate control signal to output the synchronous clock enable signal.

[0005] Based on the above, the second logic circuit can prevent the synchronous clock enable signal from continuously operating when the clock enable signal is high, thereby reducing the overall power consumption of the circuit even in standby mode. Attached Figure Description

[0006] Figure 1The control circuit of a known pulse signal input buffer is shown;

[0007] Figure 2 It is a pulse signal gate control circuit according to the embodiment of the present invention;

[0008] Figure 3 This is a timing diagram of the operation of the pulse signal gate control circuit according to an embodiment of the present invention. Detailed Implementation

[0009] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0010] Figure 2 This is a clock signal gate circuit shown according to an embodiment of the present invention. This clock signal gate circuit 100 can be applied to a memory device, such as dynamic random access memory (DRAM) or any other type of memory device. Furthermore, in the case of DRAM, the DRAM may, for example, conform to the double data rate (DDR) specification.

[0011] like Figure 2 As shown, the clock signal gate circuit 100 includes at least a clock signal input buffer 110, a first logic circuit 112, a second logic circuit 114, and a latch circuit 116. The clock signal gate circuit 100 may also include an input buffer 118.

[0012] Input buffer 118 is configured to receive the clock enable signal CKE and the reference voltage signal VREF, and output an asynchronous clock enable signal CKE_ASYNC accordingly. In other words, input buffer 110 can convert the clock enable signal CKE and output the asynchronous clock enable signal CKE_ASYNC based on whether the reference voltage signal VREF is high or low. The asynchronous clock enable signal CKE_ASYNC can be used to enable the clock signal input buffer 110.

[0013] The clock signal input buffer 110 is configured to receive the clock signal CLK and output an internal clock signal CK_t based on the clock switch signal CLK_EN. That is, the clock input buffer 110 receives the externally input clock signal CLK and outputs the internal clock signal CK_t for various operations within the memory device. As an example, the clock signal CLK may include a pair of complementary clock signals CLK_T and CKT_C. Figure 2 (Example shown). The clock input buffer 110 is controlled by the clock switch signal CLK_EN output from the first logic circuit 112 to turn the clock input buffer 110 on or off.

[0014] The first logic circuit 112 is configured to receive an asynchronous clock enable signal CKE_ASYNC and a synchronous clock enable signal CKE_SYNC, and output a clock switch signal CLK_EN. The clock switch signal CLK_EN is further provided to the clock input buffer 110 to switch the clock input buffer 110 on and off. Here, as an example, the first logic circuit 112 can be constructed from an OR gate, or it can be a combination of various other logic gates capable of the same logic operation.

[0015] Generally, after receiving the external clock enable signal CKE, it is converted into two paths: the path of the asynchronous clock enable signal CKE_ASYNC and the path of the synchronous clock enable signal CKE_SYNC. The asynchronous clock enable signal CKE_ASYNC and the synchronous clock enable signal CKE_SYNC then generate the clock switch signal CLK_EN via the first logic circuit 112.

[0016] When the clock enable signal CKE goes high, the output asynchronous clock enable signal CKE_ASYNC enables the clock signal input buffer 110, causing it to output the internal clock signal CK_t. After the clock enable signal CKE goes low, the latch circuit 116 generates a synchronous clock enable signal CKE_SYNC delayed by a predetermined number of clock cycles. The synchronous clock enable signal CKE_SYNC can disable the clock signal input buffer 110, preventing it from outputting the internal clock signal CK_t.

[0017] The second logic circuit 114 is configured to receive the asynchronous clock enable signal CKE_ASYNC, the synchronous clock enable signal CKE_SYNC, and the internal clock signal CK_t, and output a clock gate signal CK_CKE. Furthermore, when the asynchronous clock enable signal CKE_ASYNC and the synchronous clock enable signal CKE_SYNC are in different phases, the second logic circuit 114 outputs the signal CK_CKE_EN high, and during the period when the output signal CK_CKE_EN is high, it outputs the clock gate signal CK_CKE. The clock gate signal CK_CKE is further provided to the latch circuit 116.

[0018] Furthermore, according to an embodiment of the present invention, the second logic circuit 114 may further include a phase comparison circuit 114a and a switch 114b. The phase comparison circuit 114a receives and compares the phases of the asynchronous clock enable signal CKE_ASYNC and the synchronous clock enable signal CKE_SYNC, and when the phases are different, the output signal CK_CKE_EN of the phase comparison circuit 114a becomes a high-level signal. The switch 114b receives the output signal CK_CKE_EN of the phase comparison circuit 114a and the internal clock signal CK_t, and outputs a clock gate signal CK_CKE.

[0019] In one embodiment, the phase comparison circuit 114a may be an XOR gate (hereinafter referred to as XOR gate 114a), and the switch may be an AND gate (hereinafter referred to as AND gate 114b). Here, both XOR gate 114a and AND gate 114b may be replaced by combinations of other logic gates that can achieve the same logic operation.

[0020] The latch circuit 116 is configured to receive the asynchronous clock enable signal CKE_ASYNC and the clock gate signal CK_CKE, and output the synchronous clock enable signal CKE_SYNC. That is, the asynchronous clock enable signal CKE_ASYNC from the input buffer 118 is further input to the latch circuit 116. The latch circuit 116 also receives the clock gate signal CK_CKE output from the second logic circuit 114, and outputs the synchronous clock enable signal CKE_SYNC accordingly. The latch circuit 116 can delay the asynchronous clock enable signal CKE_ASYNC by a predetermined number of clock cycles based on the asynchronous clock enable signal CKE_ASYNC and the clock gate signal CK_CKE to generate the synchronous clock enable signal CKE_SYNC.

[0021] Next, the operation of the second logic circuit 114 will be explained. As an example, the phase comparison circuit 114a can be constructed using an XOR gate, and the switch 114b can be constructed using an AND gate. Figure 2 As shown, the XOR gate 114a receives the asynchronous clock enable signal CKE_ASYNC and the synchronous clock enable signal CKE_SYNC. Through the XOR gate 114a, the output signal CK_CKE_EN of the XOR gate 114a will only become a high-level signal when the asynchronous clock enable signal CKE_ASYNC and the synchronous clock enable signal CKE_SYNC are in different phases (out of phase) or at different levels.

[0022] Subsequently, the output signal CK_CKE_EN is further provided to the AND gate 114b. The AND gate 114b receives the output signal CK_CKE_EN and the internal clock signal CK_t from the clock signal input buffer 110, and outputs the clock switching signal CK_CKE accordingly. Here, when the output signal CK_CKE_EN is at a high level, the AND gate 114b can output the same gate control signal CK_CKE as the internal clock signal CK_t to the latch circuit 116, and when the output signal CK_CKE_EN is at a low level, it stops outputting the gate control signal CK_CKE to the latch circuit 116. Therefore, the AND gate 114b can be regarded as a clock path that provides the internal clock signal CK_t to the latch circuit 116 according to the output signal CK_CKE_EN.

[0023] Figure 3 This is a timing diagram of the pulse signal gate control circuit according to an embodiment of the present invention. Please refer to... Figure 3 First, when the asynchronous clock enable signal CKE_ASYNC changes from low to high, the output signal CLK_CKE_EN of the XOR gate 114a becomes high because the synchronous clock enable signal CKE_SYNC is low. Next, the AND gate 114b generates a gate control signal CK_CKE, identical to the internal clock signal CK_t, and sends it to the latch circuit 116. The latch circuit 116 then re-latches the high-level asynchronous clock enable signal CKE_ASYNC based on the gate control signal CK_CKE, and generates a high-level synchronous clock enable signal CKE_SYNC accordingly. Afterward, the synchronous clock enable signal CKE_SYNC remains high.

[0024] At this time, as Figure 3 As shown, since both the asynchronous clock enable signal CKE_ASYNC and the synchronous clock enable signal CKE_SYNC are high, the output signal CLK_CKE_EN of the XOR gate 114a will become low, and the AND gate 114b will stop generating the gate control signal CK_CKE.

[0025] On the other hand, when the asynchronous clock enable signal CKE_ASYNC changes from high to low, since the synchronous clock enable signal CKE_SYNC is high, the output signal CLK_CKE_EN of the XOR gate 114a will become high. Then, the AND gate 114b generates a gate control signal CK_CKE, identical to the internal clock signal CK_t, and sends it to the latch circuit 116. The latch circuit 116 then re-latches the low-level asynchronous clock enable signal CKE_ASYNC based on the gate control signal CK_CKE, and generates a low-level synchronous clock enable signal CKE_SYNC accordingly. Afterward, the synchronous clock enable signal CKE_SYNC will remain low.

[0026] At this time, as Figure 3 As shown, since both the asynchronous clock enable signal CKE_ASYNC and the synchronous clock enable signal CKE_SYNC are low, the output signal CLK_CKE_EN of the XOR gate 114a will become low, and the AND gate 114b will stop generating the gate control signal CK_CKE.

[0027] Therefore, through this circuit architecture, in standby mode, the latch circuit 116 maintains the state of the synchronous clock enable signal CKE_SYNC, while the gate signal CK_CKE, which controls the latch circuit 116 to re-latch the asynchronous clock enable signal CKE_ASYNC, changes and remains at a low level to stop the latch circuit 116 from re-latching the asynchronous clock enable signal CKE_ASYNC, thereby saving power consumption. The gate signal CK_CKE is only regenerated when the synchronous clock enable signal CKE_SYNC and the asynchronous clock enable signal CKE_ASYNC are out of phase, so that the latch circuit 116 re-latches the asynchronous clock enable signal CKE_ASYNC. Compared to Figure 1 In the example, the internal clock signal CK_t is continuously provided to the latch circuit 12 even in standby mode, causing the latch circuit 12 to continuously latch the asynchronous clock enable signal CKE_ASYNC. Therefore, the present invention can further reduce power consumption in standby mode, and thus better meet the standby specifications of DRAM memory (such as IDD2N specification).

[0028] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock signal gate control circuit, characterized in that, include: The clock signal input buffer receives the clock signal and outputs the internal clock signal based on the clock switch signal. The first logic circuit receives the asynchronous clock enable signal and the synchronous clock enable signal, and outputs the clock switch signal. The second logic circuit receives the asynchronous clock enable signal, the synchronous clock enable signal, and the internal clock signal, and outputs a clock gate signal. as well as The latch circuit receives the asynchronous clock enable signal and the clock gate signal to output the synchronous clock enable signal.

2. The clock signal gate control circuit according to claim 1, characterized in that, The second logic circuit outputs a high-level signal when the asynchronous clock enable signal and the synchronous clock enable signal are in different phases, and outputs the clock gate signal during the output of the high-level signal.

3. The clock signal gate control circuit according to claim 1, characterized in that, The first logic circuit is an OR gate.

4. The clock signal gate control circuit according to claim 2, characterized in that, The second logic circuit also includes: A phase comparison circuit receives and compares the phases of the asynchronous clock enable signal and the synchronous clock enable signal, and outputs a high-level signal when the phases are different; and The switch receives the output of the phase comparison circuit and the internal clock signal, and outputs the clock gate signal.

5. The clock signal gate control circuit according to claim 4, characterized in that, The phase comparison circuit is an XOR gate, and the switch is an AND gate.

6. The clock signal gate control circuit according to claim 1, characterized in that, Also includes: An input buffer receives a clock enable signal and a reference voltage signal to generate the asynchronous clock enable signal.

7. The clock signal gate control circuit according to claim 1, characterized in that, The latching circuit generates the synchronous clock enable signal by delaying the asynchronous clock enable signal by a predetermined number of clock cycles based on the asynchronous clock enable signal and the clock gate signal.

8. The clock signal gate control circuit according to claim 1, characterized in that, The clock signal comprises a pair of complementary clock signals.

9. The clock signal gate control circuit according to claim 1, characterized in that, The clock signal gate circuit is applied to the memory, which is a dynamic random access memory.

10. The clock signal gate control circuit according to claim 9, characterized in that, The dynamic random access memory conforms to the double data rate specification.

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